1377662 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種多晶 片覆晶封裝構造。 【先前技術】 由於電子產品朝向尚效能以及小型化的發展趨勢，在 半導體裝置中，為了有效達到功能的擴充或減少晶片所 佔據的空間’通常會將多個晶片重疊配置在一起，並電 性連接至基板。而常見的電性連接方式係為打線接合以 及覆晶接合。其中，以覆晶接合達到多晶片堆疊的技術 最為困難’在封裝過程中，位於上方之覆晶晶片通常係 透過中介基板（interposer)或位於下方之覆晶晶片之晶背 重分配線路層（redistribution wiring layer)，作為電性傳 輸媒介。然而，此構造會增加製造成本與使得製程較為 繁瑣。 請參閱第1圖所示，習知多晶片覆晶封裝構造1〇〇 包含一基板11 0、一第一覆晶晶片1 2〇、一第二覆晶晶片 130、一第一底部填充膠141、一第二底部填充膠142、 一中介基板160以及一模封膠體i 70。該基板11〇係具 有一上表面111以及一相對之下表面114,該上表面m 係設有複數個第一凸塊接點112以及第一打線接指 113，該下表面114係設有複數個外接墊115。該第一覆 晶晶片12 0係覆晶接合於該基板11 〇，以使其具有之複 數個第一凸塊121係接合於該基板u〇之該些第一凸塊 3 13776,62 接點112。該第一底部填充膠141係形成於該第一覆晶 晶片120與該基板110之該上表面ill之間，並密封該 些第一凸塊121»該中介基板160係設置於該第—覆晶 晶片120上’並具有複數個第二凸塊接點161與複數個 第二打線接指162。該第二覆晶晶片130係覆晶接合於 該中介基板110，並使該第二覆晶晶片130之複數個第 二凸塊131接合於該些第二凸塊接點161。另藉由複數 個銲線163連接該中介基板160之該些第二打線接指 162至該基板110之該些第一打線接指113,以使該第二 覆晶晶片130可電性連接至該基板110 ^該第二底部填 充膠142係形成於該第二覆晶晷片13〇與該中介基板 160之間，並密封該些第二凸塊131。該模封膠體170 係垠成於該基板110之該上表面111，並密封該些覆晶 晶片120與130、該些底部填充膠141與142、該中介基 板160以及該些銲線163。複數個外接端子150係設置 於該基板11〇之該些外接墊115» 因此’在覆晶接合該第二覆晶晶片1 3 〇之前，必須先 設置該中介基板160於該第一覆晶晶片12〇上，才可設 置該第二覆晶晶片130。並且，再藉由該些銲線163電 性連接至該基板110，才可達到該第二覆晶晶片1 3 0與 該基板11〇之電性連接。在覆晶接合該第一覆晶晶片120 之後，會形成該第一底部填充膠141以密封該些第一凸 塊1 2 1。同樣地，在覆晶接合該第二覆晶晶片1 30之後， 亦會形成該第二底部填充膠142以密封該些第二凸塊 4 13776.62 m。此外’為了保護該些銲線163，會在該基板ιι〇上 形成該模封勝^70以密封該些鲜線163。由上述可知 該習知多晶片覆晶封裝構造—包含有該中介基板 160以及該些銲線163，才能達到該第_ 咬㈠。茨弟一覆晶晶片1 3 〇 與該基板110之電性連接，不伯 钱不但封裝厚度與製造成本増 加，並且必須經過至少三次的 膠步驟，才可密封該些 凸塊121與131以及該此鋥始] ~ 二紅線163 ,使得封裝製程相當 繁瑣。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 -種多晶片覆晶封裝構造’達到多晶片覆晶封裝之立體 堆疊’可嗜略中介基板並有易於填膠與節省填膠次數之 功效。 本發明之次—目的係在於提供一種多晶片t晶封裝 構造，能省略中介基板或晶背重分配線路層之設置以及 φ 省略打線接合之步驟，能減少電性傳輸媒介、減少空間 需求與提高構裝密度。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種多晶片覆晶封裝構造主 要包含一基板、一第一覆晶晶片以及一第二覆晶晶片。 該基板係具有一上表面’其上係設有複數個第一凸塊接 點與複數個第一凸塊接點，其中該些第二凸塊接點係排 列於該些第一凸塊接點之周邊並且為凸柱狀。該第一覆 晶晶片係具有複數個第一凸塊’係接合至該些第一凸塊 5 1377662 接點’並在該第一覆晶晶片與該基板之間形成一第一覆 晶間隙。該第二覆晶晶片係具有複數個第二凸塊，係接 合至該些第二凸塊接點，並在該第二覆晶晶片與該第一 覆晶晶片之間形成一第二覆晶間隙。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的多晶片覆晶封裝構造中，可另包含一底部填 充膠，其係同時填滿該第一覆晶間隙與該第二覆晶間隙。 在前述的多晶片覆晶封裝構造中，該底部填充膠係可 密封該些第二凸塊接點。 在前述的多晶片覆晶封裝構造中，該第一覆晶間隙與 該第二覆晶間隙可為大致相等。 在前述的多晶片覆晶封裝構造中，可另包含有一第一 中央接合劑，其係不填滿地形成於該第一覆晶間隙内。 在前述的多晶片覆晶封裝構造中，可另包含有一第二 Φ 中央接合劑，其係不填滿地形成於該第二覆晶間隙内。 在前述的多晶片覆晶封裝構造中，可另包含一模封膠 體，係形成於該基板之該上表面並填滿該第一覆晶間隙 與該第二覆晶間隙’ d密封該第一覆晶晶片、該第一中 央接合劑與該第二中央接合劑。 在前述的多晶片覆晶封裝構造中，該些第二凸塊接點 係可高出或水平於該第一覆晶晶片之一背面。 在則述的多B曰片覆晶封袭構造中，該些第二凸塊接點 係可包含複數個鋼柱。 13776.62 在前述的多晶片覆晶封裝構造中，每一第二凸塊係可 包含一間隙維持塊與一焊接劑。 在前述的多晶片覆晶封裝構造中’每一第一凸塊係可 包含一間隙維持塊與一焊接劑。 在前述的多晶片覆晶封裝構造中，該基板之該上表面 之上係可更a又有複數個第三凸塊接點，其中該些第三凸 塊接點係排列於該些第二凸塊接點之周邊並且為更高於 該些第二凸塊接點之凸柱狀。 在前述的多晶片覆晶封裝構造中，可另包含一第三覆 晶晶>1 ’係具有複數個第三凸塊’係接合至該些第三凸 塊接點，並在該第三覆晶晶片與該第二覆晶晶片之間形 成一第三覆晶間隙。 在前述的多晶片覆晶封裝構造中，可另包含一第三中 央接合劑’其係不填滿地形成於該第三覆晶間隙内。 在前述的多晶片覆晶封裝構造中，可另包含一第四覆 晶晶片’係覆晶接合於該基板之一下表面。 在前述的多晶片覆晶封裝構造中，該第二覆晶晶片係 可具有一大於該第一覆晶晶片之尺寸，以完全覆蓋該第 一覆晶晶片。 在前述的多晶片覆晶封裝構造中，可另包含有複數個 外接端子，係接合至該基板之一下表面。 由以上技術方案可以看出，本發明之多晶片覆晶封裝 構造，具有以下優點與功效： 一、可藉由基板的不等高凸塊接點的形狀與覆晶晶片的 1377662 特定組合型態作為其中_姑辦王饥 * ?技術手段，能提供一懸空 的覆晶接合面，並且多個覆晶間隙為重疊地平行排 列在最大晶片覆蓋區域内，達到多晶片覆晶封裝之 體隹疊彳省略中介基板並有易於填膠與節省填 膠次數之功效。 -、可藉由基板的不等高凸塊接點的形狀與覆晶晶片的 特定組合型態作為其卜技術手段，能省略中介基1377662 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a polycrystalline flip chip package structure. [Prior Art] Due to the trend toward electronic performance and miniaturization, in semiconductor devices, in order to effectively achieve the expansion of functions or reduce the space occupied by wafers, multiple wafers are usually overlapped and electrically connected. Connect to the substrate. The common electrical connection methods are wire bonding and flip chip bonding. Among them, the technology of flip chip bonding to achieve multi-wafer stacking is the most difficult. In the packaging process, the overlying wafer wafer is usually passed through an interposer or a crystal back-rearrangement layer underlying the flip-chip wafer (redistribution). Wiring layer) as an electrical transmission medium. However, this configuration increases manufacturing costs and makes the process cumbersome. Referring to FIG. 1 , the conventional multi-chip flip chip package structure 1 includes a substrate 110 , a first flip chip 12 , a second flip chip 130 , and a first underfill 141 . A second underfill 142, an interposer substrate 160, and a molding compound i 70. The substrate 11 has an upper surface 111 and an opposite lower surface 114. The upper surface m is provided with a plurality of first bump contacts 112 and a first wire bonding finger 113. The lower surface 114 is provided with a plurality of An external pad 115. The first flip chip 120 is flip-chip bonded to the substrate 11 以 so that the plurality of first bumps 121 are bonded to the first bumps 3 13776, 62 of the substrate u 112. The first underfill 141 is formed between the first flip chip 120 and the upper surface ill of the substrate 110, and seals the first bumps 121» the interposer 160 is disposed on the first overlay The crystal wafer 120 has 'a plurality of second bump contacts 161 and a plurality of second wire bonding fingers 162. The second flip chip 130 is flip-chip bonded to the interposer 110, and the plurality of second bumps 131 of the second flip chip 130 are bonded to the second bump contacts 161. The second bonding wires 162 of the interposer 160 are connected to the first bonding fingers 113 of the substrate 110 by a plurality of bonding wires 163, so that the second flip chip 130 can be electrically connected to The second underfill 142 is formed between the second flip chip 13 and the interposer 160 and seals the second bumps 131. The molding compound 170 is formed on the upper surface 111 of the substrate 110, and seals the flip chip 120 and 130, the underfills 141 and 142, the interposer 160, and the bonding wires 163. The plurality of external terminals 150 are disposed on the external pads 115 of the substrate 11 . Therefore, before the flip chip bonding the second flip chip 13 3 , the interposer substrate 160 must be disposed on the first flip chip. The second flip chip 130 can be disposed on the 12 。. Moreover, the electrical connection between the second flip-chip wafer 130 and the substrate 11A can be achieved by electrically connecting the bonding wires 163 to the substrate 110. After the flip chip is bonded to the first flip chip 120, the first underfill 141 is formed to seal the first bumps 112. Similarly, after the flip chip is bonded to the second flip chip 130, the second underfill 142 is also formed to seal the second bumps 4 13776.62 m. In addition, in order to protect the bonding wires 163, the die bond 70 is formed on the substrate ι to seal the fresh wires 163. It can be seen from the above that the conventional multi-chip flip chip package structure includes the interposer substrate 160 and the bonding wires 163 to achieve the first bite (1). The electrical connection between the flip chip and the substrate 110 is not only the package thickness and the manufacturing cost, but also must pass at least three glue steps to seal the bumps 121 and 131 and the This start] ~ two red lines 163, making the packaging process quite cumbersome. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a multi-wafer flip chip package structure to achieve a multi-wafer flip-chip package of a three-dimensional stack of 'appropriate intermediate substrates and easy to fill and save filling The effect of the number of glues. The second objective of the present invention is to provide a multi-wafer t-crystal package structure, which can omit the arrangement of the interposer substrate or the crystal back redistribution circuit layer and φ omit the wire bonding step, thereby reducing the electrical transmission medium, reducing the space requirement and improving Construction density. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a multi-wafer flip chip package structure mainly comprising a substrate, a first flip chip and a second flip chip. The substrate has an upper surface on which a plurality of first bump contacts and a plurality of first bump contacts are disposed, wherein the second bump contacts are arranged on the first bumps The periphery of the point is a convex column. The first flip chip has a plurality of first bumps attached to the first bumps 5 1377662 and forming a first through gap between the first flip chip and the substrate. The second flip chip has a plurality of second bumps bonded to the second bump contacts and a second flip chip is formed between the second flip chip and the first flip chip gap. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the above multi-wafer flip-chip package structure, a bottom fill adhesive may be further included, which simultaneously fills the first flip-chip gap and the second flip-chip gap. In the aforementioned multi-wafer flip chip package configuration, the underfill layer can seal the second bump contacts. In the above multi-wafer flip chip package structure, the first flip-chip gap and the second flip-chip gap may be substantially equal. In the above multi-wafer flip-chip package construction, a first central bonding agent may be further included which is formed in the first flip-chip gap without filling. In the foregoing multi-wafer flip chip package structure, a second Φ central bonding agent may be further included, which is formed in the second flip-chip gap without filling. In the above multi-wafer flip-chip package structure, a mold encapsulant may be further formed on the upper surface of the substrate and fill the first flip-chip gap and the second flip-chip gap d d to seal the first A flip chip, the first central bonding agent and the second central bonding agent. In the multi-wafer flip-chip package construction described above, the second bump contacts may be elevated or horizontal to the back side of one of the first flip chip. In the multi-B flip-chip encapsulation structure described above, the second bump contacts may comprise a plurality of steel columns. 13776.62 In the foregoing multi-wafer flip chip package construction, each of the second bumps may include a gap maintaining block and a solder. In the foregoing multi-wafer flip chip package construction, each of the first bumps may include a gap maintaining block and a solder. In the above multi-wafer flip-chip package structure, the upper surface of the substrate may have a plurality of third bump contacts on the upper surface, wherein the third bump contacts are arranged in the second The periphery of the bump contact is a convex column shape higher than the second bump contacts. In the foregoing multi-wafer flip chip package structure, a third flip chip crystal >1 ' has a plurality of third bumps 'bonded to the third bump contacts, and in the third A third flip-chip gap is formed between the flip chip and the second flip chip. In the above multi-wafer flip chip package structure, a third central bonding agent may be further included which is formed in the third flip-chip gap without filling. In the above multi-wafer flip chip package structure, a fourth flip chip may be further bonded to the lower surface of one of the substrates. In the foregoing multi-wafer flip chip package configuration, the second flip chip may have a size larger than the first flip chip to completely cover the first flip chip. In the above multi-wafer flip chip package structure, a plurality of external terminals may be further included and bonded to a lower surface of the substrate. It can be seen from the above technical solution that the multi-chip flip chip package structure of the present invention has the following advantages and effects: 1. The shape of the unequal bump contact of the substrate and the specific combination type of the flip-chip wafer 1377662 As a technical means, a floating crystal bond surface can be provided, and a plurality of flip-chip gaps are arranged in parallel in a maximum wafer coverage area to achieve a multi-chip flip chip package.彳The interposer substrate is omitted and has the effect of easy filling and saving the number of fillings. - The medium-based base can be omitted by the shape of the unequal bump contact of the substrate and the specific combination of the flip chip.
板或晶背重分配線路層之設置以及省略打線接合之 步驟’能減少電性傳輸媒介、減少空間需求與提高 構裝密度。 三、 可藉由基板的不等高凸塊接點的形狀與覆晶晶片的 位置作為其中一技術手段，並結合覆晶晶片以焊接 劑接合至基板之凸塊接點，能避免焊接劑在基板上 表面之擴散污染。The arrangement of the board or the crystal back redistribution wiring layer and the step of omitting the wire bonding can reduce the electrical transmission medium, reduce the space requirement, and increase the density of the package. 3. The shape of the unequal bump contact of the substrate and the position of the flip chip can be used as one of the technical means, and the bump contact of the flip chip bonded to the substrate by the solder can be avoided. Diffusion contamination of the upper surface of the substrate.
四、 可藉由基板的不等高凸塊接點與覆晶晶片的特定組 合型態作為其中一技術手段，更結合覆晶晶片之凸 塊包含有間隙維持塊，可使基板上位於不同高度的 多個覆晶間隙為平行形成。 五、 可藉由基板的柱狀凸塊接點的設計與覆晶晶片堆疊 的特定組合型態作為其中一技術手段，更結合在覆 晶間隙内形成中央接合劑，以使立體堆疊之覆晶晶 片在接合後即得到良好固著強度並能以預先填充的 方式降低封膠材料填滿覆晶間隙的困難度，有助於 提昇封裝品質，特別可以達成以模封膠體填滿覆晶 8 1377662 間隙並且不會造成柱狀凸塊接點斷裂之功效。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他㈣尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種多晶片覆晶封裝 構造舉例說明於第2圖之截面示意圖以及第3圖之頂面 透視圖。該多晶片覆晶封裝構造2〇〇主要包含一基板 21〇、-第-覆晶晶片220以及一第二覆晶晶片23〇。該 基板210係具有一上矣911 上录面211。該上表面211係作為晶 片設置表面，以供覆晶接合該第一覆晶晶片22〇與該第 二覆晶晶片230。該上表面211係設有複數個第一凸塊 接點212與複數個第二凸塊接點213。該些第—凸塊接 點212係可供該第—覆晶晶片220之電性連接，該些第 二凸塊接點213係可供該第二覆晶晶片23〇之電性連 接。在本實施例中，該些第一凸塊接點212係為平墊狀、 或者在防焊層之厚度影響下為微凹形狀，或者在表面電 鐘層之厚度影響下為微凸的形狀，並且該些第一凸塊接 點2 12係可耕列成如口字形之周邊排列。& π _ ^ ^ 在不同實施例 9 13776.62 中’該些第一凸塊接點212係可排列成矩陣排列。該些 第一凸塊接點213係排列於該些第一凸塊接點212之周 邊並且為凸杈狀，以提供一懸空的覆晶接合面。也就是 說’該些第一凸塊接點212與該些第二凸塊接點213係 分別提供不同高度之覆晶接合面，以使該第二覆晶晶片 230可如懸空狀覆晶接合於該基板210上之一預定高 度，並在該第二覆晶晶片230下方形成可供容置該第一 覆曰曰晶片220與複數個覆晶間隙之空間。該些第二凸塊 接點2 1 3之凸柱高度係可以利用電鍍方法控制。較佳 地，該些第二凸塊接點213係可包含複數個銅柱，用以 支撐與限定該第二覆晶晶片230之設置高度。請參閱第 2圖所不，該基板21〇係可具有一下表面214，該下表面 214係設置有複數個外接墊215，並以適當之線路圖案電 性導通。該些外接墊2 1 5係可為圓形墊。在本實施例中， 該多晶片覆晶封裝構造200可另包含有複數個外接端子 250 ’係接合至該基板210之該下表面214之該些外接墊 2 1 5 ’以供對外接合。該些外接端子25〇係可為多排或矩 陣排列之銲球。 請參閱第2圖所示，該第一覆晶晶片22〇係具有複數 個第一凸塊221。通常該第一覆晶晶片22〇係内設有積 體電路元件，如控制器、微處理器、邏輯元件、記憶體 等或上述的組合，並藉由該些第一凸塊221作為該第一 覆晶sa片220對外連接之電極。該些第一凸塊221係接 合至該些第一凸塊接點212,並在該第一覆晶晶片22〇 10 1377662 與該基板2 1 0之間形成一第一覆晶間隙s丨。適用於設置 該第一覆晶晶月220的覆晶接合技術係包含熱超音波加 熱鍵合、回焊與熱壓合。請參閱第3圖所示，該些第一 凸塊221係可形成於該第一覆晶晶片22〇之周邊。在不 同實施例中，該些第一 6塊221的形成位置係為矩陣排 列。在本實施例中，如第2圖的放大圖所示，每一第一 凸塊221係可包含一間隙維持塊222與一焊接劑223。 該些間隙維持塊2 2 2之材質係可為電鍍形成之耐高溫金 屬，例如銅。該第一覆晶晶片22〇可藉由該些間隙維持 塊222維持該第一覆晶晶片22〇在覆晶接合時之水平度 與高度’並可用以避免碰觸位於上方之該第二覆晶晶片 23 0。該些焊接劑223係可為銲料，可焊接連接至該基板 21〇之該些第一凸塊接點212。 請參閱第2圖所示，該第二覆晶晶片23〇係具有複數 個第二凸塊231。該些第二凸塊231係可作為該第二覆 晶晶片230對外連接之電極。該些第二凸塊23丨係接合 至該些第二凸塊接點213，並在該第二覆晶晶片230與 該第一覆晶晶片220之間形成一第二覆晶間隙S2。該第 二覆晶晶片230係如懸空般覆晶接合於該基板21〇之上 方’而無須透過中介基板電性傳輸。具體而言，該第二 覆晶晶片230與該第一覆晶晶片22〇為同向堆疊且該第 二覆晶晶片230係疊設在該第一覆晶晶片22〇之上方， 但不緊貼該第一覆晶晶片220以形成該第二覆晶間隙 S2 °請參閱第3 .圖所示，在本實施例中，該第二覆晶晶 11 13776.62 片230係可具有一大於該第一覆晶晶片22〇之尺寸，以 完全覆蓋該第一覆晶晶片220。該些第二凸塊231係形 成於該第二覆晶晶片230之邊緣，並在該第二覆晶晶片 23 0之中央區域係為非凸塊設置區，而該第一覆晶晶片 220之尺寸係對準在上述非凸塊設置區内。更具體地， 每一第二凸塊23 1係可包含一間隙維持塊232與一焊接 劑233。在一較佳實施例中，該些間隙維持塊232係可 為銅柱，用以維持該第二覆晶晶片230在覆晶接合時之 水平度，以使該第二覆晶晶片230與該第一覆晶晶片22〇 為平行。該些焊接劑233係可為銲料，以作為該第二覆 晶晶片230與該基板210電性連接之接合媒介。在第二 次覆晶接合之後，該些第二凸塊231與該些第二凸塊接 點213並不會熔化，因此可維持一定的覆晶高度並得 到較佳的可靠度，故可發揮間隙維持之作用並具有低成 本優勢。並且，藉由該些第二凸塊接點213為柱狀之設 • 計，能避免該些焊接劑233在該基板2 1〇之該上表面211 之擴散污染。請參閱第2圖所示’在本實施例中，該些 第二凸塊接點213係可高出或水平於該第一覆晶晶片 2 2 0之一皮面2 2 4，以限定該第二覆晶間隙s 2不小於該 些第二凸塊231之高度，有助於填膠。 請參閱第2圖所示，該多晶片覆晶封裝構造2〇〇可另 包含一底部填充膠240，該底部填充膠24〇係形成於該 基板210之該上表面211。該底部填充膠24〇係可同時 填滿該第一覆晶間隙s 1與該第二覆晶間隙s2，以節省 12 1377662 填膠次數。更可藉由該些第一凸塊221之該些間隙維持 塊222與該些焊接劑223，以控制使該第一覆晶間隙s i 與該第二覆晶間隙S2為平行形成於該基板21〇上。也就 是說，該第一覆晶間隙S 1之高度係為一致化而該第二覆 晶間隙S2之高度亦為一致化’該底部填充膠24〇將容易 地流佈於該第一覆晶間隙S 1與該第二覆晶間隙S2，以 密封該些第一凸塊221而不會形成氣泡。在本實施例 中，該第一覆晶間隙S 1與該第二覆晶間隙82可為大致 相等。在此所稱大致相等係表示間隙比值在不大於二也 不小於二分之一。該底部填充朦240係可密封該些第二 凸塊接點2 13 ’以達到封膠保護。具體而言，該底部填 充膠24〇更可密封該些第二凸塊23丨以及該第一覆晶晶 片 220 ° 因此’可藉由該基板210之該些不等高的第一與第二 凸塊接點212、213的形狀，能提供一懸空的覆晶接合 面’並使該第二覆晶晶片230覆晶接合於該基板210之 上方’並可在省略中介基板2 10之條件下達到多晶片覆 晶封裝之立體堆疊。更可藉由平行形成於該基板21〇上 之該第一覆晶間隙S1與該第二覆晶間隙s 2，有助於該 底部填充膠240之填入而不會產生氣泡，且僅需一次之 填膠步驟便可同時密封該些第二凸塊接點213、該些第 二凸塊23 1以及該第一覆晶晶片220，以達到易於填膠 與節省填膠次數之功效。以覆晶接合技術使該些第二凸 塊231接合至該些凸柱狀第二凸塊接點213，以電性連 13 13776.62 接該基板210與該第二覆晶晶片230，能取代習知多晶 片覆晶封裝構造之中介基板之設置以及打線接合之步 驟或可省略習知技術中在第一覆晶晶片之背面進行煩 雜之重分配線路製程，故能.減少電性傳輸媒介、減少空 間需求與提高構裝密度。在該第二覆晶晶片23〇接合於 該基板210時’該些第二凸塊231與該基板21〇之該上 表面211會形成有一高度差。當該些焊接劑23 3接合至 該些第二凸塊接點213’能避免該些焊接劑233在該基 板210之該上表面211之擴散污染。 以下進一步說明本發明不局限覆晶晶片的數量。依據 本發明之第二具體實施例，另一種多晶片覆晶封裝構造 舉例說明於第4圖之截面示意圖。該多晶片覆晶封裝構 造300所包含之主要元件係與第一具體實施例的基板 21〇、第一覆晶晶片220以及第二覆晶晶片230大致為相 同’故以第一具體實施例之相同元件符號標示之並部分 省略說明。第二具體實施例中可加入更多晶片進行覆晶 堆疊。該基板210係設有複數個第一凸塊接點212與複 數個第二凸塊接點213，其中該些第二凸塊接點213係 排列於該些第一凸塊接點212之周邊並且為凸柱狀。該 第一覆晶晶片220之複數個第一凸塊221係接合至該些 第一凸塊接點212，並在該第一覆晶晶片220與該基板 210之間形成一第一覆晶間隙S1。該第二覆晶晶片230 之複數個第二凸塊231係接合至該些第二凸塊接點 213’並在該第二覆晶晶片230與該第一覆晶晶片220 14 1^/76.62 •之間形成-第二覆晶間隙S2。 '閱第4圖所示，在本實施例中，該基板210之上 表面211夕 孓上係可更設有複數個第三凸塊接點316。苴 中該些第=几44〜 、 塊接點3 1 6係排列於該些第二凸塊接點 3之周邊並且為更高於該些第二凸塊接點213之凸柱 狀。該此笛- ~乐一凸塊接點316之材質係可相同於該些第二 ^塊接點213之材質。該些第三凸塊接點3 16係可高出 籲 或X平於該第二覆晶晶片23〇之背面。在本實施例中， 該多晶片覆晶封裝構造300可另包含一第三覆晶晶片 36〇，係具有複數個第三凸塊361。該第三覆晶晶片36〇 係可具有一大於該第二覆晶晶片23〇之尺寸，以完全覆 蓋該第二覆晶晶片230。該些第三凸塊361係接合至該 些第三凸塊接點316，並在該第三覆晶晶片36〇與該第 二覆晶晶片230之間形成一第三覆晶間隙S3。更具體結 構中’該些第三凸塊361可包含複數個間隙維持塊362 鲁與複數個焊接劑363。具體而言，該第三覆晶晶片360 之覆晶接合方式係可相同於該第二覆晶晶片230之覆晶 接合方式，以該些焊接劑3 63作為與該基板210電性連 接之媒介。該多晶片覆晶封裝構造300可另包含一底部 填充膠240，其係同時填滿該第一覆晶間隙S 1、該第二 覆晶間隙S2以及該第三覆晶間隙S3。該底部填充膠240 更可密封該第一覆晶晶片220、該第二覆晶晶片230、該 些第二凸塊接點213以及該些第三凸塊接點316。 請參閱第4圖所示，在本實施.例中，該多晶片覆晶封 15 1377662 裝構造300可另包含一第四覆晶晶片370，係覆晶接合 於該基板210之下表面214 ^該第四覆晶晶片370係具 有複數個第四凸塊371，其中該些第四凸塊371之材質 係可與該些第一凸塊221之材質相同或不相同。在本實 施例中’該基板210更具有複數個第四凸塊接點317, 係形成於該基板210之下表面214。該些第四凸塊371 係接合至該些第四凸塊接點3丨7，以使該第四覆晶晶片 3 70與該基板210電性互連。在本實施例中，該多晶片 覆晶封裝構造300可另包含一底部填充膠341，係局部 形成於該基板210之該下表面214，以密封該些第四凸 塊 371 〇 由上述可知’該多晶片覆晶封裝構造300可堆疊更多 的覆晶晶片以增加電訊功能或擴大記憶體容量，並且無 論堆疊數量之多寡，該些覆晶晶片220、230、360在覆 晶堆疊時皆可得到該些凸塊接點212、213、3 16與該些 凸塊221、231 ' 361之良好支撐，並可使該基板21〇上 位於不同高度的多個覆晶間隙S 1、s 2、S 3為平行形成， 以易於控制其覆晶堆疊之水平度。 依據本發明之第三具體實施例，另一種多晶片覆晶封 裝構造舉例說明於第5圖之截面示意圖。該多晶片覆晶 封裝構造4〇〇所包含之主要元件係與第一具體實施例的 基板210、第一覆晶晶片220以及第二覆晶晶片230大 致為相同’故以第一具體實施例之相同元件符號標示之 並硭刀省略說明。此外’第三具體實施例之基本架構主 16 13776.62 要與第二具體實施例相同，並可提高多個覆晶晶片之間 的固著強度。該基板210係設有複數個第一凸塊接點212 與複數個第二凸塊接點213,其中該些第二凸塊接點213 係排列於該些第厂凸塊接點212之周邊並且為凸柱狀。 該第一覆晶晶片220係覆晶接合至該基板210，並形成 有第一覆晶間隙S 1。在本實施例中，該多晶片覆晶封裝 構造400可另包含有一第一中央接合劑481，其係不填 滿地形成於該第一覆晶間隙S 1内。該第二覆晶晶片230 係覆晶接合至該基板2 1 0，並形成有第二覆晶間隙s 2。 在本實施例中’該多晶片覆晶封裝構造400可另包含有 一第二中央接合劑482，其係不填滿地形成於該第二覆 晶間隙S 2内。 請參閱第5圖所示’該多晶片覆晶封裝構造400係可 另包含一第三覆晶晶片460與一第四覆晶晶片470。該 第三覆晶晶片460之複數個第三凸塊46 1係接合至該基 板210之複數個第三凸塊接點416，並形成有第三覆晶 間隙S3。在本實施例中，該多晶片覆晶封裝構造4〇〇可 另包含一第三中央接合劑4 83，其係不填滿地形成於該 第三覆晶間隙S3内。該第四覆晶晶片470係覆晶接合於 該基板210之下表面214。在該基板210與該第四覆晶 晶片470之間係可形成有一第四中央接合劑484。 請參閱第5圖所示’在本實施例中，該多晶片覆晶封 裝構造400可另包含一模封膠體440，係形成於該基板 2 1 0之該上表面2 11並填滿該第一覆晶間隙S 1、該第二 17 1377662 覆晶間隙S2以及該第二覆晶間隙S3，以密封該第一覆 晶晶片220、該第二覆晶晶片230、該第三覆晶晶片460、 該第一中央接合劑481、該第—中央接合劑482以及該 第二中央接合劑483。該多晶片覆晶封裂構造4〇〇更可 包3 —底部填充膠441’以密封該些第四凸塊471與該 第四中央接合劑484。 由上述可知’該多晶片覆晶封裳構造4〇〇可以使立體 堆疊之該些覆晶晶片220、230、460在接合後即得到良 好固著強度並能以預先填充的方式降低封膠填滿該些覆 晶間隙S 1、s 2、S 3的困難度’有助於提昇封裝品質。 特別可以達成以該模封膠體440填滿該些覆晶間隙δ i、 S2、S3並且不會造成該些第一凸塊接點212與該些第二 凸塊接點213斷裂之功效。 本發明進一步說明前述多晶片覆晶封裝構造4〇〇之 形成方法’例舉說明於第6A至6G圖 < 方法中元件截面 示意圖。 首先，請參閱第6A圖所示，提供該基板21〇，該基 板210之上表面211係設有該些第一凸塊接點212、該 些第二凸塊接點213以及該些第三凸塊接點416。該些 第二凸塊接點213與該些第三凸塊接點416係為凸柱 狀，其中該些第三凸塊接點416係高於該些第二凸塊接 點213。在本實施例中，該些第二凸塊接點213與該些 第三凸塊接點416係可以電鍍方式形成，藉以精確控制 該些第二凸塊接點213與該些第三凸塊接點416之高 18 度。該基板210之下表面214可更設有該些第四凸塊接 點417與該些外接墊215»之後，請參閱第6B圖所示， 可利用一喷嘴10將助焊劑11喷灑於該基板21〇之該上 表面211，並形成於該些第一凸塊接點212'該些第二凸 塊接點213以及該些第三凸塊接點416上，達到表面清 潔，以增進焊接強度。 接著，請參閱第6C圖所示，可利用點膠技術藉由一 點膠針頭20將該第一中央接合劑481點塗在該基板21〇 上之中心區域，該第一中央接合劑481係為一熱固性液 態膠。在形成該第一中央接合劑481之後，請參閱第6D 圖所示，覆晶接合該第一覆晶晶片220。可藉由一接合 頭30將該第一覆晶晶片22〇設置於該基板21〇，並使該 些第一凸塊221對準接合至對應之該些第一凸塊接點 2 1 2。在本實施例中，該些第一凸塊22丨係可利用該些焊 接劑223作為電性連接之媒介，使該些第一凸塊221焊 接至該些第一凸塊接點212，以達到電性互連。該第一 中央接合劑481係黏接該第一覆晶晶片22〇與該基板 210之中央部位，以提供該第一覆晶晶片22〇與該基板 2 1 0之間的良好固著強度。 接著’請參閱第6E圖所示，點塗該第二中央接合劑 4 82於該第一覆晶晶片22〇之晶背之中心區域’並覆晶 接合該第二覆晶晶片23〇至該基板2丨〇，以使該第二中 央接合劑482位於該第二覆晶晶片23〇與該第一覆晶晶 片220之間。該第二覆晶晶片230係懸空設置於該基板 19 1377662 210之上方，而該第二覆晶晶片230之該些第二凸塊231 係接合至該些第二凸塊接點213。在本實施例中，該些 第二凸塊231接合該些第二凸塊接點213之方式係相同 於該些第一凸塊221接合該些第一凸塊接點212之方 式。該第二中央接合劑482黏著該第二覆晶晶片230與 該第一覆晶晶片220之中央部位。 接著’請參閱第6F圖所示，點塗該第三中央接合劑 4 8 3於該第二覆晶晶片2 3 0之中心區域，並覆晶接合該 第三覆晶晶片460 ’以使該第三中央接合劑483黏著該 第三覆晶晶月4 6 0與該第二覆晶晶片2 3 0之中央部位。 該第三覆晶晶片460係懸空設置於該基板210之上方， 而該第三覆晶晶片460之該些第三凸塊461係接合至該 些第三凸塊接點416。 接著’請參閱第6G圖所示，點塗該第四中央接合劑 484於該基板210之該下表面214之中心區域，並覆晶 接合該第四覆晶晶片470，以使該第四中央接合劑484 位於該第四覆晶晶片470與該基板2 1 0之間。該第四覆 晶晶片470之該些第四凸塊471係接合至該些第四凸塊 接點4 1 7。 接著，請參閱第6H圖所示，利用壓模封裝（transfer molding)技術’形成該模封膠體440於該基板210之該 上表面211 ’以密封該些覆晶晶片22〇、23〇、46〇。請參 閱第5圖所示，該模封膠體440係更填入該些覆晶間隙 SI、S2、S3，以密封該些中央接合劑481、482、483。 20 1377662 【主要元件符號說明】Fourth, the specific combination of the unequal bump contacts of the substrate and the flip chip can be used as one of the technical means, and the bump of the flip chip is further included with the gap maintaining block, so that the substrate can be at different heights. A plurality of flip-chip gaps are formed in parallel. 5. The design of the columnar bump contact of the substrate and the specific combination of the flip chip stack can be used as one of the technical means, and the central bonding agent is formed in the flip chip gap to make the solid layer overlay. After the bonding, the wafer has good fixing strength and can reduce the difficulty of filling the gap of the sealing material in the pre-filling manner, which helps to improve the packaging quality, and in particular, can fill the crystal with the molding compound. The gap does not cause the effect of the column bump contact fracture. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. Only the components and combinations related to this case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other (4) dimensions or have been exaggerated or simplified. Provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a multi-wafer flip chip package configuration is illustrated in cross-sectional view in FIG. 2 and a top perspective view in FIG. The multi-chip flip chip package structure 2 includes a substrate 21A, a first flip chip 220, and a second flip chip 23A. The substrate 210 has a recording surface 211 on the upper 911. The upper surface 211 serves as a wafer setting surface for flip-chip bonding the first flip chip 22 and the second flip chip 230. The upper surface 211 is provided with a plurality of first bump contacts 212 and a plurality of second bump contacts 213. The first bump contacts 212 are electrically connected to the first flip chip 220, and the second bump contacts 213 are electrically connected to the second flip chip 23. In this embodiment, the first bump contacts 212 are in the form of a flat pad or a dimple shape under the influence of the thickness of the solder resist layer, or a slightly convex shape under the influence of the thickness of the surface electric clock layer. And the first bump contacts 2 12 are arable and arranged in a peripheral arrangement such as a square shape. & π _ ^ ^ In the different embodiments 9 13776.62, the first bump contacts 212 can be arranged in a matrix arrangement. The first bump contacts 213 are arranged on the periphery of the first bump contacts 212 and have a convex shape to provide a floating flip-chip bonding surface. That is, the first bump contacts 212 and the second bump contacts 213 respectively provide flip-chip bonding surfaces of different heights, so that the second flip chip 230 can be over-floating. A predetermined height on the substrate 210 is formed, and a space for accommodating the first cover wafer 220 and the plurality of flip-chip gaps is formed under the second flip chip 230. The height of the studs of the second bump contacts 2 1 3 can be controlled by an electroplating method. Preferably, the second bump contacts 213 can include a plurality of copper pillars for supporting and defining the set height of the second flip chip 230. Referring to Figure 2, the substrate 21 can have a lower surface 214 which is provided with a plurality of external pads 215 and is electrically conductive in a suitable wiring pattern. The outer pads 2 15 can be circular pads. In this embodiment, the multi-chip flip-chip package structure 200 may further include a plurality of external terminals 250' bonded to the outer pads 2 15 ' of the lower surface 214 of the substrate 210 for external bonding. The external terminals 25 can be solder balls arranged in a plurality of rows or in a matrix. Referring to FIG. 2, the first flip chip 22 has a plurality of first bumps 221. Generally, the first flip chip 22 is provided with integrated circuit components, such as a controller, a microprocessor, a logic component, a memory, etc., or a combination thereof, and the first bumps 221 are used as the first A flip-chip sa piece 220 is externally connected to the electrode. The first bumps 221 are coupled to the first bump contacts 212, and a first flip-chip gap s is formed between the first flip chip 22 〇 10 1377662 and the substrate 210. The flip chip bonding technique suitable for providing the first flip chip 220 includes thermal ultrasonic heating bonding, reflow bonding, and thermocompression bonding. Referring to FIG. 3, the first bumps 221 may be formed around the first flip chip 22A. In different embodiments, the positions of the first six blocks 221 are arranged in a matrix. In the present embodiment, as shown in the enlarged view of Fig. 2, each of the first bumps 221 may include a gap maintaining block 222 and a solder 223. The material of the gap maintaining blocks 2 2 2 may be a high temperature resistant metal such as copper formed by electroplating. The first flip chip 22 can maintain the level and height of the first flip chip 22 when the flip chip is bonded by the gap maintaining block 222 and can be used to avoid touching the second overlay located above. Crystal wafer 23 0. The soldering agents 223 can be solder and can be soldered to the first bump contacts 212 of the substrate 21 . Referring to Fig. 2, the second flip chip 23 has a plurality of second bumps 231. The second bumps 231 are used as electrodes for external connection of the second flip chip 230. The second bumps 23 are bonded to the second bump contacts 213, and a second flip-chip gap S2 is formed between the second flip chip 230 and the first flip chip 220. The second flip chip 230 is flip-chip bonded to the upper surface of the substrate 21 without being electrically transmitted through the interposer. Specifically, the second flip chip 230 and the first flip chip 22 are stacked in the same direction, and the second flip chip 230 is stacked on the first flip chip 22, but not tight. The first flip chip 220 is attached to form the second flip chip S2 °. Referring to FIG. 3, in the embodiment, the second flip chip 11 13776.62 sheet 230 may have a larger than the first A flip chip 22 is sized to completely cover the first flip chip 220. The second bumps 231 are formed on the edge of the second flip chip 230, and are non-bumped regions in the central region of the second flip chip 230, and the first flip chip 220 The dimensions are aligned in the non-bump setting area described above. More specifically, each of the second bumps 23 1 may include a gap maintaining block 232 and a solder 233. In a preferred embodiment, the gap maintaining blocks 232 can be copper pillars for maintaining the level of the second flip chip 230 during flip chip bonding, so that the second flip chip 230 and the The first flip chip 22 is parallel. The soldering agent 233 may be solder as a bonding medium for electrically connecting the second flip chip 230 to the substrate 210. After the second flip chip bonding, the second bumps 231 and the second bump contacts 213 do not melt, so that a certain flip chip height can be maintained and better reliability is obtained, so that the second bumps can be used. The role of gap maintenance and low cost advantages. Moreover, by the second bump contacts 213 being columnar, diffusion contamination of the solder 233 on the upper surface 211 of the substrate 2 1 can be avoided. Referring to FIG. 2, in the embodiment, the second bump contacts 213 may be higher or horizontal to one of the first flip chip 2 2 0 2 4 to define the second bump contact 213. The second flip-chip gap s 2 is not less than the height of the second bumps 231 to facilitate the filling. Referring to FIG. 2, the multi-wafer flip chip package structure 2 can further comprise an underfill paste 240 formed on the upper surface 211 of the substrate 210. The underfill 24 can simultaneously fill the first flip-chip gap s 1 and the second flip-chip gap s2 to save 12 1377662 fill times. The spacers 222 and the soldering agents 223 of the first bumps 221 are controlled to form the first flip-chip gaps si and the second flip-chip gaps S2 in parallel with the substrate 21 . 〇上. That is, the height of the first flip-chip gap S 1 is uniform and the height of the second flip-chip gap S2 is also uniform. The underfill 24 〇 will easily flow in the first flip-chip gap. S 1 and the second flip-chip gap S2 to seal the first bumps 221 without forming bubbles. In this embodiment, the first flip-chip gap S 1 and the second flip-chip gap 82 may be substantially equal. As used herein, approximately equal means that the gap ratio is not more than two and not less than one-half. The underfill crucible 240 seals the second bump contacts 2 13 ' to achieve encapsulation protection. Specifically, the underfill layer 24 〇 seals the second bumps 23 丨 and the first flip chip 220 ° so that the first and second portions of the substrate 210 can be unequal The shape of the bump contacts 212, 213 can provide a floating flip-chip bonding surface 'and enable the second flip chip 230 to be bonded over the substrate 210' and can be omitted under the condition that the interposer substrate 20 is omitted. A three-dimensional stack of multi-wafer flip chip packages is achieved. The first flip-chip gap S1 and the second flip-chip gap s 2 formed on the substrate 21 are parallel to facilitate the filling of the underfill 240 without generating bubbles, and only need to be The second bumping joint 213, the second bumps 23 1 and the first flip chip 220 can be sealed at the same time to achieve the effect of easy filling and saving the number of times of filling. The second bumps 231 are bonded to the bump-shaped second bump contacts 213 by a flip chip bonding technique, and the substrate 210 and the second flip chip 230 are electrically connected to 13 13776.62. The arrangement of the interposer substrate and the wire bonding step of the multi-chip flip chip package structure may omit the complicated redistribution line process on the back side of the first flip chip, so that the electric transmission medium can be reduced and the space can be reduced. Demand and increase the density of the assembly. When the second flip chip 23 is bonded to the substrate 210, the second bumps 231 and the upper surface 211 of the substrate 21 are formed with a height difference. When the soldering agents 23 3 are bonded to the second bump contacts 213', diffusion contamination of the soldering agents 233 on the upper surface 211 of the substrate 210 can be avoided. The following further illustrates that the invention is not limited to the number of flip chip wafers. In accordance with a second embodiment of the present invention, another multi-wafer flip chip package configuration is illustrated in cross-section in FIG. The main components included in the multi-chip flip chip package structure 300 are substantially the same as those of the substrate 21 〇, the first flip chip 220, and the second flip chip 230 of the first embodiment, so that the first embodiment is The same component symbols are marked and partially omitted. More wafers can be added to the flip-chip stack in the second embodiment. The substrate 210 is provided with a plurality of first bump contacts 212 and a plurality of second bump contacts 213, wherein the second bump contacts 213 are arranged around the first bump contacts 212. And it is convex column shape. A plurality of first bumps 221 of the first flip chip 220 are bonded to the first bump contacts 212, and a first flip chip gap is formed between the first flip chip 220 and the substrate 210. S1. The plurality of second bumps 231 of the second flip chip 230 are bonded to the second bump contacts 213 ′ and the second flip chip 230 and the first flip chip 220 14 1^/76.62 • A second flip-chip gap S2 is formed between. As shown in Fig. 4, in the present embodiment, a plurality of third bump contacts 316 may be further disposed on the upper surface 211 of the substrate 210. In the middle, the number of the first bumps and the third bumps are arranged in the periphery of the second bump contacts 3 and are higher than the convex pillars of the second bump contacts 213. The material of the flute-bump bump 316 can be the same as the material of the second bump contacts 213. The third bump contacts 3 16 can be raised or X flat on the back side of the second flip chip 23 . In this embodiment, the multi-wafer flip-chip package structure 300 may further include a third flip chip 36 〇 having a plurality of third bumps 361. The third flip chip 36 can have a size larger than that of the second flip chip 23 to completely cover the second flip chip 230. The third bumps 361 are bonded to the third bump contacts 316, and a third flip-chip gap S3 is formed between the third flip chip 36 and the second flip chip 230. In a more specific structure, the third bumps 361 may include a plurality of gap maintaining blocks 362 and a plurality of soldering agents 363. Specifically, the flip chip bonding manner of the third flip chip 360 can be the same as the flip chip bonding mode of the second flip chip 230, and the solder 3 63 is used as a medium for electrically connecting the substrate 210. . The multi-wafer flip-chip package structure 300 may further include a bottom filling paste 240 that simultaneously fills the first flip-chip gap S1, the second flip-chip gap S2, and the third flip-chip gap S3. The underfill 240 further seals the first flip chip 220, the second flip chip 230, the second bump contacts 213, and the third bump contacts 316. Referring to FIG. 4, in the present embodiment, the multi-wafer flip-chip 15 1377662 package structure 300 may further include a fourth flip chip 370 bonded to the lower surface 214 of the substrate 210. The fourth flip chip 370 has a plurality of fourth bumps 371. The materials of the fourth bumps 371 may be the same as or different from the materials of the first bumps 221 . In this embodiment, the substrate 210 further has a plurality of fourth bump contacts 317 formed on the lower surface 214 of the substrate 210. The fourth bumps 371 are bonded to the fourth bump contacts 3丨7 to electrically interconnect the fourth flip chip 703 with the substrate 210. In this embodiment, the multi-wafer flip-chip package structure 300 may further include an underfill 341 formed partially on the lower surface 214 of the substrate 210 to seal the fourth bumps 371. The multi-chip flip chip package structure 300 can stack more flip chip to increase the telecommunication function or expand the memory capacity, and the flip chip 220, 230, 360 can be stacked on the flip chip regardless of the number of stacks. The bump contacts 212, 213, and 3 16 and the bumps 221 and 231 361 are well supported, and the substrate 21 can be stacked with a plurality of flip-chip gaps S 1 and s 2 at different heights. S 3 is formed in parallel to easily control the level of its flip chip stack. In accordance with a third embodiment of the present invention, another multi-wafer flip-chip package configuration is illustrated in cross-section of Figure 5. The main component included in the multi-chip flip chip package structure 4 is substantially the same as the substrate 210, the first flip chip 220, and the second flip chip 230 of the first embodiment. The same component symbols are marked and the description is omitted. Further, the basic architecture main 16 13776.62 of the third embodiment is the same as the second embodiment, and the fixing strength between a plurality of flip chip wafers can be improved. The substrate 210 is provided with a plurality of first bump contacts 212 and a plurality of second bump contacts 213, wherein the second bump contacts 213 are arranged around the first bump contacts 212. And it is convex column shape. The first flip chip 220 is flip-chip bonded to the substrate 210, and a first flip-chip gap S 1 is formed. In the present embodiment, the multi-wafer flip-chip package structure 400 may further include a first central bonding agent 481 formed in the first flip-chip gap S1 without filling. The second flip chip 230 is die bonded to the substrate 210 and formed with a second flip gap s 2 . In the present embodiment, the multi-wafer flip-chip package structure 400 may further include a second central bonding agent 482 formed in the second cladding gap S 2 without filling. Referring to FIG. 5, the multi-chip flip chip package structure 400 may further include a third flip chip 460 and a fourth flip chip 470. The plurality of third bumps 46 1 of the third flip chip 460 are bonded to the plurality of third bump contacts 416 of the substrate 210 and formed with a third flip chip gap S3. In this embodiment, the multi-wafer flip-chip package structure 4b further includes a third central bonding agent 483 which is formed in the third flip-chip gap S3 without filling. The fourth flip chip 470 is flip-chip bonded to the lower surface 214 of the substrate 210. A fourth central bonding agent 484 may be formed between the substrate 210 and the fourth flip chip 470. Referring to FIG. 5, in the embodiment, the multi-chip flip-chip package structure 400 may further include a molding compound 440 formed on the upper surface 2 11 of the substrate 210 and fill the first a flip-chip gap S 1 , the second 17 1377662 flip-chip gap S2 and the second flip-chip gap S3 to seal the first flip chip 220, the second flip chip 230, and the third flip chip 460 The first central bonding agent 481, the first central bonding agent 482, and the second central bonding agent 483. The multi-wafer flip-chip sealing structure 4 is further provided with an underfill 441' to seal the fourth bumps 471 and the fourth central bonding agent 484. It can be seen from the above that the multi-wafer flip-chip structure can make the flip-chips 220, 230, 460 of the three-dimensional stack obtain good fixing strength after bonding and can reduce the seal filling in a pre-filling manner. The difficulty of filling the gaps S 1 , s 2 , and S 3 ' helps to improve the package quality. In particular, it is achieved that the laminating gaps δ i, S2, and S3 are filled with the molding compound 440 and the first bump contacts 212 and the second bump contacts 213 are not broken. The present invention further illustrates a method of forming the above-described multi-wafer flip-chip package structure ’''''''''''''' First, as shown in FIG. 6A, the substrate 21 is provided. The upper surface 211 of the substrate 210 is provided with the first bump contacts 212, the second bump contacts 213, and the third portions. Bump contact 416. The second bump contacts 213 and the third bump contacts 416 are in a convex shape, and the third bump contacts 416 are higher than the second bump contacts 213. In this embodiment, the second bump contacts 213 and the third bump contacts 416 can be formed by electroplating, so as to precisely control the second bump contacts 213 and the third bumps. Contact 416 is 18 degrees high. After the lower surface 214 of the substrate 210 is further provided with the fourth bump contacts 417 and the external pads 215», as shown in FIG. 6B, the flux 11 can be sprayed on the nozzles 10 The upper surface 211 of the substrate 21 is formed on the second bump contacts 212 213 and the third bump contacts 416 to achieve surface cleaning to improve soldering. strength. Next, referring to FIG. 6C, the first central bonding agent 481 can be spot-applied to the central region of the substrate 21 by a dispensing technique, the first central bonding agent 481. It is a thermosetting liquid glue. After the first central bonding agent 481 is formed, as shown in FIG. 6D, the first flip chip 220 is flip-chip bonded. The first flip chip 22 is disposed on the substrate 21 by a bonding head 30, and the first bumps 221 are aligned to the corresponding first bump contacts 2 1 2 . In this embodiment, the first bumps 22 can be soldered to the first bump contacts 212 by using the solder 223 as a medium for electrical connection. Achieve electrical interconnection. The first central bonding agent 481 is bonded to the central portion of the first flip chip 22 and the substrate 210 to provide good adhesion strength between the first flip chip 22 and the substrate 210. Then, as shown in FIG. 6E, the second central bonding agent 4 82 is applied to the central region of the crystal back of the first flip chip 22 and the second flip chip 23 is flip-chip bonded thereto. The substrate 2 is so that the second central bonding agent 482 is located between the second flip chip 23 〇 and the first flip chip 220. The second flip chip 230 is suspended above the substrate 19 1377662 210, and the second bumps 231 of the second flip chip 230 are bonded to the second bump contacts 213. In this embodiment, the second bumps 231 are joined to the second bump contacts 213 in the same manner as the first bumps 221 are joined to the first bump contacts 212. The second central bonding agent 482 adheres to the central portion of the second flip chip 230 and the first flip chip 220. Then, as shown in FIG. 6F, the third central bonding agent 481 is applied to the central region of the second flip chip 430, and the third flip chip 460' is flip-chip bonded to make the The third central bonding agent 483 adheres to the central portion of the third flip chip 460 and the second flip chip 2300. The third flip chip 460 is suspended above the substrate 210, and the third bumps 461 of the third flip chip 460 are bonded to the third bump contacts 416. Then, referring to FIG. 6G, the fourth central bonding agent 484 is spot-coated on a central region of the lower surface 214 of the substrate 210, and the fourth flip chip 470 is flip-chip bonded to make the fourth central portion. A bonding agent 484 is located between the fourth flip chip 470 and the substrate 210. The fourth bumps 471 of the fourth flip chip 470 are bonded to the fourth bump contacts 4 17 . Next, referring to FIG. 6H, the molding compound 440 is formed on the upper surface 211' of the substrate 210 by a transfer molding technique to seal the flip chip 22, 23, 46. Hey. Referring to Figure 5, the molding compound 440 is further filled with the flip-chip gaps SI, S2, and S3 to seal the central bonding agents 481, 482, and 483. 20 1377662 [Main component symbol description]
S1 第 — 覆 晶間隙 S2 第 二 覆 晶間隙 S3 第 三 覆 晶間隙 10 喷 嘴 11 助 焊 劑 20 點 膠 針 頭 30 接 合頭 100 多 晶 片 覆晶封 裝構造 110 基 板 111 上 表 面 112 第 一 凸 塊接點 113 第 一 打 線接指 114 下 表 面 115 外 接 墊 120 第 一 覆 晶晶片 121 第 一 凸 塊 130 第 二 覆 晶晶片 131 第 二 凸 塊 141 第 一 底 部填充 膠 142 第 二 底 部填充 膠 150 外 接 端 子 160 中 介 基 板 161 第 二 凸塊接點 162 第 二 打 線接指 163 鲜 線 170 模 封 膠 體 200 多 晶 片 覆晶封 裝楨 :造 210 基板 211 上 表 面 212 第 一 凸 塊接點 213 第 二 凸 塊接點 214 下 表 面 215 外 接 塾 220 第 一 覆 晶晶片 221 第 一 凸 塊 22 1377662S1 - flip chip gap S2 second flip chip gap S3 third flip chip gap 10 nozzle 11 flux 20 dispensing needle 30 bonding head 100 multi-chip flip chip package structure 110 substrate 111 upper surface 112 first bump contact 113 First wire bonding finger 114 lower surface 115 external pad 120 first flip chip 121 first bump 130 second flip chip 131 second bump 141 first underfill 142 second underfill 150 external terminal 160 intermediary Substrate 161 second bump contact 162 second wire bonding finger 163 fresh wire 170 molding compound 200 multi-chip flip chip package: 210 substrate 211 upper surface 212 first bump contact 213 second bump contact 214 Lower surface 215 external 塾 220 first flip chip 221 first bump 22 1377662
222間隙維持塊 223焊接劑 230第二覆晶晶片 232間隙維持塊 233烊接劑 240底部填充膠[250.外接端子 3 00多晶片覆晶封裝構造 316 第三凸塊接點 3 1 7第四凸塊接點 341底部填充膠 360第二覆晶晶片 362間隙維持塊 363焊接劑 370第四覆晶晶片 400多晶片覆晶封裝構造 4 1 6 第三凸塊接點 417 第四凸塊接點 440模封膠體 441底部填充膠 460第三覆晶晶片 470第四覆晶晶片 481第一中央接合劑 482第二中央接合劑 483第三中央接合劑 484第四中央接合劑 224背面 231第二凸塊 361第三凸塊 371第四凸塊 461第三凸塊 471第四凸塊 23222 gap maintaining block 223 solder 230 second flip chip 232 gap maintaining block 233 splicing agent 240 underfill [250. external terminal 3 00 multi-chip flip chip package structure 316 third bump contact 3 1 7 fourth Bump contact 341 underfill 360 second flip chip 362 gap sustain block 363 solder 370 fourth flip chip 400 multi wafer flip chip package structure 4 1 6 third bump contact 417 fourth bump contact 440 molding compound 441 underfill 460 third flip chip 470 fourth flip chip 481 first central bonding agent 482 second central bonding agent 483 third central bonding agent 484 fourth central bonding agent 224 back 231 second convex Block 361 third bump 371 fourth bump 461 third bump 471 fourth bump 23