TWI375310B - Semiconductor chip having bumps on chip backside, its manufacturing method and its applications - Google Patents

Description

1-375310 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor wafer structure in which a bump is on a crystal back, a method of manufacturing the same, and an application thereof. 】

According to the electrical connection method of the semiconductor crystal X to the line carrier (or printed circuit board), there are two types of wire bonding and fliP chip bonding. Widely used in semiconductor construction, and each has its own place, but each has its own shortcomings and limitations. Wire bonding is performed by placing the active side of the wafer face up (away from the line carrier) on the line carrier' and then by bending a thin metal wire (such as gold wire, copper wire or alloy wire thereof) onto the wafer. The solder pads are connected to the connection pads of the conductive lines on the line carrier board, so that the electrical signals of the chips are transmitted to the line carrier board and then transmitted to the outside. However, this type of bonding has a limitation on the number of pads, and the & method achieves a high 1/turn requirement, and cannot be applied to the semiconductor matrix of the face matrix arrangement (ai*ea a"ay I/(). At the same time, due to the connection of the thin metal wire and the right and +u E + 疋 and a long connection length, it will be detrimental to the high-frequency signal transmission. The flip-chip bonding is pre-slide on the The active surface of the wafer is flipped (toward the line to the line carrier. However, the type setting of the flip chip bonding usually has the metal bump carrier board attached to the active surface) creates reliability problems due to the thermal expansion coefficient between the wafer and the line carrier. (CTE, 13^5310 coefficient of thermal expansion) After the thermal cycling, the joints fail due to the expansion of the wafer and the line carrier.

Assembly and other processes, relatively large equipment investment, high cost bumps are mainly gold bumps and tin-lead bumps, in the manufacturing method and connection _ are not the same, but all of the metal material 'in the long-term stress caused The problem of metal fatigue and consequent bump rupture is inevitable. China Invention Patent No. 1293499 "Stereotype #, facing structure and its manufacturing method" reveals a semiconductor with bumps on the back.

It is possible to carry out multi-wafer stacking by using the 巢 主 酉 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The wafer is provided with through holes, and the walls of the holes are sequentially formed with an insulating layer and a conductive layer, and the holes are filled with solder, and the fresh materials are more electrically connected to the wafer pads. The back side of the wafer is removed to expose the composite metal in the hole to form a metal bump that penetrates the wafer and protrudes from the crystal back. Since the semiconductor material of the wafer and the solder of the metal bump do not match in thermal expansion coefficient, the volume expansion of the metal bump is much larger than the expansion and expansion of the wafer hole at a high temperature, resulting in thermal stress of extrusion in the hole, once caused Cracks in the insulating layer may have a risk of leakage current. In particular, the metal bumps penetrate the wafer and have a larger volume than the conventional metal bumps that only protrude from the wafer. The problem of thermal stress between the wafer and the bumps becomes More strict

6 1375310 SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a semiconductor wafer structure in which a bump is formed on a crystal back, which can achieve zero stress between the wafer and the bump and prevent external stress from directly acting on the active surface of the wafer. It has the effect of short electrical conduction path and thinning of the wafer. A second object of the present invention is to provide a method for fabricating a semiconductor wafer structure in which a bump is formed on a crystal back. The formation of bumps integrated into a wafer process has the effect of saving the amount of metal of the bumps and simplifying the bump process. Another object of the present invention is to provide an application of a bump in a semiconductor wafer structure of a crystal back, which can be applied to high-density multi-wafer stacking, preventing punching and achieving the effect of thinning a stacked product. The object of the present invention and solving the technical problems thereof are achieved by using a non-technical solution. According to the present invention, a bump is formed on a semiconductor wafer of a crystal back, and the wafer structure mainly comprises a semiconductor substrate. The semiconductor substrate 'haves an active surface and a back surface characterized by integrally forming a plurality of bump bodies ' of the same material as the semiconductor substrate on the back surface and forming a conductive material on the bump bodies. The object of the present invention and the technical problem thereof can be further achieved by the following technical measures. In the foregoing semiconductor wafer structure of the bump in the crystal back, the plurality of solder pads may be further included on the active surface and electrically connected. Sexually connected to the conductive material. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the solder bumps may be aligned to the bump bodies. 7 1375310 In the foregoing semiconductor wafer structure of the bump in the crystal back, a plurality of conductive pillars may be further included, which penetrate the semiconductor substrate and the bump bodies to connect the pads and the conductive material. In the foregoing semiconductor wafer structure in which the bump is in the crystal back, a passivation layer may be further included on the active surface. In the foregoing semiconductor wafer construction in which the bumps are in the crystal back, the passivation layer may have a plurality of openings to expose the pads. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, a dielectric layer may be further included between the bump bodies and the conductive material. In the foregoing semiconductor wafer structure in which the bump is in the crystal back, the conductive material may be a metal layer. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the metal layer of the conductive material may be a gold layer, and a tin layer is formed on the pads. In the foregoing semiconductor wafer structure in which the bump is in the crystal back, an anisotropic conductive film may be further included on the active surface. In the foregoing semiconductor wafer construction in which the bumps are in the crystal back, the conductive material may be solder. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the height of the bump bodies may be approximately equal to or greater than the thickness of the semiconductor substrate. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the bump main systems may have a convex plane smaller than the pads. 8 1375310 In the foregoing semiconductor wafer structure of the bump in the crystal back, a plurality of 0-day soldering pads may be additionally provided, which are disposed between the convex plane of the bump main body and the conductive material. The locations correspond to the pads. The present invention also discloses a method of fabricating a semiconductor wafer structure suitable for use in the above-described bumps. The main steps include: first, providing a half-conductor substrate having an active surface and an unthinned back surface. Then, the unthinned back surface of the semiconductor substrate is selectively etched to form a thinned back surface for reducing the thickness of the semiconductor substrate, and at the same time, a plurality of bump bodies having the same material as the semiconductor substrate are integrally formed on the back surface. . Finally, a conductive material is formed on the bump bodies. The present invention further discloses a wafer stack assembly structure suitable for the aforementioned semiconductor wafer structure of a bump in a crystal back, which comprises a plurality of semiconductor wafer structures of the bumps on the crystal back and a line carrier, wherein the bumps The semiconductor wafer structures of BB 4 are stacked on each other and disposed on the line carrier. It can be seen from the above technical solutions that the bump of the present invention has the following advantages and effects in the semiconductor wafer structure of the crystal back, its manufacturing method and its application: 1. The main material of the bump is the same material as the semiconductor substrate and protrudes from The back side of the wafer can achieve zero stress between the wafer and the bump and prevent external stress from directly acting on the active surface of the wafer. The electrical conduction path is short and the wafer is thinned. 2. The wafer process is used to select the back side of the wafer. Etching to form the bump body of the semiconductor material, thereby making the bump-saving metal 9 1-375310 heavy, bump fabrication integrated into the wafer process to simplify the bump process. 2. The fresh pad of the wafer is aligned with the bump body of the semiconductor material and the conductive piece penetrates the semiconductor substrate and the bump body, so that the block can be applied to the high density multi-b曰 in the old semiconductor wafer structure. Stacking the sheets to prevent punching and achieve the effect of thinning the stacked products. [Embodiment]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A semiconductor wafer structure is illustrated in a cross-sectional view of Fig. 1. As shown in Fig. 1, the bump is in a semiconductor wafer structure of the crystal back. The semiconductor substrate 110 has a piano active surface 111 and a back surface 112. Generally, the semiconductor substrate 11 has an integrated circuit component on its active surface 1 丨1. 73⁄4 ^ _ 〇, such as a micro-controller, a microprocessor, a bridge, a logic circuit, a special application integrated body. The combination of electricity and (such as display drive Raymond Burgundy) or the like. Features of the invention 4

The back surface 112 t - < 8 # π , the body is formed with a plurality of bump main bodies 113 of the same material as the semiconductor base 110, and the g-degrees of the bump bodies 113 may be substantially the same as The semiconductor has a thickness of the dry conductor substrate 11 ,, and the convex portions of the main body 113 may have a circular u-square column shape or a polygonal column shape. j and, in the bump bodies 113

By using t as a conductive material 120, it is used as a J-integrated circuit external electrode. The titanium layer, the copper layer, the copper/...: 枓12° system may be nickel, a gold layer, the conductive tin, and the like. In this embodiment, the 冤 冤 枓 120 series is steel / nickel / gold shore

Degrees of g of the conductive material 120; E never exceeds the bump body ^

13 one-third of the high Z P375310 protruding from the back " 2 is limited to 'the thickness should be less than a quarter of the height of the bump main bodies 113, so that the bump main bodies 113 occupy the entire bump The volume is more than 60%, and the thermal expansion coefficient of the semiconductor material can achieve the effect of 霎_stress between the wafer and the bump. In addition, the bump main body 113 of the same material as the semiconductor substrate 110 protrudes from the back surface 112 of the semiconductor substrate 110 to prevent external stress from directly acting on the active surface m of the semiconductor substrate 110, and has a short conductive path and a wafer. The effect of thinning. Specifically, as shown in FIG. 1 , the bump in the crystal back semiconductor wafer structure 100 may further include a plurality of pads 130 disposed on the active surface 111 and electrically connected to the conductive material. 12〇. The 塾130 is made of any of a conductive metal material such as indium, copper, sinter alloy or copper alloy, which is the same surface electrode of the integrated circuit on the active surface U1. In this embodiment, the solder bumps 13 are aligned to the bump bodies 3 . In addition, as shown in FIG. 1 , the semiconductor wafer structure 100 of the bump in the crystal back may further include a plurality of conductive pillars 40 extending through the semiconductor substrate no and the bump bodies 113 to connect the semiconductor wafer structure 100. The pads 13 are bonded to the conductive material 120. The formation of the conductive pillars 140 can be accomplished using sand via fabrication techniques. The bump in the crystal back semiconductor wafer structure 1 may further include a passivation layer 150 formed on the active surface 111 to protect the integrated circuit on the active surface deal with. Specifically, as shown in FIG. 1 , the bump in the crystal back semiconductor wafer structure 100 may further include a dielectric layer 11 1375310 (dielectric iayer) 16 〇 ' formed in the bump body 113 and the Between the conductive materials 120. The dielectric layer 160 can be an oxide layer or an insulating deposition layer. The present invention further illustrates the method of fabricating the semiconductor wafer structure 100 of the bumps in the crystal back to demonstrate the efficacy of the present invention. Figures 2A through 2F are schematic cross-sectional views of the components in the process. First, as shown in Fig. 2A, a semiconductor substrate n is provided having an active surface 111 and an unthinned back surface U2. The semiconductor substrate 110 is integrally formed in a wafer, and the wafer process is performed by an integrated circuit. The active surface U1 of the semiconductor substrate 110 is provided with a plurality of pads 130. In this embodiment, the pads 3 are arranged on opposite sides or the periphery of the semiconductor substrate Π 0 to avoid overlapping with the integrated circuit formation region. However, the pads I 3 0 may also be arranged in a matrix. Specifically, the active surface 丨丨i can form a passivation layer 150, such as a nitrided or phosphoric bismuth glass (PSG), and the passivation layer 150 can have a plurality of openings 151 to reveal the Pad 1 30. Next, as shown in FIG. 2B, the unthinned back surface 112' of the semiconductor substrate is selectively etched to form a thinned back surface 11 2 which reduces the thickness of the semiconductor substrate II, and simultaneously on the back surface 11 2 A plurality of bump main bodies II3 of the same material as the semiconductor substrate 11 are integrally formed. Specifically, as shown in FIG. 2B, the selective etching technique of the wafer process is performed such that the thickness of the semiconductor substrate 11 is reduced to a proper thickness of about 30//m to 1 〇〇Mm, and simultaneously The 12 Ϊ 375310 silver is selected to form the bump main bodies 11 3 , so that the bump fabrication after the conventional process can be omitted and the metal usage of the bumps can be saved. The selective etching technique can be a chemical etching or a reactive ion etching after exposure and development. Further, the conventional grinding step can be omitted. In addition, as shown in FIG. 2B, since the solders can be aligned with the bump bodies 113, the bump bodies 1 can be substantially equal to the number of the pads 130, and no additional circuit layer (RDL) is required. Reduce production costs and processes. In addition, the main body 113 may have a size 113A smaller than the pads 130. When a plurality of semiconductor substrates are stacked, the 113A may be aligned to be bonded to the pad 130 on the other semiconductor substrate 11. Thereafter, as shown in Fig. 2C, at least one hole 11 3B may be formed in each of the bump bodies by a MEMS bulk machining process. The holes 11 3B may be formed at a central position of the bump main body 113 to prevent temperature rise or process, to form improper cracks or breaks, the holes 113B, the bump main bodies 113, and the semiconductor substrate 110 and the mats 13 0. However, without limitation, the holes 11 3B may extend through the pads 130. Thereafter, as shown in Fig. 2D, a dielectric layer 16 is formed between the block body 113 and the conductive material 120. In the present embodiment, the dielectric layer 160 is further formed on the convex plane 113A of the bump body 113 of the semiconductor substrate 110 and the hole is formed in the wafer. The number of 13 is used to reconfigure the bumps of the planar raised planes of the soldering electrical machining 1 13 to form a corresponding temperature cycling system through to the soldering or not in the convex examples, the 'face 1 1 2, hole 11 3 B, 13 1-375310 This completes the surface insulating treatment of the semiconductor substrate. The dielectric layer 160 is an insulating material such as hafnium oxide. The method of forming the dielectric layer 160 can be selected from the group consisting of a germanium oxidation process or a chemical vapor deposition process in a wafer process. Thereafter, as shown in Fig. 2E, a plurality of conductive pillars 140 are formed in the holes 11 3B. One of the conductive posts 〇4〇 is bonded to the solder pads 130. In this embodiment, copper or other conductive metal is filled into the hole 113B by means of plating or plugging, to form the conductive pillars 140, but wire bonding, needle insertion, etc. may also be utilized. The conductive pillars 14 are formed in a manner. • Finally, as shown in Figure 2F, form a conductive material! 20, on the convex plane 113A of the bump body 113, and electrically connecting the pads 130 to the conductive material 113 by the conductive pillars 140, so that the semiconductor substrate 110 has double-sided electrical conduction and through The characteristics of the bumps. In particular, the electrically conductive material can be a single layer or a composite metal layer. In the present embodiment, the outermost surface layer of the conductive material 120 may be a gold layer and, preferably, as shown in Fig. 1, a tin layer 170 may be formed on the plurality of ridges 13 。. When applied to a multi-wafer stack product, a plurality of bumps are stacked on each other in a semiconductor wafer structure 1 on the back of the wafer, and the conductive material 120 is alignably bonded to the pads 13 on the block body U3. Tin layer 170 to achieve gold tin eutectic. (As shown in Fig. 3) Therefore, the method of forming the bump main body 113 of the present invention is integrated into the wafer process, which can reduce the complexity of the process and increase the mass production speed. 14 1375310 FIG. 3 is a wafer stack assembly structure using a plurality of semiconductor wafer structures 100 stacked in a crystal back as described in the first embodiment. The wafer stack assembly structure further includes a line carrier 1 〇. The bumps are stacked on the back of the semiconductor wafer structure 100 and disposed on the line carrier 10. The line carrier 1 can be a printed circuit board, a circuit film, a ceramic substrate, a glass substrate or a lead frame, and the like. In the present embodiment, the line carrier 10 has a plurality of connection pads 11 and a plurality of external pads 12. In the embodiment, the connection pads 11 are disposed in the plurality of grooves 13 of the line carrier 10. The bump bodies 113 of the semiconductor wafer structure 100 of the underlying bumps are embedded in the recesses 13 of the line carrier 10, and the conductive material 120 on the bump bodies U3 are Bonding to the connection pads 11 can reduce the height of the overall multi-wafer stack and have the effect of thinning the package. Specifically, as shown in FIG. 3, the stack of the bumps between the wafer-backed semiconductor wafer structures 100 is electrically interconnected by the bonding of the conductive material 120 and the tin layer 17A. A solder pad 13 of a semiconductor wafer structure 100 is electrically connected to the conductive material 120 through the conductive pads 14 to bond pads 130 of another semiconductor wafer structure to provide a preferred vertical electrical conduction path. . Moreover, the bumps are formed on the back of the semiconductor wafer structure 100, and the external bumps are additionally provided, and the 3D stack of the multi-chips can be completed without forming wires. In addition, since the bump main body 113 and the semiconductor substrate 11 are made of the same material and formed into a body, when the temperature changes or the temperature is cyclically 15 1-375310, there is no problem that the expansion coefficient does not match. A composition of zero or lower stress between the wafer and the bump. In detail, as shown in FIG. 3, the wafer stack assembly structure may further comprise a glue body 2, which seals the bumps in the crystal back semiconductor wafer structure to provide appropriate Package protection to prevent electrical short circuits and dust pollution. In addition, the wafer stack assembly structure may further include a plurality of external quails 30. The external terminals 30 include solder balls disposed on the external pads 12. In various embodiments, the solder terminals may be replaced by solder paste, metal balls or metal pins to form the external terminals 3〇. In accordance with a second embodiment of the present invention, another type of bump in a crystal back semiconductor wafer configuration is illustrated in cross-section in FIG. As shown in Fig. 4, the semiconductor wafer structure 2 of the bump in the crystal back mainly comprises a semiconductor substrate 210. The semiconductor substrate 21 has an active surface 211 and a back surface 212. The back surface 212 is integrally formed with a plurality of bump bodies 213 of the same material as the semiconductor substrate 210, and conductive materials are formed on the bump bodies 213. 22〇. Specifically, as shown in FIG. 4, the semiconductor wafer structure 200 of the bump in the crystal back may further include a plurality of pads 23 〇 and a plurality of positions corresponding to the crystal back pads 240, the pads 23 The crystal back pads 240 are formed on the active surface 211 ′ between the convex planes 213A of the bump bodies 213 and the conductive material 22 。. The convex planes 213A of the bump main bodies 213 are substantially equal to or smaller than the pads 23 0 . The polishing pads 230 and the crystal back pads 240 may be made of a conductive metal material such as aluminum, copper, aluminum alloy or copper alloy 16 1375310. The semiconductor wafer structure 200 of the bump in the crystal back may further comprise a passivation layer 250 formed on the active surface 211 and having a plurality of openings 25 to expose the pads 23A. A dielectric layer 26 is formed between the bump bodies 213 and the conductive material 22A. More specifically, the dielectric layer 260 is formed between the bump body 213 and the back pads 24A, and the conductive material 22 is bonded to the crystals.

Solder pad 240. Specifically, the conductive material 22 may be a solder. As shown in Fig. 4, a plurality of holes 213B are formed through the corresponding bump bodies 213 and the semiconductor substrate 21A. In this embodiment, the holes 213B extend through the pads 23 and the back pads 24 . Preferably, the conductive material % π bamboo 22 0 is formed on the convex plane 213α of the bump main body 213, and can be filled into the holes 213B and attached. For these pads ΰΐ* 丨田辟

#纪230. The conductive material 220 can be injected into the hole by using a solder jetting or printing (printin) tutorial to reach a cone, and the main J is electrically conductive and penetrates the shape of the bump. In order to save the bump process + sheet stacking, the conductive material 220 can be joined by the reflow to the abutment of the upper and lower crystals, and the shape of the bump bodies 213 does not change. The embodiment discloses another bump shown in the back of the crystal, which is semi-conductive at the back of the crystal. The third concrete semiconductor wafer construction of the present invention. For example, the <; bulk wafer structure 3 〇〇 a mainly includes a semiconductor substrate 310. The semiconductor substrate 310 has a too small active active surface 311 and a back surface 312. The back surface 17 1375310 3U is formed with a plurality of bump main bodies 3丨3' of the same material as the semiconductor substrate, and a conductive material 32 is formed on the bump main bodies 313. The semiconductor substrate 310 and the conductive material 32 are substantially the same as the semiconductor substrate 110 and the conductive material 12A of the first embodiment, and will not be further described.

As shown in FIG. 5, the bump in the back of the semiconductor wafer structure 3 can further include a plurality of fresh slabs 330 disposed on the active surface 3U and electrically connected to the conductive material 32. In a specific structure, the pads 330 are aligned with the bump bodies 313. The semiconductor wafer structure 300 of the bumps may further include a plurality of conductive pillars 340' extending through the semiconductor substrate 31. And the bump bodies 313 are connected to the solder pads 330 and the conductive material 32. A passivation layer 35 can be formed on the active surface 311 and has a plurality of openings 351' to expose the pads. 330. A dielectric layer 36 is formed between the bump bodies 313 and the conductive material 32. As shown in FIG. 5, preferably, an anisotropic conductive film 370 is formed thereon. On the active surface 311. The anisotropic conductive film 37 has conductive particles 371 of equal spherical diameter. As shown in FIG. 6, when a plurality of the above bumps are stacked on the back of the semiconductor wafer structure The anisotropic conductive film 370 is formed on the semiconductor wafer structure of the bumps in the crystal back The bump body 313 may be electrically connected to the radiant particles 330 via the conductive particles 371, and may not be directly soldered to the solder bump 330. In the embodiment, the anisotropic conductive film 370 Pre-formed on the active surface 311 of the semiconductor substrate 310, 18 1375310 is attached to the passivation layer 350 and covers the pads 330. Therefore, as shown in FIG. 6, in a wafer stack assembly structure The plurality of bumps as described above are stacked on the back of the semiconductor wafer structure 300 and disposed on a line carrier 40. In the present embodiment, the upper surface of the line carrier 40 has a plurality of ports. 41, for electrically connecting the conductive material 32. In this embodiment, the uppermost bump in the crystal back semiconductor wafer structure 300 may not need to form the anisotropic conductive film 370' and the lowermost layer The bump between the crystal back semiconductor wafer structure 300 and the line carrier 40 is further required to form an anisotropic conductive film 50. Specifically, the vertical electrical conduction path is formed by a semiconductor wafer structure 300. The pads 33 are electrically conductive via The material 32 is electrically connected to the conductive particles 371 between the bump bodies 313 and the pads 330 of the other lower semiconductor wafer structure 3, and then to the pads 33 of the lower semiconductor wafer structure 300. The semiconductor wafer structure 300 in which the bump is on the crystal back does not need to be separately provided with the external bump and the need to form a bonding wire, that is, a 3D three-dimensional stack of the multi-chip. Therefore, since the bump main body 313 and the semiconductor substrate 31 are the same material Therefore, there is no problem that the expansion coefficient does not match during temperature change or temperature cycling, and zero stress or lower stress bonding can be achieved. The above description is only a preferred embodiment of the present invention, not The invention is subject to any form of limitation, and the scope of the technical solution of the present invention is subject to the scope of the patent claimed by the household. Any one skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content without departing from the technical solution of the present invention is implemented according to the technical essence of the present invention. Example ^ Any simple modification, equivalent change, and modification of the scare still belong to the [simplified description of the schematic] of the present invention. FIG. 1 is an I bump according to the first embodiment of the present invention. A schematic cross-sectional view of a crystal wafer structure of a crystal. 2(F): is a schematic diagram of a semiconductor wafer structure of a germanium bump in a crystal back according to a first embodiment of the present invention. FIG. 3 is a third embodiment of the present invention. A cross-sectional view of a wafer stack assembly configuration of a semiconductor wafer structure using a plurality of bumps in a crystal back. • 4th circle I/ is a schematic cross-sectional view of a semiconductor wafer structure in accordance with a second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view showing a bump-on-crystal/conductor wafer structure according to the invention of the first &&& A cross-sectional view of a wafer stack assembly structure using a plurality of bumps in a semiconductor package according to a second embodiment of the present invention in accordance with a second embodiment of the present invention. I main component symbol description]

10 line carrier U 13 concave sample 12 external pad 9 20 sealant, false 3〇 external terminal 20 B75310 40 line carrier 41 connection pad 5〇 anisotropic conductive film 100 bump in crystal back semiconductor wafer structure

110 semiconductor substrate 112 unthinned back surface 113 bump body 120 conductive material 150 passivation layer 160 dielectric layer 200 bump in crystal 21〇 semiconductor substrate 2 1 3 bump body 220 conductive material 250 passivation layer

330 pad 351 opening 370 anisotropic conductive film 1 70 tin layer back semiconductor wafer structure 251 opening 3 〇〇 bump in crystal back semiconductor wafer structure 31 〇 semiconductor substrate 3 1 3 bump body 32 〇 conductive material 3 50 passivation layer 111 active surface 113A raised plane 130 pad 151 opening 211 active surface 213A raised plane 230 pad 112 back 113 B hole 140 conductive post 212 back 213B hole 240 crystal back fresh 260 dielectric layer 3 12 back 340 conductive pillar 360 dielectric layer 371 conductive particles 21

Claims (1)

1375310 / year $ month 7 revision Ben 10, the scope of the patent application: - 1, a bump in the crystal back of the semiconductor wafer structure, mainly comprising a semiconductor substrate, which has an active surface and a back surface, characterized in that A plurality of bump bodies having the same material as the semiconductor substrate are integrally formed on the back surface, and a conductive material is formed on the bump bodies. The semiconductor wafer structure further includes a plurality of pads and a plurality of conductive pads. The plurality of pads are disposed on the active surface and electrically connected to the conductive material, and the pads are aligned with the bump bodies, the conductive pillars penetrating the semiconductor substrate and the bump bodies to The pads are connected to the conductive material. 2. The bump according to claim 1, wherein the bump is in the semiconductor wafer structure of the crystal back, and further comprises a passivation layer formed on the active surface. 3. The semiconductor wafer structure of the bump according to claim 2, wherein the passivation layer has a plurality of openings to expose the pads. 4. The bump according to claim 1, wherein the bump is in the semiconductor wafer structure of the crystal back, and further comprises a dielectric layer formed between the bump body and the conductive material. 5. The bump according to claim i, wherein the bump is in the back of the semiconductor wafer structure, wherein the conductive material is a metal layer. 6. The semiconductor wafer structure of the bump according to claim 5, wherein the metal layer of the conductive material is a gold layer, and a tin layer is formed on the pads. 7. The bump according to claim i is characterized in that the bump is formed on the back of the semiconductor crystal 22 1375310 sheet, and further comprises an anisotropic conductive film formed on the active surface. 8. The bump according to claim 1, wherein the bump is in the back of the semiconductor wafer structure, wherein the conductive material is solder. 9. The semiconductor wafer structure of the bump according to claim 1, wherein the height of the bump bodies is equal to or greater than a thickness of the semiconductor substrate. 10. The semiconductor wafer structure of the bump according to the invention of claim i, wherein the bump main system has a convex plane smaller than the solder bumps. 11. The semiconductor wafer structure of the bump according to the invention of claim 2, further comprising a plurality of crystal back pads disposed on the convex plane of the bump body and the conductive The locations between the materials correspond to the pads. 12. A semiconductor wafer structure having a bump in a crystal back, comprising a semiconductor substrate having an active surface and a back surface, wherein the back surface is integrally formed with a plurality of bumps of the same material as the semiconductor substrate. And forming a conductive material on the main body of the bump; wherein the semiconductor wafer structure further comprises an anisotropic conductive adhesive formed on the active surface. 13. A semiconductor wafer structure having a bump in a crystal back, comprising a semiconductor substrate having an active surface and a back surface, wherein the back surface is integrally formed with a plurality of bumps of the same material as the semiconductor substrate. Forming a conductive material on the body of the bumps; wherein, the semiconductor wafer structure further includes a plurality of pads disposed on the active surface and electrically connected to the conductive material, and The bump master system has a raised plane that is smaller than the pads. 14' The semiconductor wafer structure of the bump in the crystal back according to claim 13 further comprising a plurality of crystal back pads disposed on the convex plane of the bump body and the conductive material The position between and corresponds to the solder fillets. 15. A method of fabricating a semiconductor wafer structure having bumps in a crystal back, comprising the steps of: providing a semiconductor substrate having an active surface and an unthinned back surface; selectively etching the semiconductor substrate without thinning The back surface is formed with a thinned back surface for reducing the thickness of the semiconductor substrate, and at the same time, a plurality of bump bodies of the same material as the semiconductor substrate are integrally formed on the back surface; and a conductive material is formed on the bump bodies. 16. The method of fabricating a semiconductor wafer structure of a bump according to claim 15, wherein the method further comprises: electrically connecting a plurality of pads on the active surface to the conductive material. A method of fabricating a semiconductor wafer structure in which a bump is described in the above-mentioned patent application, wherein the fresh lanthanum is aligned with the bump bodies. 18. The method of fabricating a semiconductor wafer structure having a bump in a crystal back according to claim 17, wherein the electrical connection step comprises 24 JJ1U1 into a plurality of conductive germanium, which is passed through the semiconductor substrate and The bump bodies are connected to the pads and the conductive material. [19] The method for manufacturing a bump according to claim 16 in the semiconductor wafer b of the crystal back, wherein a purification layer is formed on the active surface, and the passivation layer has a plurality of openings to These pads are exposed. The manufacturing method of the semiconductor wafer structure of the bump according to the fifteenth aspect of the patent application, further comprising the steps of: forming a dielectric layer on the bump body and the conductive material between. A method of fabricating a semiconductor wafer structure having bumps as described in claim 5, further comprising the step of: forming an anisotropic conductive film on the active surface. 22. A wafer stack assembly structure comprising a plurality of semiconductor wafer structures of bumps as described in claim 1 or 13 and a line carrier, wherein the semiconductor wafer structures are stacked on each other and Set on the line carrier. 23. The wafer stack assembly structure of claim 22, further comprising at least one anisotropic conductive paste film formed between the semiconductor wafer structures. 24. The wafer stack assembly of claim 22, further comprising an anisotropic conductive film formed between the semiconductor wafer structures of the lower layer and the line carrier. The wafer stack assembly structure of claim 22, wherein the line carrier has a plurality of grooves, and the bump main system 25 1375310 is embedded in the grooves. 26 1375310 Η , Schema: /·/year <Monthday revision 1 00 170 130 151 150 1 1 1 130 170 113 113Α 140 120 1 12 1 13 160 120 113Β Figure 1 130 150 111 130 151 150 111 130 151 113 112 113Α 113 Picture 2 27 1375310 150 111 130 151 113A 113 112 113A 113B 113 2C wide 150 111 130 151 113A 160 113 112 113A 113B 113 2D 150 111 130 151 TZZy / 113A 113 1 12 160 140 1 13B 113 2E Figure 28 1375310 130 ///////λ^//7, 111 130 151 150 113A 140 1 13 1 12 1 13 120 140 160 1 13B 2F 20 130 170 150 111 112 130 151 Figure 3 29 1375310 200 220 250 21 1 230 251 260 240 212 213B 240 220 213A 213 Figure 4 30 1375310 300 371 370 350 371 31 1 330 351 Figure 350 370 350 31 1 312 330 351 300-turn 300- 300- 〇0 Υ77/.///////Λ\^///// [° β:〇0 ° ° ° ° 〇° 〇〇: 〇_g ///////, 310 marriage' I _ * r\ ^ c\ Ο 0 〇 _ 〇Ο 〇 40 41 360 50 31