TWI421990B - Wafer level chip scale package with minimized substrate resistance and process of manufacture - Google Patents

Description

Wafer level wafer size package with low substrate resistance and manufacturing method thereof

The present invention relates to a semiconductor package structure and a manufacturing method, and more particularly to a wafer level wafer size package with low substrate resistance and a method of fabricating the same.

Wafer Level Chip Scale Packaging (WLCSP) is an integrated circuit chip packaging technology, which is different from the traditional chip packaging method (cutting and then sealing, and increasing the volume of the original wafer by at least 20% after packaging) The latest technology is to perform package testing on the wafer and then cut into individual IC particles. Therefore, the packaged volume is equivalent to the original size of the IC die. For the wafer level chip package, the package area is The ratio of wafer area is less than 1.2.

Recently developed electronic devices such as mobile phones, portable computers, video cameras, personal digital assistants and other similar devices use wafer level wafer size packaging technology to reduce component density, performance, and cost effectiveness while reducing component density. The weight and size of the device.

For example, in the Chinese Patent Publication No. CN101383292A, a chip package, a conductive pillar thereof, and a method of modifying the uploaded spherical layer thereof are disclosed. The wafer size package includes: a substrate; a plurality of spike-shaped conductive pillars extending from a surface of the substrate; and a plurality of soft solder balls, wherein each of the soft solder balls and the pin-shaped conductive pillars One of them is connected. When needed When different sizes of soft solder balls are used, the rework of the above semiconductors only needs to remove and replace the nail heads of the above-mentioned spike-shaped conductive posts, and the rework cost can be reduced. With the present invention, when the size of the soft solder ball is different from the size of the existing nail head of the spike-shaped conductive post, only the nail head of the nail-shaped conductive post needs to be modified, and when the size of the soft solder ball affects the contact point When the ball is displayed, the corresponding structural modification can be performed with fewer process steps, and the cost can be saved. The wafer level wafer size package has the advantages of small volume, light weight, good electrical conductivity and simple process, but the conductive column only solves the problem of electrical conduction in the vertical direction of the wafer, and the electrical connection to the horizontal direction of the substrate, Can't work.

For double-diffused metal oxide semiconductors (DMOS), especially for wafer-level wafer-scale packages of common-drain bimorph structures, as shown in Figure 1, the conductive paths are shown by the arrows in Figure 1, respectively, path a, path b, path c, where paths a and c are substrate resistances, in a wafer level wafer size package, the substrate resistance can be close to 50% of the entire on-resistance, which is significantly affected by the small size of the package itself. The performance of the wafer, and if the substrate resistance is reduced by thinning the thickness of the substrate, the wafer is easily damaged during the manufacturing and operation of the process due to the thin thickness of the wafer.

It is an object of the present invention to provide a wafer level wafer size package having a low substrate resistance and a method of fabricating the same that enables a wafer level co-drain bimorph to have a low on-resistance of the substrate and simultaneously increase the strength of the substrate. The wafer has good electrical properties and reliable stability.

In order to achieve the above object, the technical solution of the present invention is: a wafer level wafer size package with low substrate resistance, characterized by comprising: a semiconductor wafer, the semiconductor wafer further comprising a semiconductor wafer An upper surface and a lower surface of the semiconductor wafer, wherein the upper surface of the semiconductor wafer is provided with a plurality of integrated circuit wafers, a plurality of under bump metallization layers, and a wafer connection over each under bump metallization layer a plurality of solder balls; a conductive reinforcing member, the conductive reinforcing member further comprising an upper surface of the conductive reinforcing member, the upper surface of the conductive reinforcing member is provided with a first metal layer; and the first metal layer of the conductive reinforcing member Bonded to the lower surface of the semiconductor wafer.

The above-described low substrate resistance wafer level wafer size package, wherein the lower surface of the semiconductor wafer is provided with a second metal layer.

The above wafer-level wafer size package with low substrate resistance, wherein a conductive epoxy resin is disposed between the first metal layer and the second metal layer.

The above-described low substrate resistance wafer level wafer size package, wherein the first metal layer and the second metal layer are two mutually fusible metals.

The above wafer level wafer package of low substrate resistance, wherein one of the first metal layer and the second metal layer is Au.

The above-described low substrate resistance wafer level wafer size package, wherein the other of the first metal layer and the second metal layer is Sn.

A wafer level wafer size package having a low substrate resistance, wherein the first metal layer is a metal that is interfused with germanium.

The above-described low substrate resistance wafer level wafer size package, wherein the first metal layer is Au.

The above wafer level wafer size package with low substrate resistance, wherein A metal layer is AuSn.

A method of fabricating a wafer level wafer size package with low substrate resistance, comprising: step 1: providing a semiconductor wafer having an original thickness, the semiconductor wafer comprising a semiconductor wafer upper surface and a semiconductor wafer lower surface a plurality of integrated circuit wafers are disposed on the upper surface of the semiconductor wafer; step 2: forming a plurality of under bump metallization layers on the upper surface of the semiconductor wafer by solder joint technology; and step 3: grinding the lower surface of the semiconductor wafer to remove the semiconductor a lower surface of the wafer of germanium dioxide, such that the lower surface of the semiconductor wafer is a germanium layer; step 4: thinning the central region of the lower surface of the semiconductor wafer, retaining the thickness of the lower surface edge of the semiconductor wafer; step 5: in an electrically conductive reinforcement a first metal layer is disposed on the upper surface, and a metal layer on the upper surface of the electrical conductive reinforcement is bonded to the lower surface of the semiconductor wafer; Step 6: a solder ball is disposed on the metallization layer under each bump; Step 7: Excision The semiconductor wafer has an edge region of thickness; step 8: cutting each bimorph unit from the semiconductor wafer.

The method for fabricating a wafer level wafer size package having a low substrate resistance, wherein the step 4 further comprises disposing a second metal layer on a lower surface of the semiconductor wafer.

The above method for fabricating a wafer level wafer size package having a low substrate resistance, wherein in step 5, the first metal layer and the second metal layer are bonded together by a conductive epoxy resin.

The method for manufacturing a wafer level wafer size package with low substrate resistance, wherein, in step 5, further comprising disposing solder on the first metal layer on the upper surface of the electrically conductive reinforcement, and the first metal through the solder The layer and the second metal layer are bonded together.

A method of fabricating a wafer level wafer size package having a low substrate resistance, wherein the first metal layer and the second metal layer are two mutually fusible metals.

A method of fabricating a wafer level wafer size package having a low substrate resistance, wherein one of the first metal layer and the second metal layer is Au.

A method of fabricating a wafer level wafer size package having a low substrate resistance, wherein another metal layer of the first metal layer and the second metal layer is Sn.

A wafer level wafer size package having a low substrate resistance, wherein the first metal layer is a metal that is interfused with germanium.

The above-described low substrate resistance wafer level wafer size package, wherein the first metal layer is Au.

The above-described low substrate resistance wafer level wafer size package, wherein the first metal layer is AuSn.

The wafer level wafer size package with low substrate resistance and the manufacturing method thereof have the following advantages and positive effects compared with the prior art by adopting the above technical solutions:

1. The present invention reduces the substrate resistance by reducing the substrate thickness, and the first metal layer is provided on the upper surface of the conductive reinforcement, thereby greatly increasing the electrical conductivity between the source of the dual wafer.

2. The present invention provides an enhanced half by providing a conductive reinforcement on the lower surface of the wafer. The robustness of the conductor wafer prevents breakage of the semiconductor wafer during fabrication.

3. The wafer level wafer size package of the low substrate resistance of the present invention is simple in manufacturing, easy to operate, and low in manufacturing cost.

1, 1', 1''‧‧‧ semiconductor wafer

2, 2', 2''‧‧‧ conductive reinforcement

3‧‧‧ Conductive epoxy resin

11, 11', 11''‧‧‧ semiconductor wafer upper surface

12, 12', 12''‧‧‧ semiconductor wafer lower surface

21, 21', 21''‧‧‧ conductive reinforcement upper surface

111, 111', 111''‧‧‧ under bump metallization

211, 211', 211''‧‧‧ first metal layer

121, 121'‧‧‧ second metal layer

112, 112’, 112’’‧‧‧ welding balls

a, b, c‧‧‧ path

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

Figure 1 is a conductive path diagram of a double-diffused metal oxide semiconductor common-drain bimorph in a prior art wafer level wafer size package.

FIG. 2 is a structural diagram of a fabricated dual wafer unit in the first embodiment of the wafer level wafer size package with low substrate resistance of the present invention.

FIG. 3 is a schematic structural view showing a plurality of under bump metallization layers on the upper surface of the semiconductor wafer in the process flow of the first embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

4 is a schematic view showing the structure of the ceria layer on the lower surface of the semiconductor wafer in the process step of the wafer level wafer package of the low substrate resistance of the present invention.

FIG. 5 is a structural schematic view showing the central portion of the lower surface of the semiconductor wafer in the process flow of the first embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

FIG. 6 is a structural schematic view showing the arrangement of the second metal layer on the lower surface of the semiconductor wafer in the process flow of the first embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

7 is a process step of the wafer level wafer package of the low substrate resistance of the present invention. The conductive resin with the first metal layer and the second metal layer are provided by the conductive epoxy resin in the process step of the first embodiment. Schematic diagram of the bonding of semiconductor wafers together.

FIG. 8 is a structural schematic view showing the arrangement of solder balls on each under bump metallization layer in the process flow of the first embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

FIG. 9 is a structural schematic view showing the edge region of the semiconductor wafer in the process flow of the first embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

FIG. 10 is a schematic structural view of a wafer level wafer package of the low substrate resistance of the first embodiment of the present invention, which is cut from a semiconductor wafer into a dual wafer unit.

11 is a schematic structural view of a dual-wafer unit after the fabrication of the wafer level wafer package of the low substrate resistance of the present invention.

FIG. 12 is a schematic structural view of a dual-wafer unit of the fourth embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

FIG. 13 is a schematic view showing the structure of forming a plurality of under bump metallization layers on the upper surface of the semiconductor wafer in the process step of the fourth embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

Figure 14 is a schematic view showing the structure of the ceria layer on the lower surface of the semiconductor wafer in the process step of the wafer level wafer package of the low substrate resistance of the present invention.

Fig. 15 is a structural schematic view showing the central portion of the lower surface of the semiconductor wafer in the process step of the fourth embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

FIG. 16 is a structural diagram showing the bonding of the conductive reinforcement with the first metal layer and the semiconductor wafer in the process step of the fourth embodiment of the wafer level wafer package of the low substrate resistance of the present invention.

FIG. 17 is a structural schematic view showing the arrangement of solder balls on each under bump metallization layer in the process step of the fourth embodiment of the wafer level wafer size package of the low substrate resistance of the present invention.

Figure 18 is a schematic view showing the structure of the edge region of the semiconductor wafer in the process step of the wafer-level wafer size package of the low substrate resistance of the present invention.

FIG. 19 is a structural schematic view showing the process of cutting a semiconductor wafer from a semiconductor wafer to a dual wafer unit in the process step of the wafer level wafer package of the low substrate resistance of the present invention.

Embodiment 1, please refer to FIG. 2, a wafer level wafer size package with low substrate resistance, comprising a semiconductor wafer 1 and a conductive reinforcement 2, the semiconductor wafer 1 including a semiconductor wafer upper surface 11 and a The semiconductor wafer lower surface 12, the semiconductor wafer upper surface 11 is provided with a plurality of integrated circuit wafers (not shown), a plurality of under bump metallization layers 111, and each of the under bump metallization layers 111. The semiconductor wafer lower surface 12 is provided with a second metal layer 121; the conductive reinforcement 2 includes a conductive reinforcement upper surface 21, and the conductive reinforcement upper surface 21 is provided with a first metal layer 211. A conductive epoxy resin 3 is disposed between the first metal layer 211 and the second metal layer 121, and the first metal 211 and the second metal 121 are bonded by the conductive epoxy resin 3, thereby causing the semiconductor wafer 1 and the conductive The firmware 2 is combined.

A method for manufacturing a wafer level wafer size package with low substrate resistance, as shown in FIG. 3, firstly providing a semiconductor wafer 1 having an original thickness, which is usually used in an original thickness of 600 um to 700 um, and the semiconductor wafer 1 includes a semiconductor wafer upper surface 11 and a semiconductor wafer lower surface 12, a plurality of integrated circuit wafers (not shown) are disposed on the semiconductor wafer upper surface 11, and a plurality of bumps are formed on the upper surface 11 of the semiconductor wafer by solder joint technology. Metallization layer 111; as shown in FIG. 4, during the fabrication of the semiconductor process, the lower surface of the semiconductor wafer contains a layer of high hardness cerium oxide, and the lower surface 12 of the semiconductor wafer is polished to remove the lower surface of the semiconductor wafer. a layer of ruthenium dioxide to reduce the thickness of the semiconductor wafer, the preferred thickness after polishing 500 um; as shown in FIG. 5, the central region of the lower surface of the semiconductor wafer is further thinned, and the upper surface corresponding to the region is provided with a plurality of integrated circuit wafers, which retain the thickness of the lower surface edge of the semiconductor wafer because of the semiconductor The thickness of the edge of the wafer is large, which facilitates the movement of the semiconductor wafer during the process of manufacturing, thereby reducing the size of the semiconductor wafer and ensuring that the semiconductor wafer is not easily damaged; as shown in FIG. 6, followed by the semiconductor wafer A second metal layer 121 is disposed on the lower surface 12, and preferably, a second metal layer 121 is disposed on the lower surface 12 of the semiconductor wafer by sputtering evaporation, and the second metal layer 121 enhances the substrate conductivity of the bimorph structure. The lateral resistance is reduced; as shown in FIG. 7, a first metal layer 211 is then disposed on the upper surface of an electrically conductive reinforcement 2, and the first metal of the upper surface 21 of the electrically conductive reinforcement is electrically conductive through the conductive epoxy 3 The layer 211 is bonded to the second metal layer 121 of the lower surface 12 of the semiconductor wafer, and the conductive epoxy resin 3 not only has electrical conductivity but also enhances the first metal layer. The adhesion between the second metal layer 121 and the second metal layer 121, the combination of the electrically conductive reinforcement 2 and the semiconductor wafer 1 enhances the semiconductor wafer 1 while enhancing the lateral conductivity of the substrate; as shown in FIG. Next, a solder ball 112 is disposed on each under bump metallization layer 111; as shown in FIG. 9, since the electrically conductive reinforcement 2 enhances the robustness of the semiconductor wafer 1, the edge region of the semiconductor wafer can be removed. Therefore, the edge region of the semiconductor wafer 1 is cut off; as shown in FIG. 10, the wafer is finally cut from the semiconductor wafer 1 to obtain a wafer-level wafer size package having a dual wafer, which is small in size, strong in firmness, and small in size. The substrate resistance greatly improves the performance and reliability of the wafer.

Embodiment 2, as shown in FIG. 11, a wafer level wafer package with low substrate resistance, comprising a semiconductor wafer 1' and a conductive reinforcement 2', the semiconductor wafer 1' including a semiconductor wafer upper surface 11' and a semiconductor wafer lower surface 12', the semiconductor wafer upper surface 11' is provided with a plurality of integrated circuit wafers (not shown), a plurality of bumps under the gold a plurality of solder balls 112' for wafer connection over the underlying layer 111' and each under bump metallization layer 111', a second metal layer 121' is provided on the lower surface 12' of the semiconductor wafer; and a conductive reinforcement 2 'Includes a conductive reinforcing member upper surface 21', the conductive reinforcing member upper surface 21' is provided with a first metal layer 211'; the first metal layer 211' is bonded to the second, thereby bonding the semiconductor wafer 1' with the conductive reinforcement Pieces 2' are combined.

The manufacturing method of the wafer level wafer size package with low substrate resistance is the same as that of the first embodiment. As shown in FIG. 11, the conductive reinforcement 2' having the first metal layer 211' is The semiconductor wafer 1' having the second metal layer 121' is bonded together, except that the first metal layer 211' and the second metal layer 121' are not reinforced by the conductive epoxy 3 to the first metal layer 211' And the adhesion between the second metal layer 121', but the first metal layer 211' and the second metal layer 121' are bonded together by soldering in the prior art, because the soldering technology is prior art The description will not be further described here, and other process steps are the same as in the first embodiment.

In the third embodiment, the structure of the wafer level wafer size package with low substrate resistance in this embodiment is the same as that of the first embodiment, and the process is basically the same, except that the first metal layer in the third embodiment is The second metal layer is two mutually fusible metals, so that no solder connection is required, and at a high temperature, the two metals can be fused to each other, thereby bonding the conductive reinforcement to the semiconductor wafer with low The lateral resistance of the substrate. Preferably, the two mutually fusible metals are Au and Sn, respectively.

Embodiment 4, a wafer level wafer size package with low substrate resistance, comprising a semiconductor wafer 1" and a conductive reinforcement 2", the semiconductor wafer 1" includes a semiconductor wafer upper surface 11" and a semiconductor Wafer lower surface 12'', semiconductor wafer on the surface The surface 11'' is provided with a plurality of integrated circuit wafers (not shown), a plurality of under bump metallization layers 111" and a bump connection on each of the under bump metallization layers 111" The plurality of solder balls 112'', the material of the lower surface 12'' of the semiconductor wafer is 矽; the conductive reinforcement 2'' includes a conductive reinforcement upper surface 21'', and the conductive reinforcement upper surface 21'' is provided with A metal layer 211" is bonded to the lower surface 12" of the semiconductor wafer such that the semiconductor wafer 1" is bonded to the conductive reinforcement 2".

A method for fabricating a wafer level wafer size package having a low substrate resistance, as shown in FIG. 13, first providing a semiconductor wafer 1'' having an original thickness, which is usually used in a semiconductor wafer having a thickness of 600 um to 700 um, a semiconductor wafer. 1'' includes a semiconductor wafer upper surface 11" and a semiconductor wafer lower surface 12", and a plurality of integrated circuit wafers (not shown) are disposed on the semiconductor wafer upper surface 11", using solder joint technology in the semiconductor The upper surface 11'' of the wafer forms a plurality of under bump metallization layers 111"; as shown in Fig. 14, in the semiconductor process, the lower surface of the semiconductor wafer is a layer of high hardness cerium oxide, polished The lower surface of the semiconductor wafer 12", the lower layer of the semiconductor wafer is etched away to reduce the thickness of the semiconductor wafer, and the preferred thickness after polishing is 500 um; as shown in Fig. 15, the semiconductor wafer is further thinned. a central region of the lower surface 12'', the upper surface corresponding to the region is provided with a plurality of integrated circuit wafers, which retain the thickness of the lower surface edge of the semiconductor wafer, Due to the large thickness of the edge of the semiconductor wafer, it is convenient to move the semiconductor wafer during the process of manufacturing, thereby reducing the size of the semiconductor wafer while ensuring that the semiconductor wafer is not easily damaged; as illustrated in Fig. 16, then A first metal layer 211 ′′ is disposed on an upper surface of an electrically conductive reinforcing member 2 ′′, and the first metal layer 211 ′′ is a metal intertwined with the crucible, and thus the first metal layer 211 ′′ and the lower surface of the semiconductor wafer The surface of the crucible is fused together so that the electrically conductive reinforcement 2'' and the semiconducting The body wafer 1'' is tightly bonded together, and the first metal layer 211'' enhances the lateral conductivity of the substrate, while the electrically conductive reinforcement 2'' supports the semiconductor wafer 1'', increasing the robustness of the semiconductor wafer. Preferably, the first metal layer 211 ′′ is Au or AuSn; as shown in FIG. 17 , a solder ball 112 ′′ is then disposed on each under bump metallization layer 111 ′′; As shown in the figure, since the electrically conductive reinforcing member 2'' supports the semiconductor wafer 1'' at this time, the robustness of the semiconductor wafer 1'' is enhanced, and the edge region of the semiconductor wafer can be cut off, thereby cutting the semiconductor wafer 1' 'Edge region'; finally, as shown in Fig. 19, the wafer is finally cut from the semiconductor wafer 1'' to obtain a wafer-level wafer size package having a dual wafer, which is small in size, strong in firmness, and has a small lining. The bottom resistor greatly improves the performance and reliability of the wafer.

Of course, it is to be understood that the foregoing description has been described in connection with the preferred embodiments of the invention, and the invention

The present invention is by no means limited to the details and methods shown in the above description or the drawings. The invention is capable of other embodiments and of various embodiments. In addition, you must also understand that the words and terms used herein and the abstracts are for the purpose of illustration only and are by no means limited.

As such, those skilled in the art will appreciate that the present invention is based on the teachings of the present invention as well as other structures, methods and systems. Therefore, it is essential that the appended claims be construed as including all such equivalents

1‧‧‧Semiconductor wafer

2‧‧‧ Conductive reinforcement

3‧‧‧ Conductive epoxy resin

11‧‧‧Side surface of semiconductor wafer

12‧‧‧Semiconductor wafer lower surface

21‧‧‧ Conductive reinforcement upper surface

111‧‧‧ under bump metallization

211‧‧‧First metal layer

121‧‧‧Second metal layer

112‧‧‧ solder balls

Claims (18)

A wafer level wafer size package with low substrate resistance, comprising: a semiconductor wafer, the semiconductor wafer further comprising a semiconductor wafer upper surface and a semiconductor wafer lower surface, wherein the semiconductor wafer upper surface is provided a plurality of integrated circuit wafers, a plurality of under bump metallization layers, and a plurality of solder balls for wafer connection over each under bump metallization layer; a conductive reinforcement, said conductive reinforcement The upper surface of the conductive reinforcement is provided with a first metal layer, the first metal layer is a metal intertwined with the crucible; the first metal layer and the semiconductor of the conductive reinforcement The lower surface of the wafer is bonded together. A wafer level wafer size package having a low substrate resistance as described in claim 1, wherein the lower surface of the semiconductor wafer is provided with a second metal layer. A wafer level wafer size package having a low substrate resistance according to claim 2, wherein a conductive epoxy resin is disposed between the first metal layer and the second metal layer. A wafer level wafer size package having a low substrate resistance as described in claim 2, wherein the first metal layer and the second metal layer are two mutually fusible metals. A wafer level wafer size package having a low substrate resistance as described in claim 4, wherein one of the first metal layer and the second metal layer is Au. A wafer level wafer size package having a low substrate resistance according to claim 5, wherein the other of the first metal layer and the second metal layer is Sn. A wafer level wafer size package having a low substrate resistance as described in claim 1 of the patent application, It is characterized in that the first metal layer is Au. A wafer level wafer size package having a low substrate resistance as described in claim 1, wherein the first metal layer is AuSn. A method of fabricating a wafer level wafer size package with low substrate resistance, comprising: step 1: providing a semiconductor wafer having an original thickness, the semiconductor wafer comprising a semiconductor wafer upper surface and a semiconductor wafer lower surface a plurality of integrated circuit wafers are disposed on the upper surface of the semiconductor wafer; step 2: forming a plurality of under bump metallization layers on the upper surface of the semiconductor wafer by solder joint technology; and step 3: grinding the lower surface of the semiconductor wafer to remove the semiconductor a lower surface of the wafer of germanium dioxide, such that the lower surface of the semiconductor wafer is a germanium layer; step 4: thinning the central region of the lower surface of the semiconductor wafer, retaining the thickness of the lower surface edge of the semiconductor wafer; step 5: in an electrically conductive reinforcement a first metal layer is disposed on the upper surface, and a metal layer on the upper surface of the electrical conductive reinforcement is bonded to the lower surface of the semiconductor wafer; Step 6: a solder ball is disposed on the metallization layer under each bump; Step 7: Excision The semiconductor wafer has an edge region of thickness; step 8: cutting each bimorph unit from the semiconductor wafer. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 9 is characterized in that, in the step 4, the second metal layer is disposed on the lower surface of the semiconductor wafer. Wafer level wafer size package with low substrate resistance as described in claim 10 The manufacturing method is characterized in that, in the step 5, the first metal layer and the second metal layer are bonded together by a conductive epoxy resin. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 10, further comprising, in step 5, on the first metal layer of the upper surface of the electrically conductive reinforcement The solder is placed and the first metal layer and the second metal layer are bonded together by solder. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 10, wherein the first metal layer and the second metal layer are two mutually fusible metals. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 13 is characterized in that one of the first metal layer and the second metal layer is Au. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 14 is characterized in that the other metal layer of the first metal layer and the second metal layer is Sn. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 9 is characterized in that the first metal layer is a metal intertwined with germanium. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 16 is characterized in that the first metal layer is Au. A method of fabricating a wafer level wafer size package having a low substrate resistance according to claim 16 is characterized in that the first metal layer is AuSn.