200947649 九、發明說明： 【發明所屬之技術領域】 本發明係有關於—種半導體裝置，特別係有關於一 種凸塊在晶背之半導體晶片構造、其製造方法及其應 用0 【先前技術】 按’目前主要應用於半導體晶片至線路載板（或印刷 φ 電路板）的電性連接方式大致有打線接合（wire bonding) 與覆晶接合（flip chip b〇nding)二種，此二種方法均廣泛 地應用於半導體構裝之用，並各自佔有一席之地，但各 有其缺點及其限制。 打線接合是將晶片主動面朝上（遠離線路載板）的型 態設置於線路載板，再以一種可彎折之細金屬線（例如 金線、銅線或其合金線），使晶片上的銲墊和線路載板 上導電線路的連接墊相連接，藉以將晶片之電性訊號傳 〇 輸到線路載板，再對外傳導。然而，此種接合方式有銲 墊數的限制，無法達到高1/0數需求，並且也無法應用 於面矩陣排列（area array)I/0之半導體晶片。同時，由 於以細金屬線作連接及有較長之連接長度，會不利於高 頻之訊號傳輸。 而覆晶接合是預先在晶片主動面接合有金屬凸塊 (bumP)，以晶片主動面翻轉（朝向線路載板）的型態設置 於線路載板。然而，覆晶接合通常會產生可靠性的問 題由於晶片與線路載板間的熱膨脹係數（CTE， 5 200947649 coefficient of thermal expansion)不闩 同’會使得裝配元 件在熱循環後，因晶片與線路載板的撼& 頓張差異，使金屬 凸塊承受應力而造成連接失效，稱之蛊姑涵，昨^ 冊心马熱膨脹係數不匹 配（CTE mismatch)。又，通常凸塊係設於晶片之主動 面，應力易直接傳遞到主動面之積體電路，導致晶片的 失效。此外，覆晶製程相當複雜，一般來說包含形成銲 接金屬層（UBM，under bump metallurgy)、凸塊成型以及 裝配等製程，相對地設備投資很大，成本較高。目前的 ® 凸塊主要是金凸塊與錫鉛凸塊，在製造方法與接合方式 皆不相同，然皆為金屬材質，在長時間的應力作用下， 導致金屬疲勞進而造成凸塊斷裂的問題為不可避免。 我國發明專利證書號第1293499號「立體式封裝結 構及其製造方法」，揭示一種晶背具有凸塊之半導體晶 片，可進行多晶片堆疊。晶片設有貫穿孔，孔壁依序形 成有一絕緣層以及一導電層，孔内並以銲料填滿，銲料 ^ 更電性連接至晶片銲墊。移除晶片背面而使孔内複合金 ❹ 屬露出，以形成貫穿晶片並突出於晶背之金屬凸塊。由 於晶片之半導體材質與金屬凸塊之銲料兩者在熱膨脹 係數上並不匹配，在高溫時金屬凸塊的體積膨脹遠大於 晶片孔的膨脹擴大，導致孔内產生擠壓的熱應力，一旦 造成絕緣層的裂痕則會有漏電流的風險，特別是金屬凸 塊貫穿晶片比起傳統僅突設晶片的金屬凸塊會有更大 的體積，晶片與凸塊之間的熱應力的問題會變成更加嚴 重。 6 200947649 【發明内容】 有鑒於此’本發明之主要目的係在於提供一種凸塊 在晶背之半導體晶片構造，能達成晶片與凸塊之間為零 應力並且避免外來應力直接作用於晶片主動面，具有電 性傳導路徑短以及晶片薄化之功效。200947649 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor wafer structure in which a bump is on a crystal back, a method of manufacturing the same, and an application thereof. [Prior Art] 'At present, the electrical connection methods mainly used for semiconductor wafers to circuit carriers (or printed φ circuit boards) are roughly two types: wire bonding and flip chip b〇nding. Widely used in semiconductor construction, and each has its own place, but each has its own shortcomings and limitations. Wire bonding is performed by placing the active side of the wafer face up (away from the line carrier) on the line carrier and then by bending a thin metal wire (such as gold wire, copper wire or alloy wire thereof) onto the wafer. The solder pads are connected to the connection pads of the conductive lines on the line carrier board, so that the electrical signals of the chips are transmitted to the line carrier board and then transmitted to the outside. However, this type of bonding has a limitation on the number of pads, cannot meet the high 1/0 number requirement, and cannot be applied to a semiconductor array of area array I/0. At the same time, due to the connection of thin metal wires and a long connection length, it is disadvantageous for high-frequency signal transmission. The flip chip bonding is performed by bonding a metal bump (bumP) to the active surface of the wafer in advance, and is disposed on the line carrier in a state in which the active surface of the wafer is reversed (toward the line carrier). However, flip-chip bonding usually creates reliability problems because the thermal expansion coefficient (CTE, 5 200947649 coefficient of thermal expansion) between the wafer and the line carrier does not latch the same, which causes the assembly components to be thermally cycled, due to wafer and line loading. The difference between the 撼& of the plate causes the metal bump to withstand the stress and cause the connection to fail. It is called the 蛊 涵, and the thermal expansion coefficient of the heart is not matched (CTE mismatch). Moreover, usually, the bumps are disposed on the active surface of the wafer, and the stress is easily transmitted directly to the integrated circuit of the active surface, resulting in failure of the wafer. In addition, the flip chip process is quite complicated, and generally includes a process of forming a bump metal layer (UBM), bump molding, and assembly, and the equipment investment is relatively large and the cost is high. The current ® bumps are mainly gold bumps and tin-lead bumps. They are different in manufacturing methods and bonding methods. They are all made of metal. Under long-term stress, metal fatigue causes cracks in the bumps. For the inevitable. China Patent No. 1293499 "Three-dimensional package structure and method of manufacturing the same" discloses a semiconductor wafer having bumps on a crystal back, which enables multi-wafer stacking. The wafer is provided with through holes, and the walls of the holes are sequentially formed with an insulating layer and a conductive layer, and the holes are filled with solder, and the solder ^ is electrically connected to the wafer pads. The back side of the wafer is removed to expose the composite gold metal in the hole to form a metal bump that penetrates the wafer and protrudes from the crystal back. Since the semiconductor material of the wafer and the solder of the metal bump do not match in thermal expansion coefficient, the volume expansion of the metal bump is much larger than the expansion and expansion of the wafer hole at a high temperature, resulting in thermal stress of extrusion in the hole, once caused Cracks in the insulating layer may have a risk of leakage current. In particular, the metal bumps penetrate the wafer and have a larger volume than the conventional metal bumps that only protrude from the wafer. The problem of thermal stress between the wafer and the bumps becomes more serious. 6 200947649 SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a semiconductor wafer structure in which a bump is formed on a crystal back, which can achieve zero stress between the wafer and the bump and prevent external stress from directly acting on the active surface of the wafer. It has the effect of short electrical conduction path and thinning of the wafer.
❹ 本發明之次一目的係在於提供一種凸塊在晶背之半 導體晶片構造之製造方法，凸塊的形成整合於晶圓製 程，具有節省凸塊之金屬用量與簡化凸塊製程的功效。 本發明之另一目的係在於提供一種凸塊在晶背之半 導體晶片構造之應用，能應用於高密度多晶片堆疊，防 止沖線並達成堆疊產品薄化的功效。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之—種凸塊在晶背之半 =晶片構造’該晶片構造主要包含—半導體基板。該 :導體基板’其係具有一主動表面與一背面，其特徵在 2該背面上-體形成有複數個與該半導體基板相同材 、塊主體，並在該些凸塊主體上形成導電材料。 本進發明的目的及解決其技術問題還可採用以下技術 才曰施進一步實現。 牡刖述之凸塊在晶背之半導 合右 體晶片構造中，可另爸 3有複數個銲墊，其係設置於 該導電#料。 主動表面並電性連接3 在前述之凸塊在晶背之本迹 墊# 7 m 半導體晶片構造中，該些多 塾係可對準於該些凸塊主體。 7 200947649 在前述之凸塊在晶背之半導體晶片構造中，可另包 含有複數個導電柱，其係貫穿該半導體基板與該些凸塊 主體，以連接該些銲墊與該導電材料。 在前述之凸塊在晶背之半導體晶片構造中，可另包 含一鈍化層，其係形成於該主動表面上。 在前述之凸塊在晶背之半導體晶片構造中，該鈍化 層係可具有複數個開口，以顯露該些銲墊。 在前述之凸塊在晶背之半導體晶片構造中，可另包 含一介電層，其係形成在該些凸塊主體與該導電材料之 間。 在前述之凸塊在晶背之半導體晶片構造中，該導電 材料係可為一金屬層。 在前述之凸塊在晶背之半導體晶片構造中，該導電 材料之金屬層係可為金層，並在該些銲墊上形成一錫 層。 H 在前述之凸塊在晶背之半導體晶片構造中，可另包 含有一異方性導電膠膜，其係形成於該主動表面上。 在前述之凸塊在晶背之半導體晶片構造中’該導電 材料係可為銲料。 在前述之凸塊在晶背之半導體晶片構造中，該些凸 塊主體之高度係可概約等於或大於該半導體基板之厚 度。 在前述之凸塊在晶背之半導體晶片構造中，該些凸 塊主體係可具有一尺寸小於該些銲墊之凸起平面。 8 200947649 在前述之&塊在晶背之半導體晶片構造中，可另包 含有複數個晶背銲墊，其係設置於該些凸塊主體之該凸起= 面與該導電材料之間並位置對應於該些銲塾。 本發明還揭示適用於前述的凸塊在晶背之半導體晶 片構造之製造方法’主要步驟包含：首先，提供一半導 體基板，其係具有一主動表面與一未薄化背面。接著， 選擇性蝕刻該半導體基板之該未薄化背面，以形成—使 e 該半導體基板厚度減少之薄化背面，並同時在該背面上 —體形成有複數個與該半導體基板相同材質的凸塊主 體。最後’形成導電材料於該些凸塊主體上。 本發明另還揭示適用於前述的凸塊在晶背之半導體 晶片構造之晶片堆疊組合構造，其係包含複數個上述凸塊 在晶背之半導體晶片構造以及一線路載板，其中該些 &塊在晶背之半導體晶片構造係相互堆疊並設置於該 線路載板上。 Ο 由以上技術方案可以看出，本發明之凸塊在晶背之 半導體晶片構造、其製造方法以及其應用，具有以下優 點與功效： —、藉由凸塊主體係與半導體基板相同材質並且突出於 晶片之背面’能達成晶片與凸塊之間為零應力並且 避免外來應力直接作用於晶片主動面，具有電性傳 導路徑短以及晶片薄化之功效。 二、利用晶圓製程在晶片背面進行選擇性蝕刻以形成半 導體材質之凸塊主體，藉以達成節省凸塊之金屬用 9 200947649 塊製程的功 罝' 凸塊製作整合於晶圓製程以簡化凸 效。 用晶片之銲墊係對準於半導體材質之凸塊主體並 以導電柱貫穿該半導體基板與該些凸塊主體使得 2塊在晶背之半導體晶片#造能應用力高密度多 晶片堆疊’防止沖線並達成堆疊產品薄化的功效。 【實施方式】 φ 依據本發明之第一具體實施例，一種凸塊在晶背之 半導體晶片構造說明於第i圖之截面示意圖。 如第1圖所示，該凸塊在晶背之半導體晶片構造1〇〇 主要包含一半導體基板110。㉟半導體基110係具有 -主動表面1U與_背面112。通常該半導體基板no j其主動表面111上係設有積體電路元件，如微控制 器、微處理器、記憶體、邏輯電路、特殊應用積體電路 (如顯示器驅動電路）等或上述之組合。本發明之特點在 Ο 於，該背面112上—體形成有複數個與該半導體基板 相同材質的凸塊主體113，該些凸塊主體的高 度可概約相同於該半導體基板11〇之厚度，而該些凸塊 主體113的形狀係可為圓柱形、方柱形或多角柱形。並 在該些凸塊主體113上形成一導電材料12〇，作為 積體電路對外電極。該導電材料12〇係可為鎳/金層、 鈦層、銅層、銅/鈦合金層或錫鉛等。在本實施例中， 該導電材料120係為銅/錄/金層。該導電材料12〇的厚 度以不超過該些凸塊主體113突出於該背面ιι2的高度 10 200947649 二分之一為限’通常其厚度應在該些凸塊主體113 度四分之一以下，而使該些凸塊主體11 3佔據整個 的體積在百分之六十以上’使得凸塊能呈現半導體 的熱膨脹係數，達成晶片與凸塊之間為零應力的沒 此外，與該半導體基板丨1〇相同材質的凸塊主崔 係突出於該半導體基板110之背面112，避免外來 直接作用於該半導體基板110之主動表面111，並 電性傳導路徑短以及晶片薄化之功效。 具體而言，再如第1圖所示，該凸塊在晶背之 體晶片構造100可另包含有複數個銲墊130，其係 於該主動表面111並電性連接至該導電材料丨20。 銲塾130係為導電金屬材質’例如銘、銅、銘合金 合金之中的任一者所製成’其係為該主動表面ηι 體電路之同一表面電極。在本實施例中’該些銲整 係對準於該些凸塊主體113。 Ο 此外’如第1圖所示’該凸塊在晶背之半導體 構造100可另包含有複數個導電柱140，其係貫穿 導體基板11〇與該些凸塊主體113，以連接該些銲鸯 與該導電材料120。該些導電柱14〇的形成可利用 孔製作技術實現。該凸塊在晶背之半導體晶片構造 可另包含一鈍化層（passivati〇n iayer)15〇,其係形 該主動表面1U上，用以保護在該主動表面nl的 電路’達到絕緣處理。具體而言，如第1圖所示， 塊在晶背之半導體晶片構造100可另包含一介 的高 凸塊 材質 丨效。 (113 應力 具有 半導 設置 該些 或銅 上積 130 晶片 該半 '13〇 矽通 1 0〇 成於 積體 該凸 電層 200947649 (dielectric layer) 160’其係形成在該些凸塊主體113與 該導電材料120之間。該介電層160係可為一氧化層或 一絕緣沉積層。 本發明進一步說明該凸塊在晶背之半導體晶片構造 1〇〇之製造方法，以彰顯本案的功效。第2A至2F圖係 為製程中元件截面示意圖。 首先，如第2A圖所示，提供一半導體基板110，其 係具有一主動表面111與一未薄化背面112，。該半導體 ❹ 基板1 1 0係一體形成於一晶圓内，利用積體電路製作的 晶圓製程，該半導髏基板110之該主動表面111係已設 有複數個銲墊130。在本實施例中，該些銲塾130係可 排列在該半導體基板1 1 〇之兩相對側邊或周邊，以避免 與積體電路形成區域產生重疊。但非限定地，該些鲜塾 1 3 0亦可為矩陣排列。具體而言’該主動表面n丨上係 可形成一鈍化層150’其材質例如為氮化矽或磷矽玻璃 〇 (PSG) ’該鈍化層150係可具有複數個開口 151，以顯 露該些銲墊1 30。 接著’如第2B圖所示’選擇性蝕刻該半導體基板 110之該未薄化背面112’，以形成一使該半導體基板 110厚度減少之薄化背面112，並同時在該背面112上 一體形成有複數個與該半導體基板11〇相同材質的凸 塊主體113。具體而言，如第2B圖所示，進行晶圓製 程的選擇性蚀刻技術使該半導體基板11〇厚度減少至 一適當厚度’一般約為30/zm至100#^，並同時選擇 12 200947649 性蝕刻形成該些凸塊主體丨13，故可省去習知在晶圓製 程之後的凸塊製作並節省凸塊的金屬使用量。其中選 擇性蝕刻技術，係可為曝光顯影後的化學蝕刻、電漿蝕 刻或是反應性離子蝕刻。此外，可以省略習知的晶背研 磨步驟。此外，如第2B圖所示，由於該些銲墊13〇係 可對準於該些凸塊主體113，該些凸塊主體113之數量 可概等於該些銲墊130之數量，不需要另外製作重配置 @ 線路層（RDL)，減少製作成本與流程。另外，該些凸塊 主體113係可具有一尺寸小於該些銲墊ι3〇之凸起平面 113A，在進行多個半導體基板11〇堆疊時，該凸起平面 113A可對位接合至在另一半導體基板11〇上之該些銲 墊 130。 之後，如第2C圖所示，可利用雷射或微機電加工 (MEMS bulk machining)製程於每一凸塊主體113形成 至少一孔洞1 1 3B。該些孔洞i丨3B係可形成於對應該些 φ 凸塊主體1 1 3之中心位置，以防止溫度上昇或溫度循環 過程，形成不當裂痕或斷裂。該些孔洞113B係貫穿該 些凸塊主體113以及該半導體基板11〇並連通到該些銲 墊130。但不受限地’該些孔洞U3B係可貫穿或不可 貫穿該些銲墊130。 之後，如第2D圖所示，形成一介電層16〇在該些凸 塊主體113與該導電材料12〇之間。在本實施例中，該 介電層160更形成在該半導體基板11〇之該背面112、 該些凸塊主體113之該凸起平面U3A及該孔洞U3B， 13 200947649 _藉此完成該半導體基板110的表面絕緣處理。該介電層 1 60係為、絕緣材料，例如二氧化妙。該介電層16〇的 形成方法係可選自於晶圓製程的矽氧化處理或是化學 汽相沉積。 之後，如第2E圖所示，形成複數個導電柱14〇於該 孔词 中5玄些導電柱140之一端係接合至該些銲 塾130。在本實施例中，係利用電鑛（Plating)或塞孔沉 ❹積方式將銅或其它導電金屬填入該孔洞u3B中以形 成該些導電柱14〇’但也可以利用打線、針插接等方式 形成該些導電柱14〇。 最後，如第2F圖所示，形成導電材料12〇於該些凸 塊主體113之凸起平面U3A上，並藉由該些導電柱"ο 電性連接該些銲墊13G至料電材料ιΐ3，使該半導體 f板110具有雙面電性導通並貫穿凸塊之特性。具體而 言，該導電材料12G係可為單層或複合之金屬層。在本 ❹實施例中，該導電材料12〇之最外表面層係可為一金 層，並且較佳地，如第i圖所示，可在該些鲜塾13〇上 形成一錫層170。在應用於多晶片堆疊產品時，複數個 凸塊在晶背之半導體晶片構造1〇〇相互堆疊，該些凸塊 主體113上該導電材料120可對位接合至該些銲墊13〇 上的錫層170,以達成金錫共晶。（如第3圖所示） 因此，本發明之凸塊主體113的形成方法係整合於 晶圓製程，可達降低製程複雜度及增加量產速度之功 效0 14 200947649 第3圖係為運用複數個如第一具體實施例所述之凸 塊在晶背之半導體晶片構造100堆疊組成之一種晶片 堆叠組合構造。該晶片堆疊組合構造更係包含一線路載 板1 0。其中該些凸塊在晶背之半導體晶片構造100係 相互堆疊並設置於該線路載板10上。該線路載板10係 可為印刷電路板、電路薄膜、陶瓷基板、玻璃基板或是 導線架等等。在本實施例中，該線路載板1 〇係具有複 數個連接墊11以及複數個外接墊1 2。在本實施例中， 〇 該些連接墊11係設於該線路載板1〇之複數個凹槽13 内。而位於底層之一凸塊在晶背之半導體晶片構造1〇〇 之該些凸塊主體113係嵌陷於該線路載板10之該些凹 槽13，並且該些凸塊主體113上的導電材料120係接 合至該些連接墊 Π，可降低整體多晶片堆疊之高度並 具封裝薄化之功效《具體而言，如第3圖所示，該些凸 塊在晶背之半導體晶片構造1 〇〇之間的堆疊係以該導 ❹ 電材料120與該錫層170的結合達到電性互連。一半導 體晶片構造100之銲墊130係透過該些導電柱140與該 導電材料120電性連接至另一半導體晶片構造1〇〇之銲 塾13〇’以提供較佳的垂直電性傳導路徑。並且該些凸 塊在晶背之半導體晶片構造1 0 0毋須另外設置外接凸 塊亦毋須打線形成銲線，即可完成多晶片之3D立體堆 疊。 此外’由於該些凸塊主體113與該半導體基板110 為相同材質且一體形成，故在溫度變化時或溫度循環過 15 200947649 程，不會有膨脹係數不匹配之問題，而達到晶片與凸塊 之間為零應力或較低應力的組成。詳細而言，如第3圖 所示，該晶片堆疊組合構造可另包含一封膠體2〇,該 封膠體20係密封該些凸塊在晶背之半導體晶片構造 1 00以提供適當的封裝保護以防止電性短路與塵埃污 染。此外，該晶片堆疊組合構造可另包含有複數個外接 端子30，該些外接端子30係包含銲球（s〇ider bau)，其 ❹ 係設置於該些外接墊12上。在不同實施例中，可利用 錫膏、金屬球或金屬針置換銲球而成該些外接端子3〇。 依據本發明之第二具體實施例，另一種凸塊在晶背 之半導體晶片構造說明於第4圖之截面示意圖。 如第4圖所示，該凸塊在晶背之半導體晶片構造2〇〇 主要包含一半導體基板210。該半導體基板210係具有 一主動表面211與一背面212，該背面212上一體形成 有複數個與該半導體基板210相同材質的凸塊主體 ❷ 213 ’並在該些凸塊主體213上形成導電材料220。 具體而言，如第4圖所示’該凸塊在晶背之半導體 晶片構造200可另包含有複數個銲墊230以及複數個位 置對應之晶背銲墊240，該些銲墊230係設置於該主動 表面2 1 1，該些晶背銲墊2 4 0係形成在該些凸塊主體2 1 3 之一凸起平面213A與該導電材料220之間。該些凸塊主 體213之凸起平面213A之尺寸概等於或小於該些銲塾 230。該些銲墊230與該些晶背銲墊240係可為導電金 屬材質，例如銘、銅、銘合金或銅合金之中的任一者所 16 200947649 製成。 該凸塊在晶背之车道 半導體晶片構造200可另包含一姑 化層250，其係形成 ^ ;〜主動表面211上，並具有複數 個開口 251，以顯霡咕^ ^ 顯露該些銲墊230。一介電層26〇係形 成在該些凸塊主體2iq命#描 ® U3與該導電材料22〇之 而言，該介電層260係报^ '、形成在該些凸塊主體213與該此 晶背銲墊24〇之間，該 、二 導電材料220係結合於該此晶背 銲墊 240。呈體而^ ~ ^ ❹ 八體而S ，該導電材料22〇係可為銲料 (solder) 〇 如第4圖所示’複數個孔洞213B係貫穿對應之該些 凸塊主體213與該半導體基板⑴。在本實施例中，該 孔洞㈣係更貫穿該些銲墊⑽與該些晶背鲜塾 240。較佳地，該導電材料22()係除了形成於該些凸塊 主體213之凸起平面2nA丨，更可填充人該些孔洞 213B並附著於該些銲墊23〇。可利用銲料射出 jetting)或印刷（printing)製程將該導電材料22〇注入該 孔洞2 1 3B，達到雙面電性導通並貫穿凸塊的型態，以 節省凸塊製程。在多晶片堆疊時，該導電材料MO可藉 由回焊達到上下晶片的接合，並且該些凸塊主體213的 形狀不會改變。 本發明之第二具體實施例揭示另一種凸塊在晶背之 半導體晶片構造。如第5圖所示，該凸jt鬼在晶背之半導 體晶片構造300主要包含一半導體基板31〇。該半導體 基板310係具有一主動表面311與一背面312。該背面 17 200947649 3 12上一體形成有複數個與該半導體基板31〇相同材質 的凸塊主體313，並在該些凸塊主體313上形成導電材 料320。該半導體基板310與導電材料32〇大致與第一 實施例相同的半導體基板110與導電材料12〇,不再細加 贅述。 如第5圖所示，該凸塊在晶背之半導體晶片構造3〇〇 可另包含有複數個銲墊330’其係設置於該主動表面 ❹ 311並電性連接至該導電材料320。在一具體結構中， 該些銲墊330係對準於該些凸塊主體313。該凸塊在晶 背之半導體晶片構造3 00可另包含有複數個導電柱 3 40,其係貫穿該半導體基板31〇與該些凸塊主體313, 以連接該些銲墊330與該導電材料32〇。一鈍化層35〇 係可形成於該主動表面311上，並具有複數個開口 351’以顯露該些銲墊330。一介電層3 6〇係形成在該 些凸塊主體313與該導電材料32〇之間。 ⑩ 再如第5圖所示，較佳地，一異方性導電膠膜370 係形成於該主動表面311上。該異方性導電膝膜37〇内 含有等球徑之導電粒子371 ^如第6圖所示，在進行複 數個上述凸塊在晶背之半導體晶片構造3〇〇堆疊時，該 異方性導電膠膜370係形成於該些凸塊在晶背之半導 體晶片構造300之間。該些凸塊主體313可經由導電粒 子371電性連接至該些銲墊33〇，可不與該些銲墊33〇 直接焊接。在本實施例中，該異方性導電膠膜37〇係預 先形成於該半導體基板310之該主動表面311的上方， 18 330 ° 200947649 其係貼附於該鈍化層350並覆蓋該些銲塾 因此，如第6圖所示，在一種晶片堆疊 複數個如上所述之凸塊在晶背之半導體 係相互堆疊並設置於一線路載板40上 中’該線路載板40上表面係具有複數個^ 供該導電材料320的電性連接。在本實施 之凸塊在晶背之半導體晶片構造3〇〇可 方性導電膠膜370，而最下層之該凸塊在 ® 晶片構造300與該線路載板40之間則另 性導電膠膜5 0。 具體而言，垂直的電性傳導路徑係由 構造300的該些銲墊33〇經由其導電材料 至位於該些凸塊主體313與另一下方半 3〇0的銲墊33〇之間的導電粒子371，再 晶片構造300的銲墊330。該些凸塊在晶 φ 片構造300毋須另外設置外接凸塊與毋須 可完成多晶片之3D立體堆疊。 因此，由於該些凸塊主體313與該半 為相同材質，故在溫度變化時或溫度循環 膨脹係數不匹配之問題，可達到零應力或 接合° 以上所述，僅是本發明的較佳實施例 本發明作任何形式上的限制，本發明技術 所附申請專利範圍為準。任何熟悉本專業 組合構造中， 晶片構造 300 。在本實施例 惠接墊41，以 例中，最上層 不須形成該異 晶背之半導體 需形成一異方 一半導體晶片 3 2 0電性連接 導體晶片構造 到下層半導體 背之半導體晶 形成銲線，即 導體基板310 過程，不會有 較低之應力之 而已，並非對 方案範圍當依 的技術人員可 19 200947649 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例’但凡是未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 單修改等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：為依據本發明第一具體實施例的一種凸塊在晶The second object of the present invention is to provide a method for fabricating a semiconductor wafer structure in which a bump is formed on a crystal back. The formation of the bump is integrated into the wafer process, which has the effect of saving the amount of metal of the bump and simplifying the bump process. Another object of the present invention is to provide an application of a bump in a semiconductor wafer structure of a crystal back, which can be applied to high-density multi-wafer stacking, preventing punching and achieving the effect of thinning a stacked product. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a bump is half of the crystal back = wafer structure. The wafer structure mainly comprises a semiconductor substrate. The conductor substrate ' has an active surface and a back surface, and is characterized in that a plurality of the same material and a bulk body are formed on the back surface, and a conductive material is formed on the bump bodies. The object of the present invention and solving the technical problems thereof can be further realized by the following techniques. The bumps described in the oysters are in the semi-conductive right-body wafer structure of the crystal back, and the other dad 3 has a plurality of pads, which are disposed on the conductive material. Active Surface and Electrical Connections 3 In the semiconductor wafer construction of the aforementioned bumps in the back of the crystal back, the plurality of turns can be aligned with the bump bodies. 7 200947649 In the foregoing semiconductor wafer structure of the bump in the crystal back, a plurality of conductive pillars may be further included, which penetrate the semiconductor substrate and the bump bodies to connect the pads and the conductive material. In the foregoing semiconductor wafer structure in which the bump is in the crystal back, a passivation layer may be further included on the active surface. In the foregoing semiconductor wafer construction in which the bumps are in the crystal back, the passivation layer may have a plurality of openings to expose the pads. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, a dielectric layer may be further included between the bump bodies and the conductive material. In the foregoing semiconductor wafer structure in which the bump is in the crystal back, the conductive material may be a metal layer. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the metal layer of the conductive material may be a gold layer, and a tin layer is formed on the pads. H. In the foregoing semiconductor wafer structure in which the bump is in the crystal back, an anisotropic conductive film may be further included on the active surface. In the foregoing semiconductor wafer construction in which the bumps are in the crystal back, the conductive material may be solder. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the height of the bump bodies may be approximately equal to or greater than the thickness of the semiconductor substrate. In the foregoing semiconductor wafer structure in which the bumps are in the crystal back, the bump main systems may have a convex plane smaller than the pads. 8 200947649 In the foregoing semiconductor wafer structure of the crystal back, a plurality of crystal back pads may be further disposed between the protrusions of the bump body and the conductive material. The position corresponds to the solder fillets. The present invention also discloses a method of fabricating a semiconductor wafer structure suitable for use in the above-described bumps. The main steps include: first, providing a half-conductor substrate having an active surface and an unthinned back surface. Then, the unthinned back surface of the semiconductor substrate is selectively etched to form a thinned back surface which reduces the thickness of the semiconductor substrate, and at the same time, a plurality of convexities of the same material as the semiconductor substrate are formed on the back surface. Block body. Finally, a conductive material is formed on the bump bodies. The present invention further discloses a wafer stack assembly structure suitable for the aforementioned semiconductor wafer structure of a bump in a crystal back, which comprises a plurality of semiconductor wafer structures of the above-mentioned bumps in a crystal back and a line carrier, wherein the & The blocks are stacked on the semiconductor wafer structure of the crystal back and disposed on the line carrier. It can be seen from the above technical solutions that the bump of the present invention has the following advantages and effects in the semiconductor wafer structure of the crystal back, its manufacturing method and its application: - the same material and the same material as the semiconductor substrate by the main block system of the bump On the back side of the wafer, the zero stress between the wafer and the bump can be achieved and the external stress can be directly applied to the active surface of the wafer, and the electrical conduction path is short and the wafer is thinned. Second, the wafer process is selectively etched on the back side of the wafer to form the bump body of the semiconductor material, thereby achieving the metal for saving bumps. 9 200947649 Block process 罝 'Bump fabrication is integrated into the wafer process to simplify the convex effect . Aligning the bump pads of the wafer with the bump body of the semiconductor material and penetrating the semiconductor substrate and the bump bodies with the conductive pillars so that the two semiconductor wafers in the crystal back are capable of applying high-density multi-wafer stacking to prevent Rush the line and achieve the effect of thinning the stacked products. [Embodiment] φ According to a first embodiment of the present invention, a semiconductor wafer structure in which a bump is on a crystal back is illustrated in a cross-sectional view of Fig. i. As shown in Fig. 1, the semiconductor wafer structure 1 of the bump in the crystal back mainly includes a semiconductor substrate 110. The 35 semiconductor substrate 110 has an active surface 1U and a back surface 112. Generally, the semiconductor substrate no j is provided with integrated circuit components on its active surface 111, such as a microcontroller, a microprocessor, a memory, a logic circuit, a special application integrated circuit (such as a display driving circuit), or the like. . The present invention is characterized in that the back surface 112 is formed with a plurality of bump bodies 113 of the same material as the semiconductor substrate, and the heights of the bump bodies may be substantially the same as the thickness of the semiconductor substrate 11 . The shape of the bump main bodies 113 may be a cylindrical shape, a square column shape or a polygonal column shape. A conductive material 12 is formed on the bump main bodies 113 as an external electrode of the integrated circuit. The conductive material 12 can be a nickel/gold layer, a titanium layer, a copper layer, a copper/titanium alloy layer or tin-lead. In this embodiment, the conductive material 120 is a copper/recording/gold layer. The thickness of the conductive material 12〇 is not more than one-half of the height of the bump body 113 protruding from the back surface ιι 2, and the thickness thereof should be less than one quarter of the height of the bump body 113 degrees. The bump body 11 3 occupies the entire volume at more than sixty percent, so that the bump can exhibit the thermal expansion coefficient of the semiconductor, and the zero stress between the wafer and the bump is achieved, and the semiconductor substrate is 1 凸 The same material of the bump main Cui protrudes from the back surface 112 of the semiconductor substrate 110, to avoid externally acting directly on the active surface 111 of the semiconductor substrate 110, and the electrical conduction path is short and the wafer is thinned. Specifically, as shown in FIG. 1 , the bulk wafer structure 100 of the bump may further include a plurality of pads 130 attached to the active surface 111 and electrically connected to the conductive material 丨 20 . . The solder fillet 130 is made of a conductive metal material such as any one of the indium, copper, and alloy alloys, which is the same surface electrode of the active surface ηι body circuit. In the present embodiment, the solder joints are aligned with the bump bodies 113. In addition, as shown in FIG. 1 , the semiconductor structure 100 of the bump in the crystal back may further include a plurality of conductive pillars 140 extending through the conductor substrate 11 and the bump bodies 113 to connect the solders. The conductive material 120 is twisted. The formation of the conductive pillars 14A can be achieved by hole fabrication techniques. The semiconductor wafer structure of the bump in the crystal back may further comprise a passivation layer 15 〇 on the active surface 1U for protecting the circuit 'on the active surface n1 from the insulating process. Specifically, as shown in Fig. 1, the semiconductor wafer structure 100 of the wafer in the crystal back may further comprise a high-bump material. (113 stress has a semi-conductive setting or a copper-on-wafer 130-wafer. The half-13 is formed in the integrated body. The bumper layer 200947649 (dielectric layer) 160' is formed in the bump bodies 113. The dielectric layer 160 can be an oxide layer or an insulating deposition layer. The present invention further describes a method for manufacturing the bump in the semiconductor wafer structure of the crystal back to demonstrate the present case. 2A to 2F are schematic cross-sectional views of components in the process. First, as shown in Fig. 2A, a semiconductor substrate 110 is provided having an active surface 111 and an unthinned back surface 112. The semiconductor germanium substrate The 1 1 0 system is integrally formed in a wafer, and the active surface 111 of the semiconductor substrate 110 is provided with a plurality of pads 130 by using a wafer process made by an integrated circuit. In this embodiment, The solder pads 130 may be arranged on opposite sides or the periphery of the semiconductor substrate 1 1 to avoid overlapping with the integrated circuit forming regions. However, the non-limiting pixels may also be arranged in a matrix. Specifically, the master A passivation layer 150' may be formed on the surface of the surface, such as tantalum nitride or phosphoric glass crucible (PSG). The passivation layer 150 may have a plurality of openings 151 to expose the pads 1 30. 'Selectively etching the unthinned back surface 112' of the semiconductor substrate 110 as shown in FIG. 2B to form a thinned back surface 112 which reduces the thickness of the semiconductor substrate 110, and at the same time integrally formed on the back surface 112 a plurality of bump bodies 113 of the same material as the semiconductor substrate 11A. Specifically, as shown in FIG. 2B, a selective etching technique for performing a wafer process reduces the thickness of the semiconductor substrate 11 to a suitable thickness. It is about 30/zm to 100#^, and at the same time, 12 200947649 etching is used to form the bump bodies 13 , so that the conventional bump fabrication after the wafer process can be omitted and the metal usage of the bumps can be saved. The selective etching technique may be chemical etching, plasma etching or reactive ion etching after exposure and development. Further, the conventional crystal back grinding step may be omitted. Further, as shown in FIG. 2B, Solder pad The 〇 can be aligned with the bump bodies 113. The number of the bump bodies 113 can be substantially equal to the number of the pads 130. It is not necessary to separately fabricate the reconfigurable @circuit layer (RDL) to reduce the manufacturing cost and In addition, the bump main bodies 113 may have a convex plane 113A smaller in size than the solder pads ι3, and the bump planes 113A may be aligned to be bonded when a plurality of semiconductor substrates 11 are stacked. The other pads 110 are mounted on the other semiconductor substrate 11. Thereafter, as shown in FIG. 2C, at least one hole 1 1 may be formed in each of the bump bodies 113 by a laser or MEMS bulk machining process. 3B. The holes i 丨 3B may be formed at positions corresponding to the center of the φ bump main body 1 1 3 to prevent temperature rise or temperature cycling, forming improper cracks or fractures. The holes 113B extend through the bump bodies 113 and the semiconductor substrate 11 and communicate with the pads 130. However, the holes U3B may or may not penetrate through the pads 130. Thereafter, as shown in Fig. 2D, a dielectric layer 16 is formed between the bump bodies 113 and the conductive material 12A. In this embodiment, the dielectric layer 160 is further formed on the back surface 112 of the semiconductor substrate 11 , the convex plane U3A of the bump main bodies 113 , and the hole U3B , 13 200947649 — thereby completing the semiconductor substrate 110 surface insulation treatment. The dielectric layer 1 60 is an insulating material such as oxidizing. The dielectric layer 16 is formed by a bismuth oxidation process or a chemical vapor deposition process in a wafer process. Thereafter, as shown in Fig. 2E, a plurality of conductive pillars 14 are formed, and one end of the conductive pillars 140 are joined to the solder bumps 130. In this embodiment, copper or other conductive metal is filled into the hole u3B by using a plating or plugging method to form the conductive pillars 14' but it is also possible to use wire bonding and needle insertion. The conductive pillars 14 are formed in an equal manner. Finally, as shown in FIG. 2F, the conductive material 12 is formed on the convex plane U3A of the bump main body 113, and the conductive pads are electrically connected to the electrical material by the conductive pillars. Ϊ́3, the semiconductor f-plate 110 has the characteristics of being electrically conductive on both sides and penetrating through the bumps. Specifically, the conductive material 12G may be a single layer or a composite metal layer. In the embodiment of the present invention, the outermost surface layer of the conductive material 12 can be a gold layer, and preferably, as shown in the first drawing, a tin layer 170 can be formed on the fresh enamel 13 〇. . When applied to a multi-wafer stack product, a plurality of bumps are stacked on each other in a semiconductor wafer structure 1 on the back, and the conductive material 120 is oppositely bonded to the pads 13 on the bump bodies 113. Tin layer 170 to achieve gold tin eutectic. (As shown in FIG. 3) Therefore, the method for forming the bump main body 113 of the present invention is integrated into the wafer manufacturing process, thereby reducing the complexity of the process and increasing the mass production speed. 0 14 200947649 The third figure is the application of the plural A wafer stack assembly structure in which the bumps as described in the first embodiment are stacked on the back of the semiconductor wafer structure 100. The wafer stack assembly structure further includes a line carrier 10. The bumps are stacked on the back of the semiconductor wafer structure 100 and disposed on the line carrier 10. The line carrier 10 can be a printed circuit board, a circuit film, a ceramic substrate, a glass substrate or a lead frame or the like. In the present embodiment, the line carrier 1 has a plurality of connection pads 11 and a plurality of external pads 12. In this embodiment, the plurality of connection pads 11 are disposed in the plurality of grooves 13 of the line carrier 1 . The bump main bodies 113 of the semiconductor wafer structure 1 of the bottom layer are embedded in the recesses 13 of the circuit carrier 10, and the conductive materials on the bump main bodies 113 The 120 series bonding to the connection pads reduces the height of the overall multi-wafer stack and has the effect of thinning the package. Specifically, as shown in FIG. 3, the bumps are in the semiconductor wafer structure of the crystal back. The stack between the turns is electrically interconnected by the bonding of the conductive material 120 to the tin layer 170. The solder pads 130 of the half-conductor wafer structure 100 are electrically connected to the conductive material 120 through the conductive pillars 140 to the solder pads 13' of another semiconductor wafer structure to provide a better vertical electrical conduction path. Moreover, the bumps are formed in the semiconductor wafer structure of the crystal back. No additional external bumps are required, and no wire bonding is required to form a bonding wire, so that the multi-chip 3D stacking can be completed. In addition, since the bump main bodies 113 and the semiconductor substrate 110 are formed of the same material and are integrally formed, when the temperature changes or the temperature cycles through 15 200947649, there is no problem that the expansion coefficient does not match, and the wafer and the bump are reached. Composition between zero or lower stress. In detail, as shown in FIG. 3, the wafer stack assembly structure may further comprise a glue body 2, which seals the bumps in the crystal back semiconductor wafer structure 100 to provide proper package protection. To prevent electrical short circuit and dust pollution. In addition, the wafer stack assembly structure may further include a plurality of external terminals 30, the external terminals 30 including solder balls disposed on the external pads 12. In various embodiments, the solder balls may be replaced by solder paste, metal balls or metal pins to form the external terminals 3〇. In accordance with a second embodiment of the present invention, another type of bump in a crystal back semiconductor wafer configuration is illustrated in cross-section in FIG. As shown in Fig. 4, the semiconductor wafer structure 2 of the bump in the crystal back mainly comprises a semiconductor substrate 210. The semiconductor substrate 210 has an active surface 211 and a back surface 212. The back surface 212 is integrally formed with a plurality of bump bodies 213 ′ of the same material as the semiconductor substrate 210 and conductive materials are formed on the bump bodies 213 . 220. Specifically, as shown in FIG. 4, the semiconductor wafer structure 200 of the bump in the crystal back may further include a plurality of pads 230 and a plurality of positions corresponding to the crystal back pads 240, and the pads 230 are disposed. The active back surface 2 1 1 is formed between one of the convex planes 213A of the bump main bodies 2 1 3 and the conductive material 220. The convex planes 213A of the bump main bodies 213 are substantially equal to or smaller than the solder pads 230. The pads 230 and the back pads 240 may be made of a conductive metal material such as Ming, Bronze, Ming alloy or copper alloy 16 200947649. The bump in the crystal back of the semiconductor wafer structure 200 may further include a guillotine layer 250 formed on the active surface 211 and having a plurality of openings 251 to reveal the pads. 230. A dielectric layer 26 is formed on the bump body 2i and the conductive material 22, and the dielectric layer 260 is formed on the bump body 213 and Between the crystal back pads 24 , the two conductive materials 220 are bonded to the crystal back pads 240 . The body of the conductive material 22 can be a solder. As shown in FIG. 4, a plurality of holes 213B penetrate through the corresponding bump bodies 213 and the semiconductor substrate. (1). In the present embodiment, the holes (4) extend through the pads (10) and the crystal clear crucibles 240. Preferably, the conductive material 22() is formed on the convex plane 2nA of the bump main body 213, and further fills the holes 213B and adheres to the pads 23A. The conductive material 22 can be injected into the hole 2 1 3B by a solder shot or printing process to achieve double-sided electrical conduction and through the bump shape to save the bump process. When the multi-wafer is stacked, the conductive material MO can be joined to the upper and lower wafers by reflow, and the shape of the bump bodies 213 does not change. A second embodiment of the present invention discloses another semiconductor wafer construction in which the bumps are in the crystal back. As shown in Fig. 5, the semiconductor wafer structure 300 of the convex jt ghost in the crystal back mainly comprises a semiconductor substrate 31. The semiconductor substrate 310 has an active surface 311 and a back surface 312. The back surface 17 200947649 3 12 is integrally formed with a plurality of bump bodies 313 of the same material as the semiconductor substrate 31, and a conductive material 320 is formed on the bump bodies 313. The semiconductor substrate 310 and the conductive material 32 are substantially the same as the semiconductor substrate 110 and the conductive material 12 of the first embodiment, and will not be further described. As shown in FIG. 5, the semiconductor wafer structure 3 of the bump may further include a plurality of pads 330' disposed on the active surface 311 and electrically connected to the conductive material 320. In a specific structure, the pads 330 are aligned with the bump bodies 313. The semiconductor wafer structure 300 of the bump in the crystal back may further include a plurality of conductive pillars 340 extending through the semiconductor substrate 31 and the bump bodies 313 to connect the pads 330 and the conductive material. 32〇. A passivation layer 35 can be formed on the active surface 311 and has a plurality of openings 351' to expose the pads 330. A dielectric layer 36 is formed between the bump bodies 313 and the conductive material 32A. Further, as shown in FIG. 5, preferably, an anisotropic conductive film 370 is formed on the active surface 311. The anisotropic conductive knee film 37 含有 contains conductive particles 371 having equal spherical diameter. As shown in FIG. 6, the anisotropy is performed when a plurality of the above-mentioned bumps are stacked on the semiconductor wafer structure of the crystal back. A conductive adhesive film 370 is formed between the bumps and the semiconductor wafer structure 300 of the crystal back. The bump bodies 313 can be electrically connected to the pads 33 via the conductive particles 371, and can be directly soldered to the pads 33A. In this embodiment, the anisotropic conductive film 37 is pre-formed on the active surface 311 of the semiconductor substrate 310, and 18 330 ° 200947649 is attached to the passivation layer 350 and covers the solder pads. Therefore, as shown in FIG. 6, in a wafer stack, a plurality of bumps as described above are stacked on the back of the semiconductor system and disposed on a line carrier 40. The upper surface of the line carrier 40 has a plurality of The electrical connection of the conductive material 320 is provided. In the present embodiment, the bump is formed on the semiconductor wafer of the crystal back, and the lowermost layer of the bump is between the wafer structure 300 and the line carrier 40. 5 0. Specifically, the vertical electrical conduction path is conducted by the pads 33 of the structure 300 via their conductive materials to the conductive between the bump bodies 313 and the pads 33 〇 of the other lower half 3〇0. Particle 371, pad 330 of re-wafer construction 300. The bumps in the crystal φ sheet construction 300 need not be additionally provided with external bumps and whiskers to complete the 3D stereo stacking of the multi-wafer. Therefore, since the bump main bodies 313 and the half are the same material, the problem of zero temperature stress or bonding can be achieved when the temperature changes or the temperature cycle expansion coefficient does not match, and the present invention is only a preferred embodiment of the present invention. EXAMPLES The present invention is to be limited in any form, and the scope of the appended claims is incorporated by reference. Any familiarity with the professional combination construction, wafer construction 300. In the embodiment, the splicing pad 41, for example, the uppermost layer does not need to form the semiconductor of the hetero-crystalline back, and a semiconductor-shaped semiconductor wafer is required to be formed into a semiconductor wafer. The wire, that is, the process of the conductor substrate 310, does not have a lower stress, and the skilled person who is not dependent on the scope of the solution can make a slight change or modify the equivalent embodiment of the equivalent change by using the technical content disclosed above. However, any simple modifications and modifications of the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a bump in a crystal according to a first embodiment of the present invention.
背之半導體晶片構造之截面示意圖。 第2A至2F圖：為依據本發明第—具體實施例在該凸 塊在晶背之半導體晶片構造的製程中元件截 面示意圖。 第3圖 為依據本發明第一具體實施例的利用複數個凸 塊在晶背之半導體晶片構造組成的一種晶片 堆疊組合構造之截面示意圖。 第4圖：為依據本發明第二具體實施例的—種凸塊在晶 背之半導體晶片構造之截面示意圖。 第5圖：為依據本發明第三具體實施例 背之半導體晶片構造之截面示意：。凸塊在明 為依據本發明第三具體實施例的利用複數個凸 塊在晶背之半導體晶片構造組成的晶片堆疊 【主要元件符號說明 ] 10線路載板 11 連接墊 13凹槽 20 封膠體 20 12外接墊 30外接端子 200947649A schematic cross-sectional view of a semiconductor wafer structure on the back. 2A to 2F are schematic cross-sectional views showing the structure of the semiconductor wafer structure in which the bump is in the crystal back according to the first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing a wafer stack assembly structure of a semiconductor wafer structure using a plurality of bumps in a crystal back according to a first embodiment of the present invention. Figure 4 is a cross-sectional view showing the structure of a semiconductor wafer in which the bumps are on the back side in accordance with the second embodiment of the present invention. Figure 5 is a cross-sectional view showing the structure of a semiconductor wafer according to a third embodiment of the present invention: The bump is a wafer stack composed of a semiconductor wafer structure using a plurality of bumps in a crystal back according to a third embodiment of the present invention. [Main component symbol description] 10 line carrier 11 connection pad 13 recess 20 encapsulant 20 12 external mat 30 external terminal 200947649
40 線路載板 41 連接墊 50 異方性導電膠 膜 100 凸塊在晶背之半導體晶片構 造 110 半導體基板 111 主動表面 112 背 面 112, 未薄化背面 113 凸塊主體 113A凸起平面 113B 1孑L洞 120 導電材料 130 銲墊 140 導 電柱 150 鈍化層 151 開口 160 介電層 170 錫層 200 凸塊在晶背之半導體晶片構 造 210 半導體基板 211 主動表面 212 背 面 213 凸塊主體 213A凸起平面 213E 1孔洞 220 導電材料 230 銲墊 240 晶 背銲墊 250 鈍化層 251 開口 260 介 電層 300 凸塊在晶背之半導體晶片構 造 310 半導體基板 311 主動表面 312 背 面 313 凸塊主體 320 導電材料 330 銲墊 340 導 電柱 350 鈍化層 351 開口 360 介 電層 370 異方性導電膠膜 371 導 電粒子 2140 line carrier board 41 connection pad 50 anisotropic conductive film 100 bump in the crystal back of the semiconductor wafer structure 110 semiconductor substrate 111 active surface 112 back 112, unthinned back side 113 bump body 113A convex plane 113B 1孑L Hole 120 Conductive Material 130 Pad 140 Conductive Post 150 Passivation Layer 151 Opening 160 Dielectric Layer 170 Tin Layer 200 Bump in Crystal Back Semiconductor Wafer Construction 210 Semiconductor Substrate 211 Active Surface 212 Back Side 213 Bump Body 213A Raised Plane 213E 1 Hole 220 Conductive Material 230 Pad 240 Crystal Back Pad 250 Passivation Layer 251 Opening 260 Dielectric Layer 300 Bump in Crystal Back Semiconductor Wafer Construction 310 Semiconductor Substrate 311 Active Surface 312 Back Side 313 Bump Body 320 Conductive Material 330 Solder Pad 340 Conductive pillar 350 passivation layer 351 opening 360 dielectric layer 370 anisotropic conductive film 371 conductive particles 21