JP5763116B2 - Manufacturing method of semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  In order to realize miniaturization and high functionality of a semiconductor device, a stacked semiconductor device in which a plurality of semiconductor chips are stacked and sealed in one package has been put into practical use. A stacked semiconductor device is required to transmit and receive electrical signals between semiconductor chips at high speed. In such a case, micro bumps are used for electrical connection between the semiconductor chips. The micro bumps have a diameter of about 5 to 50 μm, for example, and are formed on the surface of the semiconductor chip at a pitch of about 10 to 100 μm. When stacking semiconductor chips with micro-bumps, the alignment marks formed on the surface of the semiconductor chip are recognized by a camera, etc., and the upper and lower semiconductor chips are aligned based on the recognition result, and then the bumps are bonded by thermocompression bonding. Connecting.

  As a method of aligning a semiconductor chip using an alignment mark, a method of aligning a semiconductor chip to be stacked on top of the recognition result of the alignment mark formed on the surface of the lowermost semiconductor chip is known. Yes. In this case, not only the second-stage semiconductor chip but also the third and subsequent semiconductor chips are aligned with the lowermost semiconductor chip. For example, the third-stage semiconductor chip is stacked on the second-stage semiconductor chip while being aligned with the lowermost-stage semiconductor chip without recognizing the alignment mark of the second-stage semiconductor chip. The same applies to the fourth and subsequent semiconductor chips. Therefore, even if a positional deviation exceeding the allowable range occurs when bumps are connected to each other in any of the second and subsequent semiconductor chips, the positional deviation cannot be detected. Laminated. This causes an increase in the number of used semiconductor chips and a decrease in the manufacturing yield of multi-layered laminated chips.

JP 2005-175263 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress misalignment between semiconductor chips when the semiconductor chips are stacked while being connected with bump electrodes.

  The method for manufacturing a semiconductor device according to the embodiment includes a step of preparing a first semiconductor chip including a first bump electrode and a first alignment mark provided on the first surface, and a method provided on the second surface. A second bump electrode and a second alignment mark; a third bump electrode and a third alignment mark provided on a third surface opposite to the second surface; and the second bump electrode; A step of preparing a second semiconductor chip including a through electrode that electrically connects the third bump electrode, and a fourth bump electrode and a fourth alignment mark provided on the fourth surface. Preparing a third semiconductor chip; moving the second semiconductor chip onto the first semiconductor chip; and causing the first surface and the second surface to face each other; Half of Obtaining the positional information of the first alignment mark of the body chip and the second alignment mark of the second semiconductor chip moved onto the first semiconductor chip; and the first and second Based on the positional information of the alignment mark, the step of stacking the first semiconductor chip and the second semiconductor chip while aligning them, and moving the third semiconductor chip onto the second semiconductor chip A step of making the third surface and the fourth surface face each other, and the third alignment mark of the second semiconductor chip and the third semiconductor chip moved onto the second semiconductor chip Obtaining the position information of the fourth alignment mark, the position information of the first alignment mark, and the positions of the third and fourth alignment marks. Based on the distribution, and a step of laminating while aligning with the second semiconductor chip and the third semiconductor chip.

It is sectional drawing which shows the semiconductor device manufactured with the manufacturing method of embodiment. It is sectional drawing which shows the alignment process and lamination process of the 2nd semiconductor chip in the manufacturing method of the semiconductor device of embodiment. It is sectional drawing which shows the position alignment process and lamination process of the 3rd semiconductor chip in the manufacturing method of the semiconductor device of embodiment. It is sectional drawing which shows the alignment process and lamination process of the 4th semiconductor chip in the manufacturing method of the semiconductor device of embodiment. It is sectional drawing which shows the 1st semiconductor package using the semiconductor device shown in FIG. It is sectional drawing which shows the 2nd semiconductor package using the semiconductor device shown in FIG.

  Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings. First, a semiconductor device manufactured by applying the manufacturing method of the embodiment will be described with reference to FIG. A semiconductor device 1 shown in FIG. 1 includes a first semiconductor chip 2A, a second semiconductor chip 2B, a third semiconductor chip 2C, and a fourth semiconductor chip 2D. The second to fourth semiconductor chips 2B to 2D are sequentially stacked on the first semiconductor chip 2A. Here, the semiconductor device 1 in which four semiconductor chips 2 are stacked is shown, but the number of stacked semiconductor chips 2 is not limited to this. The number (stacking number) of the semiconductor chips 2 constituting the semiconductor device 1 may be three or more, and may be three or five or more.

  A first bump electrode 3A is formed on the top surface (first surface) of the first semiconductor chip 2A. A second bump electrode 4A is formed on the lower surface (second surface) of the second semiconductor chip 2B. A first alignment mark 5A is provided on the formation surface (first surface) of the first bump electrode 3A of the first semiconductor chip 2A. A second alignment mark 5B is provided on the formation surface (second surface) of the second bump electrode 4A of the second semiconductor chip 2B. The second semiconductor chip 2B is stacked on the first semiconductor chip 2A while connecting the second bump electrode 4A to the first bump electrode 3A. That is, the first semiconductor chip 2A and the second semiconductor chip 2B are electrically and mechanically connected via the connection body 6A of the first bump electrode 3A and the second bump electrode 4A. .

  A third bump electrode 3B and a third alignment mark 5C are formed on the upper surface (third surface) of the second semiconductor chip 2B. The second bump electrode 4A and the third bump electrode 3B are electrically connected via a through electrode (Through Silicon Via: TSV) 7A provided in the second semiconductor chip 2B. A fourth bump electrode 4B and a fourth alignment mark 5D are formed on the lower surface (fourth surface) of the third semiconductor chip 2C. The third semiconductor chip 2C is stacked on the second semiconductor chip 2B while connecting the fourth bump electrode 4B to the third bump electrode 3B. That is, the second semiconductor chip 2B and the third semiconductor chip 2C are electrically and mechanically connected via the connection body 6B of the third bump electrode 3B and the fourth bump electrode 4B. .

  A fifth bump electrode 3C and a fifth alignment mark 5E are formed on the upper surface (fifth surface) of the third semiconductor chip 2C. The fourth bump electrode 4B and the fifth bump electrode 3C are electrically connected via a through electrode (TSV) 7B provided in the third semiconductor chip 2C. A sixth bump electrode 4C and a sixth alignment mark 5F are formed on the lower surface (sixth surface) of the fourth semiconductor chip 2D. The fourth semiconductor chip 2D is stacked on the third semiconductor chip 2C while connecting the sixth bump electrode 4C to the fifth bump electrode 3C. That is, the third semiconductor chip 2C and the fourth semiconductor chip 2D are electrically and mechanically connected via the connection body 6C of the fifth bump electrode 3C and the sixth bump electrode 4C. . The sixth bump electrode 4C is electrically connected to the electrode 8 provided on the upper surface of the fourth semiconductor chip 2D via a through electrode (TSV) 7C.

  Examples of the combination of the bump electrode 3 (3A, 3B, 3C) and the bump electrode 4 (4A, 4B, 4C) include a combination of solder / solder, Au / solder, solder / Au, Au / Au, and the like. Examples of the solder for forming the bump electrodes 3 and 4 include Pb-free solder using an Sn alloy in which Cu, Ag, Bi, In, or the like is added to Sn. Specific examples of the Pb-free solder include Sn—Cu, Sn—Ag, Sn—Ag—Cu and the like. As a metal for forming the bump electrodes 3 and 4, Cu, Ni, Sn, Pd, Ag, an alloy containing these elements, or the like may be used instead of Au. These metal materials are not limited to a single layer film, and a laminated film of a plurality of metal materials may be used. Examples of the shape of the bump electrodes 3 and 4 include protrusion shapes such as a hemispherical shape and a columnar shape, but may be a flat shape such as a pad. Examples of the combination of the bump electrodes 3 and 4 include a combination of protrusions, a combination of a protrusion and a flat body, and the like.

  The bump electrode 3 provided on the upper surface of the lower semiconductor chip 2 (2A, 2B, 2C) and the bump electrode 4 provided on the lower surface of the upper semiconductor chip 2 (2B, 2C, 2D) are, for example, heat Or by applying pressure while applying ultrasonic waves. The bump electrode 3 and the bump electrode 4 may be connected individually or may be connected after all the semiconductor chips 2A, 2B, 2C, and 2D are stacked. When the bump electrodes 3 and 4 are connected after all the semiconductor chips 2 are stacked, the bump electrodes 3 and 4 are temporarily fixed when the semiconductor chips 2 are stacked, and the chip stack is bumped after the semiconductor chips 2 are stacked. Pressure bonding or reflow is performed at a temperature equal to or higher than the connection temperature of the electrodes 3 and 4. An underfill resin 9 is filled between the semiconductor chips 2 connected via the connection body 6 of the bump electrode 3 and the bump electrode 4. Not only when the underfill resin 9 is filled between the semiconductor chips 2, but also when the semiconductor chips 2 are stacked using a non-conductive adhesive film (NCF) or an adhesive paste (NCP) having an underfill function. Good.

  The semiconductor device 1 of the above-described embodiment is manufactured as follows, for example. A manufacturing process (stacking process) of the semiconductor device 1 will be described with reference to FIGS. 2, 3, and 4. As shown in FIG. 2A, a first semiconductor chip 2A having a first bump electrode 3A and a second semiconductor chip 2B having second and third bump electrodes 4A and 3B are prepared. A first alignment mark 5A is provided on the formation surface of the first bump electrode 3A of the first semiconductor chip 2A. A second alignment mark 5B is provided on the formation surface of the second bump electrode 4A of the second semiconductor chip 2B. Since the third semiconductor chip 2C is stacked on the second semiconductor chip 2B, the third alignment mark 5C is provided on the formation surface of the third bump electrode 3B of the second semiconductor chip 2B. Yes.

  The shape and arrangement position of the alignment mark 5 are not particularly limited. The alignment mark 5 is formed of, for example, a wiring material (Al wiring forming material or the like) formed on the outermost surface of the semiconductor chip 2 or a bump electrode 3 (4) forming material. When the alignment mark 5 is formed of a wiring material, a rectangular mark, a mark hollowed into a rectangular shape, or the like is used as the alignment mark 5. When the alignment mark 5 is formed of the material for forming the bump electrode 3 (4), the bump electrode is arranged in a unique pattern different from the surrounding and used as the alignment mark 5. The alignment mark 5 is preferably formed at at least one of the four corners of the rectangular semiconductor chip 2, for example, and further at two locations on the diagonal line of the four corners or at two locations corresponding to both ends of one outer side. More preferably, it is formed.

  1 to 4 show the state in which the alignment marks 5 are formed at both ends of one outer side of the semiconductor chip 2 for convenience, but the same applies when the alignment marks 5 are formed at two diagonal positions. It is. Hereinafter, the alignment process and the stacking process of the semiconductor chip 2 will be described based on the drawings in which the alignment marks 5 are formed on both ends of one outer side of the semiconductor chip 2. When the mark 5 is formed, the alignment process and the stacking process of the semiconductor chip 2 are performed in the same manner. Therefore, the alignment process and the lamination process described below can be applied to the alignment mark 5 formed at any position.

  As shown in FIG. 2A, the second semiconductor chip 2B sucked and held by the bonding head 12 is moved above the first semiconductor chip 2A placed on the stage 11 and sucked and held. . The second semiconductor chip 2B has a surface on which the second bump electrode 4A and the second alignment mark 5B are formed, and a surface on which the first bump electrode 3A and the first alignment mark 5A are formed on the first semiconductor chip 2A. Make them face each other. The first alignment mark 5A of the first semiconductor chip 2A and the second alignment mark 5B of the second semiconductor chip 2B moved onto the first semiconductor chip 2A are recognized by an image recognition device such as a camera 13. The coordinates are acquired as the position information of the first and second alignment marks 5A and 5B.

Based on the coordinates indicating the positions of the first and second alignment marks 5A and 5B, the second semiconductor chip 2B is aligned with the first semiconductor chip 2A. Specifically, the coordinates (x ₁₁ , y ₁₁ ) and the coordinates (x ₁₂ , y ₁₂ ) of the first mark in the first alignment mark 5A and the coordinates of the first mark in the second alignment mark 5B. (X ₂₁ , y ₂₁ ) and the coordinates (x ₂₂ , y ₂₂ ) of the second mark, and the difference ((x ₁₁ , y ₁₁ ) and (x ₂₁ , y ₂₁ ) between the coordinates of the first mark ) And the difference between the coordinates of the second mark (difference between (x ₁₂ , y ₁₂ ) and (x ₂₂ , y ₂₂ )) are minimized, respectively. Adjustment is made in the xy coordinate direction and the rotation direction (θ direction). Here, to minimize the maximum value of the difference between the corresponding marks is minimum (for example, the difference between the coordinates of the first mark and the difference between the coordinates of the second mark, whichever is larger is the minimum). Or the sum of the differences between the corresponding marks means the minimum. Then, as shown in FIG. 2 (b), the aligned second semiconductor chip 2B is stacked on the first semiconductor chip 2A while the second bump electrode 4A is in contact with the first bump electrode 3A. To do.

  Next, the second semiconductor chip 2B is heated while being heated to a temperature equal to or higher than the connection temperature of the first and second bump electrodes 3A and 4A, or while applying ultrasonic waves to the first and second bump electrodes 3A and 4A. Is pressure-bonded to the first semiconductor chip 2A. In such a crimping process, the first bump electrode 3A and the second bump electrode 4A are connected. The connection temperature of the bump electrodes 3A and 4A is a temperature equal to or higher than the melting point of the used solder when at least one of the bump electrodes 3A and 4A is formed of solder. Here, a case where the first bump electrode 3A and the second bump electrode 4A are connected when the first semiconductor chip 2A and the second semiconductor chip 2B are stacked will be described. 2 may be temporarily fixed between the bump electrodes 3A and 4A, and the bump electrodes 3 and 4 may be fully connected after all the semiconductor chips 2 are stacked.

  Here, in aligning the first semiconductor chip 2A and the second semiconductor chip 2B, the formation accuracy of the alignment mark 5 (for example, the formation accuracy and exposure accuracy of the exposure mask used for forming the alignment mark 5) and the camera 13 may be misaligned between the first semiconductor chip 2A and the second semiconductor chip 2B. Such misalignment between the semiconductor chips 2A and 2B is not a problem as long as it is within the mounting accuracy of the semiconductor chip 2, and the connection accuracy between the bump electrodes 3A and 4A is not lowered.

  Next, as shown in FIG. 3A, a third semiconductor chip 2C having fourth and fifth bump electrodes 4B and 3C is prepared. In the third semiconductor chip 2C, a fourth alignment mark 5D is provided on the formation surface of the fourth bump electrode 4B, and a fifth alignment mark 5E is provided on the formation surface of the fifth bump electrode 3C. . The third semiconductor chip 2C sucked and held by the bonding head 12 is moved above the second semiconductor chip 2B stacked on the first semiconductor chip 2A. The third semiconductor chip 2C has a formation surface of the fourth bump electrode 4B and the fourth alignment mark 5D, and a formation surface of the third bump electrode 3B and the third alignment mark 5C of the second semiconductor chip 2B. Make them face each other.

  The camera 13 recognizes the third alignment mark 5C of the second semiconductor chip 2B and the fourth alignment mark 5D of the third semiconductor chip 2C moved onto the second semiconductor chip 2B. Coordinates are acquired as position information of the alignment marks 5C and 5D. At this time, if the third semiconductor chip 2C is aligned with the second semiconductor chip 2B based only on the coordinates indicating the positions of the third and fourth alignment marks 5C and 5D, the first semiconductor chip 2A Similarly to the stacking of the second semiconductor chip 2B and the second semiconductor chip 2B, the position between the second semiconductor chip 2B and the third semiconductor chip 2C is determined based on the formation accuracy of the alignment mark 5, the recognition accuracy by the camera 13, and the like. Deviation may occur.

  When only the alignment between the second semiconductor chip 2B and the third semiconductor chip 2C is considered, similarly to the stacking of the first semiconductor chip 2A and the second semiconductor chip 2B, between the semiconductor chips 2B and 2C. This positional deviation is not a problem as long as it is within the range of mounting accuracy of the semiconductor chip 2, and the connection accuracy between the third bump electrode 3B and the fourth bump electrode 4B is not lowered. However, even if the positional deviation of the third semiconductor chip 2C is within an allowable range with respect to the second semiconductor chip 2B, the third semiconductor chip 2C is viewed from the first semiconductor chip 2A. The position shift between the semiconductor chips 2A and 2B is arranged at a position where the position shift between them is accumulated. The amount of misalignment (accumulated misregistration amount) due to the accumulated misalignment between the semiconductor chips 2 increases as the number of stacked semiconductor chips 2 increases.

  For example, if the mounting accuracy of the semiconductor chip 2 is 2 μm, the positional deviation between the semiconductor chips 2 is allowed up to that value. When the eight semiconductor chips 2 are stacked, the amount of positional deviation between the adjacent semiconductor chips 2 is 2 μm at the maximum, whereas the lowermost semiconductor chip 2 and the uppermost semiconductor chip 2 in the eight stacked chips. There is a maximum positional deviation of 14 μm between the two. The amount of positional deviation between the lowermost semiconductor chip 2 and the uppermost semiconductor chip 2 naturally increases as the number of stacked semiconductor chips 2 increases. 30 μm. Such misalignment of the semiconductor chip 2 may cause, for example, the outer size of the multi-layered chip to exceed an allowable range, or may reduce the resin filling property between the semiconductor chips 2.

  Therefore, in the manufacturing method according to the embodiment, the coordinates of the first alignment mark 5A acquired when the second semiconductor chip 2B is stacked and the newly acquired coordinates of the third and fourth alignment marks 5C and 5D are used. Based on this, the third semiconductor chip 2C is aligned with the second semiconductor chip 2B. For example, an average coordinate between the coordinates of the first alignment mark 5A and the coordinates of the third alignment mark 5C is obtained, and the fourth alignment mark 5D is aligned with respect to this average coordinate. Thereby, even when the positional deviation amount between the adjacent semiconductor chips 2 is the maximum value within the allowable range, an increase in the positional deviation amount of the third semiconductor chip 2C with respect to the first semiconductor chip 2A can be suppressed. it can.

Regarding specific alignment, the average of the coordinates (x ₁₁ , y ₁₁ ) of the first mark in the first alignment mark 5A and the coordinates (x ₃₁ , y ₃₁ ) of the first mark in the third alignment mark 5C. The coordinates (x _A11 , y _A11 ), the coordinates (x ₁₂ , y ₁₂ ) of the second mark in the first alignment mark 5A, and the coordinates (x ₃₂ , y ₃₂ ) of the second mark in the third alignment mark 5C Average coordinates (x _A12 , y _A12 ) are obtained, and the difference ((x _A11 , y _A11 ) and (x ₄₁ , y) between these average coordinates and the coordinates of the first and second marks in the fourth alignment mark 5D are obtained. the difference between the _41), and (as x _A12, y _A12) and (the difference between the x _42, y ₄₂₎₎ is minimized, adjust the position of the third semiconductor chip 2C in the xy coordinate direction and the rotational direction To do. Then, as shown in FIG. 3B, the aligned third semiconductor chip 2C is stacked on the second semiconductor chip 2B while the fourth bump electrode 4B is in contact with the third bump electrode 3B. To do.

  Next, the third semiconductor chip 2C is heated while being heated to a temperature equal to or higher than the connection temperature of the third and fourth bump electrodes 3B and 4B, or while applying ultrasonic waves to the third and fourth bump electrodes 3B and 4B. Is bonded to the second semiconductor chip 2B to connect the third bump electrode 3B and the fourth bump electrode 4B. The connection between the third and fourth bump electrodes 3B and 4B is performed in the same manner as the connection between the first and second bump electrodes 3A and 4A. Accordingly, the third bump electrode 3B and the fourth bump electrode 4B are not limited to being connected when the second semiconductor chip 2B and the third semiconductor chip 2C are stacked, and the bump electrode 3B is not stacked when the semiconductor chip 2 is stacked. 4B may be temporarily fixed, and after all the semiconductor chips 2 (2A to 2D) are stacked, all the bump electrodes 3 and 4 may be permanently connected.

  In stacking the third semiconductor chip 2C on the second semiconductor chip 2B, the fourth alignment mark 5D with respect to the coordinates of the first alignment mark 5A is obtained without acquiring the coordinates of the third alignment mark 5C. Although the alignment accuracy of the third semiconductor chip 2C with respect to the first semiconductor chip 2A can be maintained, for example, it is assumed that a positional deviation exceeding the allowable range has occurred when connecting the bump electrodes 3A and 4A. However, such a positional deviation cannot be detected. This causes an increase in the number of used semiconductor chips 2 and a decrease in manufacturing yield of multi-layered laminated chips. On the other hand, in the manufacturing method of the embodiment, since the coordinates of the third alignment mark 5C are acquired, it is possible to detect a sudden positional deviation or the like generated in the second semiconductor chip 2B.

  The alignment of the third semiconductor chip 2C with respect to the second semiconductor chip 2B is performed by aligning the fourth alignment mark 5D with respect to the average coordinates of the coordinates of the first alignment mark 5A and the coordinates of the third alignment mark 5C. It is not limited to that. In order to prevent the positional deviation of the semiconductor chip 2 from accumulating, the fourth alignment mark 5D may be aligned with the inner region between the coordinates of the first alignment mark 5A and the coordinates of the third alignment mark 5C. Good. In this case, the fourth alignment mark 5D is aligned with the inner regions of the first and third alignment marks 5A and 5C with reference to the center coordinate of each coordinate. Specifically, the coordinates of the first alignment mark 5 </ b> A and the coordinates of the third alignment mark 5 </ b> C are inside the quadrangular area that is a diagonal vertex (connecting each vertex of the quadrangular area with the center coordinates as a reference). The fourth alignment mark 5D is aligned with the area excluding the line segment. In order to effectively suppress an increase in the accumulated amount of misalignment of the semiconductor chip 2, it is preferable to align the fourth alignment mark 5D within a region inside the above-described square region.

  Next, as shown in FIG. 4A, a fourth semiconductor chip 2D having a sixth bump electrode 4C is prepared. A sixth alignment mark 5F is provided on the formation surface of the sixth bump electrode 4C of the fourth semiconductor chip 2D. The fourth semiconductor chip 2D attracted and held by the bonding head 12 is moved above the third semiconductor chip 2C stacked on the second semiconductor chip 2B. The fourth semiconductor chip 2D has a surface on which the sixth bump electrode 4C and the sixth alignment mark 5F are formed, and a surface on which the fifth bump electrode 3C and the fifth alignment mark 5E in the third semiconductor chip 2C are formed. Make them face each other.

  The camera 13 recognizes the fifth alignment mark 5E of the third semiconductor chip 2C and the sixth alignment mark 5F of the fourth semiconductor chip 2D moved onto the third semiconductor chip 2C. The coordinates are acquired as position information of the alignment marks 5E and 5F. Similar to the stacking of the third semiconductor chip 2C, the coordinates of the first alignment mark 5A acquired at the time of stacking the second semiconductor chip 2B and the coordinates of the newly acquired fifth and sixth alignment marks 5E, 5F are obtained. Then, the fourth semiconductor chip 2D is aligned with the third semiconductor chip 2C. The alignment of the fourth semiconductor chip 2D is performed based on at least the coordinates of the first, fifth and sixth alignment marks 5A, 5E, 5F.

  For example, an average coordinate between the coordinates of the first alignment mark 5A and the coordinates of the fifth alignment mark 5E is obtained, and the sixth alignment mark 5D is aligned with respect to this average coordinate. In addition to the coordinates of the first, fifth, and sixth alignment marks 5A, 5E, and 5F, the coordinates of the third alignment mark 5C may be considered. For example, the first average coordinates (the average coordinates of the coordinates of the first alignment mark 5A and the coordinates of the third alignment mark 5C) obtained when the second semiconductor chip 2B is stacked and the coordinates of the fifth alignment mark 5E And the sixth alignment mark 5D is aligned with respect to the second average coordinate. Alternatively, the average coordinates of the coordinates of the first alignment mark 5A, the coordinates of the third alignment mark 5C, and the coordinates of the fifth alignment mark 5E are obtained, and the sixth alignment mark 5D is aligned with respect to the average coordinates. To do. As a result, even when the positional deviation amount between the adjacent semiconductor chips 2 is the maximum value within the allowable range, an increase in the positional deviation amount of the fourth semiconductor chip 2D with respect to the first semiconductor chip 2A can be suppressed. .

  Next, the fourth semiconductor chip 2D is heated while being heated to a temperature equal to or higher than the connection temperature of the fifth and sixth bump electrodes 3C and 4C, or while applying ultrasonic waves to the fifth and sixth bump electrodes 3C and 4C. Is bonded to the third semiconductor chip 2C, thereby connecting the fifth bump electrode 3C and the sixth bump electrode 4C. The connection between the fifth and sixth bump electrodes 3C, 4C is performed in the same manner as the connection between the first and second bump electrodes 3A, 4A. Accordingly, the fifth bump electrode 3C and the sixth bump electrode 4C are not limited to being connected when the third semiconductor chip 2C and the fourth semiconductor chip 2D are stacked, and the bump electrode 3C is not stacked when the semiconductor chip 2 is stacked. 4C may be temporarily fixed, and after all the semiconductor chips 2 (2A to 2D) are stacked, all the bump electrodes 3 and 4 may be permanently connected.

  The alignment of the fourth semiconductor chip 2D with respect to the third semiconductor chip 2C is not limited to the alignment of the sixth alignment mark 5F with respect to the average coordinates as described above. In order to suppress the accumulation of misalignment of the semiconductor chip 2, the sixth alignment mark 5F is located in an inner region (center coordinate reference) between the coordinates of the first alignment mark 5A and the coordinates of the fifth alignment mark 5E. It only needs to be aligned. Specifically, the area inside the quadrangular area where the coordinates of the first alignment mark 5A and the coordinates of the fifth alignment mark 5E are diagonal vertices (excluding the vertices of the quadrangular area and the line segment connecting them) ) To align the sixth alignment mark 5F. When five or more semiconductor chips are stacked, the fifth and subsequent semiconductor chips 2 may be aligned in the same manner as the fourth semiconductor chip 2D.

  According to the manufacturing method of the embodiment, the coordinates of the third and fourth alignment marks 5C and 5D or the fifth and sixth alignment marks 5E and 5F when the third and fourth semiconductor chips 2C and 2D are stacked. In addition to the coordinates of the second semiconductor chip 2B, the third and fourth semiconductor chips 2C, 2D are taken as the semiconductor chip 2B immediately below them by taking into account the coordinates of the first alignment mark 5A acquired when the second semiconductor chip 2B is stacked. Since the alignment is performed with respect to 2C, an increase in the amount of misalignment due to the accumulation of misalignment between the semiconductor chips 2 can be suppressed. On top of that, when the third and fourth semiconductor chips 2C and 2D are stacked, the coordinates of the alignment marks 5C and 5E of the semiconductor chips 2B and 2C immediately below them are also acquired, so that the semiconductor chip is suddenly performed. Even if an abnormal positional shift occurs in 2B and 2C, such a positional shift can be detected. Therefore, according to the manufacturing method of the semiconductor device of the embodiment, the increase in the usage amount of the semiconductor chip 2 and the manufacturing yield of the multistage multilayer chip are suppressed while suppressing the increase in the cumulative amount of misalignment of the semiconductor chip 2 in the multistage multilayer chip. Can be prevented.

  When the main connection between the bump electrodes 3 and 4 is performed after all the semiconductor chips 2 (2A to 2D) are stacked, the bump electrodes 3 and 4 are temporarily fixed when the semiconductor chips 2 are stacked. The chip laminated body in which the bump electrodes 3 and 4 are temporarily fixed is pressure-bonded or reflowed at a temperature equal to or higher than the connection temperature of the bump electrodes 3 and 4. As a result, all the bump electrodes 3 and 4 are fully connected. Even in the case where the bump electrodes 3 and 4 are connected when the semiconductor chip 2 is stacked, the step of pressure bonding or reflowing at a temperature equal to or higher than the connection temperature of the bump electrodes 3 and 4 may be performed supplementarily.

  After stacking the semiconductor chips 2A to 2D while connecting the bump electrodes 3 and 4 by the alignment process and the stacking process of the embodiment described above, the gap between the first conductor chip 2A and the second semiconductor chip 2B, Underfill resin 9 is filled and cured in the gap between the second semiconductor chip 2B and the third semiconductor chip 2C and the gap between the third semiconductor chip 2C and the fourth semiconductor chip 2D, respectively. In this way, the semiconductor device 1 according to the embodiment is manufactured. Since the increase in the amount of misalignment due to the accumulated misalignment of the semiconductor chip 2 is suppressed, the filling property of the underfill resin 9 in each gap between the semiconductor chips 2 is good even when the semiconductor chips 2 are stacked in multiple stages. In addition, it is possible to suppress the occurrence of a defective outer size. That is, the manufacturing yield of the semiconductor device 1 can be increased.

  The semiconductor device 1 manufactured by the manufacturing method of the embodiment described above is used as a semiconductor package 20 as shown in FIG. 5, for example. In the semiconductor package 20 shown in FIG. 5, the semiconductor device 1 according to the embodiment is mounted on a wiring board 23 having an external connection terminal 21 and an internal connection terminal 22. The internal connection terminal 22 of the wiring board 23 is electrically connected to the semiconductor device 1 through a rewiring layer 24 and a bonding wire 25 formed on the upper surface of the uppermost semiconductor chip 2D of the semiconductor device 1. A resin sealing layer 26 that seals the semiconductor device 1 together with the bonding wires 25 and the like is formed on the wiring substrate 23.

  The electrical connection between the semiconductor device 1 and the wiring board 23 may be performed by flip chip bonding. FIG. 6 shows a state where the semiconductor device 1 and the wiring board 22 are flip-chip bonded. In order to perform flip chip bonding of the semiconductor device 1, a seventh bump electrode 27 is provided on the upper surface of the fourth semiconductor chip 2D. The semiconductor device 1 is mounted on the wiring board 23 in a state reversed from the stacking order so that the uppermost semiconductor chip 2D in the stacking order is positioned on the wiring board 22 side. The wiring board 23 and the fourth semiconductor chip 2D are electrically and mechanically connected via a connecting body of an eighth bump electrode 28 and a seventh bump electrode 27 provided on the internal connection terminal 22 of the wiring board 23. Connected.

  When the semiconductor chips 2A to 2D constituting the semiconductor device 1 are memory chips such as a NAND flash memory, a semiconductor that performs data communication with an external device such as a controller chip or an interface chip on the semiconductor device 1. A chip may be mounted. Such a semiconductor chip is stacked on the semiconductor chip 2D, for example, and is electrically connected to the semiconductor device 1 via a solder bump or the like. When a controller chip, an interface chip or the like is mounted on the semiconductor device 1, the semiconductor device 1 and the wiring substrate 33 are connected via such semiconductor chips and bonding wires or solder bumps provided on the semiconductor chip 2D. Can be electrically connected.

  In addition, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and at the same time included in the invention described in the claims and the equivalents thereof.

Claims (5)

Providing a first semiconductor chip comprising a first bump electrode and a first alignment mark provided on the first surface;
A second bump electrode and a second alignment mark provided on the second surface; a third bump electrode and a third alignment mark provided on a third surface opposite to the second surface; Preparing a second semiconductor chip comprising a through electrode for electrically connecting the second bump electrode and the third bump electrode;
Preparing a third semiconductor chip comprising a fourth bump electrode and a fourth alignment mark provided on the fourth surface;
Moving the second semiconductor chip onto the first semiconductor chip and causing the first surface and the second surface to face each other;
Position information of the second alignment mark of the second semiconductor chip moved onto the first semiconductor chip as a position information of the first alignment mark of the first semiconductor chip Obtaining a second xy coordinate as
Stacking the first semiconductor chip and the second semiconductor chip while aligning them based on the first and second xy coordinates as positional information of the first and second alignment marks; ,
Heating the first bump electrode and the second bump electrode in contact with each other, and connecting the first bump electrode and the second bump electrode;
Moving the third semiconductor chip onto the second semiconductor chip and causing the third surface and the fourth surface to face each other;
Position information of the fourth alignment mark of the third semiconductor chip moved onto the second semiconductor chip and a third xy coordinate as position information of the third alignment mark of the second semiconductor chip Obtaining a fourth xy coordinate as
An average coordinate between the first xy coordinate as the position information of the first alignment mark and the third xy coordinate as the position information of the third alignment mark obtained at the time of stacking the second semiconductor chip is obtained. Stacking the second semiconductor chip and the third semiconductor chip while aligning them by aligning the fourth alignment mark with the average coordinates;
A step of contacting and heating the third bump electrode and the fourth bump electrode, and connecting the third bump electrode and the fourth bump electrode. Manufacturing method. Providing a first semiconductor chip comprising a first bump electrode and a first alignment mark provided on the first surface;
A second bump electrode and a second alignment mark provided on the second surface; a third bump electrode and a third alignment mark provided on a third surface opposite to the second surface; Preparing a second semiconductor chip comprising a through electrode for electrically connecting the second bump electrode and the third bump electrode;
Preparing a third semiconductor chip comprising a fourth bump electrode and a fourth alignment mark provided on the fourth surface;
Moving the second semiconductor chip onto the first semiconductor chip and causing the first surface and the second surface to face each other;
Obtaining positional information of the first alignment mark of the first semiconductor chip and the second alignment mark of the second semiconductor chip moved on the first semiconductor chip;
Stacking the first semiconductor chip and the second semiconductor chip while aligning them based on positional information of the first and second alignment marks;
Moving the third semiconductor chip onto the second semiconductor chip and causing the third surface and the fourth surface to face each other;
Obtaining positional information of the third alignment mark of the second semiconductor chip and the fourth alignment mark of the third semiconductor chip moved onto the second semiconductor chip;
Stacking the second semiconductor chip and the third semiconductor chip while aligning them based on the positional information of the first alignment mark and the positional information of the third and fourth alignment marks; A method for manufacturing a semiconductor device, comprising: The third semiconductor chip includes a fifth bump electrode and a fifth alignment mark provided on a fifth surface opposite to the fourth surface, the fourth bump electrode, and the fifth bump. A through electrode for electrically connecting the electrode,
A step of preparing a fourth semiconductor chip including a sixth bump electrode and a sixth alignment mark provided on the sixth surface;
Moving the fourth semiconductor chip onto the third semiconductor chip and causing the fifth surface and the sixth surface to face each other;
Obtaining positional information of the fifth alignment mark of the third semiconductor chip and the sixth alignment mark of the fourth semiconductor chip moved on the third semiconductor chip;
A step of stacking the third semiconductor chip and the fourth semiconductor chip while aligning them based on at least the position information of the first alignment mark and the position information of the fifth and sixth alignment marks. When,
A method for manufacturing a semiconductor device according to claim 2, comprising:   The alignment between the second semiconductor chip and the third semiconductor chip is performed by using the xy coordinates as the position information of the first alignment mark acquired when the second semiconductor chip is stacked and the third alignment mark. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the fourth alignment mark is aligned inside a quadrangular area whose xy coordinates as position information of the first position are diagonal vertices.   The alignment between the second semiconductor chip and the third semiconductor chip is performed by using the xy coordinates as the position information of the first alignment mark acquired when the second semiconductor chip is stacked and the third alignment mark. The method of manufacturing a semiconductor device according to claim 2, wherein the fourth alignment mark is aligned with an average coordinate with an xy coordinate as the position information.

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