TWI358810B - Alignment device for a chip package structure - Google Patents

Description

I35S810 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to a aligning device β in more detail with respect to a aligning device for a wafer package construction. [Prior Art]

In recent years, with the continuous maturity and development of semiconductor process technology, 'a variety of high-performance electronic products are constantly being introduced,' and the integration of integrated circuit (IC) chips has also increased. The integrated circuit chip package type can be roughly classified into a wire bonding package (Wire Bonding Package), a tape automatic bonding (TAB), and a flip chip package (Flip Chip Package), and each package type. Both have their particularity and application areas. Compared to the traditional wire bonding package technology, the tape automatic bonding package has the advantages of reducing the pad pitch and thinning of the wafer. It is currently used in liquid crystal display driver 1C packaging and mobile electronic products, such as notebook computers, mobile phones, digital cameras, etc., because the switchable substrate has dynamic connection, flexibility and thinning characteristics. Therefore, it is widely used as material. At present, the bonding of the flexible substrate to the wafer is mostly achieved by using a tape automated bonding (TAB) packaging technology, wherein the tape automatic bonding and packaging technology can be further divided into a tape carrier package (TCP) and a film overlay package. | (Chip 〇n Film COF) two technologies. The film flip-chip package (COF) is used for the para-dusting bonding of the bumps on the replaceable substrate with the corresponding bumps on the wafer to form the 5 I35S810 between the leads and the bumps. An electrical connection '俾 enables the data of the chip to communicate with the external circuit by means of bumps and 5-pin connections. As the process progresses and the integrated circuit is intensively produced, the size and pitch of the pin and the bump are becoming smaller and smaller. However, this also means that the alignment of the pins and bumps is more difficult to align, and the tolerances that can be tolerated will be more stringent. In addition, during the press bonding, the stress tends to concentrate on the corner 隅 of the cover region of the wafer p, causing the outer pin to be broken or peeled, so that the electrical connection cannot be made far away, and the function of the wafer is made. It is affected and cannot function properly. Therefore, if the %^^ 遵 step by step improves the alignment structure, it will seriously affect the yield of the package. Lu ▼ In the conventional alignment technology, the alignment of the wafer and the slidable substrate is performed by the human eye through the camera. As shown in Fig. 1, the flexible substrate 1 has a cymbal footprint 10 〇, and a pin is provided on each side of the wafer footprint 100 as an example. The wafer footprint 100 has two long sides 10〇3 and two short sides i〇〇b, and two diagonal corners (or four corners) of the wafer coverage area 100 define a teaching area 104, which covers the long side. a portion of the first long side pin ll 〇 a and a short side l 〇〇 b _ first short side pin ll 〇 b; in addition, the wafer (not shown) also has a corresponding length The side and the two short sides, and the corresponding corners in the # wafer also define the teaching area. The image reading area of the wafer and the flexible substrate 100 is separately viewed by the camera, and the gray scale values of the respective teaching areas are obtained, so that the image overlap alignment can be performed. However, if the first long side pin is far away from the first short side pin, the range of the teaching area needs to be enlarged to make the teaching area contain both the long side and the short side pin. This will reduce the resolution; in addition, this alignment technique is only used for flexible substrates with pins on both the long side and the short side, which cannot be aligned without the short side pins; Improper lead to uneven surface of the pin will also affect the alignment of the fine 6 1358810 degrees; in addition, this technology can not provide the offset adjustment of the pin and the bump alignment. support. * In summary, the conventional alignment technology is not only limited in use, but also unable to solve the problem of stress concentration at the corners causing the outer pins to break. Therefore, a new alignment structure is designed and can be provided at the same time. And the protection of the bumps during the pressing is a goal that the industry has to solve. Qin [Invention] It is an object of the present invention to provide a aligning device for a chip package structure, the chip package structure comprising a flexible substrate, a conductive layer and a wafer, the flexible substrate having a wafer cover The area, the wafer footprint includes a peripheral area. A conductive layer is formed on the wafer footprint and defines the peripheral region as a plurality of pin regions and a plurality of pinless regions. The wafer system is disposed on the conductive layer. The aligning device includes at least one first pair of privilege. At least one second alignment mark. At least one first alignment mark is formed on at least one of the wafer footprints, and at least one second alignment mark is formed on one of the wafers Φ active planes. Wherein, when the wafer is electrically positioned on the wafer footprint, the at least one second alignment mark is adapted to correspond to the at least one first alignment mark. With the above-mentioned alignment device, the pins on the flexible substrate and the bumps on the wafer can be accurately aligned. In addition, the alignment device has the function of supporting and dispersing stress, thereby protecting the outer side pins on the wafer footprint from being broken or peeled due to stress concentration at the corners. The objects of the present invention, as well as the technical means and implementations of the present invention, will be apparent to those of ordinary skill in the art. 7 1358810 [Embodiment] A first embodiment of the present invention is a aligning device for a chip package construction. The cross-sectional view of the chip package structure 2 through the leads and the bumps is as shown in FIG. 2A. FIGS. 2B and 2C are respectively a bottom view of the wafer 22 and a plan view of the flexible substrate 20 in the chip package structure 2. .

Referring also to FIGS. 2A-2C, the chip package structure 2 includes a flexible substrate 20, a conductive layer 21, and a wafer 22. The flexible substrate 20 has a wafer footprint 200, and the wafer footprint 200 includes a peripheral region (not shown). In this embodiment, the flexible substrate 20 is made of polyamine, and has a height. Flexibility In other embodiments, the flexible substrate 20 can also be made of a material such as polyethylene terephthalate (PET). The conductive layer 21 includes a plurality of pins 210, and the conductive layer 21 is formed on the wafer footprint 200 and defines the peripheral regions into four lead regions 204a, 204b, 204c, and 204d and four leadless regions 206a. 206b, 206c, and 206d, and the pins 210 are formed on the four pin regions 204a, 204b, 204c, and 204d. The wafer 22 is aligned on the conductive layer 21, and one of the active faces 220 of the wafer 22 has a plurality of bumps 221, thereby electrically connecting to the pins 210. Further, the alignment device includes four first alignment marks 201a, 201b, 201c, 201d and four second alignment marks 222a, 222b, 222c, 222d. Four first alignment marks 201a, 201b, 201c and 201d are respectively formed on the four corners of the wafer footprint 200, that is, four leadless regions 206a, 206b, 206c and 206d; four second alignment marks 222a 222b, 222c, and 222d are formed on the 8 1358810 active surface 220 of the wafer 22. The shapes of the four first alignment marks 201a, 201b, 201c, and 201d and the four second alignment marks 222a, 222b, 222c, and 222d are each a U shape and a cross shape. In other implementations, the first alignment mark and the second alignment mark may also be selected from the group of shapes such as a 卍 shape, a cross shape, a m shape, a T shape, an L shape, and a square shape, or may be other known The shape can be easily replaced by the skilled person, and is not limited to the above shape. When the wafer 22 is electrically positioned on the wafer footprint 200, the four first-parameters 201a, 201b, 201c, and 201d may correspond to the four second alignment marks 222a, 222b, 222c, and 222d, respectively. Similarly, the wafer footprint 2 and wafer 22 are also defined - with a teach area. In the case of the wafer footprint 200, its teaching area is the four leadless areas 206a, 206b, ? 06c and 206d' and the respective alignment areas 201a, 201b, 201c, and 201d are included in the teaching area; in the case of the wafer 22, the teaching area corresponds to the leadless areas 206a, 206b, and 206c. The four corners of 206d. The shape of the first alignment mark and the second alignment mark are such that when the pins 21 are aligned, the bumps 221 are aligned, and each of the teaching areas is viewed through the camera. The grayscale value of the region compares the relative positions between the first alignment mark and the second alignment mark (such as the X direction, the y direction, and the offset angle Θ) to determine whether the two are properly joined and adjusted. The alignment of the pins 210 with the bumps 221 is more precise. After the alignment, the device is then pressed to complete the electrical bonding between the two. 0 In more detail, the pins 210 formed on the four pin regions 204a' 204b, 204c, and 204d have a first The thickness 'and the four first alignment marks 201a, 9 1358810 201b, 201c, and 201d have a second thickness, the first thickness is substantially equal to the second thickness, and the four first alignment marks 201a, 201b, 201c And 201d and the pins 210 are both made of a first material. Further, when the pins of this embodiment are prepared by etching, the first alignment mark is also etched at the same time, in other words, the two are formed of the same material and simultaneously. In this embodiment, the first material is copper. It should be noted that in other embodiments, the first material is not limited to the copper metal described above, which can be easily considered by those skilled in the art. It is made of other metals.

The bumps 221 on the active surface 220 of the wafer 22 have a third thickness, and the four second alignment marks 222a, 222b, 222c and 222d on the wafer 22 have a fourth thickness, a third thickness. The fourth thickness is substantially equal to the fourth thickness, and the four second alignment marks 222a, 222b, 222c, and 222d and the bumps 221 are composed of the second material. When the bump of this embodiment is prepared, the second alignment mark is also formed at the same time, so that both are formed of the same material and simultaneously. In this embodiment, the second material is gold. It should be noted that in other embodiments, the first material is not limited to the above-mentioned gold metal, which can be easily considered by those skilled in the art. And other metals. In this embodiment, the thicknesses of the first alignment mark and the second alignment mark are equal to the thicknesses of the pins and the bumps, respectively, so when the pins are bonded to the bumps, the first alignment mark and the second alignment mark At the same time, the bonding is completed, and the supporting force is further provided in the four corners of the wafer 22 and the wafer covering area 200, so as to avoid breakage or peeling of the pins 210 near the outer side due to stress concentration at the corners during pressing, thereby reducing electrical properties. The possibility of connecting a short circuit or an open circuit. The second embodiment of the present invention is also an alignment device 1358810 for a chip package construction. Different from the previous embodiment, the number of the no-pin regions and the alignment devices in the chip package structure 2 of the present embodiment is different, so only the portion of the leadless region and the alignment device will be specifically described herein. 3A and 3B, wherein FIG. 3A is a bottom view of the wafer 22' in the wafer package structure 2 of the present embodiment, and FIG. 3B is a flexible substrate 20' of the wafer package structure 2 of the present embodiment. Top view. In the wafer package structure 2 of the present embodiment, the flexible substrate 20 has a wafer covering region 200', and the wafer covering region 200' includes a peripheral region. The surrounding area is divided into four

Pin areas 204a', 204b, 204c' and 204d' and four leadless areas 206a', 206b', 206c' and 206d', the plurality of pins 210' are formed in the four pin areas 204a', 204b', 204c' and 204d, on. The wafer 22, one of the active faces 220, has a plurality of bumps 221' correspondingly electrically connected to the pins 210'. Further, the alignment device includes two first alignment marks 201a', 201c, and two second alignment marks 222a, 222c'. Two first alignment marks 201a, 201c are respectively formed on the wafer footprint 200, two diagonal corners, that is, two leadless regions 206a' and 206c'i; two second alignment marks 222a', 222c' are formed on the active surface 220 of the wafer 22', above the first alignment mark 201a', 201c'. When the wafer 22' is electrically positioned on the wafer footprint 200', The two first alignment marks 201a' and 201c' are adapted to correspond to the two second alignment marks 222a, and 222c', respectively. Similarly, the wafer footprint 200 and the wafer 22' are also defined with a teaching area. In the case of the wafer footprint 200', the teaching areas are the lead-free areas 206a, 206c', and the first alignment marks 201a' and 201c' are respectively included in each of the teaching areas; The teaching read area is the two corners corresponding to the leadless areas 206a' and 206c'. Then, 1358810 also makes the image look at each (4) region, and confirms the relative position of the first-alignment mark and the second alignment mark with the gray-scale value of each teaching region (such as the direction of the 丫, the direction of the 及, and the offset ), in order to judge whether the two are correctly connected and adjusted, so that the bow|foot 21〇, and the bumps 221, the alignment is more precise. After the alignment, press the machine to complete the electrical joint between the two. In this embodiment, only the first alignment mark and the second alignment mark are disposed on the two opposite corners of the wafer and the wafer footprint, but the alignment mechanism and the sufficient thrust can be provided. It should be noted that the number of the first alignment mark and the second alignment mark is not limited to the number of the above-mentioned real numbers, and may be arbitrarily increased or decreased, and is not limited to the above number. The shape of the first alignment mark and the second alignment mark may be the same or different. - The second embodiment of the invention is also a aligning device for a wafer package construction. Different from the first embodiment, in the alignment device of the chip package structure 3 of the embodiment, the first alignment mark and the second alignment mark are both thinner lines, that is, the first in the embodiment. The alignment mark and the second alignment mark are far thinner than the first alignment mark and the second alignment mark of the foregoing embodiments. The chip package structure 3 simultaneously passes through the 0 alignment device, the leads and the bumps. The cross-sectional view is as shown in FIG. 4A, and the fourth and fourth C-th views are respectively a top view of the wafer 32 and a plan view of the flexible substrate 30 in the chip package structure 3. In the wafer package construction 3, the flexible substrate 30 has a wafer footprint 300, and the wafer footprint 300 includes a peripheral region. The peripheral region is defined as four pin regions 3〇4a, 304b, 304c, and 304d and four leadless regions 306a, 306b' 306c and 306d, and the plurality of pins 310 are formed in the four pin regions 304a, 304b, and 304c. And on 304d. The active surface 320 of one of the wafers 32 has a plurality of bumps 321 , thereby electrically connecting 12 1358810 to the pins 310 .

Further, the alignment device includes two first alignment marks 301a, 301c and two second alignment marks 322a, 322c. Two first alignment marks 301a, 301c are respectively formed on two diagonal corners of the wafer footprint 300, that is, two of the leadless regions 306a and 306c; two second alignment marks 322a, 322c are formed. On the active surface 320 of the wafer 32, the position corresponding to the first alignment mark 301a, 301c. Preferably, the first pair of bit marks 301a, 301c are formed simultaneously with the pin 310 by the same process (such as an etching process), and the thickness of the first bit mark 301a, 301c is equal to the thickness of the pin 310. In more detail, the first thickness of each of the pins 310 will substantially correspond to the second thickness of the first alignment marks 301a, 301c. On the other hand, the second alignment mark 322a, 322c is preferably formed simultaneously with the bump 321 , but since the lines of the second alignment mark 322a, 322c are thin, in the actual process, the second alignment mark 322a, The thickness of 322c is typically less than the thickness of bump 321 . In more detail, the third thickness of each bump 321 is substantially greater than the fourth thickness of the second alignment mark 322a, 322c. The shapes of the first alignment marks 301a, 301c and the second alignment marks 322a, 322c are all line-shaped marks of a m-shaped shape. More specifically, the stroke width of the rice-shaped shape is much smaller than that of the foregoing embodiments. In other implementations, the first alignment mark and the second alignment mark may also be selected from the group of shapes such as a chevron, a cross, a T, an L, and a square, or may be used by other known techniques. The shape can be easily replaced, so it is not limited to the above shape. When the wafer 32 is electrically positioned on the wafer footprint 300, the two first alignment marks 301a and 301c may correspond to the two second alignment marks 322a and 322c, respectively. Similarly, wafer footprint 300 and wafer 32 are also defined with a read area. In the case of the wafer footprint 13 1358810 300, the teaching areas are the lead-free areas 306a and 306c, and the first alignment marks 301a and 301c are respectively included in the teaching area; for the wafer 32, the teaching is performed. The area is the two corners corresponding to the leadless areas 306a and 306c. Then, the camera is also used to view each of the teaching areas, and the offset values of the first and second alignment marks are confirmed by the grayscale values of the teaching areas (for example, the offset in the X direction and the deviation in the y direction). The shift amount and the offset angle Θ) are used to judge whether the relative positions of the two are correctly aligned and perform the offset adjustment of the details, so that the alignment of the pins 310 and the bumps 321 is more accurate. After the alignment, press the machine to complete the electrical joint between the two.

In this embodiment, the first alignment mark and the second alignment mark are disposed only on two diagonal corners of the wafer and the wafer coverage area, thereby providing an alignment mechanism, and more specifically, due to the shape of the line shape. It can be used as a basis for rapid fine-tuning when viewing the school reading area with a camera. It should be noted that the number of the first aligning mark and the second aligning mark is not limited to the number of the above embodiments, and may be arbitrarily increased or decreased, and is not limited to the above. In addition, in other implementations, the shapes of the first alignment mark and the second alignment mark may be the same or different. It can be seen from the above embodiments that the present invention can be used for the pin on the flexible substrate and the bump on the wafer by the above-mentioned alignment device for a chip package structure and respectively disposed on the wafer and the flexible substrate. When the block is aligned, it can be precisely aligned, and is not limited to the distance between the pin on the long side and the pin on the short side, and is more applicable to only the long side (or only the short side). The case of the pin. In addition, the alignment device according to the first embodiment and the second embodiment of the present invention can provide a supporting and dispersing stress, thereby protecting the pins and the bumps near the corners, and not at the corners of the pressing. Stress is concentrated and damaged. The above-described embodiments are only intended to illustrate the embodiments of the present invention, and to illustrate the technical features of the present invention 14 1358810, and are not intended to limit the scope of the present invention. Any change or singularity that can be easily accomplished by those skilled in the art is within the scope of the invention, and the scope of the invention should be determined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a flexible substrate in a chip package structure of a prior art; FIG. 2A is a cross-sectional view showing a chip package structure according to a first embodiment of the present invention;

2B is a bottom view of the wafer in the wafer package structure according to the first embodiment of the present invention; FIG. 2C is a plan view of the flexible substrate in the chip package structure according to the first embodiment of the present invention; In the wafer package structure of the second embodiment of the present invention, a bottom view of the wafer, and FIG. 3B is a wafer package structure according to a second embodiment of the present invention. FIG. 4A is a plan view of the flexible substrate. FIG. 4B is a bottom view of a wafer in a wafer package structure according to a third embodiment of the present invention; and FIG. 4C is a wafer package structure according to a third embodiment of the present invention, Top view of the flexible substrate. [Description of main component symbols] 10: Flexible substrate 15 1358810 100: Wafer footprint 100a: Long side 100b: Short side 104: Teaching area 110a · First long side pin 110b: First short side pin 2 Chip package construction

20: Flexible substrate 20': Flexible substrate 200: Wafer coverage area 200': Wafer coverage area

201a, 201b, 201c, 201d: first alignment mark 201a', 201c': first alignment mark 204a, 204b, 204c, 204d:, pin area 204a', 204b', 204c', 204d': pin Areas 206a, 206b, 206c, 206d: leadless areas 206a', 206b', 206c', 206d': leadless area 21: conductive layer 210: pin 210': pin 22: wafer 22': wafer 220 Active surface 16 1358810 220': active surface 222a, 222b, 222c, 222d: second alignment mark 222a', 222c': second alignment mark 221: bump 221': bump 3: wafer package construction 30: Flexible substrate 300: wafer footprint

301a, 301c: first alignment mark 304a, 304b, 304c, 304d: pin area 306a, 306b, 306c, 306d: leadless area 310: pin 32: wafer 320: active surface 321 : bump

322a, 322c: second alignment mark 17

Claims (1)

1358810,. EJnf Patent Application No. 096138202 i Patent Application Range Replacement (no-line version, 8 pages of the following year) * X. Patent application scope: 1. A registration device for a chip package structure, The chip package structure comprises: a flexible substrate having a wafer footprint, the wafer footprint comprising a peripheral region; a conductive layer formed on the wafer footprint and defining the peripheral region as a plurality of pin regions and a plurality of lead-free regions; a wafer disposed on the conductive layer; the alignment device comprising: ® at least a first alignment mark formed in the lead-free region of at least one corner of the wafer footprint And at least one second alignment mark is formed on one active surface of the wafer, wherein the at least one second alignment mark is suitable when the wafer is electrically positioned on the wafer coverage area 2. The alignment device according to claim 1, wherein the conductive layer comprises a plurality of pins and the at least one first alignment mark. φ 3. As claimed in claim 2 Place The alignment device, wherein the plurality of leadless regions comprise two leadless regions, wherein the leadless regions are respectively formed at two diagonal corners of the wafer coverage area; the alignment device includes two first alignment marks and And a second alignment mark, wherein the two first alignment marks are respectively formed on the lead-free areas, and when the wafer is electrically positioned on the wafer coverage area, the second alignment marks are adapted to correspond to 4. The alignment device according to claim 1, wherein each of the pin regions is formed with a plurality of pins, each of the pins having a first thickness, the at least one first alignment mark The first thickness is substantially equal to the second thickness, and the first thickness is substantially equal to the second thickness. 5. The alignment device of claim 1, wherein each of the pin regions is formed with a plurality of pins, each of the leads The foot has a first thickness, and the at least one first alignment mark has a second thickness, the first thickness being substantially greater than the second thickness. 6. The alignment device of claim 1, wherein the wafer The active surface has a plurality of bumps corresponding to the electrical connection Each of the bumps has a third thickness, and the at least one second alignment mark has a fourth thickness, the third thickness being substantially equal to the fourth thickness. 7. The pair of claim 1 The bit device, wherein the active surface of the wafer has a plurality of bumps correspondingly electrically connected to the plurality of pins, each of the bumps has a third thickness, and the at least one second alignment mark has a fourth thickness. The third thickness is substantially greater than the fourth thickness. 8. The alignment device of claim 4, wherein the at least one first alignment mark and the pins are the same one of the first materials 9. The alignment device of claim 8, wherein the first material is copper. 10. The alignment device of claim 6, wherein the at least one second alignment mark and the bumps , formed by one of the same second materials. 11. The alignment device of claim 10, wherein the second material is gold. 12. The alignment device of claim 1, wherein the shape of the at least one first alignment mark is selected from the group consisting of a U shape, a cross shape, a m shape, a T shape, an L shape, and a square shape. 13. The alignment device according to claim 1, wherein the shape of the at least one second alignment mark is a U-shape, a cross, a m-shape, a T-shape, an L-shape, and a square shape. Elected.