JP4280907B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP4280907B2
JP4280907B2 JP2003147847A JP2003147847A JP4280907B2 JP 4280907 B2 JP4280907 B2 JP 4280907B2 JP 2003147847 A JP2003147847 A JP 2003147847A JP 2003147847 A JP2003147847 A JP 2003147847A JP 4280907 B2 JP4280907 B2 JP 4280907B2
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semiconductor substrate
pads
semiconductor device
hole
pad
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JP2004349631A (en
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勝彦 小口
紀夫 今岡
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
【０００３】
【特許文献１】
特開平１−２６１８３７号公報
【特許文献２】
特開平１１−３５４２３１号公報
【０００４】
【発明の背景】
半導体基板の表面には、パッドが形成されることが一般的である。半導体装置の信頼性を高めるためには、パッドによる半導体基板へのストレスを軽減することが必要である。特に、一方向に大きなストレスがかかる事を防止することができれば、信頼性の高い半導体装置を提供することができる。
【０００５】
本発明の目的は、信頼性の高い半導体装置及びその製造方法を提供することにある。
【０００６】
【課題を解決するための手段】
（１）本発明に係る半導体装置は、集積回路が内部に形成されてなる半導体基板と、
前記半導体基板上に、その内部に電気的に接続されるように形成されてなる複数のパッドと、
を含み、
前記パッドには第１の貫通穴が、前記半導体基板には前記第１の貫通穴とオーバーラップする第２の貫通穴が、それぞれ形成されてなり、
前記第２の貫通穴の内面に形成された絶縁層と、
前記絶縁層の内側を通り前記半導体基板を貫通する貫通電極と、
をさらに有し、
前記複数のパッドは、相似の位置にあって内側に相似の中心を有する複数の相似形の線上に中心が位置するように配列され、
それぞれの前記パッドは、その中心が他の２つの前記パッドの中心を結んだ仮想直線上を避けて配置されてなる半導体装置を複数積層し、かつ、複数積層した前記半導体装置が前記貫通電極を通して電気的接続が図られてなる。本発明によれば、半導体装置は、パッドが３個以上並ばないように配置された半導体基板を有する。パッドが３個以上並ばないことから、パットが一方向へ与える力が小さい半導体基板を提供することができる。そのため、ストレスが集中しない半導体基板を有する、信頼性の高い半導体装置を提供することができる。本発明によれば、半導体基板には、貫通電極が、３個以上並ばないように配置されるため、半導体基板が割れにくくなる。そのため、割れにくい半導体基板を有する信頼性の高い半導体装置を提供することができる。本発明によれば、割れにくい半導体基板を有する半導体装置が積層された、信頼性の高い積層型の半導体装置を提供することができる。
（２）この半導体装置において、
前記パッドは、前記半導体基板の中央部を避けて、周縁部に形成されていてもよい。
（３）本発明に係る半導体装置の製造方法は、集積回路が内部に形成されてなる半導体基板に、その内部に電気的に接続されるように複数のパッドを形成すること、
前記パッドには第１の貫通穴を、前記半導体基板には前記第１の貫通穴とオーバーラップする第２の貫通穴を、それぞれ形成すること、
前記第２の貫通穴の内面に絶縁層を形成すること、及び、
前記絶縁層の内側を通り前記半導体基板を貫通する貫通電極を形成すること、
を含む製造方法で得られた半導体装置を複数積層し、かつ、複数積層した前記半導体装置を前記貫通電極を通して電気的接続を図ることを含み、
前記複数のパッドを、相似の位置にあって内側に相似の中心を有する複数の相似形の線上に中心が位置するように配列し、
それぞれの前記パッドを、その中心が他の２つの前記パッドの中心を結んだ仮想直線上を避けるように配置する。本発明によれば、半導体基板には、パッドが、３個以上並ばないように配置される。パッドが３個以上並ばないことから、パッドが一方向へ与える力が小さい半導体基板を製造することができる。そのため、ストレスが集中しない半導体基板を有する、信頼性の高い半導体装置を製造することができる。本発明によれば、半導体基板には、貫通電極が、３個以上並ばないように形成されため、半導体基板が割れにくくなる。そのため、割れにくい半導体基板を有する、信頼性の高い半導体装置を製造することができる。本発明によれば、割れにくい半導体基板を有する半導体装置を積層するため、信頼性の高い積層型の半導体装置を製造することができる。
【０００７】
【発明の実施の形態】
以下、本発明を適用した実施の形態について図面を参照して説明する。ただし、本発明は、以下の実施の形態に限定されるものではない。
【０００８】
（第１の実施の形態）
図１（Ａ）〜図２は、本発明を適用した第１の実施の形態に係る半導体装置を説明するための図である。なお、図１（Ａ）は、パッド１４の配置を説明するための補助線（相似形２０及び相似の中心２２）が記載された半導体基板１０を示す図である。図１（Ｂ）は、図１（Ａ）から該補助線を取り除いた、半導体基板１０を示す図である。
【０００９】
本実施の形態に係る半導体装置は、半導体基板１０を有する。半導体基板１０は、半導体チップであってもよい。半導体基板１０の内部には集積回路１２が形成されてなる（図２参照）。半導体基板１０の平面形状は特に限定されず、例えば矩形であってもよい。
【００１０】
本実施の形態に係る半導体装置は、複数のパッド１４を有する。パッド１４は、半導体基板１０上に形成されてなる。パッド１４は、半導体基板１０の内部と電気的に接続するように形成されていてもよい。例えば、パッド１４は集積回路１２と電気的に接続されていてもよい。あるいは、集積回路１２とは電気的に接続されないパッドを含めて、パッド１４と称してもよい。パッド１４は、アルミニウムで形成されていてもよい。パッド１４の平面形状は特に限定されないが、図１（Ａ）及び図１（Ｂ）に示すように円形であってもよく、あるいは、矩形（図示せず）であってもよい。また、図１（Ａ）及び図１（Ｂ）に示すように、パッド１４は、半導体基板１０の中央部を避け、周縁部にのみ形成されていてもよい。
【００１１】
パッド１４は、相似の位置にあって内側に相似の中心２２を有する複数の相似形２０の線上に中心が位置するように配列されてなる。ここで、２つの図形上の点どうしの間に１対１の対応が付けられ、その対応する点を結ぶ直線が全て１点で交わり、その直線が該１点によって全て同じ比に内分あるいは外分されている場合に、その２つの図形は相似の位置にあるという。また、このとき、直線が交わるその１点を相似の中心という。本実施の形態に係る半導体装置では、上記の関係を有する複数の相似形２０の線上に中心が位置するように、パッド１４が配置されてなる。なお、本実施の形態に係る半導体装置では、図１（Ａ）に示すように、相似の中心２２は、すべての相似形２０の内側に存在する。
【００１２】
それぞれのパッド１４は、その中心が他の２つのパッド１４の中心を結んだ仮想直線上を避けて配置されてなる。言い換えると、パッド１４は、３個以上のパッドが一直線上に並ばないように配置されてなる。そして、３個以上のパッドが一直線上に並ばないことから、パッド１４から半導体基板１０に対して一方向への大きな力を与えることを防止することができる。そのため、ストレスが集中しない半導体基板を有する、信頼性の高い半導体装置を提供することができる。
【００１３】
半導体基板１０には、１層又はそれ以上の層の絶縁膜が形成されていてもよい（図２参照）。該絶縁膜は、半導体基板１０におけるパッド１４が形成された面上に形成されていてもよい。図２に示す例では、半導体基板１０には絶縁膜１６，１８が形成されている。絶縁膜１６上には、パッド１４と、集積回路１２とパッド１４とを電気的に接続する配線（図示せず）が形成されていてもよい。また、絶縁膜１６上には、他の絶縁膜１８が、パッド１４の少なくとも一部を避けて形成されていてもよい。パッド１４の表面を覆うように絶縁膜１８を形成した後、その一部をエッチングして開口を形成し、該開口からパッド１４の一部を露出させてもよい。なお、絶縁膜１６は酸化膜によって形成されていてもよい。また、絶縁膜１８は、パッシベーション膜と称してもよく、ＳｉＮ、ＳｉＯ２、ポリイミド樹脂等で形成してもよい。
【００１４】
本発明を適用した第１の実施の形態に係る半導体装置１は、以上のように構成されてなる。なお、本発明を適用した第１の実施の形態に係る半導体装置は、配線基板３０をさらに有してもよい（図２参照）。配線基板３０には、複数の配線３２が形成されてなる。上記半導体装置１は、配線基板３０に搭載されていてもよく、パッド１４と配線３２とが電気的に接続されていてもよい。配線基板３０には、複数の外部端子３４が形成されていてもよく、これにより、回路基板等に実装しやすい半導体装置１００を提供することができる。
【００１５】
図２に示すように、半導体基板１０（半導体装置１）は、配線基板３０にフェースダウンボンディングされてもよく、パッド１４と配線３２とは、バンプ１５を介して電気的に接続されていてもよい。ここで、バンプ１５は、パッド１４における絶縁膜１８から露出する部分に形成されていてもよい。バンプ１５は、例えば無電解メッキで形成してもよいし、ワイヤーボンディングによるボールバンプであってもよい。パッド１４とバンプ１５との間にバンプ金属の拡散防止層として、ニッケル、クロム、チタン等を付加してもよい。
【００１６】
また、半導体基板１０と配線基板３０との間には樹脂層３６が形成されていてもよい。樹脂層３６は、アンダーフィル材と称してもよい。樹脂層３６は、液状またはゲル状で用意される接着剤であってもよいし、シート状で用意される接着シートであってもよい。樹脂層３６には、図示しない導電粒子が含まれていてもよく、該導電粒子を介して、バンプ１５と配線３２とを電気的に接続させてもよい。これにより、電気的な信頼性、及び、外力に対する信頼性の高い半導体装置１００を提供することができる。
【００１７】
図３には、本発明を適用した実施の形態に係る半導体装置１００が実装された回路基板１０００を示す。また、本発明を適用した実施の形態に係る半導体装置を有する電子機器として、図４にはノート型パーソナルコンピュータ２０００が、図５には携帯電話３０００が、それぞれ示されている。
【００１８】
以下、本発明を適用した第１の実施の形態に係る半導体装置１の製造方法について説明する。半導体装置１の製造方法は、集積回路１２が内部に形成されてなる半導体基板１０に、その内部に電気的に接続されるように複数のパッド１４を形成することを含む。このとき、複数のパッド１４を、相似の位置にあって内側に相似の中心２２を有する複数の相似形２０の線上に中心が位置するように配列し、それぞれのパッド１４を、その中心が他の２つのパッド１４の中心を結んだ仮想直線上を避けるように配置する。これにより、信頼性の高い半導体装置を製造することができる。このとき、パッド１４は、半導体基板１０の中央部を避けて、周縁部に形成してもよい。
【００１９】
なお、本発明は、上記実施の形態に限定されるものではなく、種々の変形が可能である。例えば、図６に示すように、半導体基板１０は、エリアアレイ状に配置されたパッド４０を有してもよい。
【００２０】
あるいは、例えば、図７に示すように、半導体基板１０は、同心円５０の線上に中心が位置するように配列されたパッド５２を有してもよい。言い換えると、パッド５２は、相似形５０の線上に中心が位置するように配列されており、相似形５０は円であってもよい。そして、１つの相似形５０上に複数のパッド５２の中心が位置するように、パッド５２が配列されていてもよい。パッド５２の配列は特に限定されるものではないが、相似形５０上に等間隔に配列されていてもよい。各相似形５０に、同数のパッド５２が配置されてもよい。例えば、２つの相似形５０に、偶数個のパッド５２が同数ずつ配置されている場合、パッド５２配列の位相をずらすことによって、パッド５２を３個以上並ばないように配列してもよい（図７参照）。あるいは、２つの相似形５２に、奇数個のパッドが同数ずつ配置されている場合、図８に示すように、パッド５４の配列の位相をずらすことによって、あるいは、図９に示すように、パッド５６の配列を同位相として、パッドを３個以上並ばないように配置してもよい。なお、相似形５０の数、及び、１つの相似形５０上に配置されるパッドの数については、これに限定されるものではない。また、それぞれの相似形５０上に、異なる数のパッドが配置されていてもよい。
【００２１】
以上の変形例で、具体的に説明した内容以外の点については、上述した実施の形態と同じ内容が当てはまり、同じ効果を達成することができる。
【００２２】
（第２の実施形態）
以下、本発明を適用した第２の実施の形態に係る半導体装置について説明する。なお、本実施の形態でも、既に述べた内容を可能な限り適用するものとする。
【００２３】
図１０は、本実施の形態に係る半導体装置の断面の一部拡大図である。本実施の形態に係る半導体装置は、半導体基板６０を有する。半導体基板６０の内部には、集積回路６２が形成されてなる。半導体基板６０には、１層又はそれ以上の層の絶縁膜が形成されていてもよい。図１０に示す例では、半導体基板６０には絶縁膜６６，６８が形成されている。絶縁膜６６，６８の内容については、既に述べた絶縁膜１６，１８の内容を適用することができる。
【００２４】
半導体基板６０には、複数のパッド７０が形成されてなる。パッド７０の配置については、既に説明したいずれかの内容を適用してもよい。パッド７０には貫通穴７２が形成されてなる。また、半導体基板６０には、貫通穴７２とオーバーラップする貫通穴６４が形成されてなる。すなわち、半導体基板６０の貫通穴６４は、パッド７０とオーバーラップするように形成されてなる。そのため、貫通穴６４は、３個以上が直線上に並ばないように配列される。なお、貫通穴７２を第１の貫通穴と、貫通穴６４を第２の貫通穴と、それぞれ称してもよい。
【００２５】
貫通穴６４，７２は、エッチング（ドライエッチング又はウエットエッチング）を適用して形成してもよい。エッチングは、リソグラフィ工程によってパターニングされたレジストを形成した後に行ってもよい。例えば、パッド７０に貫通穴７２を形成した後に、貫通穴７２の領域内に貫通穴６４を形成してもよい。パッド７０の下に絶縁膜６６が形成されている場合、これにも貫通穴６７を形成する。貫通穴６７の形成にも、エッチング（ドライエッチング又はウエットエッチング）を適用してもよい。あるいは、貫通穴６４，６７，７２を、レーザ（例えばＣＯ２レーザ、ＹＡＧレーザ等）によって形成してもよい。一種類のエッチャント又はレーザによって、貫通穴６４，６７，７２を連続して形成してもよい。
【００２６】
本実施の形態に係る半導体装置は、絶縁層８０を有する。絶縁層８０は、貫通穴６４の内面に形成されてなる。絶縁層６４は、酸化膜であってもよい。例えば、半導体基板６０の基材がＳｉである場合、絶縁層８０はＳｉＯ２であってもよいしＳｉＮであってもよい。絶縁層８０は、パッド７０の一部（例えばその上面）を避けて形成されていてもよい。これによって、パッド７０と後述する貫通電極９０との電気的な接続を図ることができる。なお、絶縁層８０は、絶縁膜６８（パッシベーション膜）上に形成されていてもよい（図示せず）。あるいは、絶縁層８０は、半導体基板６０におけるパッド７０が形成された面とは反対側の面上に形成されていてもよい。
【００２７】
本実施の形態に係る半導体装置は、貫通電極９０を有する。貫通電極９０は、絶縁層８０の内側を通り、半導体基板６０を貫通する。これによって、半導体基板６０の両面を電気的に接続することができる。なお、貫通穴９０は、貫通穴７２の内側を通り、パッド７０を貫通するように形成される。先に述べたように、貫通穴６４は、３個以上が直線上に並ばないように配置されてなる。そして、貫通電極９０は貫通穴６４の内側を通るため、貫通電極９０も、３個以上が直線上に並ばないように配置される。これにより、貫通電極９０から半導体基板６０に対して一方向への大きな力を与えることを防止することができる。そのため、ストレスが集中しない半導体基板を有する、信頼性の高い半導体装置を提供することができる。
【００２８】
貫通電極９０は、パターニングされたレジストを形成する工程と、レジストから露出した部分に貫通電極９０を形成する工程と、によって形成してもよい。このとき、貫通電極９０は、電解メッキやインクジェット方式等の既に公知となっているいずれかの方法を適用して形成してもよい。なお、貫通電極９０の材料は特に限定されないが、例えば、Ｃｕであってもよい。
【００２９】
本発明を適用した第２の実施の形態に係る半導体装置２は、以上のように構成されてなる。以下、半導体装置２の製造方法について説明する。半導体装置の製造方法は、内部に集積回路６２を有する半導体基板６０に複数のパッド７０を形成すること、パッド７０に貫通穴（第１の貫通穴）７２を、半導体基板６０に貫通穴（第２の貫通穴）６４を、それぞれ形成すること、貫通穴６４の内面に絶縁層８０を形成すること、及び、絶縁層８０の内側を通り半導体基板６０を貫通する貫通電極９０を形成することを含んでもよい。なお、パッド７０の配置や、貫通穴６４，７２及び貫通電極９０の形成方法については、既に述べた内容を適用することができる。
【００３０】
図１１は、積層型の半導体装置２００を示す図である。半導体装置２００は、積層された半導体装置２を有する。そして、該半導体装置同士は、貫通電極９０を通して電気的接続が図られてなる。図１１に示すように、貫通電極９０同士接触させて、電気的に接続してもよい。あるいは、図示しない導電粒子を含む異方性導電ペースト（ＡＣＰ）や異方性導電フィルム（ＡＣＦ）を用いて、非接触で貫通電極９０同士を電気的に接続してもよい。
【００３１】
半導体装置２００は、配線基板２１０を有してもよく、積層された半導体装置２は配線基板２１０に搭載されていてもよい。配線基板２１０には、複数の配線２１２が形成されていてもよく、また、外部端子２１４が形成されていてもよい。これにより、回路基板等に実装しやすい半導体装置２００を提供することができる。さらに、積層された各半導体装置２の間には、図示しない絶縁層（応力緩和機能を有してもよい）が形成されていてもよい。これにより、信頼性の高い半導体装置２００を製造することができる。なお、図１２には、本発明を適用した第２の実施の形態に係る積層型の半導体装置２００が実装された回路基板４０００を示す。
【００３２】
なお、本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び効果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。
【図面の簡単な説明】
【図１】 図１（Ａ）及び図１（Ｂ）は、本発明を適用した第１の実施の形態に係る半導体装置を示す図である。
【図２】 図２は、本発明を適用した第１の実施の形態に係る半導体装置を示す図である。
【図３】 図３は、本発明を適用した第１の実施の形態に係る半導体装置が実装された回路基板を示す図である。
【図４】 図４は、本発明を適用した第１の実施の形態に係る半導体装置を有する電子機器を示す図である。
【図５】 図５は、本発明を適用した第１の実施の形態に係る半導体装置を有する電子機器を示す図である。
【図６】 図６は、本発明を適用した第１の実施の形態に係る半導体装置の変形例を示す図である。
【図７】 図７は、本発明を適用した第１の実施の形態に係る半導体装置の変形例を示す図である。
【図８】 図８は、本発明を適用した第１の実施の形態に係る半導体装置の変形例を示す図である。
【図９】 図９は、本発明を適用した第１の実施の形態に係る半導体装置の変形例を示す図である。
【図１０】 図１０は、本発明を適用した第２の実施の形態に係る半導体装置を示す図である。
【図１１】 図１１は、本発明を適用した第２の実施の形態に係る半導体装置を示す図である。
【図１２】 図１２は、本発明を適用した第２の実施の形態に係る半導体装置が実装された回路基板を示す図である。
【符号の説明】
１０ 半導体基板、 １２ 集積回路、 １４ パッド、 ２０ 相似形、
２２ 相似の中心[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing how.
[0002]
[Prior art]
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 1-261837 [Patent Document 2]
Japanese Patent Laid-Open No. 11-354231 [0004]
BACKGROUND OF THE INVENTION
A pad is generally formed on the surface of a semiconductor substrate. In order to increase the reliability of the semiconductor device, it is necessary to reduce the stress on the semiconductor substrate due to the pads. In particular, a highly reliable semiconductor device can be provided if a large amount of stress in one direction can be prevented.
[0005]
An object of the present invention is to provide a highly reliable semiconductor device and a manufacturing how.
[0006]
[Means for Solving the Problems]
(1) A semiconductor device according to the present invention includes a semiconductor substrate having an integrated circuit formed therein,
A plurality of pads formed on the semiconductor substrate so as to be electrically connected thereto;
Including
The pad is formed with a first through hole, and the semiconductor substrate is formed with a second through hole that overlaps the first through hole, respectively.
An insulating layer formed on the inner surface of the second through hole;
A through electrode passing through the semiconductor substrate through the inside of the insulating layer;
Further comprising
The plurality of pads are arranged such that their centers are located on a plurality of similar lines having similar centers at the same position and having similar centers inside.
Each of the pads has a plurality of stacked semiconductor devices arranged so as to avoid a virtual straight line connecting the centers of the other two pads , and the stacked semiconductor devices pass through the through electrodes. Electrical connection is made . According to the present invention, the semiconductor device has a semiconductor substrate arranged so that three or more pads are not lined up. Since three or more pads are not arranged, it is possible to provide a semiconductor substrate in which the force exerted by the pad in one direction is small. Therefore, a highly reliable semiconductor device including a semiconductor substrate in which stress is not concentrated can be provided. According to the present invention, since three or more through electrodes are not arranged in the semiconductor substrate, the semiconductor substrate is hardly broken. Therefore, a highly reliable semiconductor device including a semiconductor substrate that is difficult to break can be provided. According to the present invention, it is possible to provide a highly reliable stacked semiconductor device in which semiconductor devices each having a semiconductor substrate that is not easily broken are stacked.
(2) In this semiconductor device,
The pad may be formed on the peripheral edge, avoiding the central part of the semiconductor substrate .
(3) In the semiconductor device manufacturing method according to the present invention, a plurality of pads are formed on a semiconductor substrate having an integrated circuit formed therein so as to be electrically connected to the inside .
Forming a first through hole in the pad and a second through hole overlapping the first through hole in the semiconductor substrate;
Forming an insulating layer on the inner surface of the second through hole; and
Forming a through electrode passing through the semiconductor substrate through the inside of the insulating layer;
Including stacking a plurality of semiconductor devices obtained by the manufacturing method, and electrically connecting the plurality of stacked semiconductor devices through the through electrodes ,
The plurality of pads are arranged so that the centers are located on a plurality of similar lines having similar centers at the similar positions on the inside,
Each of the pads is arranged so as to avoid a virtual straight line connecting the centers of the other two pads. According to the present invention, three or more pads are arranged on the semiconductor substrate so as not to line up. Since three or more pads are not arranged, it is possible to manufacture a semiconductor substrate having a small force exerted by the pads in one direction. Therefore, a highly reliable semiconductor device including a semiconductor substrate on which stress is not concentrated can be manufactured . According to the present invention , the semiconductor substrate is formed such that three or more through electrodes are not arranged in the semiconductor substrate, so that the semiconductor substrate is hardly broken. Therefore, a highly reliable semiconductor device having a semiconductor substrate that is difficult to break can be manufactured . According to the present invention, since a semiconductor device having a semiconductor substrate that is hard to break is stacked, a highly reliable stacked semiconductor device can be manufactured.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.
[0008]
(First embodiment)
FIG. 1A to FIG. 2 are diagrams for explaining a semiconductor device according to a first embodiment to which the present invention is applied. FIG. 1A is a diagram illustrating the semiconductor substrate 10 on which auxiliary lines (similar shape 20 and similar center 22) for describing the arrangement of the pads 14 are described. FIG. 1B is a diagram illustrating the semiconductor substrate 10 in which the auxiliary line is removed from FIG.
[0009]
The semiconductor device according to the present embodiment has a semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor chip. An integrated circuit 12 is formed inside the semiconductor substrate 10 (see FIG. 2). The planar shape of the semiconductor substrate 10 is not particularly limited, and may be rectangular, for example.
[0010]
The semiconductor device according to the present embodiment has a plurality of pads 14. The pad 14 is formed on the semiconductor substrate 10. The pad 14 may be formed so as to be electrically connected to the inside of the semiconductor substrate 10. For example, the pad 14 may be electrically connected to the integrated circuit 12. Alternatively, it may be referred to as a pad 14 including a pad that is not electrically connected to the integrated circuit 12. The pad 14 may be made of aluminum. The planar shape of the pad 14 is not particularly limited, but may be circular as shown in FIGS. 1A and 1B, or may be rectangular (not shown). Further, as shown in FIGS. 1A and 1B, the pad 14 may be formed only at the peripheral portion, avoiding the central portion of the semiconductor substrate 10.
[0011]
The pads 14 are arranged in such a manner that their centers are located on the line of a plurality of similar shapes 20 having similar centers 22 at similar positions. Here, there is a one-to-one correspondence between the points on the two figures, all the straight lines connecting the corresponding points intersect at one point, and the straight lines are all divided into the same ratio by the one point or The two figures are said to be in a similar position when they are divided. At this time, one point where the straight lines intersect is called a similar center. In the semiconductor device according to the present embodiment, the pad 14 is arranged so that the center is located on the line of the plurality of similar shapes 20 having the above relationship. In the semiconductor device according to the present embodiment, as shown in FIG. 1A, the similar center 22 exists inside all the similar shapes 20.
[0012]
Each pad 14 is arranged so that its center avoids the virtual straight line connecting the centers of the other two pads 14. In other words, the pads 14 are arranged so that three or more pads do not line up in a straight line. Since three or more pads do not line up in a straight line, it is possible to prevent a large force from being applied in one direction from the pad 14 to the semiconductor substrate 10. Therefore, a highly reliable semiconductor device including a semiconductor substrate in which stress is not concentrated can be provided.
[0013]
One or more insulating films may be formed on the semiconductor substrate 10 (see FIG. 2). The insulating film may be formed on the surface of the semiconductor substrate 10 on which the pad 14 is formed. In the example shown in FIG. 2, insulating films 16 and 18 are formed on the semiconductor substrate 10. On the insulating film 16, a pad (not shown) that electrically connects the integrated circuit 12 and the pad 14 may be formed. Further, another insulating film 18 may be formed on the insulating film 16 while avoiding at least a part of the pad 14. After the insulating film 18 is formed so as to cover the surface of the pad 14, a part thereof may be etched to form an opening, and a part of the pad 14 may be exposed from the opening. The insulating film 16 may be formed of an oxide film. The insulating film 18 may be referred to as a passivation film, and may be formed of SiN, SiO 2 , polyimide resin, or the like.
[0014]
The semiconductor device 1 according to the first embodiment to which the present invention is applied is configured as described above. Note that the semiconductor device according to the first embodiment to which the present invention is applied may further include a wiring board 30 (see FIG. 2). A plurality of wirings 32 are formed on the wiring board 30. The semiconductor device 1 may be mounted on the wiring board 30, and the pad 14 and the wiring 32 may be electrically connected. A plurality of external terminals 34 may be formed on the wiring board 30, whereby the semiconductor device 100 that can be easily mounted on a circuit board or the like can be provided.
[0015]
As shown in FIG. 2, the semiconductor substrate 10 (semiconductor device 1) may be face-down bonded to the wiring substrate 30, and the pad 14 and the wiring 32 may be electrically connected via the bump 15. Good. Here, the bump 15 may be formed on a portion of the pad 14 exposed from the insulating film 18. The bump 15 may be formed by electroless plating, for example, or may be a ball bump by wire bonding. Nickel, chromium, titanium or the like may be added as a bump metal diffusion prevention layer between the pad 14 and the bump 15.
[0016]
In addition, a resin layer 36 may be formed between the semiconductor substrate 10 and the wiring substrate 30. The resin layer 36 may be referred to as an underfill material. The resin layer 36 may be an adhesive prepared in liquid or gel form, or may be an adhesive sheet prepared in sheet form. The resin layer 36 may contain conductive particles (not shown), and the bumps 15 and the wirings 32 may be electrically connected through the conductive particles. Accordingly, it is possible to provide the semiconductor device 100 with high electrical reliability and high reliability against external force.
[0017]
FIG. 3 shows a circuit board 1000 on which a semiconductor device 100 according to an embodiment to which the present invention is applied is mounted. Further, as an electronic device having a semiconductor device according to an embodiment to which the present invention is applied, FIG. 4 shows a notebook personal computer 2000 and FIG. 5 shows a mobile phone 3000.
[0018]
A method for manufacturing the semiconductor device 1 according to the first embodiment to which the present invention is applied will be described below. The manufacturing method of the semiconductor device 1 includes forming a plurality of pads 14 on a semiconductor substrate 10 in which an integrated circuit 12 is formed so as to be electrically connected to the inside. At this time, the plurality of pads 14 are arranged so that the centers are located on the line of the plurality of similar shapes 20 having similar centers 22 at the similar positions on the inside, and each pad 14 has the center at the other side. Are arranged so as to avoid a virtual straight line connecting the centers of the two pads 14. Thereby, a highly reliable semiconductor device can be manufactured. At this time, the pad 14 may be formed at the peripheral edge, avoiding the central portion of the semiconductor substrate 10.
[0019]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, as shown in FIG. 6, the semiconductor substrate 10 may have pads 40 arranged in an area array.
[0020]
Alternatively, for example, as shown in FIG. 7, the semiconductor substrate 10 may have pads 52 arranged so that the centers thereof are located on the lines of the concentric circles 50. In other words, the pads 52 are arranged so that their centers are located on the line of the similar shape 50, and the similar shape 50 may be a circle. The pads 52 may be arranged so that the centers of the plurality of pads 52 are positioned on one similar shape 50. The arrangement of the pads 52 is not particularly limited, but may be arranged on the similar shape 50 at equal intervals. The same number of pads 52 may be arranged in each similar shape 50. For example, when the same number of pads 52 are arranged in two similar shapes 50, three or more pads 52 may be arranged so as not to line up by shifting the phase of the pad 52 arrangement (see FIG. 7). Alternatively, when the odd number of pads are arranged in two similar shapes 52, the pads 54 are shifted in phase as shown in FIG. 8, or as shown in FIG. The arrangement of 56 may be the same phase, and three or more pads may not be arranged. The number of similar shapes 50 and the number of pads arranged on one similar shape 50 are not limited to this. Further, a different number of pads may be arranged on each similar shape 50.
[0021]
In the above modification, the same contents as in the above-described embodiment apply to points other than the contents specifically described, and the same effect can be achieved.
[0022]
(Second Embodiment)
The semiconductor device according to the second embodiment to which the present invention is applied will be described below. Note that the contents described above are applied as much as possible in this embodiment.
[0023]
FIG. 10 is a partially enlarged view of a cross section of the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment has a semiconductor substrate 60. An integrated circuit 62 is formed inside the semiconductor substrate 60. One or more insulating films may be formed on the semiconductor substrate 60. In the example shown in FIG. 10, insulating films 66 and 68 are formed on the semiconductor substrate 60. As the contents of the insulating films 66 and 68, the contents of the insulating films 16 and 18 already described can be applied.
[0024]
A plurality of pads 70 are formed on the semiconductor substrate 60. Any of the contents described above may be applied to the arrangement of the pad 70. A through hole 72 is formed in the pad 70. The semiconductor substrate 60 is formed with a through hole 64 that overlaps the through hole 72. That is, the through hole 64 of the semiconductor substrate 60 is formed so as to overlap the pad 70. Therefore, the through holes 64 are arranged so that three or more do not line up on a straight line. The through hole 72 may be referred to as a first through hole, and the through hole 64 may be referred to as a second through hole.
[0025]
The through holes 64 and 72 may be formed by applying etching (dry etching or wet etching). Etching may be performed after forming a patterned resist by a lithography process. For example, the through hole 64 may be formed in the region of the through hole 72 after the through hole 72 is formed in the pad 70. When the insulating film 66 is formed under the pad 70, the through hole 67 is also formed there. Etching (dry etching or wet etching) may also be applied to the formation of the through hole 67. Alternatively, the through holes 64, 67, 72 may be formed by a laser (for example, a CO 2 laser, a YAG laser, etc.). The through holes 64, 67, 72 may be continuously formed by one kind of etchant or laser.
[0026]
The semiconductor device according to the present embodiment has an insulating layer 80. The insulating layer 80 is formed on the inner surface of the through hole 64. The insulating layer 64 may be an oxide film. For example, when the base material of the semiconductor substrate 60 is Si, the insulating layer 80 may be SiO 2 or SiN. The insulating layer 80 may be formed avoiding a part of the pad 70 (for example, the upper surface thereof). As a result, electrical connection between the pad 70 and a through electrode 90 described later can be achieved. The insulating layer 80 may be formed on the insulating film 68 (passivation film) (not shown). Alternatively, the insulating layer 80 may be formed on the surface of the semiconductor substrate 60 opposite to the surface on which the pads 70 are formed.
[0027]
The semiconductor device according to the present embodiment has a through electrode 90. The through electrode 90 passes through the inside of the insulating layer 80 and penetrates the semiconductor substrate 60. Thereby, both surfaces of the semiconductor substrate 60 can be electrically connected. The through hole 90 is formed so as to pass through the pad 70 through the inside of the through hole 72. As described above, the through holes 64 are arranged so that three or more of the through holes 64 do not line up on a straight line. And since the penetration electrode 90 passes the inner side of the penetration hole 64, the penetration electrode 90 is also arrange | positioned so that three or more may not line up on a straight line. Thereby, it is possible to prevent a large force in one direction from being applied to the semiconductor substrate 60 from the through electrode 90. Therefore, a highly reliable semiconductor device including a semiconductor substrate in which stress is not concentrated can be provided.
[0028]
The through electrode 90 may be formed by a step of forming a patterned resist and a step of forming the through electrode 90 in a portion exposed from the resist. At this time, the through electrode 90 may be formed by applying any known method such as electrolytic plating or an inkjet method. The material of the through electrode 90 is not particularly limited, but may be Cu, for example.
[0029]
The semiconductor device 2 according to the second embodiment to which the present invention is applied is configured as described above. Hereinafter, a method for manufacturing the semiconductor device 2 will be described. In the method for manufacturing a semiconductor device, a plurality of pads 70 are formed in a semiconductor substrate 60 having an integrated circuit 62 therein, through holes (first through holes) 72 are formed in the pads 70, and through holes (first holes) are formed in the semiconductor substrate 60. 2 through holes) 64, forming the insulating layer 80 on the inner surface of the through hole 64, and forming the through electrode 90 that passes through the inside of the insulating layer 80 and penetrates the semiconductor substrate 60. May be included. The contents already described can be applied to the arrangement of the pad 70 and the method of forming the through holes 64 and 72 and the through electrode 90.
[0030]
FIG. 11 is a diagram illustrating a stacked semiconductor device 200. The semiconductor device 200 includes stacked semiconductor devices 2. The semiconductor devices are electrically connected through the through electrode 90. As shown in FIG. 11, the through electrodes 90 may be brought into contact with each other and electrically connected. Alternatively, the through electrodes 90 may be electrically connected to each other in a non-contact manner using an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF) containing conductive particles (not shown).
[0031]
The semiconductor device 200 may include a wiring substrate 210, and the stacked semiconductor device 2 may be mounted on the wiring substrate 210. A plurality of wirings 212 may be formed on the wiring board 210, and external terminals 214 may be formed. Thereby, the semiconductor device 200 that can be easily mounted on a circuit board or the like can be provided. Furthermore, an insulating layer (not shown) (which may have a stress relaxation function) may be formed between the stacked semiconductor devices 2. Thereby, the semiconductor device 200 with high reliability can be manufactured. FIG. 12 shows a circuit board 4000 on which the stacked semiconductor device 200 according to the second embodiment to which the present invention is applied is mounted.
[0032]
In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1A and FIG. 1B are diagrams showing a semiconductor device according to a first embodiment to which the present invention is applied.
FIG. 2 is a diagram illustrating a semiconductor device according to a first embodiment to which the present invention is applied.
FIG. 3 is a diagram showing a circuit board on which the semiconductor device according to the first embodiment to which the present invention is applied is mounted.
FIG. 4 is a diagram illustrating an electronic apparatus having the semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 5 is a diagram showing an electronic apparatus having the semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 6 is a diagram showing a modification of the semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 7 is a diagram showing a modification of the semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 8 is a diagram showing a modification of the semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 9 is a diagram showing a modification of the semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 10 is a diagram showing a semiconductor device according to a second embodiment to which the present invention is applied.
FIG. 11 is a diagram showing a semiconductor device according to a second embodiment to which the present invention is applied.
FIG. 12 is a diagram showing a circuit board on which a semiconductor device according to a second embodiment to which the present invention is applied is mounted.
[Explanation of symbols]
10 semiconductor substrates, 12 integrated circuits, 14 pads, 20 analogs,
22 The center of similarity

Claims (3)

集積回路が内部に形成されてなる半導体基板と、
前記半導体基板上に、その内部に電気的に接続されるように形成されてなる複数のパッドと、
を含み、
前記パッドには第１の貫通穴が、前記半導体基板には前記第１の貫通穴とオーバーラップする第２の貫通穴が、それぞれ形成されてなり、
前記第２の貫通穴の内面に形成された絶縁層と、
前記絶縁層の内側を通り前記半導体基板を貫通する貫通電極と、
をさらに有し、
前記複数のパッドは、相似の位置にあって内側に相似の中心を有する複数の相似形の線上に中心が位置するように配列され、
それぞれの前記パッドは、その中心が他の２つの前記パッドの中心を結んだ仮想直線上を避けて配置されてなる半導体装置を複数積層し、かつ、複数積層した前記半導体装置が前記貫通電極を通して電気的接続が図られてなる半導体装置。A semiconductor substrate having an integrated circuit formed therein;
A plurality of pads formed on the semiconductor substrate so as to be electrically connected thereto;
Including
The pad is formed with a first through hole, and the semiconductor substrate is formed with a second through hole that overlaps the first through hole, respectively.
An insulating layer formed on the inner surface of the second through hole;
A through electrode passing through the semiconductor substrate through the inside of the insulating layer;
Further comprising
The plurality of pads are arranged such that their centers are located on a plurality of similar lines having similar centers at the same position and having similar centers inside.
Each of the pads has a plurality of stacked semiconductor devices arranged so as to avoid a virtual straight line connecting the centers of the other two pads , and the stacked semiconductor devices pass through the through electrodes. A semiconductor device in which electrical connection is achieved . 請求項１記載の半導体装置において、
前記パッドは、前記半導体基板の中央部を避けて、周縁部に形成されてなる半導体装置。The semiconductor device according to claim 1,
The said pad is a semiconductor device formed in a peripheral part avoiding the center part of the said semiconductor substrate. 集積回路が内部に形成されてなる半導体基板に、その内部に電気的に接続されるように複数のパッドを形成すること、
前記パッドには第１の貫通穴を、前記半導体基板には前記第１の貫通穴とオーバーラップする第２の貫通穴を、それぞれ形成すること、
前記第２の貫通穴の内面に絶縁層を形成すること、及び、
前記絶縁層の内側を通り前記半導体基板を貫通する貫通電極を形成すること、
を含む製造方法で得られた半導体装置を複数積層し、かつ、複数積層した前記半導体装置を前記貫通電極を通して電気的接続を図ることを含み、
前記複数のパッドを、相似の位置にあって内側に相似の中心を有する複数の相似形の線上に中心が位置するように配列し、
それぞれの前記パッドを、その中心が他の２つの前記パッドの中心を結んだ仮想直線上を避けるように配置する半導体装置の製造方法。Forming a plurality of pads on a semiconductor substrate having an integrated circuit formed therein so as to be electrically connected to the inside ;
Forming a first through hole in the pad and a second through hole overlapping the first through hole in the semiconductor substrate;
Forming an insulating layer on the inner surface of the second through hole; and
Forming a through electrode passing through the semiconductor substrate through the inside of the insulating layer;
Including stacking a plurality of semiconductor devices obtained by the manufacturing method, and electrically connecting the plurality of stacked semiconductor devices through the through electrodes ,
The plurality of pads are arranged so that the centers are located on a plurality of similar lines having similar centers at the similar positions on the inside,
A method of manufacturing a semiconductor device, wherein each of the pads is arranged so that a center thereof avoids a virtual straight line connecting the centers of the other two pads.
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