JP2004327527A - Electronic device, its manufacturing process and electronic apparatus - Google Patents

Electronic device, its manufacturing process and electronic apparatus Download PDF

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JP2004327527A
JP2004327527A JP2003116896A JP2003116896A JP2004327527A JP 2004327527 A JP2004327527 A JP 2004327527A JP 2003116896 A JP2003116896 A JP 2003116896A JP 2003116896 A JP2003116896 A JP 2003116896A JP 2004327527 A JP2004327527 A JP 2004327527A
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Prior art keywords
electrode
substrate
electronic device
elastically deformable
wiring pattern
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Nobuaki Hashimoto
伸晃 橋元
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2003116896A priority Critical patent/JP2004327527A/en
Priority to CNB2004100328987A priority patent/CN1316309C/en
Priority to US10/829,146 priority patent/US6965164B2/en
Publication of JP2004327527A publication Critical patent/JP2004327527A/en
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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1345—Conductors connecting electrodes to cell terminals
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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Abstract

<P>PROBLEM TO BE SOLVED: To enhance bonding strength at the electrical joint of a semiconductor substrate and a substrate. <P>SOLUTION: The electronic device has a semiconductor substrate 10 having an integrated circuit 12 formed internally, an insulating layer 20 formed on the semiconductor substrate 10 and having an elastically deformable part 24, an electrode 34 formed on the elastically deformable part 24 while being connected electrically with the interior of the semiconductor substrate 10, and a substrate 58 on which a wiring pattern 62 is formed oppositely to the electrode 34 while being connected electrically therewith. The elastically deformable part 24 deforms elastically to sink below the electrode 34 and presses the electrode 34 against the wiring pattern 62 with an elastic force. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、電子装置及びその製造方法並びに電子機器に関する。
【０００２】
【従来の技術】
【０００３】
【特許文献１】
特開平９−３３９４０号公報
【特許文献２】
特許第２７９８０２７号公報
【０００４】
【発明の背景】
ＣＯＧ（Ｃｈｉｐ Ｏｎ Ｇｌａｓｓ）のように、硬い基板に半導体チップをフェースダウンボンディングすることが知られている。この実装形態では、基板の弾力性がほとんどないため、半導体チップと基板との電気的接続部分の接合力強化が課題となっていた。
【０００５】
本発明の目的は、半導体基板と基板との電気的接続部分の接合力強化を強化することにある。
【０００６】
【課題を解決するための手段】
（１）本発明に係る電子装置は、集積回路が内部に形成された半導体基板と、
前記半導体基板上に形成されて弾性変形可能部を有する絶縁層と、
前記半導体基板の内部に電気的に接続されて前記弾性変形可能部上に形成されてなる電極と、
前記電極と対向して電気的に接続された配線パターンが形成されてなる基板と、
を有し、
前記弾性変形可能部は、前記電極の下方において窪むように弾性変形し、弾性力によって、前記電極を前記配線パターンに押圧してなる。本発明によれば、絶縁層がその弾力性によって電極を配線パターンに押圧するので、半導体基板と基板との電気的接続部分の接合力を強化することができる。
（２）この電子装置は、
前記電極及び前記配線パターン間に設けられたバンプをさらに有し、前記バンプによって前記電極と前記配線パターンが電気的に接続されていてもよい。
（３）この電子装置において、
前記バンプは、ニッケル層を含んでもよい。
（４）本発明に係る電子機器は、上記電子装置を有する。
（５）本発明に係る電子装置の製造方法は、半導体装置を、配線パターンが形成されてなる基板に実装することを含み、
前記半導体装置は、集積回路が内部に形成された半導体基板と、前記半導体基板上に形成されて弾性変形可能部を有する絶縁層と、前記半導体基板の内部に電気的に接続されて前記弾性変形可能部上に形成されてなる電極と、を含み、
前記実装工程で、
前記半導体装置と前記基板を、前記電極が前記配線パターンと対向するように配置し、
前記弾性変形可能部を、前記電極の下方において窪むように弾性変形させる。本発明によれば、絶縁層を弾性変形させるので、絶縁層の弾力性によって電極を配線パターンに押圧することができ、半導体基板と基板との電気的接続部分の接合力を強化することができる。
（６）この電子装置の製造方法において、
前記半導体装置は、前記電極上に設けられたバンプをさらに有し、
前記バンプを介して、前記弾性変形可能部を弾性変形させてもよい。
【０００７】
【発明の実施の形態】
図１は、本発明の実施の形態に係る電子装置を説明する図である。電子装置は、半導体装置１を有する。図２及び図３は、半導体装置を説明する図であり、図２は、図３のＩＩ−ＩＩ線断面図である。
【０００８】
半導体装置１は、半導体基板（例えば半導体チップ）１０を有する。半導体基板１０の内部には、集積回路１２が形成されている。半導体基板１０には、複数のパッド１４が形成されている。パッド１４は半導体基板１０の内部と電気的に接続されている。パッド１４は、集積回路１２に電気的に接続された配線の一部（端部）であってもよい。複数のパッド１４は、半導体基板１０の表面の周縁部（端部）に形成されていてもよい。例えば、複数のパッド１４は、半導体基板１０の表面の四辺に沿って配列されていてもよいし、二辺に沿って配列されていてもよい。パッド１４は、例えばＡｌで形成されている。また、図示しないがパッド１４は、集積回路１２とオーバーラップするように形成してもよい。
【０００９】
半導体基板１０には、絶縁層（詳しくは電気的絶縁層）２０が形成されている。絶縁層２０は、パッシベーション膜２２を含んでもよい。パッシベーション膜２２は、樹脂でない材料（例えばＳｉＯ２又はＳｉＮ）のみで形成してもよいし、樹脂層を含んでもよい。パッシベーション膜２２には、パッド１４の少なくとも一部（例えば中央部）を露出させる開口が形成されている。すなわち、パッシベーション膜２２は、パッド１４の少なくとも中央部を避けて形成されている。パッド１４の端部にパッシベーション膜２２が載っていてもよい。
【００１０】
絶縁層２０は、弾性変形可能部２４を有する。弾性変形可能部２４は、弾性変形する性質（あるいは応力緩和機能）を有している。弾性変形可能部２４は、パッシベーション膜２２上に形成されている。弾性変形可能部２４は、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、ポリベンゾオキサゾール（ＰＢＯ；ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）等の弾性を有する樹脂で形成することが好ましい。また、弾性を有するものであれば無機材料（ガラスなど）でも構わない。弾性変形可能部２４は、パッシベーション膜２２の一部の領域に形成されていてもよい。例えば半導体基板１０の中央からいずれかの端部に偏った位置に、弾性変形可能部２４を形成してもよい。弾性変形可能部２４の少なくとも一部（例えば一部のみ）は、集積回路１２とオーバーラップする領域に形成されていてもよい。弾性変形可能部２４は、傾斜した側面を有していてもよい。
【００１１】
絶縁層２０は、第１及び第２の面２６，２８を有する。第２の面２８は、第１の面２６よりも半導体基板１０から高くなるように形成されている。第１の面２６は、パッシベーション膜２２の表面（上面）であってもよい。第２の面２８は、弾性変形可能部２４の表面（上面）であってもよい。
【００１２】
半導体装置１は、第１及び第２の電極３２，３４を有する。第１及び第２の電極３２，３４は、半導体基板１０の外側では電気的に接続されないようになっていてもよい。第１の電極３２は、第２の面２８を避けて形成されている。第１の電極３２は、上述したパッド１４である。第１の電極３２は、半導体基板１０の内部（例えば集積回路１２）に電気的に接続されてなる。第１の電極３２には、バンプ３６が形成されていてもよい。また、第１の電極３２は、パッシベーション膜２２上で再配置（ピッチ変換）されていても良く、複数列で配列しても良い。複数列で配列する場合には、千鳥状に配列しても良い。
【００１３】
第２の電極３４は、弾性変形可能部２４（第２の面２８）上に形成されている。第２の電極３４は、第１の電極３２よりも高い位置に形成されている。複数の第２の電極３４を千鳥状に配列すれば、ピッチを広くすることができる（図３参照）。また、第２の電極３４は単列で配置しても良い。第２の電極３４には、バンプ３８が形成されていてもよい。バンプ３６，３８は、同じ材料で形成してもよい。バンプ３６，３８は、Ｎｉ層を含み、Ｎｉ層にＡｕ、Ｃｒ又はＡｌからなる層を積層した構造を有してもよい。
【００１４】
第２の電極３４は、半導体基板１０の内部（例えば集積回路１２）に電気的に接続されてなる。そのために、いずれかのパッド１４と第２の電極３４とが配線４０によって電気的に接続されていてもよい。配線４０は、パッド１４上から第２の面２８上に至るように形成されている。配線４０は、第１の面２６上を通ってもよい。
【００１５】
電子装置は、支持部材５０を有する。支持部材５０は、第１の支持面５２と第１の支持面５２よりも低い第２の支持面５４を有する。支持部材５０は、第１及び第２の基板５６，５８を含んでもよい。第１及び第２の基板５６，５８は、オーバーラップ領域を有するように取り付けられてなる。その取り付けには、接着剤等を使用してもよい。第１の基板５６は、例えばフレキシブル基板である。第１の基板５６には電子部品７２を実装してもよい。第２の基板５８は、例えば、電子パネル（液晶パネル、有機エレクトロルミネセンスパネル等）の少なくとも一部である。液晶パネルでは、第２の基板５８と対向するように他の基板７４が設けられている。第２の基板５８は、基板７４から突出するように配置されており、第２の基板５８の第２の支持面５４上であって基板７４の周縁部には樹脂７６を設けてもよい。
【００１６】
第１の基板５６の、第２の基板５８とのオーバーラップ領域内であって第２の基板５８とは反対側の面が、第１の支持面５２である。第２の基板５８の、第１の基板５６とのオーバーラップ領域外であって第１の基板５６側の面が、第２の支持面５４である。
【００１７】
第１の支持面５２には第１の配線パターン６０が形成され、第２の支持面５４には第２の配線パターン６２が形成されている。半導体装置１の第１の電極３２と第１の配線パターン６０が対向して電気的に接続されている。半導体装置１の第２の電極３４と第２の配線パターン６２が対向して電気的に接続されている。なお、第１の電極３２と第１の配線パターン６０の間にバンプ３６が介在し、第２の電極３４と第２の配線パターン６２の間にバンプ３８が介在している。したがって、バンプ３６によって第１の電極３２と第１の配線パターン６０が電気的に接続され、バンプ３８によって第２の電極３４と第２の配線パターン６２が電気的に接続されている。電気的接続には、異方性導電材料（異方性導電膜又は異方性導電ペースト等）６４を使用してもよい。また、異方性導電材料の代わりに、絶縁性の接着剤や接着フィルムなどを使用してもよい。
【００１８】
図１に示すように、半導体基板１０と支持部材５０（第２の基板５８）とは、例えば接着剤（異方性導電材料６４のバインダや絶縁性の接着剤、接着フィルム等）の収縮力を利用して、引きつけ合うように接着されている。これにより、弾性変形可能部２４は、第２の電極３４の下方において窪むように弾性変形している。そして、弾性変形可能部２４の弾性力によって、第２の電極３４（又はバンプ３８）は第２の配線パターン６２に押圧されている。本実施の形態によれば、絶縁層２０（詳しくは弾性変形可能部２４）がその弾力性によって第２の電極３４（又はバンプ３８）を第２の配線パターン６２に押圧するので、半導体基板１０と第２の基板５８との電気的接続部分の接合力を強化することができる。
【００１９】
また、本実施の形態によれば、半導体装置１は、異なる高さの面に形成された第１及び第２の電極３２，３４を有し、段差のある領域（第１及び第２の支持面５２，５４）に実装されている。また、本実施の形態では、半導体装置１の一部が第１の基板５６とオーバーラップするだけなので、第１の基板５６の小型化が可能である。
【００２０】
図４（Ａ）〜図５（Ｃ）は、半導体装置の製造方法を説明する図である。図４（Ａ）に示すように、半導体基板１０に、第１の面２６と第１の面２６よりも高い第２の面２８を有する絶縁層２０を形成する。半導体基板１０が半導体ウエハである場合、それぞれの半導体チップとなる領域に弾性変形可能部２４を形成する。弾性変形可能部２４は、集積回路１２とオーバーラップする領域に形成する。弾性変形可能部２４は、半導体基板１０（例えばその全面）に形成した絶縁層（例えば樹脂層）をパターニング（例えばエッチング）して形成してもよい。
【００２１】
図４（Ｂ）に示すように、一層又は複数層の導電膜８０を形成する。例えば、ＴｉＷ膜とその上のＣｕ膜によって導電膜８０を形成してもよい。導電膜８０は、スパッタリングによって形成してもよい。導電膜８０は、第１及び第２の面２６，２８全体に形成してもよい。
【００２２】
図４（Ｃ）に示すように、導電膜８０上に、第１及び第２の電極３２，３４の領域を除くように、第１のレジスト層（例えば樹脂層）８２を形成する。配線４０（図３参照）を形成する場合には、第１のレジスト層８２は、配線４０の領域を除くように形成する。導電膜８０（例えばその全面）に設けたレジスト層を、フォトリソグラフィなどの工程を経てパターニングしてもよい。
【００２３】
図４（Ｄ）に示すように、導電膜８０の第１のレジスト層８２からの露出面上に、導電膜８０を電極として電解メッキによって、第１の金属層（例えばＣｕ層）８４を形成する。なお、第１の金属層８４の形成には、無電解メッキを適用してもよい。その後、第１のレジスト層８２を除去する。
【００２４】
図５（Ａ）に示すように、第１の金属層８４をマスクとして、導電膜８０をエッチングする。これにより、第２の電極３４及び配線４０を形成することができる。第２の電極３４は、第２の面２８上に形成される。なお、本実施の形態では、パッド１４が第１の電極３２である。
【００２５】
図５（Ｂ）に示すように、バンプ３６，３８の形成領域（第１及び第２の電極３２，３４の少なくとも中央部）を除いて、第２のレジスト層（例えば樹脂層）８６を形成する。
【００２６】
図５（Ｃ）に示すように、第１の金属層８４の、第２のレジスト層８６からの露出面（バンプ３６，３８の形成領域）に、第２の金属層（Ｎｉ、Ａｕ、Ｃｒ、Ａｌなど）８８を、１層又は複数層で設ける。こうして、バンプ３６，３８を形成することができる。
【００２７】
半導体装置の製造方法は、半導体基板１０が半導体ウエハである場合、これを切断（例えばダイシング）することを含んでもよい。その他の製造方法は、上述した半導体装置の構成から導き出される内容である。本実施の形態によれば、第１及び第２の電極３２，３４が異なる高さの面に形成されているので、段差のある領域への実装が可能になる。
【００２８】
図６は、本実施の形態に係る電子装置の製造方法を説明する図である。この製造方法は、半導体装置１を、第２の配線パターン６２が形成されてなる第２の基板５８に実装することを含む。あるいは、この製造方法は、半導体装置１を、第１の支持面５２と第１の支持面５２よりも低い第２の支持面５４とを有する支持部材５０に実装することを含む。半導体装置１の実装前に、第１及び第２の基板５６，５８を取り付けておく。そして、半導体装置１の第１の電極３２と第１の配線パターン６０を対向させて電気的に接続する。半導体装置１の第２の電極３４と第２の配線パターン６２を対向させて電気的に接続する。これらの電気的接続には、異方性導電材料（異方性導電膜又は異方性導電ペースト等）６４を使用してもよい。また、接着剤などの樹脂による圧接によって電気的接続を行なってもよい。
【００２９】
実装工程で、半導体装置１と第２の基板５８を、第２の電極３４が第２の配線パターン６２と対向するように配置する。そして、弾性変形可能部２４を、第２の電極３４の下方において窪むように弾性変形させる。例えば、半導体装置１と第２の基板５８の間に押圧力を加える。バンプ３８を介して、弾性変形可能部２４を弾性変形させてもよい。そして、接着剤（例えば異方性導電材料６４のバインダ等）の収縮力等を利用して、半導体装置１と第２の基板５８の間に両者を引きつける力を加える。この引きつける力は、接着剤が硬化すれば維持される。
【００３０】
本実施の形態によれば、絶縁層２０（詳しくはその弾性変形可能部２４）を弾性変形させ、その弾性変形を維持する。したがって、弾力性によって第２の電極３４を第２の配線パターン６２に押圧することができ、半導体基板１０と第２の基板５８との電気的接続部分の接合力を強化することができる。また、本実施の形態によれば、半導体装置１の第１及び第２の電極３２，３４が異なる高さの面に形成されているので、段差のある領域（第１及び第２の支持面５２，５４）への実装が可能になっている。
【００３１】
図７は、本実施の形態に係る他の電子装置の製造方法を説明する図である。この製造方法では、半導体装置１の第１の電極３２と、第１の基板５６に形成された第１の配線パターン６０と、を対向させて電気的に接続する。すなわち、半導体装置１は、第２の基板５８への実装前に、第１の基板５６に実装する。その接合には、異方性導電材料もしくは樹脂による圧接、または他のＣＯＦ（Ｃｈｉｐ Ｏｎ Ｆｉｌｍ）実装に用いられるようなＡｕ−Ｓｕ合金接合やＡｕ−Ａｕ金属接合にて接合されてもよい。そして、半導体装置１及び第１の基板５６を第２の基板５８に取り付ける。詳しくは、半導体装置１の第２の電極３４と、第２の基板５８に形成された第２の配線パターン６２と、を対向させて電気的に接続する。その電気的接続には、異方性導電材料（異方性導電膜又は異方性導電ペースト等）６４を使用してもよい。または樹脂による圧接を行なってもよい。また、第１の配線パターン６０の、第１の電極３２との電気的接続部が第２の基板５８とオーバーラップするように、第１の基板５６を第２の基板５８に取り付ける。その取り付けに、異方性導電材料６４を使用してもよい。本実施の形態によれば、第１及び第２の基板５６，５８がオーバーラップすることで段差が形成されるが、半導体装置１の第１及び第２の電極３２，３４が異なる高さの面に形成されているので、この段差に対応できるようになっている。それ以外の内容は、図６を参照して説明した内容が該当する。
【００３２】
図８は、本実施の形態に係る電子装置の変形例を説明する図である。図８に示す電子装置は、支持部材５０に、複数の半導体装置１が実装されている。半導体装置１の構造や実装の形態等の詳細については、上述した内容が該当する。本発明は、この形態も含む。
【００３３】
本発明の実施の形態に係る電子装置を有する電子機器として、図９にはノート型パーソナルコンピュータ１０００、図１０には携帯電話２０００が示されている。
【００３４】
本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。
【図面の簡単な説明】
【図１】図１は、本発明の実施の形態に係る電子装置を説明する図である。
【図２】図２は、図３のＩＩ−ＩＩ線断面図である。
【図３】図３は、半導体装置を説明する図である。
【図４】図４（Ａ）〜図４（Ｄ）は、半導体装置の製造方法を説明する図である。
【図５】図５（Ａ）〜図５（Ｃ）は、半導体装置の製造方法を説明する図である。
【図６】図６は、本実施の形態に係る電子装置の製造方法を説明する図である。
【図７】図７は、本実施の形態に係る他の電子装置の製造方法を説明する図である。
【図８】図８は、本実施の形態に係る電子装置の変形例を説明する図である。
【図９】図９は、本実施の形態に係る電子装置を有する電子機器を示す図である。
【図１０】図１０は、本実施の形態に係る電子装置を有する電子機器を示す図である。
【符号の説明】
１…半導体装置 １０…半導体基板 １２…集積回路 １４…パッド ２０…絶縁層 ２２…パッシベーション膜 ２４…弾性変形可能部 ３２…第１の電極３４…第２の電極 ３６…バンプ ３８…バンプ ４０…配線 ５０…支持部材 ５２…第１の支持面 ５４…第２の支持面 ５６…第１の基板 ５８…第２の基板 ６０…第１の配線パターン ６２…第２の配線パターン ６４…異方性導電材料 ７２…電子部品 ７４…基板 ７６…樹脂 ８０…導電膜 ８２…第１のレジスト層 ８４…第１の金属層 ８６…第２のレジスト層 ８８…第２の金属層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic device, a method for manufacturing the same, and an electronic apparatus.
[0002]
[Prior art]
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-33940 [Patent Document 2]
Japanese Patent No. 2798027
BACKGROUND OF THE INVENTION
It is known that a semiconductor chip is face-down bonded to a hard substrate like COG (Chip On Glass). In this mounting mode, since the substrate has little elasticity, it has been a problem to increase the bonding strength of the electrical connection between the semiconductor chip and the substrate.
[0005]
An object of the present invention is to enhance the bonding strength of an electrical connection between a semiconductor substrate and the substrate.
[0006]
[Means for Solving the Problems]
(1) An electronic device according to the present invention includes: a semiconductor substrate having an integrated circuit formed therein;
An insulating layer having an elastically deformable portion formed on the semiconductor substrate;
An electrode electrically connected to the inside of the semiconductor substrate and formed on the elastically deformable portion;
A substrate on which a wiring pattern electrically connected to the electrode is formed,
Has,
The elastically deformable portion is elastically deformed so as to be depressed below the electrode, and presses the electrode against the wiring pattern by an elastic force. According to the present invention, the insulating layer presses the electrode against the wiring pattern due to its elasticity, so that the bonding strength of the electrical connection between the semiconductor substrate and the substrate can be enhanced.
(2) This electronic device
The semiconductor device may further include a bump provided between the electrode and the wiring pattern, and the electrode and the wiring pattern may be electrically connected by the bump.
(3) In this electronic device,
The bump may include a nickel layer.
(4) An electronic apparatus according to the present invention includes the above electronic device.
(5) The method of manufacturing an electronic device according to the present invention includes mounting the semiconductor device on a substrate on which a wiring pattern is formed,
The semiconductor device includes a semiconductor substrate having an integrated circuit formed therein, an insulating layer formed on the semiconductor substrate and having an elastically deformable portion, and an elastically deformable portion electrically connected to the inside of the semiconductor substrate. And an electrode formed on the possible portion,
In the mounting step,
The semiconductor device and the substrate are arranged such that the electrode faces the wiring pattern,
The elastically deformable portion is elastically deformed so as to be recessed below the electrode. According to the present invention, since the insulating layer is elastically deformed, the electrode can be pressed against the wiring pattern by the elasticity of the insulating layer, and the bonding strength of the electrical connection between the semiconductor substrate and the substrate can be enhanced. .
(6) In this method of manufacturing an electronic device,
The semiconductor device further includes a bump provided on the electrode,
The elastically deformable portion may be elastically deformed via the bump.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a diagram illustrating an electronic device according to an embodiment of the present invention. The electronic device has a semiconductor device 1. 2 and 3 are diagrams illustrating a semiconductor device, and FIG. 2 is a cross-sectional view taken along line II-II of FIG.
[0008]
The semiconductor device 1 has a semiconductor substrate (for example, a semiconductor chip) 10. An integrated circuit 12 is formed inside the semiconductor substrate 10. A plurality of pads 14 are formed on the semiconductor substrate 10. The pad 14 is electrically connected to the inside of the semiconductor substrate 10. The pad 14 may be a part (end) of a wiring electrically connected to the integrated circuit 12. The plurality of pads 14 may be formed on the peripheral edge (end) of the surface of the semiconductor substrate 10. For example, the plurality of pads 14 may be arranged along four sides of the surface of the semiconductor substrate 10, or may be arranged along two sides. The pad 14 is formed of, for example, Al. Although not shown, the pad 14 may be formed so as to overlap the integrated circuit 12.
[0009]
An insulating layer (specifically, an electrical insulating layer) 20 is formed on the semiconductor substrate 10. The insulating layer 20 may include a passivation film 22. The passivation film 22 may be formed only of a non-resin material (for example, SiO 2 or SiN), or may include a resin layer. The passivation film 22 has an opening for exposing at least a part (for example, a central part) of the pad 14. That is, the passivation film 22 is formed avoiding at least the central portion of the pad 14. The passivation film 22 may be placed on the end of the pad 14.
[0010]
The insulating layer 20 has an elastically deformable portion 24. The elastically deformable portion 24 has a property of being elastically deformed (or a stress relaxation function). The elastically deformable portion 24 is formed on the passivation film 22. The elastically deformable portion 24 is formed of an elastic resin such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO). Is preferred. Further, an inorganic material (such as glass) may be used as long as it has elasticity. The elastically deformable portion 24 may be formed in a part of the passivation film 22. For example, the elastically deformable portion 24 may be formed at a position offset from the center of the semiconductor substrate 10 to any one of the ends. At least a part (for example, only a part) of the elastically deformable portion 24 may be formed in a region overlapping with the integrated circuit 12. The elastically deformable portion 24 may have an inclined side surface.
[0011]
The insulating layer 20 has first and second surfaces 26 and 28. The second surface 28 is formed to be higher than the first surface 26 from the semiconductor substrate 10. The first surface 26 may be a surface (upper surface) of the passivation film 22. The second surface 28 may be a surface (upper surface) of the elastically deformable portion 24.
[0012]
The semiconductor device 1 has first and second electrodes 32 and. The first and second electrodes 32 and 34 may not be electrically connected outside the semiconductor substrate 10. The first electrode 32 is formed so as to avoid the second surface 28. The first electrode 32 is the pad 14 described above. The first electrode 32 is electrically connected to the inside of the semiconductor substrate 10 (for example, the integrated circuit 12). A bump 36 may be formed on the first electrode 32. Further, the first electrodes 32 may be rearranged (pitch converted) on the passivation film 22 or may be arranged in a plurality of rows. When arranged in a plurality of rows, they may be arranged in a staggered manner.
[0013]
The second electrode 34 is formed on the elastically deformable portion 24 (the second surface 28). The second electrode 34 is formed at a position higher than the first electrode 32. If the plurality of second electrodes 34 are arranged in a staggered manner, the pitch can be widened (see FIG. 3). Further, the second electrodes 34 may be arranged in a single row. A bump 38 may be formed on the second electrode 34. The bumps 36 and 38 may be formed of the same material. The bumps 36 and 38 may include a Ni layer and have a structure in which a layer made of Au, Cr, or Al is stacked on the Ni layer.
[0014]
The second electrode 34 is electrically connected to the inside of the semiconductor substrate 10 (for example, the integrated circuit 12). For this purpose, any of the pads 14 and the second electrode 34 may be electrically connected by the wiring 40. The wiring 40 is formed so as to reach from the pad 14 to the second surface 28. The wiring 40 may pass on the first surface 26.
[0015]
The electronic device has a support member 50. The support member 50 has a first support surface 52 and a second support surface 54 lower than the first support surface 52. The support member 50 may include first and second substrates 56 and 58. The first and second substrates 56 and 58 are attached so as to have an overlap area. An adhesive or the like may be used for the attachment. The first substrate 56 is, for example, a flexible substrate. The electronic component 72 may be mounted on the first substrate 56. The second substrate 58 is, for example, at least a part of an electronic panel (a liquid crystal panel, an organic electroluminescence panel, or the like). In the liquid crystal panel, another substrate 74 is provided so as to face the second substrate 58. The second substrate 58 is disposed so as to protrude from the substrate 74, and a resin 76 may be provided on the second support surface 54 of the second substrate 58 and at the peripheral portion of the substrate 74.
[0016]
The surface of the first substrate 56 in the overlap region with the second substrate 58 and opposite to the second substrate 58 is the first support surface 52. The surface of the second substrate 58 outside the overlap region with the first substrate 56 and on the first substrate 56 side is the second support surface 54.
[0017]
A first wiring pattern 60 is formed on the first support surface 52, and a second wiring pattern 62 is formed on the second support surface 54. The first electrode 32 of the semiconductor device 1 and the first wiring pattern 60 are electrically connected to face each other. The second electrode 34 of the semiconductor device 1 and the second wiring pattern 62 are opposed and electrically connected. The bump 36 is interposed between the first electrode 32 and the first wiring pattern 60, and the bump 38 is interposed between the second electrode 34 and the second wiring pattern 62. Therefore, the first electrode 32 and the first wiring pattern 60 are electrically connected by the bump 36, and the second electrode 34 and the second wiring pattern 62 are electrically connected by the bump 38. For electrical connection, an anisotropic conductive material (such as an anisotropic conductive film or an anisotropic conductive paste) 64 may be used. Further, an insulating adhesive or an adhesive film may be used instead of the anisotropic conductive material.
[0018]
As shown in FIG. 1, the semiconductor substrate 10 and the support member 50 (the second substrate 58) are, for example, contracted by an adhesive (a binder of the anisotropic conductive material 64, an insulating adhesive, an adhesive film, or the like). It is glued so as to attract each other. Thereby, the elastically deformable portion 24 is elastically deformed so as to be recessed below the second electrode 34. Then, the second electrode 34 (or the bump 38) is pressed against the second wiring pattern 62 by the elastic force of the elastically deformable portion 24. According to the present embodiment, the insulating layer 20 (specifically, the elastically deformable portion 24) presses the second electrode 34 (or the bump 38) against the second wiring pattern 62 due to its elasticity. Bonding strength of the electrical connection between the second substrate 58 and the second substrate 58 can be enhanced.
[0019]
In addition, according to the present embodiment, the semiconductor device 1 has the first and second electrodes 32 and 34 formed on surfaces of different heights, and has a stepped region (the first and second supporting portions). Surfaces 52, 54). Further, in the present embodiment, since only a part of the semiconductor device 1 overlaps with the first substrate 56, the size of the first substrate 56 can be reduced.
[0020]
4A to 5C are diagrams illustrating a method for manufacturing a semiconductor device. As shown in FIG. 4A, an insulating layer 20 having a first surface 26 and a second surface 28 higher than the first surface 26 is formed on the semiconductor substrate 10. When the semiconductor substrate 10 is a semiconductor wafer, the elastically deformable portion 24 is formed in a region to be each semiconductor chip. The elastically deformable portion 24 is formed in a region overlapping with the integrated circuit 12. The elastically deformable portion 24 may be formed by patterning (for example, etching) an insulating layer (for example, a resin layer) formed on the semiconductor substrate 10 (for example, the entire surface).
[0021]
As shown in FIG. 4B, one or more conductive films 80 are formed. For example, the conductive film 80 may be formed by a TiW film and a Cu film thereon. The conductive film 80 may be formed by sputtering. The conductive film 80 may be formed on the entire first and second surfaces 26 and 28.
[0022]
As shown in FIG. 4C, a first resist layer (for example, a resin layer) 82 is formed over the conductive film 80 so as to exclude regions of the first and second electrodes 32 and 34. When forming the wiring 40 (see FIG. 3), the first resist layer 82 is formed so as to exclude the region of the wiring 40. The resist layer provided on the conductive film 80 (for example, the entire surface) may be patterned through a process such as photolithography.
[0023]
As shown in FIG. 4D, a first metal layer (eg, a Cu layer) 84 is formed on the exposed surface of the conductive film 80 from the first resist layer 82 by electrolytic plating using the conductive film 80 as an electrode. I do. Note that the first metal layer 84 may be formed by electroless plating. After that, the first resist layer 82 is removed.
[0024]
As shown in FIG. 5A, the conductive film 80 is etched using the first metal layer 84 as a mask. Thereby, the second electrode 34 and the wiring 40 can be formed. The second electrode 34 is formed on the second surface 28. In the present embodiment, the pad 14 is the first electrode 32.
[0025]
As shown in FIG. 5B, a second resist layer (for example, a resin layer) 86 is formed except for a region where the bumps 36 and 38 are to be formed (at least the center of the first and second electrodes 32 and 34). I do.
[0026]
As shown in FIG. 5C, a second metal layer (Ni, Au, Cr) is formed on the exposed surface of the first metal layer 84 from the second resist layer 86 (the area where the bumps 36 and 38 are formed). , Al, etc.) 88 are provided in one or more layers. Thus, the bumps 36 and 38 can be formed.
[0027]
When the semiconductor substrate 10 is a semiconductor wafer, the method for manufacturing a semiconductor device may include cutting (for example, dicing) the semiconductor wafer. Other manufacturing methods are contents derived from the configuration of the semiconductor device described above. According to the present embodiment, since the first and second electrodes 32 and 34 are formed on surfaces having different heights, it is possible to mount the first and second electrodes 32 and 34 on a stepped area.
[0028]
FIG. 6 is a diagram illustrating a method for manufacturing the electronic device according to the present embodiment. This manufacturing method includes mounting the semiconductor device 1 on a second substrate 58 on which a second wiring pattern 62 is formed. Alternatively, this manufacturing method includes mounting the semiconductor device 1 on a support member 50 having a first support surface 52 and a second support surface 54 lower than the first support surface 52. Before mounting the semiconductor device 1, the first and second substrates 56 and 58 are attached. Then, the first electrode 32 of the semiconductor device 1 and the first wiring pattern 60 are opposed to each other and are electrically connected. The second electrode 34 of the semiconductor device 1 and the second wiring pattern 62 are opposed and electrically connected. For these electrical connections, an anisotropic conductive material (such as an anisotropic conductive film or an anisotropic conductive paste) 64 may be used. Alternatively, the electrical connection may be performed by pressure welding with a resin such as an adhesive.
[0029]
In the mounting step, the semiconductor device 1 and the second substrate 58 are arranged such that the second electrode 34 faces the second wiring pattern 62. Then, the elastically deformable portion 24 is elastically deformed so as to be depressed below the second electrode 34. For example, a pressing force is applied between the semiconductor device 1 and the second substrate 58. The elastically deformable portion 24 may be elastically deformed via the bump 38. Then, a force for attracting both is applied between the semiconductor device 1 and the second substrate 58 by utilizing a contraction force or the like of an adhesive (for example, a binder of the anisotropic conductive material 64). This attractive force is maintained as the adhesive cures.
[0030]
According to the present embodiment, the insulating layer 20 (specifically, the elastically deformable portion 24) is elastically deformed, and the elastic deformation is maintained. Therefore, the second electrode 34 can be pressed against the second wiring pattern 62 by elasticity, and the bonding strength of the electrical connection between the semiconductor substrate 10 and the second substrate 58 can be enhanced. Further, according to the present embodiment, since the first and second electrodes 32 and 34 of the semiconductor device 1 are formed on surfaces having different heights, a stepped region (the first and second support surfaces) is provided. 52, 54).
[0031]
FIG. 7 is a diagram illustrating a method of manufacturing another electronic device according to the present embodiment. In this manufacturing method, the first electrode 32 of the semiconductor device 1 and the first wiring pattern 60 formed on the first substrate 56 are opposed and electrically connected. That is, the semiconductor device 1 is mounted on the first substrate 56 before mounting on the second substrate 58. The bonding may be performed by pressure welding with an anisotropic conductive material or resin, or Au-Su alloy bonding or Au-Au metal bonding as used for other COF (Chip On Film) mounting. Then, the semiconductor device 1 and the first substrate 56 are attached to the second substrate 58. Specifically, the second electrode 34 of the semiconductor device 1 is electrically connected to the second wiring pattern 62 formed on the second substrate 58 so as to face each other. An anisotropic conductive material (such as an anisotropic conductive film or an anisotropic conductive paste) 64 may be used for the electrical connection. Alternatively, pressure welding with a resin may be performed. Further, the first substrate 56 is attached to the second substrate 58 such that the electrical connection between the first wiring pattern 60 and the first electrode 32 overlaps with the second substrate 58. An anisotropic conductive material 64 may be used for the attachment. According to the present embodiment, a step is formed by overlapping the first and second substrates 56 and 58, but the first and second electrodes 32 and 34 of the semiconductor device 1 have different heights. Since it is formed on the surface, it is possible to cope with this step. Other contents correspond to the contents described with reference to FIG.
[0032]
FIG. 8 is a diagram illustrating a modification of the electronic device according to the present embodiment. In the electronic device illustrated in FIG. 8, a plurality of semiconductor devices 1 are mounted on a support member 50. The details described above, such as the structure and the form of mounting of the semiconductor device 1, correspond to the contents described above. The present invention also includes this mode.
[0033]
As an electronic apparatus having the electronic apparatus according to the embodiment of the present invention, a notebook personal computer 1000 is shown in FIG. 9, and a mobile phone 2000 is shown in FIG.
[0034]
The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the invention includes configurations substantially the same as the configurations described in the embodiments (for example, a configuration having the same function, method, and result, or a configuration having the same object and result). Further, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. Further, the invention includes a configuration having the same operation and effect as the configuration described in the embodiment, or a configuration capable of achieving the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an electronic device according to an embodiment of the present invention.
FIG. 2 is a sectional view taken along line II-II in FIG. 3;
FIG. 3 is a diagram illustrating a semiconductor device.
FIGS. 4A to 4D are diagrams illustrating a method for manufacturing a semiconductor device.
FIGS. 5A to 5C are views illustrating a method for manufacturing a semiconductor device.
FIG. 6 is a diagram illustrating the method for manufacturing the electronic device according to the embodiment.
FIG. 7 is a diagram illustrating a method of manufacturing another electronic device according to the embodiment.
FIG. 8 is a diagram illustrating a modification of the electronic device according to the embodiment;
FIG. 9 is a diagram illustrating an electronic apparatus including the electronic device according to the embodiment;
FIG. 10 is a diagram illustrating an electronic apparatus including the electronic device according to the embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Semiconductor substrate 12 ... Integrated circuit 14 ... Pad 20 ... Insulating layer 22 ... Passivation film 24 ... Elastic deformable part 32 ... First electrode 34 ... Second electrode 36 ... Bump 38 ... Bump 40 ... Wiring 50 support member 52 first support surface 54 second support surface 56 first substrate 58 second substrate 60 first wiring pattern 62 second wiring pattern 64 anisotropic conductive Material 72 Electronic component 74 Substrate 76 Resin 80 Conductive film 82 First resist layer 84 First metal layer 86 Second resist layer 88 Second metal layer

Claims (6)

集積回路が内部に形成された半導体基板と、
前記半導体基板上に形成されて弾性変形可能部を有する絶縁層と、
前記半導体基板の内部に電気的に接続されて前記弾性変形可能部上に形成されてなる電極と、
前記電極と対向して電気的に接続された配線パターンが形成されてなる基板と、
を有し、
前記弾性変形可能部は、前記電極の下方において窪むように弾性変形し、弾性力によって、前記電極を前記配線パターンに押圧してなる電子装置。A semiconductor substrate having an integrated circuit formed therein;
An insulating layer having an elastically deformable portion formed on the semiconductor substrate;
An electrode electrically connected to the inside of the semiconductor substrate and formed on the elastically deformable portion;
A substrate on which a wiring pattern electrically connected to the electrode is formed,
Has,
The electronic device, wherein the elastically deformable portion elastically deforms so as to be depressed below the electrode, and presses the electrode against the wiring pattern by an elastic force. 請求項１記載の電子装置において、
前記電極及び前記配線パターン間に設けられたバンプをさらに有し、前記バンプによって前記電極と前記配線パターンが電気的に接続されてなる電子装置。The electronic device according to claim 1,
An electronic device further comprising a bump provided between the electrode and the wiring pattern, wherein the electrode and the wiring pattern are electrically connected by the bump. 請求項２記載の電子装置において、
前記バンプは、ニッケル層を含む電子装置。The electronic device according to claim 2,
The electronic device, wherein the bump includes a nickel layer. 請求項１から請求項３のいずれかに記載の電子装置を有する電子機器。An electronic apparatus comprising the electronic device according to claim 1. 半導体装置を、配線パターンが形成されてなる基板に実装することを含み、
前記半導体装置は、集積回路が内部に形成された半導体基板と、前記半導体基板上に形成されて弾性変形可能部を有する絶縁層と、前記半導体基板の内部に電気的に接続されて前記弾性変形可能部上に形成されてなる電極と、を含み、
前記実装工程で、
前記半導体装置と前記基板を、前記電極が前記配線パターンと対向するように配置し、
前記弾性変形可能部を、前記電極の下方において窪むように弾性変形させる電子装置の製造方法。Including mounting the semiconductor device on a substrate on which a wiring pattern is formed,
The semiconductor device includes a semiconductor substrate having an integrated circuit formed therein, an insulating layer formed on the semiconductor substrate and having an elastically deformable portion, and an elastically deformable portion electrically connected to the inside of the semiconductor substrate. And an electrode formed on the possible portion,
In the mounting step,
The semiconductor device and the substrate are arranged such that the electrode faces the wiring pattern,
A method of manufacturing an electronic device, wherein the elastically deformable portion is elastically deformed so as to be recessed below the electrode. 請求項５記載の電子装置の製造方法において、
前記半導体装置は、前記電極上に設けられたバンプをさらに有し、
前記バンプを介して、前記弾性変形可能部を弾性変形させる電子装置の製造方法。The method for manufacturing an electronic device according to claim 5,
The semiconductor device further includes a bump provided on the electrode,
A method for manufacturing an electronic device, wherein the elastically deformable portion is elastically deformed via the bump.
JP2003116896A 2003-04-22 2003-04-22 Electronic device, its manufacturing process and electronic apparatus Withdrawn JP2004327527A (en)

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