200917451 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種對位裝置。更詳細地來說，係關於一種用於 一晶片封裝構造i之對位裝置。 【先前技術】 近年來，隨著半導體製程技術的不斷成熟與發展，各種高效能 的電子產品不斷推陳出新，而積體電路（Integrated Circuit，1C ) 晶片之積集度（integration )也不斷提高。積體電路晶片封裝型態 可大致區分為打線接合封裝（Wire Bonding Package )、捲帶自動接 合封裝（Tape Automatic Bonding，TAB )與覆晶接合封裝（FHp chip200917451 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a registration device. In more detail, it relates to a aligning device for a chip package construction i. [Prior Art] In recent years, with the continuous maturity and development of semiconductor process technology, various high-performance electronic products have been continuously developed, and the integration of integrated circuit (1C) chips has been continuously improved. The integrated circuit chip package type can be roughly classified into a wire bonding package (Wire Bonding Package), a tape automatic bonding package (TAB), and a flip chip bonding package (FHp chip).
Package )等型式’且每種封裝形式均具有其特殊性與應用領域。 相較於傳統打線接合封裝技術，捲帶自動接合封裝具有可縮小晶 片的金屬焊塾間距（Pad Pitch)及薄化等優點。 目如運用於液晶顯不益驅動1C之封裝及行動化電子產品，例 如：筆記型電腦、手機、數位相機等之晶片封裝中，因為可撓性 基板具有動態連結、可撓曲性與薄化的特性，故大量地採用為素 材。而目别可挽性基板與晶片的接合多運用捲帶自動接合（TAB ) 封裝技術來達成’其中捲帶自動接合封裝技術又可分成捲帶承載 封裝（Tape Carrier Package, TCP)及薄膜覆晶封裝（chip_〇n_FUm, COF)二種技術。 薄膜覆晶封裝（COF)係以可撓性基板上之引腳（lead)與晶片 上相對應之凸塊（bump)進行對位加壓接合，以於弓丨腳與凸塊間 200917451 建構一電性連接，俾使晶片之資料可藉由凸塊及引腳之連接而盥 外部電路騎_。隨㈣程㈣步、㈣電路密錢提高，引 腳4之尺寸及間距(Pltch)也愈來愈小。然而，這亦代表了引腳 4之對位加㈣合更難以對齊，可料之對位誤差也將愈趨 嚴t。、此外，在加麗接合時；因應力易集中於晶片覆蓋區之角隅， 而&成外側引腳斷裂或剝離(peding)，以致不能達到電性連接，而 使晶片的魏受到料無法正t運作。是故，料進—步改良對 位結構，將嚴重地影響封裝之良率。 習知對位技術中，係以人眼透過攝影機進行晶片及可撓性基板 1 對位檢視。日如第1圖所示，可撓性基板W上具有—晶片覆蓋區 H) 0且=%片覆起1G G之各邊均具有引腳為例。晶片覆蓋區 /、一長邊100a與二短邊1〇〇b，於晶片覆蓋區⑽之二對角 隅淋或四角隅）各定義一教讀區域1〇4,其涵蓋一長邊職之部 1—長邊引腳服與短邊祕之部分—第—短邊引聊 曰，卜晶片（圖未示出）亦具有相對應之二長邊與二短邊，而 =中相對應的角隅亦定義出教讀區域。透過攝影機分別檢視晶 可撓性基板100之教讀區域，並取得各教讀區域之灰階值， 便可進行影像重疊對位。 =而對位時’若第—長邊引腳與第—短邊⑽距離較遠 =讀區域同時包含長邊與短邊之引腳’便需放大教讀區域之範 盘但此舉卻會使得解析度降低；此外，這種對位技術僅用 邊與短邊均具有引聊之可換性基板，無法完成無短邊引腳之對 且右内引腳钱刻不當導致引腳表面不均勻，亦會影響對位精 200917451 度’·再者，此技術更無法提供_與凸塊對位時偏移量調整之依 據或壓合時角隅區域之支撐。 綜上所言，習知對位技術不但於使用時處處受限，更無法解決 角隅處應力集中造成外側引腳斷裂等問題。因此，設計—個新的 對位結構且能同時提供㈣及凸塊在進行屡合時之保護，乃為此 業界所亟待解決的目標。 【發明内容】 本發明之-目的在於提供—種詩―晶片封裝構造之對位裝 置’晶片封裝構造包含-可撓性基板、—導電層及—晶片，可挽 性基板具有曰曰片覆蓋區，晶片覆蓋區包含一週邊區域。導電層 形成於晶片覆蓋區上’並將週邊區域界定成複數引腳區及複數無 引腳區。晶片係、言史置於導電層上。對位裝置包含至少一第一對位 標記及至少-第二對位標記。至少—第―對位標記係形成於晶片 •覆蓋區之至少一角隅上，至少一第二對位標記係形成於晶片之一 主動面。其中，當晶片電性定位於晶片覆蓋區上時，至少一第二 對位標記適可對應至少一第一對位標記。 藉由上述對位裝置，可撓性基板上之引腳及晶片上之凸塊便能 精確對位。此外，對位裝置更具有支撐及分散應力之作用，藉以 保護晶片覆蓋區上之外側引腳’不會因為應力集中於角隅處而產 生斷裂或剝離。 在參閲圖式及隨後描述之實施方式後，該技術領域具有通常知 識者便可瞭解本發明之目的，以及本發明之技術手段及實施態樣。 200917451 【實施方式】 本發明之第一實施例係為一種用於一晶片封裝構造之對位裝 置。晶片封裝構造2通過引腳及凸塊之剖面圖係如第2A圖所示， 第2B圖與第2C圖則分別為晶片封裝構造2中，晶片22之仰視圖 與可撓性基板20之俯視圖。 同時參考第2A圖至第2C圖，晶片封裝構造2包含一可撓性基 板20、一導電層21及一晶片22。可撓性基板20具有一晶片覆蓋 區200 ’晶片覆蓋區200包含一週邊區域（圖未示出），於此實施例 中，可撓性基板20係以聚亞醯胺製成，具有高度可撓性，在其他 實施態樣裡，可撓性基板20亦可由聚對苯二曱酸乙二酯 (Polyethylene terephthalate, PET)—類之材料所製成。導電層 21 包 含複數個引腳210，且導電層21係形成於晶片覆蓋區200上，並 將週邊區域界定成四個引腳區204a、204b、204c及204d及四個 無引腳區206a、206b、206c及206d，而該等引腳210即形成於四 個引腳區204a、204b、204c及204d上。晶片22則對位壓合於導 電層21之上，晶片22之一主動面220具有複數凸塊221，藉此對 應電性連接於該等引腳210。 進一步來看，對位裝置包含四個第一對位標記201a、201b、 201c、201d及四個第二對位標記222a、222b、222c、222d。四個 第一對位標記201a、201b、201c及201d係分別形成於晶片覆蓋 區200之四角隅，即四個無引腳區206a、206b、206c及206d上； 四個第二對位標記222a、222b、222c及222d則形成於晶片22之 200917451 主動面220。 四個第一對位標記201a、201b、201c及201d及四個第二對位 標記222a、222b、222c及222d之形狀係分別均為卍字形及十字 形。於其他實施態樣中，第一對位標記與第二對位標記亦可自卍 字形、十字形、米字形、T字形、L字形及方形等形狀之群組選出’ 或可由其他習知此項技術者可輕易思及之形狀替代，故不限於上 述之形狀。 當晶片22電性定位於晶片覆蓋區200上時，四個第一對位標記 201a、201b、201c及201d適可分別對應四個第二對位標記222a、 222b、222c及222d。同樣地，晶片覆蓋區200與晶片22亦定義 有教讀區域。以晶片覆盖區200而言，其教讀區域即四個無引腳 區206a、206b、206c及206d，且各教讀區域中分別包含了第一對 位標記201 a、20lb、201 c及201 d ;以晶片22而言，其教讀區域 即為對應於無引腳區206a、206b、206c及206d之四角隅。而上 述之第一對位標記及第二對位標記之形狀係可使該等引腳210與 該等凸塊221進行對位接合時，透過攝影機檢視各個教讀區域， 以各教讀區域之灰階值比對第一對位標記及第二對位標記兩者之 間的相對位置（譬如X方向、y方向及偏移角0)，藉以判斷兩者是 否接合正確並進行調整，俾使該等引腳210與該等凸塊221之對 位更加精準。對位後，再以機器進行壓合，完成兩者間的電性接 合。 更詳細而言’形成於四個引腳區204a、204b、204c及204d上 的該等引腳210具有一第一厚度，而四個第一對位標記2〇la、 200917451 2〇lb、201c及201d具有一第二厚度，第一厚度係與第二厚度實質 上相等，且四個第一對位標記2〇la、2〇lb、2〇lc及2〇id與該等 引腳210均係由第一材料構成。此外，於钱刻製備此實施例之引 腳時’亦同時蝕刻出第一對位標記，換言之，兩者係為同一材料 且同時形成。於本實施例中，第—材料係、為銅，須注意的是，於 其他實施態樣中’第—材料並不限於以上所述之銅金屬，其可由 習知此項技術者可輕易思及之其他金屬所構成。 而於晶片22之主動面22〇上之該等凸塊22ι具有—第三厚度， 位於晶上之四個第二對位標記加、2现、ah及2咖則 ^帛叫度，第三厚度係與第四厚度實質上相等，且四個第 1標€如、222b、取及222d與該等凸塊221係由第二 材料構成。於製備廿音y 故兩者例之凸塊時，亦同時形成第二對位標記， 兩者係為同—材料且同時形成1 金，須注意的是，於弟一材料係為 述之金金屬，其可Μ施_ ’第—材料並不限於以上所 成。 “此項技術者可輕易思及之其他金屬所構 由於此貫施例中，第_ 7 引腳及凸塊之厚声相算…記及第二對位標記之厚度分別與 / 予度相等’故W腳與凸 第二對位標記亦同時完成接合，可進第—對位標記與 200之四角隅提供支衿 ν ;曰曰片22及晶片覆蓋區 近外側之該”腳免壓合時角隅處因應力射而造成靠 之可能性。 離’而降低電性連接短路或斷路 本發明之第二實施例亦 用於一晶片封裝構造之對位裝 10 200917451 置。與前一實施例不同的是，本實施例之晶片封裝構造2中，無 引腳區及對位裝置之數目有所不同，故於此僅特別描述無引腳區 及對位裝置之部分。同時對照第3A圖及第3B圖，其中第3A圖 為本實施例之晶片封裝構造2中晶片22’之仰視圖，第3B圖為本 實施例之晶片封裝構造2中可撓性基板20’之俯視圖。 於本實施例之晶片封裝構造2中，可撓性基板20’具有一晶片覆 蓋區200’，晶片覆蓋區200’包含一週邊區域。週邊區域界定成四 個引腳區204a’、204b’、204c’及204d’及四個無引腳區206a’、 206b’、206c’及206d’，複數引腳210’即形成於四個引腳區204a’、 204b’、204c’及204d’上。而晶片22’之一主動面220’具有複數凸 塊221’，對應電性連接於該等引腳210’。 進一步來看，對位裝置包含兩個第一對位標記201a’、201c’、 及兩個第二對位標記222a’、222c’。兩個第一對位標記201a’、201c’ 係分別形成於晶片覆蓋區200’之兩對角隅，即其中之兩個無引腳 區206a’及206c’上；兩個第二對位標記222a’、222c’則形成於晶 片22’之主動面220’上，與第一對位標記201a’、201c’相對應之位 置。 當晶片22’電性定位於晶片覆蓋區200’上時，兩個第一對位標記 201a’及201c’適可分別對應兩個第二對位標記222a’及222c’。同 樣地，晶片覆蓋區200’與晶片22’亦定義有教讀區域。以晶片覆蓋 區200’而言，其教讀區域即無引腳區206a’及206c’，且各教讀區 域中分別包含了第一對位標記201a’及201c’ ；以晶片22’而言，其 教讀區域即為對應於無引腳區206a’及206c’之二角隅。接著，亦 200917451 同樣使用攝’錢檢視各個教讀區域，以各教讀區域之灰階值確認 第-對位標記及第二對位標記之相對位置（譬如 X方向、y方向及 偏移角Θ) ’藉以判斷兩者是否接合正確並進行調整，使引腳训， 與《亥等凸塊221之對位更為精準。對位後，再以機器進行壓合， 完成兩者間的電性接合。 於此實把例中，雖僅將第一對位標記及第二對位標記設置於晶 片及晶片覆蓋區之兩對角隅，但亦可提供對準之機制及足夠之支 r 撐力。須注意的是，第一對位標記及第二對位標記之數目並不限 " 於上述實施例之數目，而可任意增加或減少，並不為上述之數目 所限。第一對位標記與第二對位標記之形狀可相同亦可不同。 本♦明之第二實施例同樣為一種用於一晶片封裝構造之對位裝 置。與前二貫施例不同的是’本實施例之晶片封裝構造3之對位 裝置中’第一對位標記與第二對位標記均為較細之線條狀，亦即 本實施例中第一對位標記與第二對位標記之線條遠細於前述各實 施例之第一對位標記與第二對位標記。晶片封裝構造3同時通過 [; 對位裝置、引腳及凸塊之剖面圖係如第4A圖所示，第4B圖與第 4C圖則分別為晶片封裝構造3中，晶片32之仰視圖與可撓性基 板30之俯視圖。 晶片封裝構造3中，可撓性基板30具有一晶片覆蓋區300，晶 片覆蓋區300包含一週邊區域。週邊區域界定成四個引腳區304a、 304b、304c 及 304d 及四個無引腳區 306a、306b、306c 及 306d， 複數引腳310即形成於四個引腳區304a、304b、304c及304d上。 而晶片32之一主動面320具有複數凸塊321，藉此對應電性連接 12 200917451 於該等引腳310。 進一步來看，對位裝置包含兩個第一對位標記301a、301c及兩 個第二對位標記322a、322c。兩個第一對位標記301a、301c係分 別形成於晶片覆蓋區300之兩對角隅，即其中之兩個無引腳區306a 及306c上；兩個第二對位標記322a、322c則形成於晶片32之主 動面320上，與第一對位標記301a、301c相對應之位置。其中第 一對位標記301a、301c較佳係均以相同製程（譬如蝕刻製程）與引 腳310同時形成，第一對位標記301a、301c之厚度會與引腳310 之厚度相等。更詳細而言，各引腳310之第一厚度實質上會相當 於第一對位標記301a、301c之第二厚度。另一方面，第二對位標 記322a、322c較佳係與凸塊321同時形成，但由於第二對位標記 322a、322c之線條較細，故於實際製程中，第二對位標記322a、 322c之厚度通常會小於凸塊321之厚度。更詳細而言，各凸塊321 之第三厚度實質上會大於第二對位標記322a、322c之第四厚度。 第一對位標記301a、301c及第二對位標記322a、322c之形狀係 均為米字形之線條形標記，更詳細而言，此米字形之各筆劃寬度 係遠小於前述各實施例。於其他實施態樣中，第一對位標記與第 二對位標記亦可自卍字形、十字形、T字形、L字形及方形等形狀 之群組選出，或可由其他習知此項技術者可輕易思及之形狀替 代，故不限於上述之形狀。 當晶片32電性定位於晶片覆蓋區300上時，兩個第一對位標記 301a及301c適可分別對應兩個第二對位標記322a及322c。同樣 地，晶片覆盖區300與晶片32亦定義有教言買區域。以晶片覆盖區 13 200917451 300而言，其教讀區域 ㈣£她及逢，且各㈣區域令 . —對位標記3013及301c ;以晶片32而t1教& 區域即為對應於無引腳區鳥及篇接著，^ 使用攝影機檢視各個教讀區域，以各教 ’ 對位標，對位標記之偏移量(譬如X方向之偏:量:方第向— =偏=及偏移角e)，藉以判斷兩者之相對位置是否正確對準並 仃、，，田敎偏移量調整，使引腳310與該等凸塊32〗之對位更為 精準。對位後，再以機器進㈣合，完成兩者間的電性接合/、 於此實她例中，第-對位標記及第二對位標記僅設置於晶片及 晶片覆蓋區之兩對角隅，即可提供對準之機制，更詳細…因 其線條形之特性，在以攝影機檢視校讀區域時，可作為快速微調 之依據。射意的是，第—對位標記及第二對位標記之數目並不 限於上述實_之數目，而可任意增加或減少，並不為上述之數 目所限。此外，於其他實施態樣中，第—對位標記與第二對位標 s己之形狀可相同亦可不同。 由上述各實施例可知，本發明藉由上述用於一晶片封裝構造且 分別設置於晶片上及可撓性基板上之對位裝置，能夠使可挽性基 板上之引腳及晶片上之凸塊在進行對位時，能精確地對準，並不 受限於長邊上之引腳與短邊上之5丨腳的距離，更可適用於僅於長 邊（或僅於短邊）具有引聊之情況。此外，本發明第一實施例與第二 實施例所述之對位|置更可提供_切及分散應力之作用，藉以 保護靠近角隅之引腳及凸塊，不因壓合時角隅處應力集中而受損。 上述之實施例僅用來例舉本發明之實施態樣，以及闊述本發明 14 200917451 之技術特徵，並非用來限制本發明之範疇。任何熟悉此技術者可 輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本 發明之權利範圍應以申請專利範圍為準。 【圖式簡單說明】 第1圖係為習知技術之晶片封裝構造中，可撓性基板之俯視圖； 第2A圖係為本發明第-實施例之晶片封裝構造之剖面圖； 第2B圖係為本發明第-實施例之晶片封裝構造中，晶片之仰視 圖， 第2C圖係為本發明第一實施例之日 K曰曰片封裝構造中，可撓性基板 之俯視圖； 圖； 第 第从圖料本發明第二實施例之晶片封裝構造中，晶片之仰視 可撓性基板 3B圖係為本發明第二實施例之晶 曰封裝構造中， 之俯視圖 第 第 圖；以及 第4C圖係為本發明第三實施例之晶 之俯視圖。 4A圖係為本發明第三實施例之晶 MB圖係為本發明第三實施例之十裏構&之剖面圖， • .、，tz 封聚·構造中，晶片之仰視 片封裝構造中，可撓性基板 【主要元件符號說明】 10 :可撓性基板 15 200917451 100 :晶片覆蓋區 100a :長邊 100b :短邊 104 .教讀區域 110a :第一長邊引腳 110b :第一短邊引腳 2 .晶片封裝構造 20 :可撓性基板 20’ ：可撓性基板 200 :晶片覆蓋區 200’ ：晶片覆蓋區Package ) and the like 'and each package has its particularity and application area. Compared to the traditional wire bonding package technology, the tape automatic bonding package has the advantages of reducing the pad pitch and thinning of the wafer. It is used in LCD packaging and mobile electronic products such as notebook computers, mobile phones, digital cameras, etc., because the flexible substrate has dynamic connection, flexibility and thinning. The characteristics are so large that they are used as materials. The bonding between the substrate and the wafer is achieved by the use of tape automated bonding (TAB) packaging technology. The tape automatic bonding and packaging technology can be divided into tape carrier package (TCP) and film flip chip. Package (chip_〇n_FUm, COF) two technologies. The film flip chip package (COF) is a positional press bonding of a lead on a flexible substrate with a corresponding bump on the wafer to construct a bow and a bump between the blocks 200917451. Electrical connection, so that the data of the chip can be pulled by the external circuit by the connection of the bump and the pin. With the (4) steps (4) and (4) circuit money increased, the size and spacing (Pltch) of pin 4 is getting smaller and smaller. However, this also means that the alignment of the pin 4 plus (four) is more difficult to align, and the alignment error can be more stringent. In addition, during the bonding of the Garley; the stress tends to concentrate on the corners of the wafer coverage area, and the outer pins are broken or peded, so that the electrical connection cannot be achieved, and the wafer is not able to receive the material. Positive t is working. Therefore, it is expected that the improved alignment structure will seriously affect the yield of the package. In the conventional alignment technology, the wafer and the flexible substrate 1 are inspected by a human eye through a camera. As shown in Fig. 1, the flexible substrate W has a wafer covering area H) 0 and the % sheet is covered with 1 G G, and each side has a pin as an example. The wafer coverage area /, a long side 100a and two short sides 1 〇〇 b, in the wafer coverage area (10) two diagonally or four corners each define a teaching area 1 〇 4, which covers a long-term job Part 1—long-side pin serving and short-side secret part—first—short-side 曰, 卜 wafer (not shown) also has two corresponding long and two short sides, and corresponding to Corners also define the teaching area. The image reading area of the crystal flexible substrate 100 is separately observed by the camera, and the gray scale values of the respective teaching areas are obtained, so that the image overlap alignment can be performed. = When the alignment is 'if the first long-side pin is farther away from the first-short edge (10) = the read area contains both the long-side and the short-side pins', then the mode of the teaching area needs to be enlarged, but the move will This makes the resolution lower. In addition, this alignment technology only uses the replaceable substrate with the side and the short side. It can't complete the pair of short-side pins and the right inner pin is not properly printed. Evenly, it will also affect the alignment precision 200917451 degrees. · Again, this technology can not provide the basis for the offset adjustment when the bump is aligned or the support of the corner region when pressing. In summary, the conventional alignment technology is not only limited in use, but also unable to solve the problem of stress cracking at the corners causing the outer pins to break. Therefore, designing a new alignment structure and providing both (4) and bump protection in an epoch-making manner is an urgent task for the industry. SUMMARY OF THE INVENTION It is an object of the present invention to provide a transposition device for a poem-wafer package structure. The chip package structure includes a flexible substrate, a conductive layer, and a wafer, and the slidable substrate has a ruthenium coverage area. The wafer footprint includes a peripheral region. A conductive layer is formed on the wafer footprint and defines the peripheral region as a plurality of pin regions and a plurality of pinless regions. The wafer system and history are placed on the conductive layer. The alignment device includes at least a first alignment mark and at least a second alignment mark. At least a first-to-paragraph mark is formed on at least one corner of the wafer/coverage area, and at least one second alignment mark is formed on one of the active faces of the wafer. Wherein, when the wafer is electrically positioned on the wafer footprint, the at least one second alignment mark is adapted to correspond to the at least one first alignment mark. With the above-mentioned alignment device, the pins on the flexible substrate and the bumps on the wafer can be accurately aligned. In addition, the alignment device has the function of supporting and dispersing stress, thereby protecting the outer side pins on the wafer footprint from being broken or peeled due to stress concentration at the corners. The objects of the present invention, as well as the technical means and implementations of the present invention, will be apparent to those of ordinary skill in the art. [Embodiment] A first embodiment of the present invention is a aligning device for a chip package construction. The cross-sectional view of the chip package structure 2 through the leads and the bumps is as shown in FIG. 2A, and the second and second C-graphs are respectively the wafer package structure 2, the bottom view of the wafer 22 and the top view of the flexible substrate 20. . Referring also to FIGS. 2A-2C, the chip package structure 2 includes a flexible substrate 20, a conductive layer 21, and a wafer 22. The flexible substrate 20 has a wafer footprint 200'. The wafer footprint 200 includes a peripheral region (not shown). In this embodiment, the flexible substrate 20 is made of polyamine, and has a height. Flexibility, in other embodiments, the flexible substrate 20 can also be made of a material such as polyethylene terephthalate (PET). The conductive layer 21 includes a plurality of pins 210, and the conductive layer 21 is formed on the wafer footprint 200, and defines the peripheral regions into four lead regions 204a, 204b, 204c, and 204d and four leadless regions 206a. 206b, 206c, and 206d, and the pins 210 are formed on the four pin regions 204a, 204b, 204c, and 204d. The wafer 22 is aligned on the conductive layer 21, and one of the active faces 220 of the wafer 22 has a plurality of bumps 221, thereby electrically connecting to the pins 210. Further, the alignment device includes four first alignment marks 201a, 201b, 201c, 201d and four second alignment marks 222a, 222b, 222c, 222d. Four first alignment marks 201a, 201b, 201c and 201d are respectively formed on the four corners of the wafer footprint 200, that is, four leadless regions 206a, 206b, 206c and 206d; four second alignment marks 222a 222b, 222c, and 222d are formed on the 200917451 active surface 220 of the wafer 22. The shapes of the four first alignment marks 201a, 201b, 201c, and 201d and the four second alignment marks 222a, 222b, 222c, and 222d are each a U shape and a cross shape. In other implementations, the first alignment mark and the second alignment mark may also be selected from the group of shapes such as a glyph, a cross, a m-shape, a T-shape, an L-shape, and a square. The shape can be easily replaced by the skilled person, and is not limited to the above shape. When the wafer 22 is electrically positioned on the wafer footprint 200, the four first alignment marks 201a, 201b, 201c, and 201d may correspond to the four second alignment marks 222a, 222b, 222c, and 222d, respectively. Similarly, wafer footprint 200 and wafer 22 are also defined as teach areas. In the case of the wafer footprint 200, the teaching area is four lead-free areas 206a, 206b, 206c, and 206d, and each of the teaching areas includes first alignment marks 201a, 20lb, 201c, and 201, respectively. d; in the case of the wafer 22, the teaching area is the four corners corresponding to the lead-free areas 206a, 206b, 206c, and 206d. The shape of the first alignment mark and the second alignment mark are such that when the pins 210 are aligned with the bumps 221, the respective teaching areas are viewed through the camera, and the teaching areas are The gray scale value compares the relative positions between the first alignment mark and the second alignment mark (such as the X direction, the y direction, and the offset angle 0), thereby judging whether the two are properly engaged and adjusted, so that The alignment of the pins 210 with the bumps 221 is more precise. After the alignment, press the machine to complete the electrical connection between the two. In more detail, the pins 210 formed on the four lead regions 204a, 204b, 204c, and 204d have a first thickness, and the four first alignment marks 2〇la, 200917451 2〇lb, 201c And 201d have a second thickness, the first thickness is substantially equal to the second thickness, and the four first alignment marks 2〇la, 2〇lb, 2〇lc, and 2〇id are connected to the pins 210 It is composed of the first material. Further, when the pins of this embodiment are prepared, the first alignment mark is also etched at the same time, in other words, the two are formed of the same material and simultaneously formed. In the present embodiment, the first material is copper. It should be noted that in other embodiments, the material is not limited to the copper metal described above, and can be easily considered by those skilled in the art. And other metals. The bumps 22ι on the active surface 22 of the wafer 22 have a third thickness, four second alignment marks on the crystal, 2 current, ah, and 2 coffee, and a third degree. The thickness is substantially equal to the fourth thickness, and the four first standards, such as 222b, 222d, and 222d, are formed of the second material. In the preparation of the yoke y, the two aligning marks are also formed at the same time, and the two are the same material and form 1 gold at the same time. It should be noted that the Yudi material is the gold The metal, which can be applied to the material is not limited to the above. "The structure of other metals that can be easily considered by this technology is due to the thick acoustic phase of the _ 7 pin and the bump in this example. The thickness of the second alignment mark is equal to / 'When the W-foot and the convex second-alignment mark are also joined at the same time, the —-position mark and the 200-corner 200 can provide the support ν; the 22 piece 22 and the wafer cover area near the outer side of the foot are free of pressure The time angle is caused by the stress shot. The second embodiment of the present invention is also used for the alignment of a wafer package structure. Different from the previous embodiment, in the chip package structure 2 of the present embodiment, the number of the leadless regions and the alignment devices are different, and therefore only the portions of the leadless regions and the alignment devices are specifically described herein. 3A and 3B, wherein FIG. 3A is a bottom view of the wafer 22' in the wafer package structure 2 of the present embodiment, and FIG. 3B is a flexible substrate 20' of the wafer package structure 2 of the present embodiment. Top view. In the wafer package structure 2 of the present embodiment, the flexible substrate 20' has a wafer cover region 200', and the wafer cover region 200' includes a peripheral region. The peripheral region is defined as four lead regions 204a', 204b', 204c' and 204d' and four leadless regions 206a', 206b', 206c' and 206d', and the plurality of pins 210' are formed in four leads Foot areas 204a', 204b', 204c' and 204d'. The active surface 220' of one of the wafers 22' has a plurality of bumps 221' correspondingly electrically connected to the pins 210'. Further, the alignment device includes two first alignment marks 201a', 201c', and two second alignment marks 222a', 222c'. Two first alignment marks 201a', 201c' are respectively formed on two diagonal corners of the wafer footprint 200', that is, two of the leadless regions 206a' and 206c'; two second alignment marks 222a', 222c' are formed on the active surface 220' of the wafer 22' at positions corresponding to the first alignment marks 201a', 201c'. When the wafer 22' is electrically positioned on the wafer footprint 200', the two first alignment marks 201a' and 201c' are adapted to correspond to the two second alignment marks 222a' and 222c', respectively. Similarly, wafer footprint 200' and wafer 22' are also defined with a read area. In the case of the wafer footprint 200', the teaching regions are the lead-free regions 206a' and 206c', and the first alignment marks 201a' and 201c' are respectively included in each of the teaching regions; The teaching read area is the two corners corresponding to the leadless areas 206a' and 206c'. Next, 200917451 also uses the camera to view each teaching area, and confirms the relative position of the first-alignment mark and the second alignment mark by the gray-scale value of each teaching area (for example, the X direction, the y direction, and the offset angle). Θ) 'By judging whether the two are properly connected and adjusted, so that the pin training is more accurate with the alignment of the bumps 221 such as Hai. After the alignment, press the machine to complete the electrical joint between the two. In this embodiment, although only the first alignment mark and the second alignment mark are disposed on the two diagonal corners of the wafer and the wafer footprint, an alignment mechanism and a sufficient support force can be provided. It should be noted that the number of the first aligning mark and the second aligning mark is not limited to the number of the above embodiments, and may be arbitrarily increased or decreased, and is not limited to the above number. The shape of the first alignment mark and the second alignment mark may be the same or different. The second embodiment of the present invention is also a aligning device for a chip package construction. The difference between the first alignment mark and the second alignment mark in the alignment device of the chip package structure 3 of the present embodiment is that the first alignment mark and the second alignment mark are thinner lines, that is, the first embodiment. The lines of the one-bit mark and the second match mark are much thinner than the first and second alignment marks of the foregoing embodiments. The chip package structure 3 is simultaneously passed through [; the alignment device, the lead and the bump are shown in FIG. 4A, and the 4B and 4C are respectively in the chip package structure 3, and the bottom view of the wafer 32 is A top view of the flexible substrate 30. In the chip package construction 3, the flexible substrate 30 has a wafer footprint 300, and the wafer footprint 300 includes a peripheral region. The peripheral region is defined as four lead regions 304a, 304b, 304c, and 304d and four leadless regions 306a, 306b, 306c, and 306d, and the plurality of pins 310 are formed in the four lead regions 304a, 304b, 304c, and 304d. on. The active surface 320 of one of the wafers 32 has a plurality of bumps 321 , thereby correspondingly electrically connecting 12 200917451 to the pins 310 . Further, the alignment device includes two first alignment marks 301a, 301c and two second alignment marks 322a, 322c. Two first alignment marks 301a, 301c are respectively formed on two diagonal corners of the wafer footprint 300, that is, two of the leadless regions 306a and 306c; two second alignment marks 322a, 322c are formed. On the active surface 320 of the wafer 32, the position corresponding to the first alignment mark 301a, 301c. Preferably, the first pair of bit marks 301a, 301c are formed simultaneously with the pin 310 by the same process (such as an etching process), and the thickness of the first bit mark 301a, 301c is equal to the thickness of the pin 310. In more detail, the first thickness of each of the pins 310 will substantially correspond to the second thickness of the first alignment marks 301a, 301c. On the other hand, the second alignment mark 322a, 322c is preferably formed simultaneously with the bump 321 , but since the lines of the second alignment mark 322a, 322c are thin, in the actual process, the second alignment mark 322a, The thickness of 322c is typically less than the thickness of bump 321 . In more detail, the third thickness of each bump 321 is substantially greater than the fourth thickness of the second alignment mark 322a, 322c. The shapes of the first alignment marks 301a, 301c and the second alignment marks 322a, 322c are all line-shaped marks of a m-shaped shape. More specifically, the stroke width of the rice-shaped shape is much smaller than that of the foregoing embodiments. In other implementations, the first alignment mark and the second alignment mark may also be selected from the group of shapes such as a chevron, a cross, a T, an L, and a square, or may be used by other known techniques. The shape can be easily replaced, so it is not limited to the above shape. When the wafer 32 is electrically positioned on the wafer footprint 300, the two first alignment marks 301a and 301c may correspond to the two second alignment marks 322a and 322c, respectively. Similarly, wafer footprint 300 and wafer 32 are also defined with a teaching buy area. In the case of the wafer coverage area 13 200917451 300, the teaching area (4) is her and the (4) area is ordered. The alignment marks 3013 and 301c; the wafer 32 and the t1 teaching & area correspond to the no-pin Area Birds and Articles Next, ^ Use the camera to view each teaching area, to teach each of the 'parameters, the offset of the alignment mark (such as the deviation of the X direction: quantity: square direction - = partial = and offset angle) e), by which it is judged whether the relative positions of the two are correctly aligned, and the offset of the field is adjusted to make the alignment of the pin 310 and the bumps 32 more precise. After the alignment, the machine is further (4) combined to complete the electrical bonding between the two. In this example, the first-alignment mark and the second alignment mark are only disposed on the wafer and the wafer coverage area. The corners provide a mechanism for alignment, in more detail... because of its line shape, it can be used as a basis for rapid fine-tuning when viewing the calibration area with a camera. It is to be noted that the number of the first-alignment mark and the second-alignment mark is not limited to the number of the above-mentioned real_, and may be arbitrarily increased or decreased, and is not limited to the above-mentioned number. In addition, in other implementations, the shape of the first-to-paragraph mark and the second pair of bit marks may be the same or different. It can be seen from the above embodiments that the present invention can be used for the pin on the switchable substrate and the bump on the wafer by the above-mentioned alignment device for a chip package structure and respectively disposed on the wafer and the flexible substrate. When the block is aligned, it can be precisely aligned, and is not limited to the distance between the pin on the long side and the 5 foot on the short side, and is more applicable to only the long side (or only the short side). Have a chat. In addition, the alignment of the first embodiment and the second embodiment of the present invention can provide the effect of _cutting and dispersing stress, thereby protecting the pins and bumps near the corners, and not by the angle of the pressing. Stress is concentrated and damaged. The above-described embodiments are merely illustrative of the embodiments of the present invention, and the technical features of the present invention are not limited to the scope of the present invention. Any change or singularity that can be easily accomplished by those skilled in the art is within the scope of the invention, and the scope of the invention should be determined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a flexible substrate in a wafer package structure of a prior art; FIG. 2A is a cross-sectional view of a chip package structure according to a first embodiment of the present invention; In the wafer package structure of the first embodiment of the present invention, a bottom view of the wafer, and FIG. 2C is a plan view of the flexible substrate in the K-chip package structure of the first embodiment of the present invention; In the wafer package structure of the second embodiment of the present invention, the bottom view flexible substrate 3B of the wafer is the top view of the wafer package structure of the second embodiment of the present invention; and FIG. 4C A plan view of a crystal according to a third embodiment of the present invention. 4A is a cross-sectional view of a third embodiment of the present invention, which is a cross-sectional view of a third embodiment of the present invention, and a tz encapsulation and structure in a bottom-view package structure of a wafer. Flexible substrate [Description of main components] 10: Flexible substrate 15 200917451 100: Wafer coverage area 100a: Long side 100b: Short side 104. Teaching area 110a: First long side pin 110b: First short Side pin 2. Wafer package structure 20: flexible substrate 20': flexible substrate 200: wafer footprint 200': wafer footprint
201a、201b、201c、201d :第一對位標記 201a’、201c’ ：第一對位標記 204a、204b、204c、204d :引腳區 204a’、204b’、204c’、204d’ ··引腳區 206a、206b、206c、206d :無引腳區 206a’、206b’、206c’、206d’ ：無引腳區 21 :導電層 210 :引腳 210’ ：引腳 22 :晶片 22’ ：晶片 220 :主動面 16 200917451 220’ ：主動面 222a、222b、222c、222d :第二對位標記 222a’、222c’ ：第二對位標記 221 :凸塊 22Γ :凸塊 3:晶片封裝構造 30 :可撓性基板 300 :晶片覆蓋區 301a、301c :第一對位標記 304a、304b、304c、304d :引腳區 306a、306b、306c、306d :無弓丨腳區 310 :引腳 32 :晶片 320 :主動面 321 :凸塊 322a、322c :第二對位標記 17201a, 201b, 201c, 201d: first alignment mark 201a', 201c': first alignment mark 204a, 204b, 204c, 204d: pin areas 204a', 204b', 204c', 204d' · pin Areas 206a, 206b, 206c, 206d: leadless areas 206a', 206b', 206c', 206d': leadless area 21: conductive layer 210: pin 210': pin 22: wafer 22': wafer 220 Active surface 16 200917451 220': active surface 222a, 222b, 222c, 222d: second alignment mark 222a', 222c': second alignment mark 221: bump 22 Γ: bump 3: chip package structure 30: Flexible substrate 300: wafer footprints 301a, 301c: first alignment marks 304a, 304b, 304c, 304d: pin regions 306a, 306b, 306c, 306d: no-bow-foot region 310: pin 32: wafer 320: Active surface 321 : bumps 322a, 322c: second alignment mark 17