JP2001168268A - Semiconductor module and electronic circuit device - Google Patents
Semiconductor module and electronic circuit deviceInfo
- Publication number
- JP2001168268A JP2001168268A JP34805999A JP34805999A JP2001168268A JP 2001168268 A JP2001168268 A JP 2001168268A JP 34805999 A JP34805999 A JP 34805999A JP 34805999 A JP34805999 A JP 34805999A JP 2001168268 A JP2001168268 A JP 2001168268A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- wiring portion
- substrate
- flexible substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体モジュールお
よび電子回路装置に関し、特に、小型化および高密度化
されたパッケージ形態を有する半導体装置をモジュール
化した半導体モジュールと、当該半導体モジュールを実
装基板上に実装した電子回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module and an electronic circuit device, and more particularly, to a semiconductor module in which a semiconductor device having a compact and high-density package is modularized, and the semiconductor module is mounted on a mounting board. The present invention relates to a mounted electronic circuit device.
【０００２】[0002]
【従来の技術】デジタルビデオカメラ、ＩＣカード、デ
ジタル携帯電話、ノートパソコンあるいはＰＤＡ（Pers
onal Digital Assistant）など、携帯用電子機器の小型
化、薄型化、軽量化に対する要求は強くなる一方であ
り、これに応えるために近年のＶＬＳＩなどの半導体装
置においては３年で７割の縮小化を実現してきた一方
で、実装基板上の部品実装密度をいかに向上させるかが
重要な課題として研究および開発がなされてきた。2. Description of the Related Art A digital video camera, an IC card, a digital cellular phone, a notebook computer or a PDA (Pers
Onal Digital Assistant) and other portable electronic devices are increasingly required to be smaller, thinner and lighter. To meet this demand, semiconductor devices such as recent VLSIs have been reduced by 70% in three years. On the other hand, research and development have been carried out as an important issue how to increase the component mounting density on a mounting board.
【０００３】従来、半導体装置のパッケージ形態として
は、ＤＩＰ（Dual In-line Package）あるいはＰＧＡ
（Pin Grid Array）などのプリント基板に設けたスルー
ホールにリード線を挿入して実装するリード挿入型（Ｔ
ＨＤ：Through Hole Mount Device ）や、ＱＦＰ（Quad
Flat Package ）あるいはＴＣＰ（Tape Carrier Packa
ge）などのリード線を基板の表面にハンダ付けして実装
する表面実装型（ＳＭＤ：Surface Mount Device）が用
いられてきた。Conventionally, as a semiconductor device package, a DIP (Dual In-line Package) or PGA
(Tin Grid Array) and other lead insertion type (T
HD: Through Hole Mount Device), QFP (Quad
Flat Package) or TCP (Tape Carrier Packa)
ge) and the like, and a surface mount device (SMD: Surface Mount Device) has been used in which a lead wire is soldered and mounted on the surface of a substrate.
【０００４】上記のように装置の小型化および高密度化
を進めるために、半導体装置のパッケージ形態は、パッ
ケージサイズを半導体チップの大きさに限りなく近づけ
たチップサイズパッケージ（ＣＳＰ：Chip Size Packag
e ）と呼ばれるパッケージ形態へと移行し、さらには、
はんだや金などからなる突起電極（バンプ）をパッド電
極に接続するように設けてＣＳＰ化した半導体装置のバ
ンプ形成面側を実装基板に向け、フェースダウンで実装
するフリップチップ実装形態へと移行してきている。さ
らなる小型化および高密度化のために、パッド電極に接
続するように突起電極（バンプ）を設けた半導体チップ
を、ベアチップ状態でフリップチップ実装する方法が開
発され、現在までに活発に研究がなされ、多くの提案が
示されている。As described above, in order to reduce the size and increase the density of the device, the semiconductor device is packaged in a chip size package (CSP: Chip Size Package) in which the package size is as close as possible to the size of a semiconductor chip.
e) into a package form called
A bump-forming surface made of CSP is provided by connecting a bump electrode made of solder, gold, etc. to a pad electrode, and the bump forming surface side of the semiconductor device is turned to a mounting board, and the flip-chip mounting mode in which the semiconductor device is mounted face down has been shifted. ing. For further miniaturization and higher density, a method of flip chip mounting a semiconductor chip provided with bump electrodes (bumps) so as to be connected to pad electrodes in a bare chip state has been developed. , Many suggestions are given.
【０００５】上記のベアチップ状態で半導体チップを実
装基板に実装した電子回路装置について、図面を参照し
て説明する。図８は上記のベアチップ実装用の半導体チ
ップの断面図である。半導体チップ１０’のアルミニウ
ムなどからなるパッド電極１１形成面は、例えば窒化シ
リコン層からなる第１表面保護膜１２とポリイミド膜か
らなる第２表面保護膜１３が被覆しており、パッド電極
１１部分が開口しており、この開口部においてクロム、
銅、金の積層膜などからなる導電膜１４がパッド電極１
１に接続して形成されている。この導電膜は、ＢＬＭ
（Ball Limitting Metal）膜と呼ばれることがある。さ
らに導電膜（ＢＬＭ膜）１４に接続して例えば高融点は
んだボールからなるバンプ１６ｂが形成されている。以
上のようにベアチップ実装用の半導体チップ１が構成さ
れている。An electronic circuit device in which a semiconductor chip is mounted on a mounting board in a bare chip state will be described with reference to the drawings. FIG. 8 is a sectional view of the semiconductor chip for mounting the bare chip. The surface of the semiconductor chip 10 'on which the pad electrode 11 made of aluminum or the like is formed is covered with a first surface protection film 12 made of, for example, a silicon nitride layer and a second surface protection film 13 made of a polyimide film. Chrome in this opening,
The conductive film 14 made of a copper, gold laminated film or the like forms the pad electrode 1.
1 is formed. This conductive film is made of BLM
(Ball Limiting Metal) film. Further, a bump 16b made of, for example, a high melting point solder ball is formed so as to be connected to the conductive film (BLM film) 14. The semiconductor chip 1 for mounting a bare chip is configured as described above.
【０００６】一方、実装基板２’は、例えばガラスエポ
キシ系材料よりなる実装基板基材２０’の上面におい
て、実装する半導体チップ１のバンプ１６ｂの形成位置
に対応する位置に形成された銅などからなるランド（電
極）を含み、実装基板基材２０’の表面上あるいは裏面
上、もしくは両面上に形成されている配線部２６を有し
ている。配線部２６部分を除く実装基板基材２０’表面
は例えば不図示のソルダーレジストにより被覆されてい
る。On the other hand, the mounting substrate 2 ′ is made of, for example, copper formed at a position corresponding to the position where the bump 16 b of the semiconductor chip 1 to be mounted is formed on the upper surface of the mounting substrate base material 20 ′ made of, for example, a glass epoxy material. And a wiring portion 26 formed on the front surface, the back surface, or both surfaces of the mounting substrate 20 ′. The surface of the mounting substrate 20 'excluding the wiring portion 26 is covered with, for example, a solder resist (not shown).
【０００７】上記の半導体チップ１は、バンプ１６ｂと
ランドを対応させて実装基板２’上にマウントされてお
り、共晶はんだ層１９あるいはバンプ１６ｂ自身により
バンプ１６ｂとランドとが機械的、電気的に接続されて
いる。さらに、半導体チップ１と実装基板２’の間隙部
は、エポキシ樹脂などからなる封止樹脂３により封止さ
れている。The semiconductor chip 1 is mounted on the mounting substrate 2 'with the bumps 16b and the lands corresponding to each other. The bumps 16b and the lands are mechanically and electrically connected by the eutectic solder layer 19 or the bumps 16b themselves. It is connected to the. Further, a gap between the semiconductor chip 1 and the mounting board 2 'is sealed with a sealing resin 3 made of epoxy resin or the like.
【０００８】上記の半導体装置において、はんだバンプ
を所定の位置に形成する方法としては、例えば電解メッ
キを用いる方法が知られているが、この場合にはバンプ
の下地となる材料層の表面状態や電気抵抗のわずかなば
らつきにより成膜されるはんだバンプの膜厚が影響を受
け、半導体チップ内に均一で高さの揃ったはんだボール
バンプを形成することが非常に難しいという問題点を有
している。In the above-described semiconductor device, as a method of forming solder bumps at predetermined positions, for example, a method using electrolytic plating is known. In this case, the surface condition of a material layer serving as a base of the bumps or the like is known. There is a problem that it is very difficult to form uniform and uniform solder ball bumps in a semiconductor chip, because the thickness of the solder bumps formed is affected by slight variations in electrical resistance. I have.
【０００９】真空蒸着によるはんだ層の成膜とフォトレ
ジスト膜のリフトオフとを用いて、はんだボールバンプ
を高さを揃えて形成する方法が開発されている。この方
法について、図面を参照して以下に説明する。まず、図
９（ａ）に示すように、例えばスパッタリング法やエッ
チングなどにより半導体チップの回路パターンが形成さ
れた半導体ウェーハ１０上にアルミニウム−銅合金など
からなるパッド電極１１をパターン形成し、その上層に
例えば窒化シリコン層あるいはポリイミド膜などからな
る表面保護膜１３を全面に被覆して形成する。表面保護
膜１３のパッド電極１１部分を開口した後、例えばスパ
ッタリング法によりクロム、銅、金の積層体である導電
膜（ＢＬＭ膜）１４をパッド電極１１に接続するように
パターン形成する。A method has been developed in which solder ball bumps are formed to have uniform heights by using the deposition of a solder layer by vacuum deposition and the lift-off of a photoresist film. This method will be described below with reference to the drawings. First, as shown in FIG. 9A, a pad electrode 11 made of an aluminum-copper alloy or the like is pattern-formed on a semiconductor wafer 10 on which a circuit pattern of a semiconductor chip is formed by, for example, a sputtering method or etching. A surface protective film 13 made of, for example, a silicon nitride layer or a polyimide film is coated on the entire surface. After opening the pad electrode 11 portion of the surface protection film 13, a conductive film (BLM film) 14, which is a laminate of chromium, copper, and gold, is formed by, for example, a sputtering method so as to be connected to the pad electrode 11.
【００１０】次に、図９（ｂ）に示すように、フォトリ
ソグラフィー工程により、導電膜（ＢＬＭ膜）１４形成
領域にパターン開口部Ａを有するレジスト膜Ｒをパター
ン形成する。次に、図９（ｃ）に示すように、例えば真
空蒸着法により全面にはんだ層を成膜することで、レジ
スト膜Ｒのパターン開口部Ａ内にはんだ層１６を形成す
る。このとき、レジスト膜Ｒの上層にもはんだ層１６ａ
が形成される。Next, as shown in FIG. 9B, a resist film R having a pattern opening A in a conductive film (BLM film) 14 formation region is patterned by a photolithography process. Next, as shown in FIG. 9C, the solder layer 16 is formed in the pattern opening A of the resist film R by forming a solder layer on the entire surface by, for example, a vacuum evaporation method. At this time, the solder layer 16a is also formed on the resist film R.
Is formed.
【００１１】次に、図１０（ａ）に示すように、リフト
オフによりレジスト膜Ｒを除去することで、レジスト膜
Ｒの上層に形成されたはんだ層１６ａを同時に除去す
る。これにより、レジスト膜Ｒのパターン開口部Ａ内に
形成されたはんだ層１６のみを残すことができる。次
に、図１０（ｂ）に示すように、熱処理を行ってはんだ
層１６を溶融させ、表面張力により球形となった状態で
冷却、固化することではんだボールのバンプ１６ｂを形
成する。Next, as shown in FIG. 10A, by removing the resist film R by lift-off, the solder layer 16a formed on the resist film R is simultaneously removed. Thus, only the solder layer 16 formed in the pattern opening A of the resist film R can be left. Next, as shown in FIG. 10B, the solder layer 16 is melted by heat treatment, and cooled and solidified in a spherical state by surface tension to form solder ball bumps 16b.
【００１２】[0012]
【発明が解決しようとする課題】しかしながら、上記の
ような半導体装置を用いたＩＣカード、デジタル携帯電
話あるいはＰＤＡなどの携帯用電子機器としては、デバ
イスの実装スペースはできるだけ小型化することが望ま
れており、２次元的な縮小に加えて３次元的な縮小、即
ち薄型化ができるような半導体デバイスの高密度な３次
元実装技術を確立して、より一層の高密度化、高機能化
を実現することが切望されている。However, as a portable electronic device such as an IC card, a digital mobile phone, or a PDA using the above-described semiconductor device, it is desired that the mounting space of the device be as small as possible. In addition to the two-dimensional reduction, three-dimensional reduction, that is, a high-density three-dimensional mounting technology for semiconductor devices that can be reduced in thickness is established, and further higher density and higher functionality are achieved. It is eager to achieve.
【００１３】上記の半導体デバイスを３次元に実装する
技術が、例えば、特開平６−２４４３６０号公報に開示
されている。即ち、図１１に示すように、実装基板基材
２０’とその表面に形成された配線部２６から構成され
ている実装基板上に、表面に電極１１が形成され、大き
さがほぼ等しい４個の半導体チップ（１０ａ’，１０
ｂ’，１０ｃ’，１０ｄ’）が、各電極１１形成面を上
側にして積層されている。上側から３個の各半導体装置
には、各半導体チップの周辺部（ペリフェラル領域）に
形成された各電極１１を露出させるために切欠部Ｘが設
けられている。半導体チップの各電極１１と実装基板の
配線部２６とがワイヤボンディング２７により接続され
ており、積層された半導体チップ全体を封止樹脂３が被
覆している。A technique for mounting the above-described semiconductor device three-dimensionally is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-244360. That is, as shown in FIG. 11, on a mounting board composed of a mounting board base material 20 'and a wiring portion 26 formed on the surface, the electrodes 11 are formed on the surface and four Semiconductor chips (10a ', 10
b ', 10c', 10d ') are stacked with the surface on which each electrode 11 is formed facing upward. Each of the three semiconductor devices from the upper side is provided with a notch X for exposing each electrode 11 formed in a peripheral portion (peripheral region) of each semiconductor chip. Each electrode 11 of the semiconductor chip and the wiring portion 26 of the mounting board are connected by wire bonding 27, and the entire laminated semiconductor chip is covered with the sealing resin 3.
【００１４】また、同様に半導体デバイスを３次元に実
装する技術が、例えば、特開昭６０−９４７５６号公報
に開示されている。即ち、図１２（（ａ）は平面図であ
り、（ｂ）は（ａ）中のＹ−Ｙ’における断面図）に示
すように、表面に電極（１１ａ，１１ｂ，１１ｃ）が形
成された３個の半導体チップ（１０ａ’，１０ｂ’，１
０ｃ’）が、各電極形成面を上側にして積層されてい
る。ここで、３個の各半導体チップは大きさは上側程小
さくなっており、これにより各半導体チップの周辺部に
形成された各電極が露出している。半導体チップの各電
極間、あるいは各電極１１とその外周領域に設けられて
いる配線部２６とがワイヤボンディング２７により接続
されている。A technique for similarly mounting a semiconductor device three-dimensionally is disclosed, for example, in Japanese Patent Application Laid-Open No. 60-94756. That is, as shown in FIG. 12 ((a) is a plan view, (b) is a cross-sectional view taken along line YY ′ in (a)), electrodes (11a, 11b, 11c) are formed on the surface. Three semiconductor chips (10a ', 10b', 1
0c ′) are stacked with the respective electrode formation surfaces facing upward. Here, the size of each of the three semiconductor chips becomes smaller toward the upper side, whereby each electrode formed at the peripheral portion of each semiconductor chip is exposed. Each electrode of the semiconductor chip, or each electrode 11 and a wiring portion 26 provided in an outer peripheral region thereof are connected by wire bonding 27.
【００１５】しかしながら、上記の半導体デバイスを３
次元に実装した電子回路装置はワイヤボンディングの引
回しのために余分な空間を必要としており、さらに長い
ワイヤボンディングによるインダクタンスのために高周
波デバイスを実装する場合には信号遅延を顕在化させる
という問題があった。さらにまた、半導体デバイスを直
接積層させているために放熱が十分でない場合があり、
ロジック系デバイスなどの消費電力の大きなデバイスに
適用した場合には発熱量が多いために半導体デバイスが
高温となってしまい、電気特性に支障を来すことがある
という問題があった。However, the above semiconductor device is
Electronic circuit devices mounted in three dimensions require extra space for routing of wire bonding, and there is a problem that signal delay becomes apparent when mounting high-frequency devices due to the inductance due to longer wire bonding. there were. Furthermore, heat dissipation may not be sufficient because the semiconductor devices are stacked directly,
When applied to a device with a large power consumption such as a logic device, there is a problem that the semiconductor device is heated to a high temperature due to a large amount of heat generation, which may affect the electrical characteristics.
【００１６】本発明は上記の問題を鑑みなされたもので
あり、本発明は、実装基板への接続部のインダクタンス
による信号遅延の問題を改善でき、各半導体デバイスか
らの放熱量を確保して半導体デバイスが高温となること
を回避することが可能である、複数個の半導体チップを
積層してモジュール化した半導体モジュールと、当該半
導体モジュールを実装した電子回路装置を提供すること
を目的とする。The present invention has been made in view of the above-mentioned problems, and the present invention can improve the problem of signal delay due to the inductance of a connection portion to a mounting board, and can secure the amount of heat radiation from each semiconductor device. It is an object of the present invention to provide a semiconductor module in which a plurality of semiconductor chips can be stacked to form a module, and an electronic circuit device on which the semiconductor module is mounted, which can prevent the device from becoming hot.
【００１７】[0017]
【課題を解決するための手段】上記の目的を達成するた
め、本発明の半導体モジュールは、両面に配線部を有す
る可撓性基板と、半導体装置の回路パターンと、前記回
路パターンに接続する第１突起電極を有し、前記第１突
起電極形成面側から前記配線部に接続するように前記可
撓性基板の一方の面上に実装された第１半導体装置およ
び第２半導体装置と、前記第１半導体装置の上面に固着
された放熱性基板とを有し、前記第１半導体装置と前記
第２半導体装置の実装部分の間における前記可撓性基板
が湾曲しており、前記第２半導体装置の上面が前記放熱
性基板の前記第１半導体装置固着面の反対側の面に固着
されている。In order to achieve the above object, a semiconductor module according to the present invention comprises a flexible substrate having wiring portions on both sides, a circuit pattern of a semiconductor device, and a semiconductor device connected to the circuit pattern. A first semiconductor device and a second semiconductor device, each having one protruding electrode, mounted on one surface of the flexible substrate so as to be connected to the wiring portion from the first protruding electrode forming surface side; A heat dissipating substrate fixed to an upper surface of the first semiconductor device, wherein the flexible substrate between the mounting portion of the first semiconductor device and the mounting portion of the second semiconductor device is curved; An upper surface of the device is fixed to a surface of the heat dissipation substrate opposite to the fixing surface of the first semiconductor device.
【００１８】上記の本発明の半導体モジュールは、好適
には、前記半導体モジュールを実装基板に実装するため
に、前記配線部に接続するように第２突起電極が形成さ
れている。In the semiconductor module of the present invention, preferably, the second protruding electrode is formed so as to be connected to the wiring portion in order to mount the semiconductor module on a mounting board.
【００１９】上記の本発明の半導体モジュールは、好適
には、前記第１半導体装置および前記第２半導体装置が
それぞれ２００μｍ以下の高さである。In the above-described semiconductor module of the present invention, preferably, each of the first semiconductor device and the second semiconductor device has a height of 200 μm or less.
【００２０】上記の本発明の半導体モジュールは、好適
には、前記配線部に接続するように前記可撓性基板の他
方の面上に第３半導体装置が実装されている。さらに好
適には、前記半導体モジュールを実装基板に実装するた
めに、前記配線部に接続するように第２突起電極が形成
されており、前記第１、前記第２および第３半導体装置
の高さがそれぞれ２００μｍ以下であり、前記第２突起
電極の高さが３００μｍ以上である。In the above-described semiconductor module of the present invention, preferably, a third semiconductor device is mounted on the other surface of the flexible substrate so as to be connected to the wiring portion. More preferably, in order to mount the semiconductor module on a mounting substrate, a second protruding electrode is formed so as to be connected to the wiring portion, and the height of the first, second and third semiconductor devices is increased. Are 200 μm or less, respectively, and the height of the second protruding electrode is 300 μm or more.
【００２１】上記の本発明の半導体モジュールは、好適
には、前記第１および第２半導体装置のそれぞれの上面
が、絶縁性接着剤により前記放熱性基板に固着されてい
る。In the semiconductor module according to the present invention, preferably, the upper surfaces of the first and second semiconductor devices are fixed to the heat-radiating substrate with an insulating adhesive.
【００２２】上記の本発明の半導体モジュールは、半導
体装置の回路パターンに接続する第１突起電極を有する
第１半導体装置および第２半導体装置の第１突起電極形
成面の反対側の面同士が放熱性基板を介して固着されて
おり、第１半導体装置と第２半導体装置の実装部分の間
において湾曲している可撓性基板に形成された配線部に
第１半導体装置および第２半導体装置の各第１突起電極
が接続して、モジュール化されており、可撓性基板に形
成された配線部に第２突起電極が形成されている構成と
することで、モジュール状態で実装基板に実装すること
ができる。In the above-described semiconductor module of the present invention, the surfaces of the first semiconductor device having the first protruding electrodes connected to the circuit pattern of the semiconductor device and the surfaces of the second semiconductor device opposite to the surface on which the first protruding electrodes are formed are radiated. The first semiconductor device and the second semiconductor device are fixed to a wiring portion formed on a flexible substrate that is fixed between the mounting portions of the first semiconductor device and the second semiconductor device and is fixed via a flexible substrate. Each of the first protruding electrodes is connected to form a module, and the second protruding electrode is formed on the wiring portion formed on the flexible substrate, so that the module is mounted on the mounting substrate in a module state. be able to.
【００２３】上記の本発明の半導体モジュールによれ
ば、ワイヤボンディングを用いずに実装可能であり、実
装基板への接続部のインダクタンスによる信号遅延の問
題を改善できる。また、第１半導体装置および第２半導
体装置は放熱性基板を介して積層された形態であり、各
半導体デバイスからの放熱量を確保して半導体デバイス
が高温となることを回避することが可能である。According to the above-described semiconductor module of the present invention, mounting can be performed without using wire bonding, and the problem of signal delay due to inductance of a connection portion to a mounting substrate can be improved. In addition, the first semiconductor device and the second semiconductor device are stacked with a heat-dissipating substrate interposed therebetween, and the heat dissipation from each semiconductor device can be ensured to prevent the semiconductor device from becoming hot. is there.
【００２４】上記の目的を達成するため、本発明の電子
回路装置は、両面に第１配線部を有する可撓性基板と、
半導体装置の回路パターンと、前記回路パターンに接続
する第１突起電極を有し、前記第１突起電極形成面側か
ら前記第１配線部に接続するように前記可撓性基板の一
方の面上に実装された第１半導体装置および第２半導体
装置と、前記第１半導体装置の上面に固着された放熱性
基板とを有し、前記第１半導体装置と前記第２半導体装
置の実装部分の間における前記可撓性基板が湾曲してお
り、前記第２半導体装置の上面が前記放熱性基板の前記
第１半導体装置固着面の反対側の面に固着されている半
導体モジュールと、第２配線部を有する実装基板とを有
し、前記第１配線部と前記第２配線部が接続して、前記
半導体モジュールが前記実装基板上に実装されている。To achieve the above object, an electronic circuit device according to the present invention comprises: a flexible substrate having first wiring portions on both sides;
A first protruding electrode connected to the circuit pattern, the first protruding electrode being connected to the circuit pattern, and being connected to the first wiring portion from the first protruding electrode forming surface side on one surface of the flexible substrate; A first semiconductor device and a second semiconductor device mounted on the first semiconductor device, and a heat dissipating substrate fixed to an upper surface of the first semiconductor device, wherein a portion between the first semiconductor device and the mounting portion of the second semiconductor device is provided. A semiconductor module in which the flexible substrate is curved, and an upper surface of the second semiconductor device is fixed to a surface of the heat radiation substrate opposite to the first semiconductor device fixing surface; and a second wiring portion. And the first wiring portion and the second wiring portion are connected to each other, and the semiconductor module is mounted on the mounting substrate.
【００２５】上記の本発明の電子回路装置は、好適に
は、前記第１配線部と前記第２配線部が第２突起電極に
より接続されている。In the above electronic circuit device of the present invention, preferably, the first wiring portion and the second wiring portion are connected by a second protruding electrode.
【００２６】上記の本発明の電子回路装置は、好適に
は、前記第１半導体装置および前記第２半導体装置がそ
れぞれ２００μｍ以下の高さである。In the above-described electronic circuit device of the present invention, preferably, the first semiconductor device and the second semiconductor device each have a height of 200 μm or less.
【００２７】上記の本発明の電子回路装置は、好適に
は、前記第１配線部に接続するように前記可撓性基板の
他方の面上に第３半導体装置が実装されている。さらに
好適には、前記第１配線部と前記第２配線部が第２突起
電極により接続されており、前記第１、前記第２および
第３半導体装置の高さがそれぞれ２００μｍ以下であ
り、前記第２突起電極の高さが３００μｍ以上である。In the above electronic circuit device of the present invention, preferably, a third semiconductor device is mounted on the other surface of the flexible substrate so as to be connected to the first wiring portion. More preferably, the first wiring portion and the second wiring portion are connected by a second projection electrode, and the first, second, and third semiconductor devices each have a height of 200 μm or less, The height of the second protrusion electrode is 300 μm or more.
【００２８】上記の本発明の電子回路装置は、好適に
は、前記第１および第２半導体装置のそれぞれの上面
が、絶縁性接着剤により前記放熱性基板に固着されてい
る。In the above-described electronic circuit device of the present invention, preferably, the respective upper surfaces of the first and second semiconductor devices are fixed to the heat dissipation substrate with an insulating adhesive.
【００２９】上記の本発明の電子回路装置は、半導体装
置の回路パターンに接続する第１突起電極を有する第１
半導体装置および第２半導体装置の第１突起電極形成面
の反対側の面同士が放熱性基板を介して固着されてお
り、第１半導体装置と第２半導体装置の実装部分の間に
おいて湾曲している可撓性基板に形成された第１配線部
に第１半導体装置および第２半導体装置の各第１突起電
極が接続して、モジュール化された半導体モジュール
が、可撓性基板に形成された配線部に第２突起電極など
により第２配線部を有する実装基板に実装されている。The above electronic circuit device of the present invention has a first protruding electrode having a first protruding electrode connected to a circuit pattern of a semiconductor device.
The surfaces of the semiconductor device and the second semiconductor device opposite to the surface on which the first protruding electrode is formed are fixed to each other via a heat-radiating substrate, and are curved between the mounting portions of the first semiconductor device and the second semiconductor device. The first protruding electrodes of the first semiconductor device and the second semiconductor device are connected to the first wiring portion formed on the flexible substrate, and the modularized semiconductor module is formed on the flexible substrate. It is mounted on a mounting substrate having a second wiring portion by a second protruding electrode or the like in the wiring portion.
【００３０】上記の本発明の電子回路装置によれば、ワ
イヤボンディングを用いずに実装しており、実装基板へ
の接続部のインダクタンスによる信号遅延の問題を改善
できる。また、第１半導体装置および第２半導体装置は
放熱性基板を介して積層された形態であり、各半導体デ
バイスからの放熱量を確保して半導体デバイスが高温と
なることを回避することが可能である。According to the electronic circuit device of the present invention described above, the electronic circuit device is mounted without using wire bonding, and the problem of signal delay due to the inductance of the connection portion to the mounting substrate can be improved. In addition, the first semiconductor device and the second semiconductor device are stacked with a heat-dissipating substrate interposed therebetween, and the heat dissipation from each semiconductor device can be ensured to prevent the semiconductor device from becoming hot. is there.
【００３１】[0031]
【発明の実施の形態】以下に、本発明の半導体装置の製
造方法の実施の形態について、図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
【００３２】第１実施形態 図１は本実施形態に係る電子回路装置の断面図であり、
図２は図１に示す電子回路装置におけるベアチップ実装
用の半導体チップと可撓性基板との接続部の拡大断面図
である。図２に示すように、半導体チップ１０’のアル
ミニウムなどからなるパッド電極１１形成面は、例えば
窒化シリコン層からなる第１表面保護膜１２とポリイミ
ド膜からなる第２表面保護膜１３が被覆しており、パッ
ド電極１１部分が開口しており、この開口部においてク
ロム、銅、金の積層膜などからなる導電膜１４がパッド
電極１１に接続して形成されている。この導電膜は、Ｂ
ＬＭ（Ball Limitting Metal）膜と呼ばれることがあ
る。さらに導電膜（ＢＬＭ膜）１４に接続して例えば高
融点はんだボールからなる第１バンプ（突起電極）１６
ｂが形成されている。以上のようにベアチップ実装用の
半導体チップ１（１ａ，１ｂ）が構成されている。ここ
で、半導体チップ１（１ａ，１ｂ）はそれぞれ２００μ
ｍ以下に薄膜化されている。[0032] First Embodiment FIG. 1 is a cross-sectional view of the electronic circuit device according to this embodiment,
FIG. 2 is an enlarged sectional view of a connecting portion between a semiconductor chip for mounting a bare chip and a flexible substrate in the electronic circuit device shown in FIG. As shown in FIG. 2, the surface of the semiconductor chip 10 'on which the pad electrode 11 made of aluminum or the like is formed is covered with a first surface protection film 12 made of, for example, a silicon nitride layer and a second surface protection film 13 made of a polyimide film. The pad electrode 11 is opened, and a conductive film 14 made of a laminated film of chromium, copper, gold, or the like is formed in the opening to connect to the pad electrode 11. This conductive film is B
It may be called an LM (Ball Limiting Metal) film. Further, a first bump (protruding electrode) 16 made of, for example, a high melting point solder ball connected to the conductive film (BLM film) 14
b is formed. The semiconductor chip 1 (1a, 1b) for mounting a bare chip is configured as described above. Here, each of the semiconductor chips 1 (1a, 1b) is 200 μm.
m or less.
【００３３】上記のベアチップ実装用の半導体チップ
（１ａ，１ｂ）は、可撓性基板２の一方の面（第１面）
上に実装されている。可撓性基板２は、例えばポリイミ
ドあるいはエポキシ系材料よりなる５０μｍの膜厚の可
撓性基板基材２０の一方の面（第１面）上において、実
装する半導体チップ（１ａ，１ｂ）の第１バンプ１６ｂ
の形成位置に対応する位置に形成された銅などからなる
ランド（電極）などを含む第１面第１配線部２１が形成
され、さらに可撓性基板基材２０の他方の面（第２面）
上において、第１面第１配線部２１に接続する第２面第
１配線部２４が形成されて構成されている。半導体チッ
プ（１ａ，１ｂ）は、第１バンプ１６ｂと第１面第１配
線部２１とが対応するように可撓性基板２上にマウント
され、さらに共晶はんだ層１９により第１バンプ１６ｂ
と第１面第１配線部２１とが機械的、電気的に接続され
ており、さらに、半導体チップ（１ａ，１ｂ）と可撓性
基板２の間隙部は、エポキシ樹脂などからなる封止樹脂
３により封止されている。The semiconductor chip (1a, 1b) for mounting the bare chip is provided on one surface (first surface) of the flexible substrate 2.
Implemented above. The flexible substrate 2 is formed on one surface (first surface) of a flexible substrate 20 having a thickness of 50 μm made of, for example, a polyimide or epoxy-based material, and is formed of a semiconductor chip (1a, 1b) to be mounted. 1 bump 16b
A first wiring portion 21 including a land (electrode) made of copper or the like formed at a position corresponding to the formation position of the first substrate is formed, and the other surface (second surface) of the flexible substrate 20 is further formed. )
Above, the second surface first wiring portion 24 connected to the first surface first wiring portion 21 is formed. The semiconductor chip (1a, 1b) is mounted on the flexible substrate 2 so that the first bump 16b and the first surface first wiring portion 21 correspond to each other.
And the first surface first wiring portion 21 are mechanically and electrically connected, and the gap between the semiconductor chip (1a, 1b) and the flexible substrate 2 is a sealing resin made of epoxy resin or the like. 3 is sealed.
【００３４】上記の可撓性基板２は半導体チップ（１
ａ，１ｂ）の実装部分の間において湾曲されており、可
撓性基板２上に実装された半導体チップ（１ａ，１ｂ）
の第１バンプ１６ｂ形成面の反対側の面同士が、銅ある
いはクロム鋼など金属材料などからなる放熱性基板１７
を挟んで対向するように絶縁性ペーストなどの接着剤層
１８により放熱性基板１７に固着されており、以上のよ
うにして２個の半導体チップ（１ａ，１ｂ）を積層させ
た半導体モジュールＭが構成されている。The flexible substrate 2 is provided with a semiconductor chip (1).
semiconductor chips (1a, 1b) which are curved between the mounting portions of (a, 1b) and mounted on the flexible substrate 2
The surface opposite to the surface on which the first bumps 16b are formed has a heat-radiating substrate 17 made of a metal material such as copper or chrome steel.
Is fixed to the heat-radiating substrate 17 by an adhesive layer 18 such as an insulating paste so as to face the semiconductor module M with the two semiconductor chips (1a, 1b) stacked as described above. It is configured.
【００３５】上記の半導体モジュールＭは、第２面第１
配線部２４に接続するように、はんだボールなどからな
り、例えば３００μｍ以上の直径を有する第２バンプ２
５が形成されており、実装基板基材２０’とその表面に
形成された第２配線部２６から構成される実装基板２’
上に、第２バンプ２５と第２配線部２６とが対応するよ
うにマウントされ、不図示の共晶はんだ層あるいは第２
バンプ２５自身により第２バンプ２５と第２配線部２６
とが機械的、電気的に接続されている。The above-mentioned semiconductor module M has a first surface
The second bump 2 made of a solder ball or the like and having a diameter of, for example, 300 μm or more so as to be connected to the wiring portion 24.
5 is formed, and the mounting substrate 2 ′ includes a mounting substrate base material 20 ′ and a second wiring portion 26 formed on the surface thereof.
The second bump 25 and the second wiring portion 26 are mounted on the upper surface so as to correspond to each other, and a eutectic solder layer or a second
The second bump 25 and the second wiring portion 26 are formed by the bump 25 itself.
Are connected mechanically and electrically.
【００３６】上記の本実施形態の電子回路装置によれ
ば、２個の半導体チップ（１ａ，１ｂ）を積層させたモ
ジュールとして実装基板上にワイヤボンディングを用い
ずに実装することにより、デバイスチップ間の配線長を
短縮して、実装基板への接続部のインダクタンスを低減
して高速処理が可能であり、高周波デバイスにおいても
信号遅延の問題を改善できる。また、２個の半導体チッ
プ（１ａ，１ｂ）は放熱性基板１７を介して積層されて
おり、各半導体デバイスからの放熱量を確保して半導体
デバイスが高温となることを回避することが可能であ
る。上記の２個の半導体チップ（１ａ，１ｂ）は２００
μｍ以下に薄膜化されているため、上記のようにそれら
を積層させた半導体モジュールとしても薄膜化を実現で
きる。According to the above-described electronic circuit device of the present embodiment, the two semiconductor chips (1a, 1b) are mounted on a mounting substrate as a module on which the two semiconductor chips (1a, 1b) are stacked without using wire bonding. , The inductance of the connection portion to the mounting board is reduced, high-speed processing is possible, and the problem of signal delay can be improved even in a high-frequency device. Further, the two semiconductor chips (1a, 1b) are stacked with the heat radiation substrate 17 interposed therebetween, and the amount of heat radiation from each semiconductor device can be ensured to prevent the semiconductor device from becoming hot. is there. The two semiconductor chips (1a, 1b) are 200
Since the thickness is reduced to μm or less, the thickness can be reduced even as a semiconductor module in which they are stacked as described above.
【００３７】上記の電子回路装置の製造方法について図
面を参照して説明する。各半導体チップのはんだバンプ
の形成工程までは、従来方法と同様にして行う。即ち、
まず、図９（ａ）に示すように、例えばスパッタリング
法やエッチングなどにより半導体チップの回路パターン
が形成された半導体ウェーハ１０上にアルミニウム−銅
合金などからなるパッド電極１１をパターン形成し、そ
の上層に例えば窒化シリコン層あるいはポリイミド膜な
どからなる表面保護膜１３を全面に被覆して形成する。
表面保護膜１３のパッド電極１１部分を開口した後、例
えばスパッタリング法によりクロム、銅、金の積層体で
ある導電膜（ＢＬＭ膜）１４をパッド電極１１に接続す
るようにパターン形成する。A method for manufacturing the above electronic circuit device will be described with reference to the drawings. The steps up to the step of forming solder bumps on each semiconductor chip are performed in the same manner as in the conventional method. That is,
First, as shown in FIG. 9A, a pad electrode 11 made of an aluminum-copper alloy or the like is pattern-formed on a semiconductor wafer 10 on which a circuit pattern of a semiconductor chip is formed by, for example, a sputtering method or etching. A surface protective film 13 made of, for example, a silicon nitride layer or a polyimide film is coated on the entire surface.
After opening the pad electrode 11 portion of the surface protection film 13, a conductive film (BLM film) 14, which is a laminate of chromium, copper, and gold, is formed by, for example, a sputtering method so as to be connected to the pad electrode 11.
【００３８】次に、図９（ｂ）に示すように、フォトリ
ソグラフィー工程により、導電膜（ＢＬＭ膜）１４形成
領域にパターン開口部Ａを有するレジスト膜Ｒをパター
ン形成する。次に、図９（ｃ）に示すように、例えば真
空蒸着法により全面にはんだ層を成膜することで、レジ
スト膜Ｒのパターン開口部Ａ内にはんだ層１６を形成す
る。このとき、レジスト膜Ｒの上層にもはんだ層１６ａ
が形成される。Next, as shown in FIG. 9B, a resist film R having a pattern opening A in a conductive film (BLM film) 14 formation region is patterned by a photolithography process. Next, as shown in FIG. 9C, the solder layer 16 is formed in the pattern opening A of the resist film R by forming a solder layer on the entire surface by, for example, a vacuum evaporation method. At this time, the solder layer 16a is also formed on the resist film R.
Is formed.
【００３９】次に、図１０（ａ）に示すように、リフト
オフによりレジスト膜Ｒを除去することで、レジスト膜
Ｒの上層に形成されたはんだ層１６ａを同時に除去す
る。これにより、レジスト膜Ｒのパターン開口部Ａ内に
形成されたはんだ層１６のみを残すことができる。次
に、図１０（ｂ）に示すように、熱処理を行ってはんだ
層１６を溶融させ、表面張力により球形となった状態で
冷却、固化することで高さが例えば６０μｍのはんだボ
ールからなる第１バンプ１６ｂを形成する。Next, as shown in FIG. 10A, by removing the resist film R by lift-off, the solder layer 16a formed on the resist film R is simultaneously removed. Thus, only the solder layer 16 formed in the pattern opening A of the resist film R can be left. Next, as shown in FIG. 10B, a heat treatment is performed to melt the solder layer 16, and the solder layer 16 is cooled and solidified in a spherical state due to surface tension to form a solder ball having a height of, for example, 60 μm. One bump 16b is formed.
【００４０】次に、半導体ウェーハ（ウェーハ膜厚は例
えば６２０μｍ）をデバイス形成面の反対の面から、機
械研削法、化学的機械研磨法あるいはエッチング法など
により、膜厚が２００μｍ以下（例えば１００μｍ程
度）となるまで半導体ウェーハを薄膜化する。上記の薄
膜化工程としては、まず、上記半導体ウェーハ１０の第
１バンプ１６ｂ形成面の全面に保護テープ４５を貼付
し、例えば図３に示す研削装置において、装置基台上に
保護テープ４５貼付面を下にして半導体ウェーハ１０を
戴置し、例えば、その上側から砥石を２５００ｒｐｍの
回転数で回転させながら、１５０μｍ／分の速度で下方
へ送り、例えば５１０μｍの膜厚分研削し、１１０μｍ
の膜厚の半導体ウェーハとする。このとき、これまでの
半導体ウェーハに半導体チップの回路パターンなどを形
成する工程を経ることにより、通常、半導体ウェーハ１
０の裏面に形成されてしまっているキズを研削除去でき
る。Next, a semiconductor wafer (having a wafer thickness of, for example, 620 μm) is formed to a thickness of 200 μm or less (for example, about 100 μm) from a surface opposite to the device forming surface by a mechanical grinding method, a chemical mechanical polishing method, an etching method, or the like. ) Until the semiconductor wafer becomes thinner. In the thinning step, first, the protective tape 45 is attached to the entire surface of the semiconductor wafer 10 on which the first bumps 16b are formed. For example, in a grinding device shown in FIG. Is placed on the semiconductor wafer 10 with the wafer facing downward. For example, while rotating the grindstone from above at a rotation speed of 2500 rpm, the wafer is sent downward at a speed of 150 μm / min.
A semiconductor wafer having a thickness of At this time, the semiconductor wafer 1 is usually subjected to a process of forming a circuit pattern of a semiconductor chip on the conventional semiconductor wafer.
The scratches formed on the back surface of No. 0 can be removed by grinding.
【００４１】次に、例えば図４に示す化学的機械研磨装
置において、ウェーハキャリア４１に上記保護テープ４
５を貼付した半導体ウェーハ１０を取り付け、例えば、
テーブル（定盤）４２上に設けられた研磨布（クロス）
４３上に、研磨スラリ４４を４０ｍｌ／分の供給速度で
供給しながら、研磨圧力４００ｇ／ｃｍ2 で押圧し、ウ
ェーハキャリア４１を８０ｒｐｍ、テーブルを８０ｒｐ
ｍで回転させ、かつ２ｍｍ／秒の揺動速度で揺動させ、
１０μｍの膜厚分研磨して裏面ポリッシュ仕上げとし、
１００μｍの膜厚の半導体ウェーハ１０とする。このと
き、ポリッシュ研磨仕上げとすることで半導体ウェーハ
１０の裏面の細かなキズ（研削処理時のダメージ）まで
も除去でき、薄膜化しても機械的強度の高いウェーハと
することができる。この後の工程としては、上記半導体
ウェーハから表面保護テープを剥離し、ダイシング工程
により個々の半導体チップに分離して、本実施形態にお
いて実装するベアチップ実装用の半導体チップとする。
上記工程においては、ダイシング工程により個々の半導
体チップに分離した後に、上記のように薄膜化すること
も可能である。Next, for example, in the chemical mechanical polishing apparatus shown in FIG.
5 is attached, for example,
A polishing cloth (cloth) provided on a table (platen) 42
While supplying the polishing slurry 44 onto the substrate 43 at a supply speed of 40 ml / min, the wafer is pressed at a polishing pressure of 400 g / cm 2 , the wafer carrier 41 is rotated at 80 rpm, and the table is rotated at 80 rpm.
m, and swing at a swing speed of 2 mm / sec,
Polished by a thickness of 10 μm to make the back surface polished,
The semiconductor wafer 10 has a thickness of 100 μm. At this time, even the fine scratches (damage during the grinding process) on the back surface of the semiconductor wafer 10 can be removed by polishing and finishing the semiconductor wafer 10, and a wafer having high mechanical strength can be obtained even if it is thinned. As a subsequent step, the surface protection tape is peeled off from the semiconductor wafer and separated into individual semiconductor chips by a dicing step to obtain a bare chip mounting semiconductor chip to be mounted in the present embodiment.
In the above step, it is also possible to separate the semiconductor chips into individual semiconductor chips by a dicing step and then make the semiconductor chips thinner as described above.
【００４２】次に、図５（ａ）に示すように、上記の半
導体チップを可撓性基板２上に実装する。可撓性基板２
は、例えばポリイミドあるいはエポキシ系材料よりなる
５０μｍの膜厚の可撓性基板基材２０の一方の面（第１
面）上において、実装する半導体チップ（１ａ，１ｂ）
の第１バンプ１６ｂの形成位置に対応する位置に形成さ
れた銅などからなるランド（電極）などを含む第１面第
１配線部２１が形成され、さらに可撓性基板基材２０の
他方の面（第２面）上において、第１面第１配線部２１
に接続する第２面第１配線部２４が形成されて構成され
ている。上記の第１バンプ１６ｂと第１配線層２１のラ
ンドを対応させて半導体チップ（１ａ，１ｂ）を可撓性
基板２上にマウントし、共晶はんだ層（不図示）あるい
は第１バンプ自身により第１バンプ１６ｂと第１配線層
２１のランドとを機械的、電気的に接続し、さらに、半
導体チップ（１ａ，１ｂ）と可撓性基板２の間隙部を、
エポキシ樹脂などからなる封止樹脂３により封止する。Next, as shown in FIG. 5A, the above-mentioned semiconductor chip is mounted on the flexible substrate 2. Flexible substrate 2
Is one surface of the flexible substrate 20 having a thickness of 50 μm made of, for example, polyimide or epoxy-based material (the first surface).
Semiconductor chip (1a, 1b) to be mounted on
The first surface first wiring portion 21 including a land (electrode) made of copper or the like formed at a position corresponding to the formation position of the first bump 16b is formed. On the surface (second surface), the first surface first wiring portion 21
The first wiring portion 24 connected to the second surface is formed. The semiconductor chips (1a, 1b) are mounted on the flexible substrate 2 in such a manner that the first bumps 16b correspond to the lands of the first wiring layer 21, and the eutectic solder layers (not shown) or the first bumps themselves are used. The first bumps 16b and the lands of the first wiring layer 21 are mechanically and electrically connected, and the gap between the semiconductor chip (1a, 1b) and the flexible substrate 2 is
It is sealed with a sealing resin 3 made of an epoxy resin or the like.
【００４３】次に、図５（ｂ）に示すように、半導体チ
ップ１ｂの上面に、銅あるいはクロム鋼など金属材料な
どからなる放熱性基板１７を絶縁性ペーストなどにより
固着し、２個の半導体チップ（１ａ，１ｂ）の実装部分
の間における可撓性基板２を湾曲させ、半導体チップ１
ａの上面を放熱性基板１７の半導体チップ１ｂ固着面の
反対側の面に、同様に絶縁性ペーストなどにより固着す
る。以上で、２個の半導体チップ（１ａ，１ｂ）を積層
させた半導体モジュールＭを形成することができる。以
降の工程としては、例えば第２面第１配線部２４に接続
するように、はんだボールなどからなり、例えば３００
μｍ以上の直径を有する第２バンプ２５を形成し、実装
基板基材２０’とその表面に形成された第２配線部２６
とから構成される実装基板２’上に、第２バンプ２５と
第２配線部２６とを対応させてマウントし、不図示の共
晶はんだ層あるいは第２バンプ２５自身により第２バン
プ２５と第２配線部２６とを機械的、電気的に接続し
て、図１に示す電子回路装置を形成することができる。
上記の第２バンプを形成する代わりに、実装基板２’の
第２配線部２６上に予めはんだペースト（クリームはん
だ）を供給しておき、上記半導体モジュールを戴置して
リフローさせることにより同様の構成とすることもでき
る。Next, as shown in FIG. 5B, a heat-radiating substrate 17 made of a metal material such as copper or chromium steel is fixed on the upper surface of the semiconductor chip 1b with an insulating paste or the like, and two semiconductor chips are formed. The flexible substrate 2 between the mounting portions of the chips (1a, 1b) is curved, and the semiconductor chip 1
The upper surface of “a” is fixed to the surface of the heat-radiating substrate 17 opposite to the surface to which the semiconductor chip 1b is fixed, similarly using an insulating paste or the like. Thus, a semiconductor module M in which two semiconductor chips (1a, 1b) are stacked can be formed. The subsequent steps include, for example, solder balls so as to connect to the second surface first wiring portion 24, for example, 300
A second bump 25 having a diameter of at least μm is formed, and a mounting substrate base material 20 ′ and a second wiring portion 26 formed on the surface thereof are formed.
The second bump 25 and the second wiring portion 26 are mounted on the mounting substrate 2 ′ corresponding to each other so as to correspond to each other, and the second bump 25 and the second bump 25 are connected by a eutectic solder layer (not shown) or the second bump 25 itself. By mechanically and electrically connecting the two wiring portions 26, the electronic circuit device shown in FIG. 1 can be formed.
Instead of forming the above-mentioned second bump, a solder paste (cream solder) is supplied in advance on the second wiring portion 26 of the mounting board 2 ′, and the above-mentioned semiconductor module is mounted thereon and reflowed. It can also be configured.
【００４４】第２実施形態 図６は本実施形態に係る電子回路装置の断面図である。
この電子回路装置におけるベアチップ実装用の半導体チ
ップと可撓性基板との接続部は、第１実施形態と同様で
あり、図２にその拡大断面図を示す。本実施形態に係る
電子回路装置は、実質的に第１実施形態の電子回路装置
と同様であるが、可撓性基板基材２０の一方の面（第１
面）上に第１面第１配線部２１が形成され、他方の面
（第２面）上に第２面第１配線部２４が形成された可撓
性基板２の上記一方の面（第１面）上に、第１面第１配
線部２１に接続するように半導体チップ（１ａ，１ｂ）
が実装されており、さらに可撓性基板２の他方の面（第
２面）上であって半導体チップ（１ａ，１ｂ）に対向す
る位置に、第２面第１配線部２４に接続するように半導
体チップ（１ｃ，１ｄ）が実装されていることが異な
る。上記の半導体チップ（１ａ，１ｂ，１ｃ，１ｄ）は
それぞれ２００μｍ以下に薄膜化されている。 Second Embodiment FIG. 6 is a sectional view of an electronic circuit device according to this embodiment.
The connection portion between the semiconductor chip for mounting a bare chip and the flexible substrate in this electronic circuit device is the same as that of the first embodiment, and FIG. 2 shows an enlarged cross-sectional view thereof. The electronic circuit device according to the present embodiment is substantially the same as the electronic circuit device according to the first embodiment, except that one surface (the first
The first surface (first surface) has a first surface first wiring portion 21 formed on the other surface (second surface) and the second surface first wiring portion 24 has been formed on the other surface (second surface). Semiconductor chip (1a, 1b) on the first surface) so as to be connected to the first surface first wiring portion 21.
Is mounted on the other surface (second surface) of the flexible substrate 2 and opposed to the semiconductor chips (1a, 1b) so as to be connected to the second surface first wiring portion 24. Is different in that the semiconductor chips (1c, 1d) are mounted on the semiconductor chip. Each of the semiconductor chips (1a, 1b, 1c, 1d) is thinned to 200 μm or less.
【００４５】上記の半導体チップ（１ｃ，１ｄ）は、半
導体チップ（１ａ，１ｂ）と同様に可撓性基板２上に実
装されている。即ち、半導体チップ（１ｃ，１ｄ）の第
１バンプ１６ｂと第２面第１配線部２４とが対応するよ
うにマウントされ、さらに共晶はんだ層（不図示）ある
いは第１バンプ１６ｂ自身により第１バンプ１６ｂと第
１配線部２４とが機械的、電気的に接続されており、さ
らに、半導体チップ（１ｃ，１ｄ）と可撓性基板２の間
隙部は、エポキシ樹脂などからなる封止樹脂３により封
止されている。The semiconductor chips (1c, 1d) are mounted on the flexible substrate 2 like the semiconductor chips (1a, 1b). That is, the first bump 16b of the semiconductor chip (1c, 1d) and the second surface first wiring portion 24 are mounted so as to correspond to each other, and the first bump 16b is formed by the eutectic solder layer (not shown) or the first bump 16b itself. The bump 16b and the first wiring portion 24 are mechanically and electrically connected, and the gap between the semiconductor chip (1c, 1d) and the flexible substrate 2 is formed by a sealing resin 3 made of epoxy resin or the like. Is sealed.
【００４６】上記の可撓性基板２は半導体チップ（１
ａ，１ｄ）と半導体チップ（１ｂ，１ｃ）の実装部分の
間において湾曲されており、可撓性基板２の一方の面上
に実装された半導体チップ（１ａ，１ｂ）の第１バンプ
１６ｂ形成面の反対側の面同士が、銅あるいはクロム鋼
など金属材料などからなる放熱性基板１７を挟んで対向
するように絶縁性ペーストなどの接着剤層１８により放
熱性基板１７に固着されている。このとき、可撓性基板
２の他方の面上に実装された半導体チップ（１ｃ，１
ｄ）は、それぞれ、図６に示すように最上部および最下
部に配置される。以上のようにして４個の半導体チップ
（１ａ，１ｂ，１ｃ，１ｄ）を積層させた半導体モジュ
ールＭが構成されている。The above-mentioned flexible substrate 2 has a semiconductor chip (1).
a, 1d) and the first bump 16b of the semiconductor chip (1a, 1b), which is curved between the mounting portions of the semiconductor chip (1b, 1c) and mounted on one surface of the flexible substrate 2 The opposite surfaces are fixed to the heat dissipation substrate 17 by an adhesive layer 18 such as an insulating paste so that the surfaces opposite to each other sandwich a heat dissipation substrate 17 made of a metal material such as copper or chrome steel. At this time, the semiconductor chips (1c, 1c) mounted on the other surface of the flexible substrate 2
d) are located at the top and bottom, respectively, as shown in FIG. As described above, the semiconductor module M in which the four semiconductor chips (1a, 1b, 1c, 1d) are stacked.
【００４７】上記の半導体モジュールＭは、例えば半導
体チップ１ｃの実装位置の外周部において形成された第
２面第１配線部２４に接続するように、はんだボールな
どからなり、例えば３００μｍ以上の直径を有する第２
バンプ２５が形成されており、実装基板基材２０’とそ
の表面に形成された第２配線部２６とから構成される実
装基板２’上に、第２バンプ２５と第２配線部２６とが
対応するようにマウントされ、不図示の共晶はんだ層あ
るいは第２バンプ２５自身により第２バンプ２５と第２
配線部２６とが機械的、電気的に接続されて、モジュー
ル形態で実装されている。The above-mentioned semiconductor module M is formed of a solder ball or the like so as to be connected to the second surface first wiring portion 24 formed at the outer peripheral portion of the mounting position of the semiconductor chip 1c, and has a diameter of, for example, 300 μm or more. Having a second
The bumps 25 are formed, and the second bumps 25 and the second wiring portions 26 are formed on the mounting substrate 2 ′ including the mounting substrate base material 20 ′ and the second wiring portions 26 formed on the surface thereof. The second bump 25 is mounted so as to correspond to the second bump 25 by a eutectic solder layer (not shown) or the second bump 25 itself.
The wiring part 26 is mechanically and electrically connected to the wiring part 26 and mounted in a module form.
【００４８】上記の本実施形態の電子回路装置によれ
ば、４個の半導体チップ（１ａ，１ｂ，１ｃ，１ｄ）を
積層させたモジュールとして実装基板上にワイヤボンデ
ィングを用いずに実装されており、デバイスチップ間の
配線長を短縮して、実装基板への接続部のインダクタン
スを低減して高速処理が可能であり、高周波デバイスに
おいても信号遅延の問題を改善できる。また、４個のう
ちの２個の半導体チップ（１ａ，１ｂ）は放熱性基板１
７を介して積層されており、他の２個の半導体チップ
（１ｃ，１ｄ）は他の半導体チップと直接接触しておら
ず、各半導体デバイスからの放熱量を確保して半導体デ
バイスが高温となることを回避することが可能である。
上記の４個の半導体チップ（１ａ，１ｂ，１ｃ，１ｄ）
は２００μｍ以下に薄膜化されているため、上記のよう
にそれらを積層させた半導体モジュールとしても薄膜化
を実現できる。また、第２バンプ２５により半導体モジ
ュールと実装基板の間に生じる空間にも半導体チップ１
ｃを実装しており、余分な空間を排除して最小限の高さ
で効率の良い高密度の３次元実装を実現できる。According to the electronic circuit device of the present embodiment described above, the semiconductor device is mounted on a mounting substrate as a module in which four semiconductor chips (1a, 1b, 1c, 1d) are stacked without using wire bonding. In addition, it is possible to shorten the wiring length between device chips, reduce the inductance of the connection portion to the mounting board, and perform high-speed processing, and also to solve the problem of signal delay even in a high-frequency device. Also, two of the four semiconductor chips (1a, 1b) are heat-dissipating substrates 1
7, the other two semiconductor chips (1c, 1d) are not in direct contact with the other semiconductor chips. Can be avoided.
The above four semiconductor chips (1a, 1b, 1c, 1d)
Is thinned to 200 μm or less, so that a semiconductor module in which they are stacked as described above can also be thinned. Further, the semiconductor chip 1 is also placed in a space created between the semiconductor module and the mounting board by the second bump 25.
c, so that an efficient space can be realized with a minimum height and an efficient high-density three-dimensional mounting.
【００４９】上記の電子回路装置の製造方法について図
面を参照して説明する。各半導体チップの回路パターン
を形成した半導体ウェーハにはんだからなる第１バンプ
１６ｂを形成し、膜厚が２００μｍ以下（例えば１００
μｍ程度）となるまで薄膜化し、さらにダイシング処理
により個々の半導体チップに分割する工程までは、第１
実施形態と同様にして行う。A method for manufacturing the above electronic circuit device will be described with reference to the drawings. A first bump 16b made of solder is formed on a semiconductor wafer on which a circuit pattern of each semiconductor chip is formed, and has a thickness of 200 μm or less (for example, 100 μm or less).
μm) and the first step until the step of dicing into individual semiconductor chips by dicing.
This is performed in the same manner as in the embodiment.
【００５０】次に、図７（ａ）に示すように、上記の半
導体チップを可撓性基板２上に実装する。可撓性基板２
は、例えばポリイミドあるいはエポキシ系材料よりなる
５０μｍの膜厚の可撓性基板基材２０の一方の面（第１
面）上において、実装する半導体チップ（１ａ，１ｂ）
の第１バンプ１６ｂの形成位置に対応する位置に形成さ
れた銅などからなるランド（電極）などを含む第１面第
１配線部２１が形成され、さらに可撓性基板基材２０の
他方の面（第２面）上において、実装する半導体チップ
（１ｃ，１ｄ）の第１バンプ１６ｂの形成位置に対応す
る位置に形成された銅などからなるランド（電極）など
を含み、第１面第１配線部２１に接続する第２面第１配
線部２４が形成されて構成されている。半導体チップ
（１ａ，１ｂ）の第１バンプ１６ｂと第１面第１配線層
２１のランドを対応させて、半導体チップ（１ａ，１
ｂ）を可撓性基板２上にマウントし、共晶はんだ層（不
図示）あるいは第１バンプ自身により第１バンプ１６ｂ
と第１面第１配線層２１のランドとを機械的、電気的に
接続し、さらに、半導体チップ（１ａ，１ｂ）と可撓性
基板２の間隙部を、エポキシ樹脂などからなる封止樹脂
３により封止する。さらに、上記と同様に、半導体チッ
プ（１ｃ，１ｄ）の第１バンプ１６ｂと第２面第１配線
層２４のランドとを機械的、電気的に接続し、さらに、
半導体チップ（１ｃ，１ｄ）と可撓性基板２の間隙部
を、エポキシ樹脂などからなる封止樹脂３により封止す
る。Next, as shown in FIG. 7A, the above-mentioned semiconductor chip is mounted on the flexible substrate 2. Flexible substrate 2
Is one surface of the flexible substrate 20 having a thickness of 50 μm made of, for example, polyimide or epoxy-based material (the first surface).
Semiconductor chip (1a, 1b) to be mounted on
The first surface first wiring portion 21 including a land (electrode) made of copper or the like formed at a position corresponding to the formation position of the first bump 16b is formed. On the surface (second surface), lands (electrodes) made of copper or the like are formed at positions corresponding to the formation positions of the first bumps 16b of the semiconductor chips (1c, 1d) to be mounted. The second surface first wiring portion 24 connected to the one wiring portion 21 is formed. The semiconductor chips (1a, 1b) are made to correspond to the first bumps 16b of the semiconductor chips (1a, 1b) and the lands of the first surface first wiring layer 21.
b) is mounted on the flexible substrate 2, and the first bump 16b is formed by an eutectic solder layer (not shown) or the first bump itself.
And the land of the first surface first wiring layer 21 are mechanically and electrically connected, and the gap between the semiconductor chip (1a, 1b) and the flexible substrate 2 is sealed with a sealing resin made of epoxy resin or the like. Seal with 3. Further, similarly to the above, the first bump 16b of the semiconductor chip (1c, 1d) and the land of the second surface first wiring layer 24 are mechanically and electrically connected, and further,
The gap between the semiconductor chip (1c, 1d) and the flexible substrate 2 is sealed with a sealing resin 3 made of epoxy resin or the like.
【００５１】次に、図７（ｂ）に示すように、半導体チ
ップ１ｂの上面に、銅あるいはクロム鋼など金属材料な
どからなる放熱性基板１７を絶縁性ペーストなどにより
固着し、半導体チップ（１ａ，１ｄ）と半導体チップ
（１ｂ，１ｃ）の実装部分の間における可撓性基板２を
湾曲させ、放熱性基板１７の半導体チップ１ｂ固着面の
反対側の面と半導体チップ１ａの上面とを、上記と同様
に絶縁性ペーストなどにより固着する。以上で、４個の
半導体チップ（１ａ，１ｂ，１ｃ，１ｄ）を積層させた
半導体モジュールＭを形成することができる。以降の工
程としては、例えば可撓性基板２上に形成されている第
２面第１配線部２４に接続するように、はんだボールな
どからなり、例えば３００μｍ以上の直径を有する第２
バンプ２５を形成し、実装基板基材２０’とその表面に
形成された第２配線部２６とから構成されている実装基
板２’上に、第２バンプ２５と第２配線部２６とを対応
させてマウントし、不図示の共晶はんだ層あるいは第２
バンプ２５自身により第２バンプ２５と第２配線部２６
とを機械的、電気的に接続して、図６に示す電子回路装
置を形成することができる。Next, as shown in FIG. 7 (b), a heat dissipating substrate 17 made of a metal material such as copper or chromium steel is fixed on the upper surface of the semiconductor chip 1b with an insulating paste or the like, and the semiconductor chip (1a , 1d) and the mounting portion of the semiconductor chip (1b, 1c), the flexible substrate 2 is curved, and the surface of the heat radiation substrate 17 opposite to the surface on which the semiconductor chip 1b is fixed and the upper surface of the semiconductor chip 1a are Similar to the above, it is fixed with an insulating paste. Thus, the semiconductor module M in which the four semiconductor chips (1a, 1b, 1c, 1d) are stacked can be formed. Subsequent processes include, for example, a solder ball or the like having a diameter of 300 μm or more so as to be connected to the second surface first wiring portion 24 formed on the flexible substrate 2.
The bumps 25 are formed, and the second bumps 25 and the second wiring portions 26 correspond to each other on the mounting substrate 2 ′ including the mounting substrate base material 20 ′ and the second wiring portions 26 formed on the surface thereof. And mount the eutectic solder layer (not shown)
The second bump 25 and the second wiring portion 26 are formed by the bump 25 itself.
Are mechanically and electrically connected to each other to form the electronic circuit device shown in FIG.
【００５２】本発明により積層して実装する半導体装置
としては、ＭＯＳトランジスタ系半導体装置、バイポー
ラ系半導体装置、ＢｉＣＭＯＳ系半導体装置、ロジック
とメモリを搭載した半導体装置など、半導体装置であれ
ば何でも適用可能である。As the semiconductor device to be stacked and mounted according to the present invention, any semiconductor device such as a MOS transistor semiconductor device, a bipolar semiconductor device, a BiCMOS semiconductor device, a semiconductor device having a logic and a memory mounted thereon can be applied. It is.
【００５３】本発明の半導体モジュールおよび電子回路
装置は上記の実施の形態に限定されない。例えば、半導
体ウェーハの薄膜化工程など、各プロセスの条件や材料
の種類や膜厚などは上記の実施の形態で説明した内容に
限らない。上記の半導体モジュールを実装基板上に実装
するために、半導体モジュールにはんだボールからなる
第２バンプを形成しているが、金スタッドバンプ、銅メ
ッキバンプ、異方性導電膜、導電性ペーストなどの種々
の接合手段を用いて実装してもよい。また、例えば第２
実施形態において、第２面第１配線部に接続する半導体
チップとしては１個でもよい。また、半導体ウェーハ上
への第１バンプの形成方法としては、真空蒸着により成
膜とリフトオフによるパターニングによる方法により説
明したが、スクリーン印刷法、電解メッキ法、はんだボ
ール転写法など、種々の方法を用いることができる。そ
の他、本発明の要旨を逸脱しない範囲で種々の変更が可
能である。The semiconductor module and the electronic circuit device of the present invention are not limited to the above embodiment. For example, the conditions of each process such as a thinning process of a semiconductor wafer, types of materials, and film thicknesses are not limited to those described in the above embodiment. In order to mount the above-described semiconductor module on a mounting board, a second bump made of a solder ball is formed on the semiconductor module. However, gold stud bumps, copper plating bumps, anisotropic conductive films, conductive pastes, etc. You may implement using various joining means. Also, for example, the second
In the embodiment, the number of semiconductor chips connected to the second surface first wiring portion may be one. The method of forming the first bump on the semiconductor wafer has been described by a method of forming a film by vacuum evaporation and a patterning by lift-off. However, various methods such as a screen printing method, an electrolytic plating method, and a solder ball transfer method are used. Can be used. In addition, various changes can be made without departing from the gist of the present invention.
【００５４】[0054]
【発明の効果】上記のように、本発明の半導体モジュー
ルおよびそれを実装した電子回路装置によれば、ワイヤ
ボンディングを用いずに実装されており、半導体チップ
間の配線長を短縮し、実装基板への接続部のインダクタ
ンスを低減して高速処理が可能であり、高周波デバイス
においても信号遅延の問題を改善でき、各半導体デバイ
スからの放熱量を確保して半導体デバイスが高温となる
ことを回避することが可能で、さらに各半導体チップを
積層させた半導体モジュールとしても薄膜化を実現で
き、効率の良い高密度の３次元実装を実現できる。本発
明の半導体モジュールを実装して組み立てられる最終的
な製品デバイスとして、ＩＣカード、携帯電話あるいは
ＰＤＡなどの携帯電子機器の更なる高機能化や小型化を
実現できる。As described above, according to the semiconductor module of the present invention and the electronic circuit device on which the semiconductor module is mounted, the semiconductor module is mounted without using wire bonding. High-speed processing is possible by reducing the inductance of the connection part to the semiconductor device, the problem of signal delay can be improved even in high-frequency devices, and the heat dissipation from each semiconductor device is secured to prevent the semiconductor device from becoming high temperature. It is possible to realize a thinned semiconductor module in which semiconductor chips are stacked, and to realize efficient and high-density three-dimensional mounting. As a final product device that can be assembled by mounting the semiconductor module of the present invention, it is possible to further enhance the functions and reduce the size of portable electronic devices such as IC cards, mobile phones, and PDAs.
【図１】図１は第１実施形態に係る電子回路装置の断面
図である。FIG. 1 is a sectional view of an electronic circuit device according to a first embodiment.
【図２】図２は第１および第２実施形態に係る電子回路
装置における半導体チップと可撓性基板との接続部の拡
大断面図である。FIG. 2 is an enlarged cross-sectional view of a connection portion between a semiconductor chip and a flexible substrate in the electronic circuit devices according to the first and second embodiments.
【図３】図３は研削装置の概略構成を示す斜視図であ
る。FIG. 3 is a perspective view showing a schematic configuration of a grinding device.
【図４】図４は化学的機械研磨装置の概略構成を示す図
である。FIG. 4 is a diagram showing a schematic configuration of a chemical mechanical polishing apparatus.
【図５】図５は第１実施形態に係る電子回路装置の製造
方法の製造工程を示す断面図であり、（ａ）は半導体チ
ップを可撓性基板上に実装する工程まで、（ｂ）は放熱
性基板の両面上に２個の半導体チップの上面を固着する
工程までを示す。FIGS. 5A and 5B are cross-sectional views illustrating a manufacturing process of a method of manufacturing an electronic circuit device according to the first embodiment. FIG. 5A illustrates a process of mounting a semiconductor chip on a flexible substrate, and FIG. Shows the process up to the step of fixing the upper surfaces of the two semiconductor chips on both surfaces of the heat dissipation substrate.
【図６】図６は第２実施形態に係る電子回路装置の断面
図である。FIG. 6 is a sectional view of an electronic circuit device according to a second embodiment.
【図７】図７は第２実施形態に係る電子回路装置の製造
方法の製造工程を示す断面図であり、（ａ）は半導体チ
ップを可撓性基板上に実装する工程まで、（ｂ）は放熱
性基板の両面上に２個の半導体チップの上面を固着する
工程までを示す。FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a method of manufacturing an electronic circuit device according to a second embodiment. FIG. 7A illustrates a process until a semiconductor chip is mounted on a flexible substrate, and FIG. Shows the process up to the step of fixing the upper surfaces of the two semiconductor chips on both surfaces of the heat dissipation substrate.
【図８】図８は第１従来例に係る電子回路装置の断面図
である。FIG. 8 is a sectional view of an electronic circuit device according to a first conventional example.
【図９】図９は本発明および第１従来例に係る半導体装
置の製造方法の製造工程を示す断面図であり、（ａ）は
導電膜（ＢＬＭ膜）の形成工程まで、（ｂ）はレジスト
膜の形成工程まで、（ｃ）ははんだ層の堆積工程までを
示す。9A and 9B are cross-sectional views illustrating manufacturing steps of a method of manufacturing a semiconductor device according to the present invention and the first conventional example, wherein FIG. 9A illustrates up to the step of forming a conductive film (BLM film), and FIG. (C) shows up to the step of forming a resist film and up to the step of depositing a solder layer.
【図１０】図１０は図９の続きの工程を示し、（ａ）は
リフトオフによるレジスト膜上のはんだ層の除去工程ま
で、（ｂ）はリフローによりはんだボールバンプの形成
工程までを示す。FIG. 10 shows a step subsequent to that of FIG. 9; (a) shows a step of removing a solder layer on a resist film by lift-off; and (b) shows a step of forming a solder ball bump by reflow.
【図１１】図１１は第２従来例に係る電子回路装置の断
面図である。FIG. 11 is a sectional view of an electronic circuit device according to a second conventional example.
【図１２】図１２（ａ）は第３従来例に係る電子回路装
置の平面図であり、（ｂ）は（ａ）中のＹ−Ｙ’におけ
る断面図である。12A is a plan view of an electronic circuit device according to a third conventional example, and FIG. 12B is a cross-sectional view taken along the line YY ′ in FIG.
１（１ａ，１ｂ，１ｃ，１ｄ）…ベアチップ実装用半導
体チップ、２…可撓性基板、２’…実装基板、３…封止
樹脂、１０…半導体ウェーハ、１０’（１０ａ’，１０
ｂ’，１０ｃ’１０ｄ’）…半導体チップ、１１（１１
ａ，１１ｂ，１１ｃ）…（パッド）電極、１２，１３…
表面保護膜、１４…導電膜（ＢＬＭ膜）、１６，１６ａ
…はんだ層、１６ｂ…（第１）バンプ、１７…放熱性基
板、１８…接着剤層、１９…共晶はんだ層、２０…可撓
性基板基材、２０’…実装基板基材、２１…第１面第１
配線部、２４…第２面第１配線部、２５…第２バンプ、
２６…（第２）配線部、２７…ワイヤボンディング、４
０…砥石、４１…ウェーハキャリア、４２…テーブル、
４３…研磨布、４４…研磨スラリ、４５…保護テープ、
Ｒ…レジスト膜、Ａ…開口部、Ｍ…半導体モジュール、
Ｘ…切欠部。1 (1a, 1b, 1c, 1d): semiconductor chip for mounting bare chip, 2: flexible substrate, 2 ': mounting substrate, 3: sealing resin, 10: semiconductor wafer, 10' (10a ', 10)
b ′, 10c′10d ′)... semiconductor chip, 11 (11
a, 11b, 11c) ... (pad) electrodes, 12, 13, ...
Surface protective film, 14 ... conductive film (BLM film), 16, 16a
... solder layer, 16b (first) bump, 17 ... heat dissipation substrate, 18 ... adhesive layer, 19 ... eutectic solder layer, 20 ... flexible substrate base, 20 '... mounting substrate base, 21 ... First side first
Wiring part, 24 ... second surface first wiring part, 25 ... second bump,
26: (second) wiring portion, 27: wire bonding, 4
0: whetstone, 41: wafer carrier, 42: table,
43: polishing cloth, 44: polishing slurry, 45: protective tape,
R: resist film, A: opening, M: semiconductor module,
X: Notch.
Claims (12)
する第１突起電極を有し、前記第１突起電極形成面側か
ら前記配線部に接続するように前記可撓性基板の一方の
面上に実装された第１半導体装置および第２半導体装置
と、 前記第１半導体装置の上面に固着された放熱性基板とを
有し、 前記第１半導体装置と前記第２半導体装置の実装部分の
間における前記可撓性基板が湾曲しており、前記第２半
導体装置の上面が前記放熱性基板の前記第１半導体装置
固着面の反対側の面に固着されている半導体モジュー
ル。1. A flexible substrate having wiring portions on both surfaces, a circuit pattern of a semiconductor device, and a first protruding electrode connected to the circuit pattern, wherein the wiring portion is formed from the first protruding electrode forming surface side. A first semiconductor device and a second semiconductor device mounted on one surface of the flexible substrate so as to be connected to the flexible substrate; and a heat dissipation substrate fixed to an upper surface of the first semiconductor device, The flexible substrate between the mounting portions of the first semiconductor device and the second semiconductor device is curved, and the upper surface of the second semiconductor device is on the opposite side of the heat dissipation substrate to the first semiconductor device fixing surface. Semiconductor module fixed to the surface of
るために、前記配線部に接続するように第２突起電極が
形成されている請求項１記載の半導体モジュール。2. The semiconductor module according to claim 1, wherein a second protruding electrode is formed so as to be connected to said wiring portion in order to mount said semiconductor module on a mounting board.
装置がそれぞれ２００μｍ以下の高さである請求項１記
載の半導体モジュール。3. The semiconductor module according to claim 1, wherein each of said first semiconductor device and said second semiconductor device has a height of 200 μm or less.
板の他方の面上に第３半導体装置が実装されている請求
項１記載の半導体モジュール。4. The semiconductor module according to claim 1, wherein a third semiconductor device is mounted on the other surface of the flexible substrate so as to be connected to the wiring portion.
るために、前記配線部に接続するように第２突起電極が
形成されており、 前記第１、前記第２および第３半導体装置の高さがそれ
ぞれ２００μｍ以下であり、 前記第２突起電極の高さが３００μｍ以上である請求項
４記載の半導体モジュール。5. A second protruding electrode is formed so as to be connected to the wiring portion in order to mount the semiconductor module on a mounting board, and heights of the first, second and third semiconductor devices are provided. 5. The semiconductor module according to claim 4, wherein each of the heights is 200 μm or less, and the height of the second projection electrode is 300 μm or more.
の上面が、絶縁性接着剤により前記放熱性基板に固着さ
れている請求項１記載の半導体モジュール。6. The semiconductor module according to claim 1, wherein respective upper surfaces of said first and second semiconductor devices are fixed to said heat dissipation substrate with an insulating adhesive.
半導体装置の回路パターンと、前記回路パターンに接続
する第１突起電極を有し、前記第１突起電極形成面側か
ら前記第１配線部に接続するように前記可撓性基板の一
方の面上に実装された第１半導体装置および第２半導体
装置と、前記第１半導体装置の上面に固着された放熱性
基板とを有し、前記第１半導体装置と前記第２半導体装
置の実装部分の間における前記可撓性基板が湾曲してお
り、前記第２半導体装置の上面が前記放熱性基板の前記
第１半導体装置固着面の反対側の面に固着されている半
導体モジュールと、 第２配線部を有する実装基板とを有し、 前記第１配線部と前記第２配線部が接続して、前記半導
体モジュールが前記実装基板上に実装されている電子回
路装置。7. A flexible substrate having first wiring portions on both sides,
A first protruding electrode connected to the circuit pattern, the first protruding electrode being connected to the circuit pattern, and being connected to the first wiring portion from the first protruding electrode forming surface side on one surface of the flexible substrate; A first semiconductor device and a second semiconductor device mounted on the first semiconductor device, and a heat dissipating substrate fixed to an upper surface of the first semiconductor device, wherein a portion between the first semiconductor device and the mounting portion of the second semiconductor device is provided. A semiconductor module in which the flexible substrate is curved, and an upper surface of the second semiconductor device is fixed to a surface of the heat radiation substrate opposite to the first semiconductor device fixing surface; An electronic circuit device, comprising: a mounting substrate having the first wiring unit and the second wiring unit connected to each other, and the semiconductor module is mounted on the mounting substrate.
起電極により接続されている請求項７記載の電子回路装
置。8. The electronic circuit device according to claim 7, wherein said first wiring portion and said second wiring portion are connected by a second protruding electrode.
装置がそれぞれ２００μｍ以下の高さである請求項７記
載の電子回路装置。9. The electronic circuit device according to claim 7, wherein each of said first semiconductor device and said second semiconductor device has a height of 200 μm or less.
撓性基板の他方の面上に第３半導体装置が実装されてい
る請求項７記載の電子回路装置。10. The electronic circuit device according to claim 7, wherein a third semiconductor device is mounted on the other surface of said flexible substrate so as to be connected to said first wiring portion.
突起電極により接続されており、 前記第１、前記第２および第３半導体装置の高さがそれ
ぞれ２００μｍ以下であり、 前記第２突起電極の高さが３００μｍ以上である請求項
１０記載の電子回路装置。11. The semiconductor device according to claim 1, wherein said first wiring portion and said second wiring portion are formed of a second wiring portion.
11. The electronic circuit according to claim 10, wherein the first, second, and third semiconductor devices are connected to each other by a protruding electrode, the height of each of the first, second, and third semiconductor devices is 200 μm or less, and the height of the second protruding electrode is 300 μm or more. apparatus.
れの上面が、絶縁性接着剤により前記放熱性基板に固着
されている請求項７記載の電子回路装置。12. The electronic circuit device according to claim 7, wherein respective upper surfaces of said first and second semiconductor devices are fixed to said heat-radiating substrate with an insulating adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34805999A JP4135284B2 (en) | 1999-12-07 | 1999-12-07 | Semiconductor module and electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34805999A JP4135284B2 (en) | 1999-12-07 | 1999-12-07 | Semiconductor module and electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001168268A true JP2001168268A (en) | 2001-06-22 |
| JP4135284B2 JP4135284B2 (en) | 2008-08-20 |
Family
ID=18394475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34805999A Expired - Fee Related JP4135284B2 (en) | 1999-12-07 | 1999-12-07 | Semiconductor module and electronic circuit device |
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| Country | Link |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007521636A (en) * | 2003-09-30 | 2007-08-02 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Flexible stacked chip assembly and method of forming the same |
| US8076772B2 (en) | 2007-06-25 | 2011-12-13 | Samsung Electronics Co., Ltd. | Printed circuit board, memory module having the same and fabrication method thereof |
| US8120921B2 (en) * | 2007-07-19 | 2012-02-21 | Nec Corporation | Device having electronic components mounted therein and method for manufacturing such device |
| WO2013153920A1 (en) * | 2012-04-11 | 2013-10-17 | 住友電気工業株式会社 | Semiconductor device |
| WO2022249310A1 (en) * | 2021-05-26 | 2022-12-01 | 三菱電機株式会社 | Microwave module and antenna apparatus |
-
1999
- 1999-12-07 JP JP34805999A patent/JP4135284B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007521636A (en) * | 2003-09-30 | 2007-08-02 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Flexible stacked chip assembly and method of forming the same |
| US8076772B2 (en) | 2007-06-25 | 2011-12-13 | Samsung Electronics Co., Ltd. | Printed circuit board, memory module having the same and fabrication method thereof |
| US8120921B2 (en) * | 2007-07-19 | 2012-02-21 | Nec Corporation | Device having electronic components mounted therein and method for manufacturing such device |
| WO2013153920A1 (en) * | 2012-04-11 | 2013-10-17 | 住友電気工業株式会社 | Semiconductor device |
| WO2022249310A1 (en) * | 2021-05-26 | 2022-12-01 | 三菱電機株式会社 | Microwave module and antenna apparatus |
| JPWO2022249310A1 (en) * | 2021-05-26 | 2022-12-01 | ||
| JP7412644B2 (en) | 2021-05-26 | 2024-01-12 | 三菱電機株式会社 | antenna device |
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| Publication number | Publication date |
|---|---|
| JP4135284B2 (en) | 2008-08-20 |
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