WO2011148445A1 - Semiconductor device and process for production thereof - Google Patents

Semiconductor device and process for production thereof Download PDF

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Publication number
WO2011148445A1
WO2011148445A1 PCT/JP2010/007014 JP2010007014W WO2011148445A1 WO 2011148445 A1 WO2011148445 A1 WO 2011148445A1 JP 2010007014 W JP2010007014 W JP 2010007014W WO 2011148445 A1 WO2011148445 A1 WO 2011148445A1
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Prior art keywords
substrate
semiconductor device
fine particles
conductive fine
electrode
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PCT/JP2010/007014
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French (fr)
Japanese (ja)
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青井信雄
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パナソニック株式会社
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Publication of WO2011148445A1 publication Critical patent/WO2011148445A1/en

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip-chip stacking, a chip-wafer stacking or a wafer-wafer stacking semiconductor device and a manufacturing method thereof.
  • the wiring area is expanded by three-dimensionally stacking semiconductor integrated circuit devices, thereby increasing the wiring cross-sectional area and shortening the wiring length. That is, it is possible to improve performance while increasing the degree of integration.
  • metal-metal bonding is indispensable between the electrode terminals of each substrate for electrical connection between the substrates.
  • a method of forming a metal-metal joint by thermocompression bonding of electrode terminals in chip-chip lamination, chip-wafer lamination, or wafer-wafer lamination is used for joining the metals constituting each electrode terminal.
  • Such a three-dimensional integrated circuit device is generally manufactured as follows.
  • a plurality of transistors are formed on the main surface (front surface) of the silicon substrate.
  • a through electrode forming hole is formed and copper serving as a through electrode is buried, and then a wiring layer is further formed on the interlayer insulating film.
  • CMP chemical mechanical polishing
  • the back surface side electrode terminal of this chip is thermocompression-bonded to the front surface side electrode terminal of the other chip separately manufactured, thereby stacking the substrates through the through electrodes (chip-chip stacking, chip-wafer stacking).
  • wafer-wafer stacking is performed (see, for example, Non-Patent Document 1).
  • the above-described conventional three-dimensional integration technique has a problem in that poor bonding occurs between the electrode terminals of each substrate.
  • an object of the present invention is to provide a three-dimensional integration technique that can prevent a bonding failure between electrode terminals of each substrate.
  • the inventors of the present application made various studies on the cause of bonding failure between the electrode terminals of each substrate in the conventional three-dimensional integration technology. Obtained.
  • FIG. 4 shows a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique.
  • a through electrode 101 is formed in a first substrate 100 having an element formation surface (front surface) 100a and an opposite surface (back surface) 100b.
  • a transistor 102 is formed over the surface 100 a of the first substrate 100, and a wiring layer 103 having a multilayer wiring electrically connected to the transistor 102 and the through electrode 101 is formed.
  • the bottom portion of the through electrode 101 serving as the back surface side electrode terminal is exposed.
  • the first substrate 100 includes a second substrate 200 having an element formation surface (front surface) 200a and an opposite surface (back surface) 200b, a back surface 100 of the first substrate 100, and a front surface 200a of the second substrate 200. They are stacked so as to face each other.
  • a transistor 201 is formed over the surface 200 a of the second substrate 200, and a wiring layer 202 having a multilayer wiring electrically connected to the transistor 201 is formed.
  • an electrode pad 203 is formed that is connected to the bottom portion of the through electrode 101 serving as the back surface side electrode terminal of the first substrate 100.
  • the through electrode that is, the conductive material embedded in the through hole
  • the through electrode terminal is exposed by using grinding, CMP, dry etching, etc.
  • the height of the back-side electrode terminal (exposed end portion of the through electrode) varies in the plane of the substrate (for example, wafer).
  • This height variation is due to variations in the thickness of the substrate itself, variations in the resist pattern dimensions in the lithography process when forming the through electrode, and variations in the etching rate in the wafer surface due to variations in the etching rate during dry etching. This occurs due to variations in the height of the exposed end itself.
  • the bottom surface of the through electrode 101 of the first substrate 100 and the top surface of the electrode pad 203 of the second substrate 200 are parallel to each other due to the thickness variation or warpage of the substrate in the wafer surface. Therefore, the distance between the bottom surface of the through electrode 101 (the bottom surface of the back-side electrode terminal) and the top surface of the electrode pad 203 varies within the wafer surface.
  • the inventor of the present application in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, has electrode terminals caused by variations in electrode terminal height, substrate thickness variation, substrate warpage, and the like.
  • the inventors have conceived the following invention capable of preventing poor bonding at the time of pressure bonding.
  • a first semiconductor device includes a first substrate, a wiring formed on the first substrate, an insulating film formed on the first substrate so as to cover the wiring,
  • the insulating film includes an opening formed so that the wiring is exposed, and a first electrode terminal formed in the opening and made of a plurality of conductive fine particles.
  • the electrode terminal is constituted by the conductive fine particle group filled in the opening of the insulating film on the substrate. Therefore, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, in other words, depending on the insertion depth of the conductor (electrode terminal of another substrate) inserted from above the opening into the opening, The electrode terminals are joined to each other while the conductor fine particle group is deformed as a buffer material according to the magnitude of the pressure received from the electrode terminals of the other substrate.
  • the electrode terminals in the chip or wafer due to deformation of the conductive fine particle group.
  • the two can be reliably bonded to each other.
  • each surface of the plurality of conductive fine particles may be coated with an organic material. In this way, since the oxidation of each conductive fine particle can be suppressed, it is possible to prevent an increase in the resistance of the electrode terminal composed of the conductive fine particle group.
  • the plurality of conductive fine particles may have an average particle size of 50 nm or less.
  • the conductive fine particles can be melted and bonded to the electrode terminals of another substrate in a low temperature process of about 350 ° C. or lower, so that the bonding between the electrode terminals can be reduced while reducing damage to the semiconductor device. Strength can be increased.
  • the particle diameter of the majority of the plurality of conductive fine particles is about 50 nm or less, the above-described effects can be obtained.
  • the plurality of conductive fine particles may include conductive fine particles having a particle diameter exceeding 50 nm.
  • the average particle diameter of the plurality of conductive fine particles may be about 40 nm or less in order to melt the conductive fine particles in a low temperature process of about 250 ° C. or less.
  • the majority of the plurality of conductor fine particles may have a particle diameter of about 40 nm or less, and the plurality of conductor fine particles may include conductor fine particles having a particle diameter exceeding 40 nm.
  • the above relationship between the particle size and the process temperature is for the case where the conductive fine particles are copper fine particles, but the same tendency (grains) can be obtained even for fine particles of other metals such as gold and silver. A decrease in melting point accompanying the refinement of the diameter is observed.
  • the plurality of conductive fine particles may be made of a transition metal.
  • the plurality of conductive fine particles may be made of gold, silver or copper.
  • the first semiconductor device further includes a second substrate having a second electrode terminal protruding from the front surface or the back surface, wherein the first substrate and the second substrate are the first substrate and the second substrate.
  • the electrode terminal and the second electrode terminal are stacked so as to be connected, and the second electrode terminal deforms the shape of the aggregate of the plurality of conductive fine particles to be the first electrode terminal. And may be inserted into the opening. In this way, it is possible to obtain a three-dimensional integrated semiconductor device that can prevent poor bonding between the electrode terminals of each substrate.
  • the second electrode terminal may be a part of the through electrode formed on the second substrate. In this way, further high integration, high functionality, and high speed of the semiconductor device can be realized.
  • a second semiconductor device includes a first substrate, a wiring formed on the first substrate, an insulating film formed on the first substrate so as to cover the wiring, A plurality of openings formed in the insulating film so that the wiring is exposed; a plurality of first electrode terminals formed in the plurality of openings and made of a plurality of conductive fine particles; and a surface Or a second substrate having a plurality of second electrode terminals protruding from the back surface, wherein the first substrate and the second substrate include the plurality of first electrode terminals and the plurality of second electrodes.
  • the plurality of second electrode terminals are deformed in the shape of the aggregate of the plurality of conductive fine particles that respectively become the plurality of first electrode terminals. Inserted into the plurality of openings. The insertion depth of the plurality of second electrode terminals are different from each other.
  • the first electrode terminal is constituted by the conductive fine particle group filled in the insulating film opening on the first substrate.
  • the conductive fine particle group is deformed as a buffer material, and the electrode terminal Join each other. Accordingly, even when the height of the second electrode terminal is varied, or when the substrate is varied in thickness, warpage, or the like, the electrode terminals are deformed in the chip or wafer due to deformation of the conductive fine particle group. Can be reliably bonded.
  • the first method for manufacturing a semiconductor device includes a step (a) of forming a wiring on a first substrate and a step of forming an insulating film on the first substrate so as to cover the wiring ( b), a step (c) of forming an opening in the insulating film so that the wiring layer is exposed, and a step of forming a first electrode terminal made of a plurality of conductive fine particles in the opening ( d).
  • the electrode terminal is composed of the conductive fine particle group filled in the insulating film opening on the substrate. Therefore, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, in other words, depending on the insertion depth of the conductor (electrode terminal of another substrate) inserted from above the opening into the opening, The electrode terminals are joined to each other while the conductor fine particle group is deformed as a buffer material according to the magnitude of the pressure received from the electrode terminals of the other substrate.
  • the electrode terminals in the chip or wafer due to deformation of the conductive fine particle group.
  • the two can be reliably bonded to each other.
  • the surface of each of the plurality of conductive fine particles may be coated with an organic material. In this way, since the oxidation of each conductive fine particle can be suppressed, it is possible to prevent an increase in the resistance of the electrode terminal composed of the conductive fine particle group.
  • the plurality of conductor fine particles may have an average particle size of 50 nm or less.
  • the conductive fine particles can be melted and bonded to the electrode terminals of another substrate in a low temperature process of about 350 ° C. or lower, so that the bonding between the electrode terminals can be reduced while reducing damage to the semiconductor device. Strength can be increased.
  • the particle diameter of the majority of the plurality of conductive fine particles is about 50 nm or less, the above-described effects can be obtained.
  • the plurality of conductive fine particles may include conductive fine particles having a particle diameter exceeding 50 nm.
  • the average particle diameter of the plurality of conductive fine particles may be about 40 nm or less in order to melt the conductive fine particles in a low temperature process of about 250 ° C. or less.
  • the majority of the plurality of conductor fine particles may have a particle diameter of about 40 nm or less, and the plurality of conductor fine particles may include conductor fine particles having a particle diameter exceeding 40 nm.
  • the above relationship between the particle size and the process temperature is for the case where the conductive fine particles are copper fine particles, but the same tendency (grains) can be obtained even for fine particles of other metals such as gold and silver. A decrease in melting point accompanying the refinement of the diameter is observed.
  • the plurality of conductive fine particles may be made of a transition metal.
  • the plurality of conductive fine particles may be made of gold, silver, or copper.
  • the plurality of conductive fine particles are deposited in a layer on the insulating film including the inside of the opening, and then the outside of the opening is formed.
  • a step of removing the plurality of conductive fine particles may be included.
  • a step (e) of preparing a second substrate having a second electrode terminal protruding from the front surface or the back surface, the first substrate and the second substrate A step (f) of laminating a substrate so that the first electrode terminal and the second electrode terminal are connected, and the step (f) is the first electrode terminal.
  • a step of deforming the shape of the aggregate of the plurality of conductive fine particles and inserting the second electrode terminal into the opening may be included. In this way, it is possible to obtain a three-dimensional integrated semiconductor device that can prevent poor bonding between the electrode terminals of each substrate.
  • the second electrode terminal may be a part of the through electrode formed on the second substrate.
  • the step (f) may include a step of melting the plurality of conductive fine particles by heat treatment and joining the second conductive electrode to the second electrode terminal. If it does in this way, the joint strength of electrode terminals can be strengthened.
  • the second method for manufacturing a semiconductor device includes a step (a) of forming a wiring on a first substrate and a step of forming an insulating film on the first substrate so as to cover the wiring ( b), a step (c) of forming a plurality of openings in the insulating film so as to expose the wiring layer; and a plurality of first electrodes made of a plurality of conductive fine particles in the plurality of openings.
  • a step (d) of forming a terminal a step (e) of preparing a second substrate having a plurality of second electrode terminals protruding from the front or back surface, the first substrate and the second substrate, A step (f) of stacking the plurality of first electrode terminals and the plurality of second electrode terminals so that the plurality of first electrode terminals are connected to each other.
  • the plurality of second electrodes are deformed by deforming the shape of the aggregate of the plurality of conductive fine particles to be respectively Comprising the step of inserting the child into the plurality of openings, the insertion depth of the plurality of second electrode terminals of the plurality of the openings are different from each other.
  • the first electrode terminal is constituted by the conductive fine particle group filled in the insulating film opening on the first substrate.
  • the conductive fine particle group is deformed as a buffer material, The electrode terminals are joined together. Accordingly, even when the height of the second electrode terminal is varied, or when the substrate is varied in thickness, warpage, or the like, the electrode terminals are deformed in the chip or wafer due to deformation of the conductive fine particle group. Can be reliably bonded.
  • the semiconductor device and the manufacturing method thereof in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, it is caused by height variations of electrode terminals, substrate thickness variations, substrate warpage, and the like. Since the bonding failure at the time of crimping between the electrode terminals can be prevented, a highly reliable three-dimensional integrated semiconductor device can be provided with a high yield.
  • FIG. 1A to 1D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to an embodiment.
  • 2A to 2C are diagrams for explaining the process shown in FIG. 1C in detail.
  • FIG. 3A is a diagram showing a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique as a comparative example
  • FIG. 3B is a semiconductor according to the embodiment. It is a figure which shows the cross-sectional structure of the semiconductor device by which a board
  • FIG. 4 is a diagram showing a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique.
  • FIG. 1A to 1D are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to the present embodiment.
  • a first substrate 1 having an element formation surface (front surface) 1a and an opposite surface (back surface) 1b and made of, for example, silicon is prepared.
  • the wiring layer 2 having a multilayer wiring electrically connected to the transistor 6 through the contact 7 is formed.
  • an insulating film 3 is formed on the wiring layer 2.
  • an opening 4 is formed in the insulating film 3 so that a part of the lower wiring layer 2 (specifically, the uppermost layer wiring) is exposed.
  • the electrode terminal 9 is formed by filling the opening 4 with a plurality of conductive fine particles 5 made of, for example, copper.
  • the opening 4 is formed so that a part of the lower wiring layer 2 (specifically, the uppermost wiring) is exposed to the insulating film 3 by using, for example, a dry etching method.
  • an organic solvent containing a large number of conductive fine particles 5 made of, for example, copper is applied onto the insulating film 3 including the inside of the opening 4 by using a spin coating method.
  • the diameter (particle diameter) of the conductive fine particles 5 is, for example, about 0.1 nm or more and less than about 1 ⁇ m.
  • a first heat treatment is performed at a relatively low temperature, for example, about 150 to 200 ° C. for about 10 minutes to volatilize and remove the solvent and organic components on the insulating film 3.
  • a relatively low temperature for example, about 150 to 200 ° C. for about 10 minutes to volatilize and remove the solvent and organic components on the insulating film 3.
  • a relatively low temperature for example, about 150 to 200 ° C. for about 10 minutes to volatilize and remove the solvent and organic components on the insulating film 3.
  • a relatively low temperature for example, about 150 to 200 ° C. for about 10 minutes to volatilize and remove the solvent and organic components on the insulating film 3.
  • a relatively low temperature for example, about 150 to 200 ° C. for about 10 minutes to volatilize and remove the solvent and organic components on the insulating film 3.
  • FIG. 2C the conductive fine particles 5 deposited on the outside of the opening 4 are removed by polishing using, for example, a CMP method, so that the conductive
  • a second substrate 51 having an element formation surface (front surface) 51a and an opposite surface (back surface) 51b and made of, for example, silicon is prepared.
  • a through electrode 52 is formed in the second substrate 51.
  • the side wall surface of the through electrode 52 is covered with an insulating film 53.
  • a transistor 54 is formed, and a wiring layer 56 having a multilayer wiring electrically connected to the transistor 54 through a contact 55 is formed. From the back surface 51b of the 2nd board
  • the first substrate 1 and the second substrate 51 so that the protruding portion of the through electrode 52 faces the opening 4 of the first substrate 1, that is, the electrode terminal 9 made of an aggregate of the conductive fine particles 5. And press and press the substrates together.
  • the bottom of the through electrode 52 exposed on the back surface 51 b of the second substrate 51 is inserted into the opening 4 of the insulating film 3 formed on the first substrate 1, and the opening 4 is inserted into the opening 4.
  • the shape of the aggregate of the conductive fine particles 5 filled is changed.
  • the second heat treatment is performed at a higher temperature than the first heat treatment (for example, a temperature of about 200 to 250 ° C.) for about 30 minutes, for example.
  • the electrode terminal 9 is composed of the aggregate of the conductive fine particles 5 filled in the opening 4 of the insulating film 3 on the first substrate 1, the electrode terminal of the second substrate 51 Depending on the insertion depth in the opening 4 of the (exposed bottom portion of the through electrode 52), in other words, depending on the magnitude of the pressure received from the exposed bottom portion of the through electrode 52, the aggregate of the conductive fine particles 5 is the buffer material. The electrode terminals are joined while being deformed.
  • the electrode terminals can be reliably bonded to each other in the chip or the wafer.
  • the electrical connection between the through electrode 52 and the wiring layer 2 of the first substrate 1 is improved, a highly reliable three-dimensional integrated semiconductor device can be provided with a high yield.
  • FIG. 3A is a diagram showing a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique as a comparative example
  • FIG. 3B is the above-described embodiment. It is a figure which shows the cross-sectional structure of the semiconductor device by which a board
  • 3A and 3B the same components as those of the semiconductor device according to this embodiment shown in FIG. 1D are denoted by the same reference numerals.
  • the second substrate 51 having the through electrode 52 having a variation in the height of the protruding portion (electrode terminal portion) from the back surface of the substrate, and the position facing these through electrodes 52.
  • the first substrate 1 having the electrode terminal 8 which is a normal pad electrode, is pressure-bonded to the first substrate 1, a through electrode 52 not connected to the electrode terminal 8 is generated due to the height variation of the through electrode 52. End up.
  • the second substrate 51 having the penetrating electrodes 52 having variations in the height of the protruding portion (electrode terminal portion) from the back surface of the substrate, and these
  • the electrode terminal 9 made of the aggregate of the conductive fine particles 5 serves as a buffer material.
  • the height variation of the through electrode 52 is absorbed. That is, the insertion depths of the through electrodes 52 in the openings 4 of the insulating film 3 on the first substrate 1 are different from each other.
  • the electrical connection between the electrode terminal 9 formed of the aggregate of the conductive fine particles 5 and the through electrode 52 can be reliably achieved regardless of the height variation of the protruding portion of the through electrode 52. That is, unlike the comparative example, the through electrode 52 not connected to the electrode terminal 8 due to the height variation of the through electrode 52 does not occur.
  • electrode terminals are crimped due to variations in electrode terminal height, substrate thickness variation, substrate warpage, and the like. Therefore, a highly reliable three-dimensional integrated semiconductor device can be provided with a high yield.
  • the bonding between the through electrode 52 of the second substrate 51 and the electrode terminal 9 of the first substrate 1 has been described as an example.
  • the present invention is not limited thereto, and instead of the through electrode 52,
  • the pad electrode electrically connected to the wiring formed on the back surface 51b or the front surface 51a of the second substrate 51 and the electrode terminal 9 of the first substrate 1 may be bonded.
  • copper is used as the material of the conductive fine particles 5, but the present invention is not limited to this, and for example, a transition metal such as gold, silver, platinum, or nickel can be used.
  • fine particles having a diameter (particle diameter) of about 0.1 nm or more and less than about 1 ⁇ m are used as the conductive fine particles 5, but the size of the conductive fine particles 5 is not particularly limited.
  • the average particle diameter of the conductor fine particles 5 may be 50 nm or less, more preferably
  • the average particle diameter of the conductor fine particles 5 may be about 40 nm or less.
  • the conductive fine particles 5 may include conductive fine particles having a particle diameter exceeding 50 nm (more preferably 40 nm).
  • the above relationship between the particle size and the process temperature is for the case where the conductive fine particles are copper fine particles, but the same tendency (grains) is observed even if fine particles of other metals such as gold and silver are used. A decrease in melting point accompanying the refinement of the diameter is observed.
  • the surface of the conductive fine particles 5 may be coated with an organic material (eg, 3- (6-mercaptohexyl) thiophene).
  • an organic material eg, 3- (6-mercaptohexyl) thiophene.
  • the semiconductor device and the manufacturing method thereof include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device).
  • the semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
  • the semiconductor device and the manufacturing method thereof according to the present invention are bonded at the time of pressure bonding between the electrode terminals of each substrate due to the height variation of the electrode terminals, the substrate thickness variation, the substrate warpage, and the like. It can prevent defects, and is particularly useful in three-dimensional integration by chip-chip lamination, chip-wafer lamination, or wafer-wafer lamination on a substrate.

Abstract

An insulating film (3) is formed so as to cover a wiring line formed on a substrate (1). An opening (4) is formed on the insulating film (3) so as to expose the wiring line. An electrode terminal (9) comprising multiple conductive material microparticles (5) is formed in the opening (4).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関し、特に、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層された半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip-chip stacking, a chip-wafer stacking or a wafer-wafer stacking semiconductor device and a manufacturing method thereof.
　近年、半導体集積回路装置の高集積化、高機能化及び高速化に伴って、貫通電極を用いた基板のチップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層による３次元集積化技術が提案されている。 In recent years, as semiconductor integrated circuit devices become highly integrated, highly functional, and speeded up, three-dimensional integration technology based on chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking using substrates is proposed. Has been.
　これは、従来のＳｏＣ（システムオンチップ）のような２次元的な微細化においては、配線の断面積の縮小によって引き起こされる配線抵抗の上昇と、配線長の増大により引き起こされる配線遅延の増加とに起因して、性能が劣化してしまうことが懸念されているためである。 This is because, in the two-dimensional miniaturization like the conventional SoC (system on chip), an increase in wiring resistance caused by a reduction in the cross-sectional area of wiring and an increase in wiring delay caused by an increase in wiring length. This is because there is a concern that the performance deteriorates due to the above.
　３次元集積化技術においては、半導体集積回路装置を３次元的に積層することによって配線可能エリアを拡大し、それにより、配線断面積の増大と配線長の短縮とを可能とする。すなわち、集積度を高めつつ、性能向上を実現することができる。 In the three-dimensional integration technology, the wiring area is expanded by three-dimensionally stacking semiconductor integrated circuit devices, thereby increasing the wiring cross-sectional area and shortening the wiring length. That is, it is possible to improve performance while increasing the degree of integration.
　また、３次元集積化技術においてシリコン基板等の基板を積層する場合、基板間の電気的な接続のために、各基板の電極端子同士の間で金属－金属接合が必須となる。通常、各電極端子を構成する金属同士の接合には、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層における電極端子同士を加熱圧着し、金属－金属接合を形成する方法が用いられる。 In addition, when a substrate such as a silicon substrate is stacked in the three-dimensional integration technique, metal-metal bonding is indispensable between the electrode terminals of each substrate for electrical connection between the substrates. Usually, for joining the metals constituting each electrode terminal, a method of forming a metal-metal joint by thermocompression bonding of electrode terminals in chip-chip lamination, chip-wafer lamination, or wafer-wafer lamination is used.
　このような３次元集積回路装置は、一般的に、以下のようにして製造される。 Such a three-dimensional integrated circuit device is generally manufactured as follows.
　まず、シリコン基板の主面（表面）上に複数のトランジスタを形成する。次に、層間絶縁膜及びコンタクトを形成した後、貫通電極形成用ホールを形成して貫通電極となる銅を埋め込み、その後、層間絶縁膜上にさらに配線層を形成する。その後、基板裏面に対してＣＭＰ（chemical mechanical polishing ）を行い、シリコン基板の裏面を平坦化した後、ドライエッチング法によりシリコン基板の裏面をさらにエッチング除去して、貫通電極の底部を露出させる。これにより、一方のチップの裏面側電極端子が形成される。続いて、このチップの裏面側電極端子を、別途作製された他方のチップの表面側電極端子に加熱圧着させることにより、貫通電極を介した基板同士の積層（チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層）が行われる（例えば非特許文献１参照）。 First, a plurality of transistors are formed on the main surface (front surface) of the silicon substrate. Next, after forming an interlayer insulating film and a contact, a through electrode forming hole is formed and copper serving as a through electrode is buried, and then a wiring layer is further formed on the interlayer insulating film. Thereafter, CMP (chemical mechanical polishing) is performed on the back surface of the substrate to flatten the back surface of the silicon substrate, and then the back surface of the silicon substrate is further etched away by dry etching to expose the bottom of the through electrode. Thereby, the back surface side electrode terminal of one chip | tip is formed. Subsequently, the back surface side electrode terminal of this chip is thermocompression-bonded to the front surface side electrode terminal of the other chip separately manufactured, thereby stacking the substrates through the through electrodes (chip-chip stacking, chip-wafer stacking). Alternatively, wafer-wafer stacking is performed (see, for example, Non-Patent Document 1).
　しかしながら、前述の従来の３次元集積化技術においては、各基板の電極端子同士の間で接合不良が生じるという問題がある。 However, the above-described conventional three-dimensional integration technique has a problem in that poor bonding occurs between the electrode terminals of each substrate.
　前記に鑑み、本発明は、各基板の電極端子同士の間での接合不良を防止できる３次元集積化技術を提供することを目的とする。 In view of the above, an object of the present invention is to provide a three-dimensional integration technique that can prevent a bonding failure between electrode terminals of each substrate.
　前記の目的を達成するために、従来の３次元集積化技術において各基板の電極端子同士の間で接合不良が生じる原因について本願発明者が種々の検討を行ったところ、次のような知見を得た。 In order to achieve the above-mentioned object, the inventors of the present application made various studies on the cause of bonding failure between the electrode terminals of each substrate in the conventional three-dimensional integration technology. Obtained.
　図４は、従来の３次元集積化技術を用いて基板が積層されてなる半導体装置の断面構成を示している。図４に示すように、素子形成面（表面）１００ａ及びその反対面（裏面）１００ｂを有する第１の基板１００中に貫通電極１０１が形成されている。第１の基板１００の表面１００ａ上には、トランジスタ１０２が形成されていると共に、トランジスタ１０２及び貫通電極１０１と電気的に接続する多層配線を有する配線層１０３が形成されている。第１の基板１００の裏面１００ｂには、裏面側電極端子となる貫通電極１０１の底部が露出している。第１の基板１００は、素子形成面（表面）２００ａ及びその反対面（裏面）２００ｂを有する第２の基板２００と、第１の基板１００の裏面１００と第２の基板２００の表面２００ａとが対向するように積層されている。第２の基板２００の表面２００ａ上には、トランジスタ２０１が形成されていると共に、トランジスタ２０１と電気的に接続する多層配線を有する配線層２０２が形成されている。配線層２０２の最表面部には、第１の基板１００の裏面側電極端子となる貫通電極１０１の底部と接続する電極パッド２０３が形成されている。 FIG. 4 shows a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique. As shown in FIG. 4, a through electrode 101 is formed in a first substrate 100 having an element formation surface (front surface) 100a and an opposite surface (back surface) 100b. A transistor 102 is formed over the surface 100 a of the first substrate 100, and a wiring layer 103 having a multilayer wiring electrically connected to the transistor 102 and the through electrode 101 is formed. On the back surface 100b of the first substrate 100, the bottom portion of the through electrode 101 serving as the back surface side electrode terminal is exposed. The first substrate 100 includes a second substrate 200 having an element formation surface (front surface) 200a and an opposite surface (back surface) 200b, a back surface 100 of the first substrate 100, and a front surface 200a of the second substrate 200. They are stacked so as to face each other. A transistor 201 is formed over the surface 200 a of the second substrate 200, and a wiring layer 202 having a multilayer wiring electrically connected to the transistor 201 is formed. On the outermost surface portion of the wiring layer 202, an electrode pad 203 is formed that is connected to the bottom portion of the through electrode 101 serving as the back surface side electrode terminal of the first substrate 100.
　しかしながら、図４に示すように、第１の基板１００の裏面１００ｂ側においてグラインド、ＣＭＰ及びドライエッチング法等を用いて貫通電極（つまり貫通孔内に埋め込まれた導電材料）を露出させて裏面側電極端子を形成する工程で、基板（例えばウェーハ）面内において、当該裏面側電極端子（貫通電極の露出端部）の高さにバラツキが生じてしまう。 However, as shown in FIG. 4, on the back surface 100b side of the first substrate 100, the through electrode (that is, the conductive material embedded in the through hole) is exposed by using grinding, CMP, dry etching, etc. In the step of forming the electrode terminal, the height of the back-side electrode terminal (exposed end portion of the through electrode) varies in the plane of the substrate (for example, wafer).
　この高さバラツキは、基板自体の厚さバラツキ、貫通電極を形成する際のリソグラフィ工程におけるレジストパターンの寸法バラツキ、及び、ドライエッチング時のエッチング速度のウェーハ面内でのバラツキに起因する貫通電極の露出端部自体の高さバラツキ等によって発生する。 This height variation is due to variations in the thickness of the substrate itself, variations in the resist pattern dimensions in the lithography process when forming the through electrode, and variations in the etching rate in the wafer surface due to variations in the etching rate during dry etching. This occurs due to variations in the height of the exposed end itself.
　また、図４に示すように、ウェーハ面内での基板の厚さバラツキや反りにより、第１の基板１００の貫通電極１０１の底面と、第２の基板２００の電極パッド２０３の上面とを平行に保持することができないため、ウェーハ面内において、貫通電極１０１の底面（裏面側電極端子の底面）と電極パッド２０３の上面との間の距離がばらつくことになる。 Further, as shown in FIG. 4, the bottom surface of the through electrode 101 of the first substrate 100 and the top surface of the electrode pad 203 of the second substrate 200 are parallel to each other due to the thickness variation or warpage of the substrate in the wafer surface. Therefore, the distance between the bottom surface of the through electrode 101 (the bottom surface of the back-side electrode terminal) and the top surface of the electrode pad 203 varies within the wafer surface.
　以上に述べたような、電極端子の高さバラツキや、各基板の電極端子間の距離バラツキに起因して、各基板の電極端子同士を加熱圧着させた場合に、ウェーハ面内で印加される圧力にバラツキが生じる。その結果、最悪、ウェーハ内の一部分において対向する両電極端子間に空隙が生じて接合が形成されないという問題が発生する。 As described above, when the electrode terminals of each substrate are thermocompression-bonded due to the height variation of the electrode terminals and the distance variation between the electrode terminals of each substrate, it is applied within the wafer surface. Variation in pressure occurs. As a result, there arises a problem that a gap is generated between the electrode terminals facing each other in a part of the wafer and a bond is not formed.
　以上の知見に基づいて、本願発明者は、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層において、電極端子の高さバラツキ、基板の厚さバラツキ及び基板の反り等に起因する電極端子同士の圧着時の接合不良を防止できる以下のような発明を想到した。 Based on the above knowledge, the inventor of the present application, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, has electrode terminals caused by variations in electrode terminal height, substrate thickness variation, substrate warpage, and the like. The inventors have conceived the following invention capable of preventing poor bonding at the time of pressure bonding.
　本発明に係る第１の半導体装置は、第１の基板と、前記第１の基板上に形成された配線と、前記配線を覆うように前記第１の基板上に形成された絶縁膜と、前記絶縁膜に、前記配線が露出するように形成された開口部と、前記開口部内に形成され且つ複数の導電体微粒子から構成されている第１の電極端子とを備えている。 A first semiconductor device according to the present invention includes a first substrate, a wiring formed on the first substrate, an insulating film formed on the first substrate so as to cover the wiring, The insulating film includes an opening formed so that the wiring is exposed, and a first electrode terminal formed in the opening and made of a plurality of conductive fine particles.
　本発明に係る第１の半導体装置によると、基板上の絶縁膜開口部に充填された導電体微粒子群から電極端子が構成されている。このため、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層において、開口部上方から開口部内へ挿入される導電体（他の基板の電極端子）の挿入深さに応じて、言い換えると、他の基板の電極端子から受ける圧力の大きさに応じて、導電体微粒子群が緩衝材となって変形しつつ、電極端子同士が接合する。従って、他の基板の電極端子の高さにバラツキが生じていたり、基板に厚さバラツキや反り等が生じている場合にも、導電体微粒子群の変形によって、チップ内又はウェーハ内において電極端子同士を確実に接合させることができる。 According to the first semiconductor device of the present invention, the electrode terminal is constituted by the conductive fine particle group filled in the opening of the insulating film on the substrate. Therefore, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, in other words, depending on the insertion depth of the conductor (electrode terminal of another substrate) inserted from above the opening into the opening, The electrode terminals are joined to each other while the conductor fine particle group is deformed as a buffer material according to the magnitude of the pressure received from the electrode terminals of the other substrate. Therefore, even when there are variations in the height of electrode terminals on other substrates, or variations in the thickness or warpage of the substrates, the electrode terminals in the chip or wafer due to deformation of the conductive fine particle group. The two can be reliably bonded to each other.
　本発明に係る第１の半導体装置において、前記複数の導電体微粒子のそれぞれの表面は有機材料によってコーティングされていてもよい。このようにすると、各導電体微粒子の酸化を抑制することができるので、導電体微粒子群からなる電極端子の抵抗の増大を防止することができる。 In the first semiconductor device according to the present invention, each surface of the plurality of conductive fine particles may be coated with an organic material. In this way, since the oxidation of each conductive fine particle can be suppressed, it is possible to prevent an increase in the resistance of the electrode terminal composed of the conductive fine particle group.
　本発明に係る第１の半導体装置において、前記複数の導電体微粒子の平均粒径は、５０ｎｍ以下であってもよい。このようにすると、例えば３５０℃程度以下の低温プロセスにおいて導電体微粒子を溶融させ、他の基板の電極端子と接合させることができるので、半導体装置へのダメージを低減しつつ、電極端子同士の接合強度を強くすることができる。尚、前記複数の導電体微粒子のうちの過半数の粒径が５０ｎｍ程度以下であれば、前述の効果を得ることができる。言い換えると、前記複数の導電体微粒子は、５０ｎｍを超える粒径の導電体微粒子を含んでいてもよい。また、より好ましくは、例えば２５０℃程度以下の低温プロセスにおいて導電体微粒子を溶融させるために、前記複数の導電体微粒子の平均粒径が４０ｎｍ程度以下であってもよい。この場合も、前記複数の導電体微粒子のうちの過半数の粒径が４０ｎｍ程度以下であればよく、前記複数の導電体微粒子が、４０ｎｍを超える粒径の導電体微粒子を含んでいてもよい。尚、以上の粒径とプロセス温度との関係は、導電体微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向（粒径の微細化に伴う融点の低下）が見られる。 In the first semiconductor device according to the present invention, the plurality of conductive fine particles may have an average particle size of 50 nm or less. In this way, for example, the conductive fine particles can be melted and bonded to the electrode terminals of another substrate in a low temperature process of about 350 ° C. or lower, so that the bonding between the electrode terminals can be reduced while reducing damage to the semiconductor device. Strength can be increased. In addition, if the particle diameter of the majority of the plurality of conductive fine particles is about 50 nm or less, the above-described effects can be obtained. In other words, the plurality of conductive fine particles may include conductive fine particles having a particle diameter exceeding 50 nm. More preferably, for example, the average particle diameter of the plurality of conductive fine particles may be about 40 nm or less in order to melt the conductive fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the majority of the plurality of conductor fine particles may have a particle diameter of about 40 nm or less, and the plurality of conductor fine particles may include conductor fine particles having a particle diameter exceeding 40 nm. The above relationship between the particle size and the process temperature is for the case where the conductive fine particles are copper fine particles, but the same tendency (grains) can be obtained even for fine particles of other metals such as gold and silver. A decrease in melting point accompanying the refinement of the diameter is observed.
　本発明に係る第１の半導体装置において、前記複数の導電体微粒子は遷移金属から構成されていてもよい。 In the first semiconductor device according to the present invention, the plurality of conductive fine particles may be made of a transition metal.
　本発明に係る第１の半導体装置において、前記複数の導電体微粒子は金、銀又は銅から構成されていてもよい。 In the first semiconductor device according to the present invention, the plurality of conductive fine particles may be made of gold, silver or copper.
　本発明に係る第１の半導体装置において、表面又は裏面から突出した第２の電極端子を有する第２の基板をさらに備え、前記第１の基板と前記第２の基板とは、前記第１の電極端子と前記第２の電極端子とが接続するように積層されており、前記第２の電極端子は、前記第１の電極端子となる前記複数の導電体微粒子の集合体の形状を変形させて前記開口部内に挿入されていてもよい。このようにすると、各基板の電極端子同士の間での接合不良を防止できる３次元集積化半導体装置を得ることができる。この場合、前記第２の電極端子は、前記第２の基板に形成された貫通電極の一部であってもよい。このようにすると、半導体装置のさらなる高集積化、高機能化及び高速化を実現することができる。 The first semiconductor device according to the present invention further includes a second substrate having a second electrode terminal protruding from the front surface or the back surface, wherein the first substrate and the second substrate are the first substrate and the second substrate. The electrode terminal and the second electrode terminal are stacked so as to be connected, and the second electrode terminal deforms the shape of the aggregate of the plurality of conductive fine particles to be the first electrode terminal. And may be inserted into the opening. In this way, it is possible to obtain a three-dimensional integrated semiconductor device that can prevent poor bonding between the electrode terminals of each substrate. In this case, the second electrode terminal may be a part of the through electrode formed on the second substrate. In this way, further high integration, high functionality, and high speed of the semiconductor device can be realized.
　本発明に係る第２の半導体装置は、第１の基板と、前記第１の基板上に形成された配線と、前記配線を覆うように前記第１の基板上に形成された絶縁膜と、前記絶縁膜に、前記配線が露出するように形成された複数の開口部と、前記複数の開口部内に形成され且つ複数の導電体微粒子から構成されている複数の第１の電極端子と、表面又は裏面から突出した複数の第２の電極端子を有する第２の基板とを備え、前記第１の基板と前記第２の基板とは、前記複数の第１の電極端子と前記複数の第２の電極端子とが接続するように積層されており、前記複数の第２の電極端子は、前記複数の第１の電極端子のそれぞれとなる前記複数の導電体微粒子の集合体の形状を変形させて前記複数の開口部内に挿入されており、前記複数の開口部内における前記複数の第２の電極端子の挿入深さが互いに異なる。 A second semiconductor device according to the present invention includes a first substrate, a wiring formed on the first substrate, an insulating film formed on the first substrate so as to cover the wiring, A plurality of openings formed in the insulating film so that the wiring is exposed; a plurality of first electrode terminals formed in the plurality of openings and made of a plurality of conductive fine particles; and a surface Or a second substrate having a plurality of second electrode terminals protruding from the back surface, wherein the first substrate and the second substrate include the plurality of first electrode terminals and the plurality of second electrodes. The plurality of second electrode terminals are deformed in the shape of the aggregate of the plurality of conductive fine particles that respectively become the plurality of first electrode terminals. Inserted into the plurality of openings. The insertion depth of the plurality of second electrode terminals are different from each other.
　本発明に係る第２の半導体装置によると、第１の基板上の絶縁膜開口部に充填された導電体微粒子群から第１の電極端子が構成されているため、第２の基板の第２の電極端子の絶縁膜開口部における挿入深さに応じて、言い換えると、第２の電極端子から受ける圧力の大きさに応じて、導電体微粒子群が緩衝材となって変形しつつ、電極端子同士が接合する。従って、第２の電極端子の高さにバラツキが生じていたり、基板に厚さバラツキや反り等が生じている場合にも、導電体微粒子群の変形によって、チップ内又はウェーハ内において電極端子同士を確実に接合させることができる。 According to the second semiconductor device of the present invention, the first electrode terminal is constituted by the conductive fine particle group filled in the insulating film opening on the first substrate. Depending on the insertion depth of the electrode terminal of the electrode terminal in the insulating film opening, in other words, depending on the pressure received from the second electrode terminal, the conductive fine particle group is deformed as a buffer material, and the electrode terminal Join each other. Accordingly, even when the height of the second electrode terminal is varied, or when the substrate is varied in thickness, warpage, or the like, the electrode terminals are deformed in the chip or wafer due to deformation of the conductive fine particle group. Can be reliably bonded.
　本発明に係る第１の半導体装置の製造方法は、第１の基板上に配線を形成する工程（ａ）と、前記配線を覆うように前記第１の基板上に絶縁膜を形成する工程（ｂ）と、前記絶縁膜に、前記配線層が露出するように開口部を形成する工程（ｃ）と、前記開口部内に、複数の導電体微粒子からなる第１の電極端子を形成する工程（ｄ）とを備えている。 The first method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a wiring on a first substrate and a step of forming an insulating film on the first substrate so as to cover the wiring ( b), a step (c) of forming an opening in the insulating film so that the wiring layer is exposed, and a step of forming a first electrode terminal made of a plurality of conductive fine particles in the opening ( d).
　本発明に係る第１の半導体装置の製造方法によると、基板上の絶縁膜開口部に充填された導電体微粒子群から電極端子が構成される。このため、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層において、開口部上方から開口部内へ挿入される導電体（他の基板の電極端子）の挿入深さに応じて、言い換えると、他の基板の電極端子から受ける圧力の大きさに応じて、導電体微粒子群が緩衝材となって変形しつつ、電極端子同士が接合する。従って、他の基板の電極端子の高さにバラツキが生じていたり、基板に厚さバラツキや反り等が生じている場合にも、導電体微粒子群の変形によって、チップ内又はウェーハ内において電極端子同士を確実に接合させることができる。 According to the first method of manufacturing a semiconductor device according to the present invention, the electrode terminal is composed of the conductive fine particle group filled in the insulating film opening on the substrate. Therefore, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, in other words, depending on the insertion depth of the conductor (electrode terminal of another substrate) inserted from above the opening into the opening, The electrode terminals are joined to each other while the conductor fine particle group is deformed as a buffer material according to the magnitude of the pressure received from the electrode terminals of the other substrate. Therefore, even when there are variations in the height of electrode terminals on other substrates, or variations in the thickness or warpage of the substrates, the electrode terminals in the chip or wafer due to deformation of the conductive fine particle group. The two can be reliably bonded to each other.
　本発明に係る第１の半導体装置の製造方法において、前記複数の導電体微粒子のそれぞれの表面は有機材料によってコーティングされていてもよい。このようにすると、各導電体微粒子の酸化を抑制することができるので、導電体微粒子群からなる電極端子の抵抗の増大を防止することができる。 In the first method for manufacturing a semiconductor device according to the present invention, the surface of each of the plurality of conductive fine particles may be coated with an organic material. In this way, since the oxidation of each conductive fine particle can be suppressed, it is possible to prevent an increase in the resistance of the electrode terminal composed of the conductive fine particle group.
　本発明に係る第１の半導体装置の製造方法において、前記複数の導電体微粒子の平均粒径は５０ｎｍ以下であってもよい。このようにすると、例えば３５０℃程度以下の低温プロセスにおいて導電体微粒子を溶融させ、他の基板の電極端子と接合させることができるので、半導体装置へのダメージを低減しつつ、電極端子同士の接合強度を強くすることができる。尚、前記複数の導電体微粒子のうちの過半数の粒径が５０ｎｍ程度以下であれば、前述の効果を得ることができる。言い換えると、前記複数の導電体微粒子は、５０ｎｍを超える粒径の導電体微粒子を含んでいてもよい。また、より好ましくは、例えば２５０℃程度以下の低温プロセスにおいて導電体微粒子を溶融させるために、前記複数の導電体微粒子の平均粒径が４０ｎｍ程度以下であってもよい。この場合も、前記複数の導電体微粒子のうちの過半数の粒径が４０ｎｍ程度以下であればよく、前記複数の導電体微粒子が、４０ｎｍを超える粒径の導電体微粒子を含んでいてもよい。尚、以上の粒径とプロセス温度との関係は、導電体微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向（粒径の微細化に伴う融点の低下）が見られる。 In the first method of manufacturing a semiconductor device according to the present invention, the plurality of conductor fine particles may have an average particle size of 50 nm or less. In this way, for example, the conductive fine particles can be melted and bonded to the electrode terminals of another substrate in a low temperature process of about 350 ° C. or lower, so that the bonding between the electrode terminals can be reduced while reducing damage to the semiconductor device. Strength can be increased. In addition, if the particle diameter of the majority of the plurality of conductive fine particles is about 50 nm or less, the above-described effects can be obtained. In other words, the plurality of conductive fine particles may include conductive fine particles having a particle diameter exceeding 50 nm. More preferably, for example, the average particle diameter of the plurality of conductive fine particles may be about 40 nm or less in order to melt the conductive fine particles in a low temperature process of about 250 ° C. or less. Also in this case, the majority of the plurality of conductor fine particles may have a particle diameter of about 40 nm or less, and the plurality of conductor fine particles may include conductor fine particles having a particle diameter exceeding 40 nm. The above relationship between the particle size and the process temperature is for the case where the conductive fine particles are copper fine particles, but the same tendency (grains) can be obtained even for fine particles of other metals such as gold and silver. A decrease in melting point accompanying the refinement of the diameter is observed.
　本発明に係る第１の半導体装置の製造方法において、前記複数の導電体微粒子は遷移金属から構成されていてもよい。 In the first method for manufacturing a semiconductor device according to the present invention, the plurality of conductive fine particles may be made of a transition metal.
　本発明に係る第１の半導体装置の製造方法において、前記複数の導電体微粒子は金、銀又は銅から構成されていてもよい。 In the first method for manufacturing a semiconductor device according to the present invention, the plurality of conductive fine particles may be made of gold, silver, or copper.
　本発明に係る第１の半導体装置の製造方法において、前記工程（ｄ）は、前記開口部内を含む前記絶縁膜上に前記複数の導電体微粒子を層状に堆積した後、前記開口部の外側の前記複数の導電体微粒子を除去する工程を含んでいてもよい。 In the first method of manufacturing a semiconductor device according to the present invention, in the step (d), the plurality of conductive fine particles are deposited in a layer on the insulating film including the inside of the opening, and then the outside of the opening is formed. A step of removing the plurality of conductive fine particles may be included.
　本発明に係る第１の半導体装置の製造方法において、表面又は裏面から突出した第２の電極端子を有する第２の基板を準備する工程（ｅ）と、前記第１の基板と前記第２の基板とを、前記第１の電極端子と前記第２の電極端子とが接続するように積層する工程（ｆ）とをさらに備え、前記工程（ｆ）は、前記第１の電極端子となる前記複数の導電体微粒子の集合体の形状を変形させて前記第２の電極端子を前記開口部内に挿入する工程を含んでいてもよい。このようにすると、各基板の電極端子同士の間での接合不良を防止できる３次元集積化半導体装置を得ることができる。この場合、前記第２の電極端子は、前記第２の基板に形成された貫通電極の一部であってもよい。このようにすると、半導体装置のさらなる高集積化、高機能化及び高速化を実現することができる。また、前記工程（ｆ）は、熱処理によって前記複数の導電体微粒子を溶融させて前記第２の電極端子と接合させる工程を含んでいてもよい。このようにすると、電極端子同士の接合強度を強くすることができる。 In the first method for manufacturing a semiconductor device according to the present invention, a step (e) of preparing a second substrate having a second electrode terminal protruding from the front surface or the back surface, the first substrate and the second substrate A step (f) of laminating a substrate so that the first electrode terminal and the second electrode terminal are connected, and the step (f) is the first electrode terminal. A step of deforming the shape of the aggregate of the plurality of conductive fine particles and inserting the second electrode terminal into the opening may be included. In this way, it is possible to obtain a three-dimensional integrated semiconductor device that can prevent poor bonding between the electrode terminals of each substrate. In this case, the second electrode terminal may be a part of the through electrode formed on the second substrate. In this way, further high integration, high functionality, and high speed of the semiconductor device can be realized. Further, the step (f) may include a step of melting the plurality of conductive fine particles by heat treatment and joining the second conductive electrode to the second electrode terminal. If it does in this way, the joint strength of electrode terminals can be strengthened.
　本発明に係る第２の半導体装置の製造方法は、第１の基板上に配線を形成する工程（ａ）と、前記配線を覆うように前記第１の基板上に絶縁膜を形成する工程（ｂ）と、前記絶縁膜に、前記配線層が露出するように複数の開口部を形成する工程（ｃ）と、前記複数の開口部内に、複数の導電体微粒子からなる複数の第１の電極端子を形成する工程（ｄ）と、表面又は裏面から突出した複数の第２の電極端子を有する第２の基板を準備する工程（ｅ）と、前記第１の基板と前記第２の基板とを、前記複数の第１の電極端子と前記複数の第２の電極端子とが接続するように積層する工程（ｆ）とを備え、前記工程（ｆ）は、前記複数の第１の電極端子のそれぞれとなる前記複数の導電体微粒子の集合体の形状を変形させて前記複数の第２の電極端子を前記複数の開口部内に挿入する工程を含み、前記複数の開口部内における前記複数の第２の電極端子の挿入深さが互いに異なる。 The second method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a wiring on a first substrate and a step of forming an insulating film on the first substrate so as to cover the wiring ( b), a step (c) of forming a plurality of openings in the insulating film so as to expose the wiring layer; and a plurality of first electrodes made of a plurality of conductive fine particles in the plurality of openings. A step (d) of forming a terminal, a step (e) of preparing a second substrate having a plurality of second electrode terminals protruding from the front or back surface, the first substrate and the second substrate, A step (f) of stacking the plurality of first electrode terminals and the plurality of second electrode terminals so that the plurality of first electrode terminals are connected to each other. The plurality of second electrodes are deformed by deforming the shape of the aggregate of the plurality of conductive fine particles to be respectively Comprising the step of inserting the child into the plurality of openings, the insertion depth of the plurality of second electrode terminals of the plurality of the openings are different from each other.
　本発明に係る第２の半導体装置の製造方法によると、第１の基板上の絶縁膜開口部に充填された導電体微粒子群から第１の電極端子が構成されるため、第２の基板の第２の電極端子の絶縁膜開口部における挿入深さに応じて、言い換えると、第２の電極端子から受ける圧力の大きさに応じて、導電体微粒子群が緩衝材となって変形しつつ、電極端子同士が接合する。従って、第２の電極端子の高さにバラツキが生じていたり、基板に厚さバラツキや反り等が生じている場合にも、導電体微粒子群の変形によって、チップ内又はウェーハ内において電極端子同士を確実に接合させることができる。 According to the second method for manufacturing a semiconductor device of the present invention, the first electrode terminal is constituted by the conductive fine particle group filled in the insulating film opening on the first substrate. Depending on the insertion depth in the insulating film opening of the second electrode terminal, in other words, depending on the magnitude of the pressure received from the second electrode terminal, the conductive fine particle group is deformed as a buffer material, The electrode terminals are joined together. Accordingly, even when the height of the second electrode terminal is varied, or when the substrate is varied in thickness, warpage, or the like, the electrode terminals are deformed in the chip or wafer due to deformation of the conductive fine particle group. Can be reliably bonded.
　本発明に係る半導体装置及びその製造方法によれば、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層において、電極端子の高さバラツキ、基板の厚さバラツキ及び基板の反り等に起因する電極端子同士の圧着時の接合不良を防止できるので、信頼性の高い３次元集積化半導体装置を高歩留りで提供することができる。 According to the semiconductor device and the manufacturing method thereof according to the present invention, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, it is caused by height variations of electrode terminals, substrate thickness variations, substrate warpage, and the like. Since the bonding failure at the time of crimping between the electrode terminals can be prevented, a highly reliable three-dimensional integrated semiconductor device can be provided with a high yield.
図１（ａ）～（ｄ）は、実施形態に係る半導体装置の製造方法の各工程を示す断面図である。1A to 1D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to an embodiment. 図２（ａ）～（ｃ）は、図１（ｃ）に示す工程を詳細に説明する図である。2A to 2C are diagrams for explaining the process shown in FIG. 1C in detail. 図３（ａ）は、比較例として、従来の３次元集積化技術を用いて基板が積層されてなる半導体装置の断面構成を示す図であり、図３（ｂ）は、実施形態に係る半導体装置の製造方法を用いて基板が積層されてなる半導体装置の断面構成を示す図である。FIG. 3A is a diagram showing a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique as a comparative example, and FIG. 3B is a semiconductor according to the embodiment. It is a figure which shows the cross-sectional structure of the semiconductor device by which a board | substrate is laminated | stacked using the manufacturing method of an apparatus. 図４は、従来の３次元集積化技術を用いて基板が積層されてなる半導体装置の断面構成を示す図である。FIG. 4 is a diagram showing a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique.
　以下、本発明の一実施形態に係る半導体装置及びその製造方法について、図面を参照しながら説明する。 Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
　図１（ａ）～（ｄ）は、本実施形態に係る半導体装置の製造方法の各工程を示す断面図である。 1A to 1D are cross-sectional views showing respective steps of a semiconductor device manufacturing method according to the present embodiment.
　まず、図１（ａ）に示すように、素子形成面（表面）１ａ及びその反対面（裏面）１ｂを有しており、且つ例えばシリコンからなる第１の基板１を準備する。続いて、第１の基板１の表面１ａ上に、トランジスタ６を形成した後、コンタクト７を介してトランジスタ６と電気的に接続する多層配線を有する配線層２を形成する。続いて、配線層２上に絶縁膜３を形成する。 First, as shown in FIG. 1A, a first substrate 1 having an element formation surface (front surface) 1a and an opposite surface (back surface) 1b and made of, for example, silicon is prepared. Subsequently, after forming the transistor 6 on the surface 1 a of the first substrate 1, the wiring layer 2 having a multilayer wiring electrically connected to the transistor 6 through the contact 7 is formed. Subsequently, an insulating film 3 is formed on the wiring layer 2.
　次に、図１（ｂ）に示すように、絶縁膜３に、下層の配線層２（具体的には最上層配線）の一部が露出するように開口部４を形成する。 Next, as shown in FIG. 1B, an opening 4 is formed in the insulating film 3 so that a part of the lower wiring layer 2 (specifically, the uppermost layer wiring) is exposed.
　次に、図１（ｃ）に示すように、開口部４内に、例えば銅からなる複数の導電体微粒子５を充填することによって、電極端子９を形成する。 Next, as shown in FIG. 1C, the electrode terminal 9 is formed by filling the opening 4 with a plurality of conductive fine particles 5 made of, for example, copper.
　ここで、図１（ｃ）に示す工程について、図２（ａ）～（ｃ）を参照しながら詳細に説明する。まず、図２（ａ）に示すように、例えばドライエッチング法を用いて、絶縁膜３に、下層の配線層２（具体的には最上層配線）の一部が露出するように開口部４を形成した後、開口部４内を含む絶縁膜３上に、例えば銅からなる多数の導電体微粒子５を含む有機溶剤を回転塗布法を用いて塗布する。導電体微粒子５の直径（粒径）は例えば０．１ｎｍ程度以上１μｍ程度未満である。続いて、比較的低温である例えば１５０～２００℃程度の温度で約１０分間の第１の熱処理を行い、絶縁膜３上の溶剤及び有機成分を揮発させて除去する。これにより、図２（ｂ）に示すように、開口部４内を含む絶縁膜３上において多数の導電体微粒子５が凝集して層状態で堆積される。次に、図２（ｃ）に示すように、開口部４の外側に堆積されている導電体微粒子５を例えばＣＭＰ法を用いて研磨除去して、開口部４内のみに導電体微粒子５を電極端子９として残存させる。図２（ｃ）に示す工程までが終了した時点では、導電体微粒子５は個々に独立した状態を保っており、導電体微粒子５の集合体に圧力を加えると、各導電体微粒子５が比較的容易に移動して導電体微粒子５の集合体としての形状が変化する。 Here, the process shown in FIG. 1 (c) will be described in detail with reference to FIGS. 2 (a) to 2 (c). First, as shown in FIG. 2A, the opening 4 is formed so that a part of the lower wiring layer 2 (specifically, the uppermost wiring) is exposed to the insulating film 3 by using, for example, a dry etching method. Then, an organic solvent containing a large number of conductive fine particles 5 made of, for example, copper is applied onto the insulating film 3 including the inside of the opening 4 by using a spin coating method. The diameter (particle diameter) of the conductive fine particles 5 is, for example, about 0.1 nm or more and less than about 1 μm. Subsequently, a first heat treatment is performed at a relatively low temperature, for example, about 150 to 200 ° C. for about 10 minutes to volatilize and remove the solvent and organic components on the insulating film 3. As a result, as shown in FIG. 2B, a large number of conductive fine particles 5 are aggregated and deposited in a layer state on the insulating film 3 including the inside of the opening 4. Next, as shown in FIG. 2C, the conductive fine particles 5 deposited on the outside of the opening 4 are removed by polishing using, for example, a CMP method, so that the conductive fine particles 5 are only in the opening 4. The electrode terminal 9 is left. When the process up to the step shown in FIG. 2C is completed, the conductive fine particles 5 are kept in an independent state. When the pressure is applied to the aggregate of the conductive fine particles 5, the conductive fine particles 5 are compared. Therefore, the shape as an aggregate of the conductive fine particles 5 changes.
　次に、図１（ｄ）に示すように、素子形成面（表面）５１ａ及びその反対面（裏面）５１ｂを有しており、且つ例えばシリコンからなる第２の基板５１を準備する。第２の基板５１中には貫通電極５２が形成されている。貫通電極５２の側壁面は絶縁膜５３によって覆われている。第２の基板５１の表面５１ａ上には、トランジスタ５４が形成されていると共に、コンタクト５５を介してトランジスタ５４と電気的に接続する多層配線を有する配線層５６が形成されている。第２の基板５１の裏面５１ｂからは、裏面側電極端子となる貫通電極５２の底部が突出している。続いて、当該貫通電極５２の突出部分が第１の基板１の開口部４つまり導電体微粒子５の集合体からなる電極端子９と対向するように、第１の基板１及び第２の基板５１を配置し、当該両基板を加圧して押し合わせる。この処理により、第２の基板５１の裏面５１ｂに露出した貫通電極５２の底部は、第１の基板１上に形成された絶縁膜３の開口部４内に挿入され、当該開口部４内に充填されている導電体微粒子５の集合体の形状を変形させる。 Next, as shown in FIG. 1D, a second substrate 51 having an element formation surface (front surface) 51a and an opposite surface (back surface) 51b and made of, for example, silicon is prepared. A through electrode 52 is formed in the second substrate 51. The side wall surface of the through electrode 52 is covered with an insulating film 53. On the surface 51 a of the second substrate 51, a transistor 54 is formed, and a wiring layer 56 having a multilayer wiring electrically connected to the transistor 54 through a contact 55 is formed. From the back surface 51b of the 2nd board | substrate 51, the bottom part of the penetration electrode 52 used as a back surface side electrode terminal protrudes. Subsequently, the first substrate 1 and the second substrate 51 so that the protruding portion of the through electrode 52 faces the opening 4 of the first substrate 1, that is, the electrode terminal 9 made of an aggregate of the conductive fine particles 5. And press and press the substrates together. By this processing, the bottom of the through electrode 52 exposed on the back surface 51 b of the second substrate 51 is inserted into the opening 4 of the insulating film 3 formed on the first substrate 1, and the opening 4 is inserted into the opening 4. The shape of the aggregate of the conductive fine particles 5 filled is changed.
　次に、第１の基板１と第２の基板５１とを加圧して押し合わせた状態で加熱（第２の熱処理）を行うことにより、導電体微粒子５を部分的に溶融させ、貫通電極５２の露出底部と電極端子９とを接合させる。第２の熱処理は、第１の熱処理よりも高温（例えば２００～２５０℃程度の温度）で例えば３０分間程度行う。 Next, by heating (second heat treatment) in a state where the first substrate 1 and the second substrate 51 are pressed and pressed together, the conductive fine particles 5 are partially melted, and the through electrode 52 is melted. The exposed bottom and the electrode terminal 9 are joined. The second heat treatment is performed at a higher temperature than the first heat treatment (for example, a temperature of about 200 to 250 ° C.) for about 30 minutes, for example.
　本実施形態によると、第１の基板１上の絶縁膜３の開口部４に充填された導電体微粒子５の集合体から電極端子９が構成されているため、第２の基板５１の電極端子（貫通電極５２の露出底部）の開口部４における挿入深さに応じて、言い換えると、貫通電極５２の露出底部から受ける圧力の大きさに応じて、導電体微粒子５の集合体が緩衝材となって変形しつつ、電極端子同士が接合する。従って、貫通電極５２の露出底部の位置（つまり第２の基板５１の電極端子の高さ）にバラツキが生じていたり、基板に厚さバラツキや反り等が生じている場合にも、導電体微粒子５の集合体の変形によって、チップ内又はウェーハ内において電極端子同士を確実に接合させることができる。その結果、貫通電極５２と第１の基板１の配線層２との電気的接続が良好になるので、信頼性の高い３次元集積化半導体装置を高歩留りで提供することができる。 According to this embodiment, since the electrode terminal 9 is composed of the aggregate of the conductive fine particles 5 filled in the opening 4 of the insulating film 3 on the first substrate 1, the electrode terminal of the second substrate 51 Depending on the insertion depth in the opening 4 of the (exposed bottom portion of the through electrode 52), in other words, depending on the magnitude of the pressure received from the exposed bottom portion of the through electrode 52, the aggregate of the conductive fine particles 5 is the buffer material. The electrode terminals are joined while being deformed. Therefore, even when there is a variation in the position of the exposed bottom portion of the through electrode 52 (that is, the height of the electrode terminal of the second substrate 51) or a variation in the thickness or warpage of the substrate, the conductive fine particles By the deformation of the assembly 5, the electrode terminals can be reliably bonded to each other in the chip or the wafer. As a result, since the electrical connection between the through electrode 52 and the wiring layer 2 of the first substrate 1 is improved, a highly reliable three-dimensional integrated semiconductor device can be provided with a high yield.
　以下、図３（ａ）及び（ｂ）を参照しながら、本実施形態による電極端子同士の接合信頼性向上効果を従来技術と比較して説明する。 Hereinafter, the effect of improving the bonding reliability between the electrode terminals according to the present embodiment will be described in comparison with the prior art with reference to FIGS.
　図３（ａ）は、比較例として、従来の３次元集積化技術を用いて基板が積層されてなる半導体装置の断面構成を示す図であり、図３（ｂ）は、前述の本実施形態の３次元集積化技術を用いて基板が積層されてなる半導体装置の断面構成を示す図である。尚、図３（ａ）及び（ｂ）において、図１（ｄ）に示す本実施形態に係る半導体装置と同一の構成要素には同一の符号を付している。 FIG. 3A is a diagram showing a cross-sectional configuration of a semiconductor device in which substrates are stacked using a conventional three-dimensional integration technique as a comparative example, and FIG. 3B is the above-described embodiment. It is a figure which shows the cross-sectional structure of the semiconductor device by which a board | substrate is laminated | stacked using this three-dimensional integration technique. 3A and 3B, the same components as those of the semiconductor device according to this embodiment shown in FIG. 1D are denoted by the same reference numerals.
　図３（ａ）に示す比較例では、基板裏面からの突出部分（電極端子部分）の高さにバラツキのある貫通電極５２を有する第２の基板５１と、これらの貫通電極５２に対向する位置に通常のパッド電極である電極端子８を有する第１の基板１とを圧着した際に、貫通電極５２の高さバラツキに起因して、電極端子８と接続していない貫通電極５２が生じてしまう。 In the comparative example shown in FIG. 3A, the second substrate 51 having the through electrode 52 having a variation in the height of the protruding portion (electrode terminal portion) from the back surface of the substrate, and the position facing these through electrodes 52. When the first substrate 1 having the electrode terminal 8, which is a normal pad electrode, is pressure-bonded to the first substrate 1, a through electrode 52 not connected to the electrode terminal 8 is generated due to the height variation of the through electrode 52. End up.
　それに対して、図３（ｂ）に示す本実施形態によれば、基板裏面からの突出部分（電極端子部分）の高さにバラツキのある貫通電極５２を有する第２の基板５１と、これらの貫通電極５２に対向する位置に導電体微粒子５の集合体からなる電極端子９を有する第１の基板１とを圧着した際に、導電体微粒子５の集合体からなる電極端子９が緩衝材として変形して貫通電極５２の高さバラツキを吸収する。すなわち、第１の基板１上の絶縁膜３の各開口部４内における各貫通電極５２の挿入深さは互いに異なる。このため、貫通電極５２の突出部分の高さバラツキによらず、導電体微粒子５の集合体からなる電極端子９と貫通電極５２との電気的接続を確実に達成することができる。すなわち、比較例のように、貫通電極５２の高さバラツキに起因して電極端子８と接続していない貫通電極５２が生じることはない。 On the other hand, according to the present embodiment shown in FIG. 3B, the second substrate 51 having the penetrating electrodes 52 having variations in the height of the protruding portion (electrode terminal portion) from the back surface of the substrate, and these When the first substrate 1 having the electrode terminal 9 made of the aggregate of the conductive fine particles 5 is pressure-bonded to the position facing the through electrode 52, the electrode terminal 9 made of the aggregate of the conductive fine particles 5 serves as a buffer material. By deforming, the height variation of the through electrode 52 is absorbed. That is, the insertion depths of the through electrodes 52 in the openings 4 of the insulating film 3 on the first substrate 1 are different from each other. For this reason, the electrical connection between the electrode terminal 9 formed of the aggregate of the conductive fine particles 5 and the through electrode 52 can be reliably achieved regardless of the height variation of the protruding portion of the through electrode 52. That is, unlike the comparative example, the through electrode 52 not connected to the electrode terminal 8 due to the height variation of the through electrode 52 does not occur.
　従って、本実施形態によれば、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層において、電極端子の高さバラツキ、基板の厚さバラツキ及び基板の反り等に起因する電極端子同士の圧着時の接合不良を防止できるので、信頼性の高い３次元集積化半導体装置を高歩留りで提供することができる。 Therefore, according to the present embodiment, in chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking, electrode terminals are crimped due to variations in electrode terminal height, substrate thickness variation, substrate warpage, and the like. Therefore, a highly reliable three-dimensional integrated semiconductor device can be provided with a high yield.
　尚、本実施形態において、第２の基板５１の貫通電極５２と、第１の基板１の電極端子９との接合を一例として説明したが、これに限定されず、貫通電極５２の代わりに、例えば、第２の基板５１の裏面５１ｂ上又は表面５１ａ上に形成された配線と電気的に接続するパッド電極と、第１の基板１の電極端子９とを接合させてもよい。 In the present embodiment, the bonding between the through electrode 52 of the second substrate 51 and the electrode terminal 9 of the first substrate 1 has been described as an example. However, the present invention is not limited thereto, and instead of the through electrode 52, For example, the pad electrode electrically connected to the wiring formed on the back surface 51b or the front surface 51a of the second substrate 51 and the electrode terminal 9 of the first substrate 1 may be bonded.
　また、本実施形態において、導電体微粒子５の材料として銅を用いたが、これに限らず、例えば、金、銀、白金又はニッケル等の遷移金属を用いることができる。 In the present embodiment, copper is used as the material of the conductive fine particles 5, but the present invention is not limited to this, and for example, a transition metal such as gold, silver, platinum, or nickel can be used.
　また、本実施形態において、導電体微粒子５として、直径（粒径）０．１ｎｍ程度以上１μｍ程度未満の微粒子を用いたが、導電体微粒子５の大きさは特に限定されるものではない。但し、例えば３５０℃程度以下の低温プロセスにおいて導電体微粒子５を溶融させて他の電極端子と接合させるために、導電体微粒子５の平均粒径を５０ｎｍ以下にしてもよいし、より好ましくは、例えば２５０℃程度以下の低温プロセスにおいて導電体微粒子５を溶融させて他の電極端子と接合させるために、導電体微粒子５の平均粒径を４０ｎｍ程度以下にしてもよい。これにより、半導体装置へのダメージを低減しつつ、電極端子同士の接合強度を強くすることができる。尚、導電体微粒子５のうちの過半数の粒径が５０ｎｍ程度以下（より好ましくは４０ｎｍ程度以下）であれば、前述の効果を得ることができる。言い換えると、導電体微粒子５は、５０ｎｍ（より好ましくは４０ｎｍ）を超える粒径の導電体微粒子を含んでいてもよい。また、以上の粒径とプロセス温度との関係は、導電体微粒子が銅の微粒子の場合についてのものであるが、金や銀等の他の金属の微粒子であっても、同様の傾向（粒径の微細化に伴う融点の低下）が見られる。 In the present embodiment, fine particles having a diameter (particle diameter) of about 0.1 nm or more and less than about 1 μm are used as the conductive fine particles 5, but the size of the conductive fine particles 5 is not particularly limited. However, for example, in order to melt the conductor fine particles 5 in a low temperature process of about 350 ° C. or less and join them to other electrode terminals, the average particle diameter of the conductor fine particles 5 may be 50 nm or less, more preferably For example, in order to melt the conductor fine particles 5 and join them to other electrode terminals in a low temperature process of about 250 ° C. or less, the average particle diameter of the conductor fine particles 5 may be about 40 nm or less. Thereby, it is possible to increase the bonding strength between the electrode terminals while reducing damage to the semiconductor device. If the majority of the conductive fine particles 5 have a particle size of about 50 nm or less (more preferably about 40 nm or less), the above-described effects can be obtained. In other words, the conductive fine particles 5 may include conductive fine particles having a particle diameter exceeding 50 nm (more preferably 40 nm). The above relationship between the particle size and the process temperature is for the case where the conductive fine particles are copper fine particles, but the same tendency (grains) is observed even if fine particles of other metals such as gold and silver are used. A decrease in melting point accompanying the refinement of the diameter is observed.
　また、本実施形態において、導電体微粒子５の表面は、有機材料（例えば、3-(6-mercaptohexyl)thiophene）等によってコーティングされていてもよい。このようにすると、導電体微粒子５の酸化を抑制することができるので、導電体微粒子５の集合体からなる電極端子９の抵抗の増大を防止することができる。尚、導電体微粒子５の表面を有機コーティングする場合、導電体微粒子５の生成時にその表面を有機分子によって被覆する。これにより、導電体微粒子５の凝集を防止して微粒子状態を安定化させることができると共に導電体微粒子５の酸化も防止することができる。 In the present embodiment, the surface of the conductive fine particles 5 may be coated with an organic material (eg, 3- (6-mercaptohexyl) thiophene). In this way, since the oxidation of the conductive fine particles 5 can be suppressed, an increase in the resistance of the electrode terminal 9 made of the aggregate of the conductive fine particles 5 can be prevented. When the surface of the conductive fine particles 5 is organically coated, the surface of the conductive fine particles 5 is covered with organic molecules when the conductive fine particles 5 are generated. Thereby, aggregation of the conductive fine particles 5 can be prevented to stabilize the fine particle state, and oxidation of the conductive fine particles 5 can also be prevented.
　また、本実施形態に係る半導体装置及びその製造方法は、チップ－チップ積層（ウェハダイシングにより得られたチップ状態の半導体装置同士の積層）、チップ－ウェーハ積層（チップ状態の半導体装置と、ダイシング前のウェーハ状態の半導体装置との積層）、又はウェーハ－ウェーハ積層（ウェーハ状態の半導体装置同士の積層）された半導体装置及びその製造方法のいずれにも適用可能である。 In addition, the semiconductor device and the manufacturing method thereof according to the present embodiment include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device). The semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
　以上に説明したように、本発明に係る半導体装置及びその製造方法は、電極端子の高さバラツキ、基板の厚さバラツキ及び基板の反り等に起因する各基板の電極端子同士の圧着時の接合不良を防止できるものであり、特に、基板のチップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層による３次元集積化等において有用である。 As described above, the semiconductor device and the manufacturing method thereof according to the present invention are bonded at the time of pressure bonding between the electrode terminals of each substrate due to the height variation of the electrode terminals, the substrate thickness variation, the substrate warpage, and the like. It can prevent defects, and is particularly useful in three-dimensional integration by chip-chip lamination, chip-wafer lamination, or wafer-wafer lamination on a substrate.
　　　１　　第１の基板
　　　１ａ　　第１の基板の表面
　　　１ｂ　　第１の基板の裏面
　　　２　　配線層
　　　３　　絶縁膜
　　　４　　開口部
　　　５　　導電体微粒子
　　　６　　トランジスタ
　　　７　　コンタクト
　　　９　　電極端子
　　５１　　第２の基板
　　５１ａ　　第２の基板の表面
　　５１ｂ　　第２の基板の裏面
　　５２　　貫通電極
　　５３　　絶縁膜
　　５４　　トランジスタ
　　５５　　コンタクト
　　５６　　配線層 DESCRIPTION OF SYMBOLS 1 1st board | substrate 1a The surface of 1st board | substrate 1b The back surface of 1st board | substrate 2 Wiring layer 3 Insulating film 4 Opening part 5 Conductive particle 6 Transistor 7 Contact 9 Electrode terminal 51 2nd board | substrate 51a 2nd board | substrate Front surface 51b Back surface of second substrate 52 Through electrode 53 Insulating film 54 Transistor 55 Contact 56 Wiring layer

Claims (18)

  1. 　第１の基板と、
    　前記第１の基板上に形成された配線と、
    　前記配線を覆うように前記第１の基板上に形成された絶縁膜と、
    　前記絶縁膜に、前記配線が露出するように形成された開口部と、
    　前記開口部内に形成され且つ複数の導電体微粒子から構成されている第１の電極端子とを備えていることを特徴とする半導体装置。     A first substrate;
    Wiring formed on the first substrate;
    An insulating film formed on the first substrate so as to cover the wiring;
    An opening formed in the insulating film so that the wiring is exposed;
    A semiconductor device comprising: a first electrode terminal formed in the opening and made of a plurality of conductive fine particles.
  2. 　請求項１に記載の半導体装置において、
    　前記複数の導電体微粒子のそれぞれの表面は有機材料によってコーティングされていることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A surface of each of the plurality of conductive fine particles is coated with an organic material.
  3. 　請求項１又は２に記載の半導体装置において、
    　前記複数の導電体微粒子の平均粒径は、５０ｎｍ以下であることを特徴とする半導体装置。     The semiconductor device according to claim 1 or 2,
    An average particle diameter of the plurality of conductive fine particles is 50 nm or less.
  4. 　請求項１～３のいずれか１項に記載の半導体装置において、
    　前記複数の導電体微粒子は遷移金属からなることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 3,
    The semiconductor device, wherein the plurality of conductive fine particles are made of a transition metal.
  5. 　請求項１～４のいずれか１項に記載の半導体装置において、
    　前記複数の導電体微粒子は金、銀又は銅からなることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 4,
    The semiconductor device, wherein the plurality of conductive fine particles are made of gold, silver, or copper.
  6. 　請求項１～５のいずれか１項に記載の半導体装置において、
    　表面又は裏面から突出した第２の電極端子を有する第２の基板をさらに備え、
    　前記第１の基板と前記第２の基板とは、前記第１の電極端子と前記第２の電極端子とが接続するように積層されており、
    　前記第２の電極端子は、前記第１の電極端子となる前記複数の導電体微粒子の集合体の形状を変形させて前記開口部内に挿入されていることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 5,
    A second substrate having a second electrode terminal protruding from the front surface or the back surface;
    The first substrate and the second substrate are laminated so that the first electrode terminal and the second electrode terminal are connected,
    The semiconductor device, wherein the second electrode terminal is inserted into the opening by changing the shape of the aggregate of the plurality of conductive fine particles to be the first electrode terminal.
  7. 　請求項６に記載の半導体装置において、
    　前記第２の電極端子は、前記第２の基板に形成された貫通電極の一部であることを特徴とする半導体装置。     The semiconductor device according to claim 6.
    The semiconductor device according to claim 1, wherein the second electrode terminal is a part of a through electrode formed on the second substrate.
  8. 　第１の基板と、
    　前記第１の基板上に形成された配線と、
    　前記配線を覆うように前記第１の基板上に形成された絶縁膜と、
    　前記絶縁膜に、前記配線が露出するように形成された複数の開口部と、
    　前記複数の開口部内に形成され且つ複数の導電体微粒子から構成されている複数の第１の電極端子と、
    　表面又は裏面から突出した複数の第２の電極端子を有する第２の基板とを備え、
    　前記第１の基板と前記第２の基板とは、前記複数の第１の電極端子と前記複数の第２の電極端子とが接続するように積層されており、
    　前記複数の第２の電極端子は、前記複数の第１の電極端子のそれぞれとなる前記複数の導電体微粒子の集合体の形状を変形させて前記複数の開口部内に挿入されており、
    　前記複数の開口部内における前記複数の第２の電極端子の挿入深さが互いに異なることを特徴とする半導体装置。     A first substrate;
    Wiring formed on the first substrate;
    An insulating film formed on the first substrate so as to cover the wiring;
    A plurality of openings formed in the insulating film so that the wiring is exposed;
    A plurality of first electrode terminals formed in the plurality of openings and composed of a plurality of conductive fine particles;
    A second substrate having a plurality of second electrode terminals protruding from the front surface or the back surface,
    The first substrate and the second substrate are laminated so that the plurality of first electrode terminals and the plurality of second electrode terminals are connected,
    The plurality of second electrode terminals are inserted into the plurality of openings by changing the shape of the aggregate of the plurality of conductive fine particles, which respectively become the plurality of first electrode terminals,
    The semiconductor device, wherein insertion depths of the plurality of second electrode terminals in the plurality of openings are different from each other.
  9. 　第１の基板上に配線を形成する工程（ａ）と、
    　前記配線を覆うように前記第１の基板上に絶縁膜を形成する工程（ｂ）と、
    　前記絶縁膜に、前記配線層が露出するように開口部を形成する工程（ｃ）と、
    　前記開口部内に、複数の導電体微粒子からなる第１の電極端子を形成する工程（ｄ）とを備えていることを特徴とする半導体装置の製造方法。     Forming a wiring on the first substrate (a);
    Forming an insulating film on the first substrate so as to cover the wiring (b);
    Forming an opening in the insulating film such that the wiring layer is exposed;
    And (d) forming a first electrode terminal made of a plurality of conductive fine particles in the opening.
  10. 　請求項９に記載の半導体装置の製造方法において、
    　前記複数の導電体微粒子のそれぞれの表面は有機材料によってコーティングされていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 9,
    A method of manufacturing a semiconductor device, wherein the surface of each of the plurality of conductive fine particles is coated with an organic material.
  11. 　請求項９又は１０に記載の半導体装置の製造方法において、
    　前記複数の導電体微粒子の平均粒径は５０ｎｍ以下であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 9 or 10,
    The semiconductor device manufacturing method, wherein an average particle diameter of the plurality of conductive fine particles is 50 nm or less.
  12. 　請求項９～１１のいずれか１項に記載の半導体装置の製造方法において、
    　前記複数の導電体微粒子は遷移金属からなることを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 9 to 11,
    The method of manufacturing a semiconductor device, wherein the plurality of conductive fine particles are made of a transition metal.
  13. 　請求項９～１２のいずれか１項に記載の半導体装置の製造方法において、
    　前記複数の導電体微粒子は金、銀又は銅からなることを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 9 to 12,
    The method for manufacturing a semiconductor device, wherein the plurality of conductive fine particles are made of gold, silver, or copper.
  14. 　請求項９～１３のいずれか１項に記載の半導体装置の製造方法において、
    　前記工程（ｄ）は、前記開口部内を含む前記絶縁膜上に前記複数の導電体微粒子を層状に堆積した後、前記開口部の外側の前記複数の導電体微粒子を除去する工程を含むことを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 9 to 13,
    The step (d) includes a step of removing the plurality of conductor fine particles outside the opening after depositing the plurality of conductor fine particles in layers on the insulating film including the inside of the opening. A method of manufacturing a semiconductor device.
  15. 　請求項９～１４のいずれか１項に記載の半導体装置の製造方法において、
    　表面又は裏面から突出した第２の電極端子を有する第２の基板を準備する工程（ｅ）と、
    　前記第１の基板と前記第２の基板とを、前記第１の電極端子と前記第２の電極端子とが接続するように積層する工程（ｆ）とをさらに備え、
    　前記工程（ｆ）は、前記第１の電極端子となる前記複数の導電体微粒子の集合体の形状を変形させて前記第２の電極端子を前記開口部内に挿入する工程を含むことを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to any one of claims 9 to 14,
    Preparing a second substrate having a second electrode terminal projecting from the front surface or the back surface (e);
    A step (f) of laminating the first substrate and the second substrate so that the first electrode terminal and the second electrode terminal are connected,
    The step (f) includes a step of deforming a shape of the aggregate of the plurality of conductive fine particles to be the first electrode terminal and inserting the second electrode terminal into the opening. A method for manufacturing a semiconductor device.
  16. 　請求項１５に記載の半導体装置の製造方法において、
    　前記第２の電極端子は、前記第２の基板に形成された貫通電極の一部であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 15,
    The method of manufacturing a semiconductor device, wherein the second electrode terminal is a part of a through electrode formed on the second substrate.
  17. 　請求項１５又は１６に記載の半導体装置の製造方法において、
    　前記工程（ｆ）は、熱処理によって前記複数の導電体微粒子を溶融させて前記第２の電極端子と接合させる工程を含むことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 15 or 16,
    The step (f) includes a step of melting the plurality of conductive fine particles by a heat treatment and bonding them to the second electrode terminal.
  18. 　第１の基板上に配線を形成する工程（ａ）と、
    　前記配線を覆うように前記第１の基板上に絶縁膜を形成する工程（ｂ）と、
    　前記絶縁膜に、前記配線層が露出するように複数の開口部を形成する工程（ｃ）と、
    　前記複数の開口部内に、複数の導電体微粒子からなる複数の第１の電極端子を形成する工程（ｄ）と、
    　表面又は裏面から突出した複数の第２の電極端子を有する第２の基板を準備する工程（ｅ）と、
    　前記第１の基板と前記第２の基板とを、前記複数の第１の電極端子と前記複数の第２の電極端子とが接続するように積層する工程（ｆ）とを備え、
    　前記工程（ｆ）は、前記複数の第１の電極端子のそれぞれとなる前記複数の導電体微粒子の集合体の形状を変形させて前記複数の第２の電極端子を前記複数の開口部内に挿入する工程を含み、
    　前記複数の開口部内における前記複数の第２の電極端子の挿入深さが互いに異なることを特徴とする半導体装置の製造方法。     Forming a wiring on the first substrate (a);
    Forming an insulating film on the first substrate so as to cover the wiring (b);
    A step (c) of forming a plurality of openings in the insulating film so that the wiring layer is exposed;
    A step (d) of forming a plurality of first electrode terminals made of a plurality of conductive fine particles in the plurality of openings;
    Preparing a second substrate having a plurality of second electrode terminals protruding from the front surface or the back surface (e);
    And laminating the first substrate and the second substrate so that the plurality of first electrode terminals and the plurality of second electrode terminals are connected to each other (f),
    The step (f) inserts the plurality of second electrode terminals into the plurality of openings by deforming the shape of the aggregate of the plurality of conductive fine particles that are the plurality of first electrode terminals, respectively. Including the step of
    A method for manufacturing a semiconductor device, wherein insertion depths of the plurality of second electrode terminals in the plurality of openings are different from each other.
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