JPH10223833A - Multi-chip semiconductor device chip for multi-chip semiconductor device and its formation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip semiconductor device whose device area is small, whose constitution is simple and whose thickness is thin by providing a connection plug formed of metal in a through hole passing through a semiconductor substrate and an inter-layer insulating film and electrically connecting one chip with the other chip through the connection plug. SOLUTION: A metal plug 4 is formed on the outer side of an element forming area and the insulating films 5 are provided between the metal plug 4 and the silicon substrate 1/the first inter-layer insulating film so as to constitute the connection plug. The metal plug 4 of the chip 11 is electrically connected to the pad 6 provided for the multilayer wiring layer 3 of the chip 12 through a solder bump 8. The chip 11 is electrically connected to the chip 12 . The metal plug 4 of the chip 12 is electrically connected to the pad 6 provided for the multilayer wiring layer 3 of the chip 13 through the solder bump 8. Thus, the chips 11 , 12 and 13 are electrically connected. Since the chips 11 , 12 and 13 are stacked, the device area is prevented from increasing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multichip semiconductor device which is a semiconductor device using a plurality of chips, a chip for a multichip semiconductor layer, and a method for forming the same.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (ICs) formed by integrating a large number of transistors, resistors, and the like on an important part of a computer or a communication device so as to achieve an electric circuit, and integrating them on a semiconductor substrate. Chips) are frequently used. For this reason, the performance of the entire device is greatly linked to the performance of the chip alone.

On the other hand, a so-called multi-chip semiconductor device using a plurality of chips to improve the performance of the entire device has been proposed. 25 to 27 show sectional views of a conventional multichip semiconductor device.

FIG. 25 shows, for example, a multi-chip semiconductor device of a type in which a plurality of chips 82 are arranged on a stacked wiring substrate 81 in a plane. In the drawing, reference numeral 83 denotes a solder bump. FIG. 26 illustrates a multichip semiconductor device in which chips are connected to each other with their surfaces facing each other (face to face).
FIG. 27 shows a multichip semiconductor device of a type in which a plurality of chips 82 are stacked and arranged using a stacked plate 84.

[0005]

However, these conventional multi-chip semiconductor devices have the following problems.

That is, the conventional multi-chip semiconductor device shown in FIG. 25 has a problem that the plane area of the device is large because a plurality of chips 82 are arranged on a plane.

In the conventional multi-chip semiconductor device shown in FIG. 26, since a plurality of chips 82 are stacked, there is no problem that the planar area of the device becomes large, but there is a problem that the number of stacked devices is limited to two. is there. Also, it is difficult to electrically test each chip.

In the conventional multi-chip semiconductor device shown in FIG. 27, since a plurality of chips 82 can be stacked, there is no problem that the planar area of the device becomes large or the number of stacked devices is limited to two. Since it is necessary to provide the laminated plate 84 between the chips, the structure becomes complicated and the cost and thickness increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a multi-chip semiconductor device having a small plane area, a simple structure, and a small thickness. It is in. Another object of the present invention is to provide a chip for a multi-chip semiconductor device and a method for forming the same, which can realize such a multi-chip semiconductor device.

[0010]

[Means for Solving the Problems]

[Structure] In order to achieve the above object, a multichip semiconductor device according to the present invention (Claim 1) comprises a semiconductor substrate on which elements are integrated and formed, and an interlayer insulating film formed on the surface of the semiconductor substrate. A multi-chip semiconductor device formed by stacking a plurality of chips having a structure in which at least one chip has a structure in which a connection plug made of metal is formed in a through hole penetrating the semiconductor substrate and the interlayer insulating film; Further, at least one chip having the connection plug is electrically connected to another chip via the connection plug.

The interlayer insulating film is a first layer interlayer insulating film covering the element.

Further, in another multi-chip semiconductor device according to the present invention (claim 2), in the multi-chip device (claim 1), the chip having the connection plug is the same as the chip immediately above and below the chip. It is characterized by being electrically connected to at least one of the chips via a connection member or a connection member and a mounting member.

The connection member is, for example, a metal bump, and the mounting member is, for example, a wiring board or a TAB tape.

According to another aspect of the present invention, there is provided a multi-chip semiconductor device comprising: a semiconductor substrate having elements formed on a surface thereof; an interlayer insulating film formed on the surface of the semiconductor substrate; A connection plug formed in a through hole penetrating the insulating film and the semiconductor substrate and made of metal for electrically connecting to another chip is provided.

Further, in another multi-chip semiconductor device according to the present invention (claim 4), in the multi-chip semiconductor device chip (claim 3), the connection plug is formed of a metal provided in the through hole. It is characterized by comprising a plug and an insulating film provided between the metal plug and a side wall of the through hole.

According to another aspect of the present invention, there is provided a chip for a multi-chip semiconductor device, wherein the connection plug is provided in the through-hole. A metal plug having a hollow portion, an insulating film provided between the metal plug and a side wall of the through hole, and a difference in thermal expansion coefficient between the metal plug and the semiconductor substrate provided in the hollow portion. And a smaller low stress film.

In the chip for a multi-chip semiconductor device according to the present invention (claim 6), in the above-mentioned chip for a multi-chip semiconductor device (claim 3), the connection plug may be provided on a surface side of the semiconductor substrate of the through hole. A metal plug provided to an intermediate depth, an insulating film provided between the metal plug and a side wall of the through hole, and a cap film provided on the metal plug and filling the through hole. It is characterized by having been done.

According to another aspect of the present invention, there is provided a multi-chip semiconductor device chip according to the present invention, wherein the connection plug is formed in the through-hole of the semiconductor substrate. A metal plug provided up to an intermediate depth on the back side of the substrate, and an insulating film provided between the metal plug and a side wall of the through hole. And a connection member for electrically connecting to the connection member is provided.

Here, it is preferable that the back surface of the semiconductor substrate on the side where the connection member is provided is covered with an insulating film except for the portion of the connection member.

According to a second aspect of the present invention, there is provided a method of forming a chip for a multi-chip semiconductor device, comprising the steps of: forming an element on a semiconductor substrate surface; and forming an interlayer insulating film on the semiconductor substrate surface. Forming a hole that penetrates the interlayer insulating film and does not penetrate the semiconductor substrate by etching the interlayer insulating film and the semiconductor substrate; and forming a hole that does not fill the hole on a side wall and a bottom of the hole. Forming an insulating film, and filling a metal as a metal plug into the hole covered with the insulating film, and receding the semiconductor substrate and the insulating film from the back surface of the semiconductor substrate, Exposing the metal plug at the bottom of the hole. According to another aspect of the present invention, there is provided a method of forming a chip for a multi-chip semiconductor device, comprising the steps of: forming an element on a semiconductor substrate surface; and forming an interlayer insulating film on the semiconductor substrate surface. Forming a hole that penetrates the interlayer insulating film and does not penetrate the semiconductor substrate by etching the interlayer insulating film and the semiconductor substrate, and a thickness that does not fill the hole on sidewalls and a bottom of the hole. Forming a first insulating film, filling the inside of the hole with a second insulating film having a higher etching rate than the first insulating film, forming a connection hole in the interlayer insulating film, Forming a wiring layer connected to the element through the connection hole; and retreating the semiconductor substrate and the first insulating film from the back surface of the semiconductor substrate to form a second insulating layer at the bottom of the hole. Step of exposing the film Selectively etching and removing the second insulating film in the hole, and then filling a metal as a metal plug into the hole covered with the first insulating film. I do.

According to another aspect of the present invention, there is provided a method for forming a chip for a multi-chip semiconductor device, comprising the steps of: forming an element on a semiconductor substrate surface; and forming an interlayer insulating film on the semiconductor substrate surface. And etching the interlayer insulating film and the semiconductor substrate to form a hole that penetrates the interlayer insulating film and does not penetrate the semiconductor substrate, and fills the side wall and bottom of the hole with the hole. Forming a first insulating film having a thickness not to be changed, filling a hole as a metal plug into the hole covered with the first insulating film, and forming a first insulating film at a bottom of the hole. Retreating the semiconductor substrate from the back surface of the semiconductor substrate until the insulating film is exposed; and exposing the first insulating film on the side wall of the hole above the first insulating film at the bottom of the hole. Until the bottom of the hole Selectively etching the semiconductor substrate on the side, forming a second insulating film on the entire back surface of the semiconductor substrate on the bottom side of the hole, and exposing the metal plug at the bottom of the hole. The first and second
Retreating the insulating film, and selectively leaving the second insulating film on the back surface of the semiconductor substrate on the bottom side of the hole.

According to another aspect of the present invention, there is provided a method for forming a chip for a multi-chip semiconductor device (claim 11).
In 0), the formation of the hole is performed before forming the wiring having the lowest melting point among the wirings formed on the semiconductor substrate.

According to another aspect of the present invention, there is provided a method for forming a chip for a multi-chip semiconductor device (claim 12).
0), wherein the retreating of the semiconductor substrate is performed after the semiconductor substrate is cut out from a wafer.

According to the present invention (claims 1 and 2), since a plurality of chips are stacked, unlike a conventional multi-chip semiconductor device in which a plurality of chips are arranged in a plane, the plane area of the device is different from that of the prior art. There is no problem of the increase.

According to the present invention, the chips are connected to each other by the connection plug made of metal formed in the through hole penetrating the semiconductor substrate and the interlayer insulating film.
Unlike a conventional multi-chip semiconductor device in which chips are connected by face-to-face, there is no problem that the number of stacked chips is limited to two.

Further, since a laminated board is not used for connecting the chips, unlike the conventional multi-chip semiconductor device in which the chips are connected by the laminated board, the structure becomes complicated and the thickness is increased. Absent.

Therefore, according to the present invention, a multi-chip semiconductor device having a small planar area, a simple structure, and a small thickness can be realized.

Further, the multi-chip semiconductor device chip of the present invention (claims 3 to 7) is formed in a through-hole penetrating the semiconductor substrate and the interlayer insulating film, and is used for electrically connecting to another chip. It has a connection plug made of metal.

Therefore, a multi-chip semiconductor device using such a chip for a multi-chip semiconductor device has a small planar area, a simple structure, and the same effect as the present invention (claims 1 and 2). The thickness becomes thin.

In the present invention (claims 1 to 7), the connection plug has an effect of promoting heat radiation of the chip. Further, the device or the chip can be inspected by applying an inspection probe to the connection plug from the back surface of the chip.

Further, according to the present invention (claim 8), a through hole penetrating the semiconductor substrate and the interlayer insulating film is not directly formed. This is because semiconductor substrates are generally thick and it is difficult to directly open through holes.

That is, in the present invention, first, a hole which penetrates the interlayer insulating film but does not penetrate the semiconductor substrate is formed, and then a metal film as a connection plug is formed in the hole via the insulating film.

After such a step, according to the present invention, by retracting the semiconductor substrate and the insulating film from the surface opposite to the surface on which the holes are formed, and exposing the metal film on the bottom side of the holes, A through hole is formed. Therefore, according to the present invention, a through hole can be easily formed even if the original semiconductor substrate is thick.

According to the present invention (claim 9), a connection hole is formed in the interlayer insulating film in a state where the inside of the hole is filled with the second insulating film having a higher etching rate than the first insulating film. A wiring layer connected to the element is formed through the connection hole, and then the second insulating film is selectively removed by etching to form a metal film in the hole. For this reason, the metal film does not need to be affected by a high-temperature process when forming the wiring layer.

Thus, it is possible to prevent the characteristics of the chip from deteriorating due to the diffusion of the constituent elements of the metal film into the semiconductor substrate. Also, unlike the case where a diffusion prevention structure such as a barrier film is formed to prevent the diffusion of the constituent elements of the metal film, the process does not become complicated.

Further, according to the present invention (claim 10), the through hole can be easily formed, and the exposed surface of the semiconductor substrate on the bottom side of the hole can be easily covered with the second insulating film.

It is preferable that the retreat of the semiconductor substrate is performed after the semiconductor substrate is cut out from the wafer as in the present invention (claim 12). This is because wafers are generally large and have low mechanical strength, making it difficult to uniformly retreat by polishing or etching.

[0038]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of the multi-chip semiconductor device according to the embodiment.

This multi-chip semiconductor device has a configuration in which _three chips 1 ₁ , 1 ₂ and 13 are stacked.
Each chip 1 _1, 1 _2, 1 _3, respectively, roughly, a silicon substrate 2 which elements are integrated on the surface, a multilayer wiring layer 3 for connecting the integrated forming elements in a predetermined relationship A connection plug (metal plug 4, insulating film 5) formed in a through hole penetrating through the first interlayer insulating film of the multilayer wiring layer 3 and the silicon substrate 1 to electrically connect the chips. It is configured.

The multilayer wiring layer 3 has a first interlayer insulating film covering the device and a first interlayer insulating film connected to the device via a contact hole (first connection hole) formed in the first interlayer insulating film. A wiring layer, a second interlayer insulating film formed on the first interlayer insulating film and covering the first wiring layer, and a via hole (second connection hole) formed in the second interlayer insulating film First through
And a second wiring layer connected to the wiring layer. In addition, 3
It may be a multilayer wiring layer having more than two layers.

The metal plug 4 is formed outside the element formation region. Also, between the metal plug 4 and the silicon substrate 1 and the first interlayer insulating film, in other words, the metal plug 4
An insulating film 5 is provided between the gate and the through hole. The insulating film 5 and the metal plug 4 form a connection plug.

[0043] Further, each chip ₁ 1, 1 _2, 1 ₃ of the wiring layer 3, respectively, the pad 6 is provided. Further, each chip 1 _1, 1 _2, 1 ₃ of the opposite rear surface of the silicon region of the silicon substrate 2 of the pad 6, in other words the connection plug (metal plugs 4, the insulating film 5) other than the region with the insulating film 7 Coated.

The chip 1 ₁ metal plug 4 via the solder bumps 8 are electrically connected to the pad 6 formed on the multilayer wiring layer 3 of the chip 1 _2. Thereby, chip 1
₁ will be electrically connected to the chip 1 _2. In addition,
A bump other than the solder bump 8 may be used.

[0045] Similarly, metal plug 4 of the chip 1 ₂ via the solder bumps 8, electrically connected to the pad 6 formed on the multilayer wiring layer 3 of the chip 1 _3, chip 1 ₂ chip 1 ₃ Is electrically connected to Thus, chip 1
_1, 1 _2, 1 ₃ between will be electrically connected.

According to the present embodiment, the chips 1 ₁ , 1 ₂ ,
Since the stacking 1 _3, unlike the conventional multi-chip semiconductor device which plane position a plurality of chips, there is no problem that the planar area of the device increases.

According to the present embodiment, the chips are connected to each other by the metal plug 4 penetrating the silicon substrate 2 and the first interlayer insulating film.
Unlike a conventional multi-chip semiconductor device in which chips are connected by Face, there is no problem that the number of stacked chips is limited to two.

Further, since a laminated board is not used for connecting the chips, unlike the conventional multi-chip semiconductor device in which the chips are connected by the laminated board, the structure becomes complicated and the thickness is increased. Absent.

Further, the metal plug 4 has an effect of promoting heat radiation.

Therefore, according to the present embodiment, a multi-chip semiconductor device having a small planar area, a simple structure, a small thickness, and excellent heat dissipation can be realized.

Although the embodiment has been described in connection with the case where the number of chips is three, four or more chips can be connected in the same manner with the chip structure of this embodiment. Also,
Not all the chips having the metal plugs 4 need to be connected via the metal plugs 4. That is, there may be a chip in which the metal plug 4 is formed only for the purpose of improving the heat radiation.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of the multi-chip semiconductor device according to the embodiment. Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as those of FIG. 1, and detailed description is omitted.

[0053] The present embodiment, only the middle of the chip 1 ₂ connection plug (metal plugs 4, the insulating film 5) is an example having a.

[0054] pads provided on the wiring layer 3 of the chip ₁ 6 via the solder bumps 8 are electrically connected to the pad 6 formed on the multilayer wiring layer 3 of the chip 1 _2. Thus, the chip ₁ will be electrically connected to the chip 1 _2. The metal plug 4 of the chip 1 ₂ via the solder bumps 8, electrically connected to the pad 6 formed on the multilayer wiring layer 3 of the chip 1 _3, chip 1 ₂ chip 1 ₃
Is electrically connected to In this way, chips 1 ₁ ,
1 _2, 1 ₃ between will be electrically connected.

In this embodiment, the same effects as in the first embodiment can be obtained. However, only the middle only chip 1 ₂ connection plug (metal plugs 4, the insulating film 5) because it does not have, it is not possible to stack four or more chips. However, only one connection plug is required, which is advantageous in cost.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view of the multi-chip semiconductor device according to the embodiment. Parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as those of FIG. 1, and detailed description is omitted.

This embodiment is an example in which two chips 1 ₁ and 1 ₂ are connected via a laminated wiring board 9 made of ceramic.

The pads 6 provided on the multilayer wiring layer 3 of the chip ₁ are electrically connected to the pads 6 provided on the laminated wiring board 9 via the solder bumps 8. This pad 6
Other pads 6 provided on the multilayer wiring board 9 are electrically connected to is electrically connected to the pad 6 formed on the multilayer wiring layer 3 of the chip 1 _2. This allows the chip
₁ will be electrically connected to the chip 1 _2.

In this embodiment, the same effects as in the first embodiment can be obtained. Further, according to the present embodiment, the chip 1
_The device can be inspected by applying an inspection probe to the pad 6 provided on the _second multilayer wiring layer 3.

[0060] In contrast, as shown in FIG. 2, the chip 1 ₂ having a metal plug 4 that's configured in between the chips,
Such an inspection cannot be performed because the inspection probe cannot be applied.

(Fourth Embodiment) FIGS. 4 and 5 are process sectional views showing a method for forming a chip for a multichip semiconductor device according to a fourth embodiment of the present invention.

First, as shown in FIG. 4A, a silicon substrate 10 is prepared. The silicon substrate 10 has been formed after the device has been formed, and its surface is covered with a first interlayer insulating film 11. As a material of the first interlayer insulating film 11, a material having an etching selectivity with respect to SiO ₂ such as silicon nitride is selected.

Next, as shown in FIG. 4B, after a mask pattern 12 made of SiO ₂ and having a thickness of 1 μm is formed on the first interlayer insulating film 11, an etching gas is formed using the mask pattern 12 as a mask. Etches the first interlayer insulating film 11 and the silicon substrate 10 by the RIE method using an F-based gas to form a hole 13 that penetrates the first interlayer insulating film 11 but does not penetrate the silicon substrate 10. . Thereafter, it is preferable to perform annealing for recovering a defect of the silicon substrate 10 generated at the time of forming the hole 13.

The depth of the hole in the silicon substrate 10 is 10
0 μm. The total depth of the holes 13 is obtained by adding the thickness of the first interlayer insulating film 11 to this. The hole 13 eventually becomes a through hole.

The silicon substrate 10 is etched by RIE to form holes, then a first interlayer insulating film 11 is formed, and then the first interlayer insulating film 11 or the first interlayer insulating film 11 is formed. The hole 13 can be formed by etching the film 11 and the silicon substrate 10 by RIE.

In this case, as a mask pattern used at the time of the first etching, SiO ₂ , Al or Al ₂ O ₃
Materials made of such materials can be used.

Further, the processing technique for forming the holes 13 (through holes) is not limited to RIE.
Wet etching, ultrasonic machining, and electric discharge machining can also be used. Further, the above processing techniques may be appropriately combined. A method in which RIE or optical etching is combined with wet etching will be described later.

Next, as shown in FIG. 4C, a 100-nm-thick SiO ₂ film and a 100-nm-thick Si ₃ N ₄
Films are sequentially deposited by using the LPCVD method, and SiO ₂ / S
An i ₃ N ₄ laminated insulating film 14 (first insulating film) is formed. Note that a single-layer insulating film may be used instead of the stacked insulating film 14.

Next, as shown in FIG. 4D, a metal film 15 serving as a metal plug is formed on the entire surface so as to overflow the hole 13, and the hole 13 is filled with the metal film 15.

Here, as the metal film 15, for example, W
Films, Mo films, Ni films, Ti films, and metal silicide films thereof. Examples of the method for forming the metal film 15 include a CVD method, a sputtering method, and a plating method.

Next, as shown in FIG. 5E, the first interlayer insulating film 1 is formed by using a method such as a CMP method or an etch-back method.
1 until the surface of the metal film 15 is exposed.
Retreat.

As a result, a metal film (metal plug) is formed in the hole 13.
15 is formed. Such a structure can be formed by other forming methods. The formation method will be described later (FIGS. 14 and 15).

Next, as shown in FIG. 5F, a multilayer wiring structure 16 constituting a multilayer wiring layer is formed on the silicon substrate 10 together with the first interlayer insulating film 11. Multilayer wiring structure 1
Reference numeral 6 includes a metal wiring (wiring layer), an interlayer insulating film, a plug and the like. Thereafter, a groove is formed on the surface of the multilayer wiring structure 16, and a pad 17 is formed in the groove.

FIGS. 6 and 7 show examples of specific structures of the multilayer wiring layer in the region of the hole 13 and the multilayer wiring layer in the element region, respectively.

In the element region, a MOS transistor is formed. In the figure, 11a is a second interlayer insulating film, 11b is a third interlayer insulating film, 11c is a fourth interlayer insulating film, 11n is an nth interlayer insulating film, 19a and 20a.
a indicates a first metal wiring, 19b and 20b indicate second metal wirings, and 20c indicates a third metal wiring.

Next, as shown in FIG. 5G, the silicon substrate 10 is removed from the back surface of the silicon substrate opposite to the surface where the holes 13 are formed until the insulating film 14 at the bottom of the holes 13 is exposed.
Retreat.

Here, the silicon substrate 10 is set back (thinned).
Is performed by, for example, a method using a processing technique of CMP, chemical polishing, mechanical polishing, wet etching, plasma etching, or gas etching, or a method combining these processing techniques. Of these, CMP is the most representative method and is preferred.

In the step of FIG.
It is preferable to perform the process under the condition that a selectivity can be obtained between 0 and the insulating film 14. Under such conditions, the same step can be automatically completed at the insulating film 14.

Next, as shown in FIG. 5H, the silicon substrate 10 on the bottom side of the hole 13 is exposed until the insulating film 14 on the side wall of the hole 13 is exposed above the insulating film 14 on the bottom of the hole 13. The back surface is selectively etched. For this etching, for example, dry etching such as CDE or RIE or wet etching is used. Note that instead of etching, C
MP may be used.

Thereafter, the damaged layer caused by the etching or the CMP is removed by, for example, wet etching. Note that this removal step is unnecessary when no damage layer is formed. The reason for removing the damaged layer is
This is because the damaged layer affects the next step of forming the SiO ₂ film 18.

Next, as shown in FIG.
The silicon substrate 10 on the bottom side of the hole 13 is formed by using the VD method.
To the entire back surface forming a SiO ₂ film 18 (second insulating film). When a low-temperature process is required, SiO 2
A coating film such as an SOG film may be used instead of the _two films 18. When it is desired to reduce the stress applied to the silicon substrate 10, an organic film such as a polyimide film may be used instead of the SiO ₂ film 18.

Next, as shown in FIG. 5 (i), the SiO ₂ film 1 is
8. The laminated insulating film 14 is polished.

As a result, the insulating film 1 is formed in the through hole (hole 13).
A connection plug consisting of 4 and a metal plug 15 is embedded,
The silicon region on the back surface of the silicon substrate 10 is made of SiO ₂
The structure covered with the film 18 is completed.

As described above, in the present embodiment, after the hole 13 that does not penetrate the silicon substrate 10 is formed on the surface of the silicon substrate 10, the silicon substrate 10 and the like are polished from the back surface to form the through hole (hole). 13) forms a structure in which the inside is filled with connection plugs (insulating film 14, metal plug 15).

Therefore, according to the present embodiment, even if the original silicon substrate 1 is thick (usually thick), it is not necessary to form a deep through-hole, so that the through-hole (hole 13) is connected to the connection plug (insulating). The structure embedded with the film 14 and the metal plug 15) can be easily formed.

The method of this embodiment is different from the method of forming a deep through-hole by etching from the back surface of a thick silicon substrate, and eliminates the need for photolithography which requires alignment of the front / back pattern. Therefore, the process of forming the connection plug is simple and the number of steps is small.

[0087] Incidentally, SiO ₂ film 1 a back surface of the silicon region
If the metal plug 15 does not need to be covered, the silicon substrate 10 and the laminated insulating film 14 are polished until the metal plug 15 is exposed in the step of FIG. The structure buried with (the insulating film 14 and the metal plug 15) is completed.

Polishing (retreating) of the silicon substrate 10
Is preferably performed after cutting the silicon substrate 10 from the wafer. Because wafers are generally large,
This is because it is difficult to uniformly polish (retreat) since the mechanical strength is low.

Further, since the hole 13 is formed before the formation of the metal wiring, and the metal film is buried therein to form the metal plug 15, the metal wiring is affected by the heat process when the metal plug 15 is formed. You don't have to. Furthermore, the metal wiring is not affected by annealing for defect recovery performed after the hole 13 is formed by RIE.

Thus, for example, when an Al wiring (the melting point of Al is 660 ° C.) is used as the metal wiring, the metal plug 15 is formed of a conductive paste such as Au having a low resistance (sintering temperature is about 600 ° C.). It becomes possible.

Further, since the metal plug 15 is formed after the element is formed, deterioration of the element characteristics due to diffusion of the constituent metal of the metal plug 15 can be prevented.

Conversely, when an element is formed after the metal plug 15 is formed, the constituent metal of the metal plug 15 diffuses into the element region in a high-temperature heat step required for forming the element, and the element characteristics deteriorate. Problem arises.

FIG. 8 shows sectional views of connection plugs having various structures. This is a cross-sectional view corresponding to the step of FIG. In the figure, reference numeral 19 denotes a metal wiring.

FIG. 8A shows a connection plug according to the present embodiment.

FIG. 8B shows a connection plug having the low stress film 18.

That is, in this connection plug, the metal plug 15 is formed so that an unfilled portion is formed in the through hole, and the difference in thermal expansion coefficient between the unfilled portion and the semiconductor substrate 10a is smaller than that of the metal plug 15. Stress film 18
Are formed, and the through holes are filled.

The low stress film 18 is an insulating film, a semiconductor film,
Any of a metal film may be used. Specifically, conductive paste films, FOX films, SOG films, HDP (High Density Plasm
a) An SiO ₂ film formed by a CVD method.

By using such a connection plug, a large stress is applied to a portion where the connection plug is formed.
Deterioration of element characteristics due to the occurrence of defects in the silicon substrate 10 can be prevented.

FIG. 8C shows a connection plug having a cap metal film 45.

That is, the metal plug 15 is formed only up to a certain depth in the through hole.
On the upper surface of 5, a cap metal film 45 filling the through hole is formed. FIG. 8D shows a connection plug using a cap insulating film 46 instead of the cap metal film 45.

With the cap metal film 45 and the cap insulating film 46, the surface of the metal plug 15 can be flattened.
Can be easily formed.

The cap insulating film 4 which can be formed at a low temperature
By using 6, it is possible to prevent inconvenience such as oxidation of the surface of the metal plug 15 in a later step.

FIG. 9 is a process sectional view showing another method of forming the hole 13. In FIG. This is RIE or photo etching,
This is a formation method combining wet etching.

First, as shown in FIG. 9A, a first interlayer insulating film 1 is formed on a silicon substrate 10 having a main surface of {100}.
Form one. Next, as shown in FIG. 1A, after a mask pattern 12 is formed on the first interlayer insulating film 11, the first interlayer insulating film 11 and the silicon substrate 10 are etched using the mask pattern 12 as a mask. and, the cross-sectional shape to form the hole 13 ₁ of the rectangle.

Here, RIE or photoetching (photochemical etching, photoablation (photoablation) etching) is used as the etching. Particularly light etching is fast etching, so has the advantage of low damage, it is suitable for forming a deep hole 13 _1. In the case of photochemical etching, for example, C is used as an etching gas.
L ₂ gas and ultraviolet light are used as excitation light.

Next, as shown in FIG. 9B, the silicon substrate 10 is wet-etched using the mask pattern 12 as a mask to expose the {111} plane. As a result,
Sectional shape hole 13 ₂ of the triangle is formed. As an etching solution, for example, a KOH solution having a temperature of 60 to 90 ° C. is used.

[0107] Then, as shown in FIG. (B), the holes 13 _2, for example, Ni, Ti, Zr, Hf, metals V, etc. 21
Place. Specifically, placing the metal 21 in the bottom portion of the hole 13 _2.

Next, as shown in FIG. 9C, the metal 21 and the silicon substrate 10 react with each other by heat treatment,
3 ₂ metal in the silicon substrate 10 of the lower silicide layer 22
To form

[0109] Next, as shown in FIG. 9 (d), the metal silicide film 22 is selectively etched away to form a deeper hole 13 _3. Finally, after forming the insulating film and embedding the metal, the back surface of the substrate is polished to obtain a deep through-hole.

By gradually increasing the depth of the hole as described above, it is possible to easily form a deep hole, thereby easily forming a through hole.

FIG. 10 shows another method of forming a metal plug.

FIG. 10A shows that the conductive paste 23 is formed on the entire surface.
Is applied, the conductive paste 23 is fluidized by heat treatment, and the conductive paste 23 is embedded in the holes. Excess conductive paste 23 outside the holes is removed by, for example, a CMP method.

FIG. 10B shows a method of depositing metal fine particles 24 on the entire surface, filling the inside of the holes with the fine particles 24, and then removing excess metal fine particles 24 outside the holes by using a CMP method or the like. Is shown.

Note that, instead of the metal fine particles 29, a solvent (suspension) in which metal particles are dispersed may be used.

FIG. 10C shows that a silicon film 25 is deposited on the entire surface, and then a high-melting metal film (not shown) such as a Ti film is deposited on the silicon film 25, and then a high-melting metal film is formed by heat treatment. By reacting with the silicon film 25, the metal silicide film 2
6 is shown. Excess metal silicide film 26 outside the hole is removed by using, for example, a CMP method.

The silicon film is conformally deposited on the insulating film. Further, the adhesion between the silicon film and the metal film is high.
Therefore, in the case of the method of FIG. 10C, even if the hole is deep, the entire surface of the laminated insulating film 14 in the hole is covered with the silicon film 25, so that the metal silicide film covering the entire surface of the laminated insulating film 14 in the hole is formed. 31 are formed. If a cavity remains in the hole, it may be filled with, for example, a low stress film.

FIG. 11 shows still another method of forming a metal plug.

First, as shown in FIG.
Is formed to cover the entire surface of the side wall and the bottom of the silicon film 27 and to form a silicon film 27 having a cavity. Thereafter, Ni particles 28 (metal balls) having a diameter of about 10 μm are arranged in the holes 13 as shown in FIG.

Next, as shown in FIG. 11B, the silicon film 27 and the Ni grains 28 react by heat treatment,
A nickel silicide film 29 is formed therein. Since a sufficient amount of the silicon film 27 and the Ni grains 28 do not exist in the hole 13, a cavity remains on the nickel silicide film 29.

Finally, as shown in FIG. 11C, after depositing an insulating film or a metal film to be the cap film 30 on the entire surface, the insulating film or the metal film is polished to form an upper portion of the nickel silicide film 30. Is filled with a cap film 35.

The method of forming metal plugs is the same as the method described above (CVD method, sputtering method, plating method, method using conductive paste, method using metal fine particles, method using metal balls, The method is not limited to a method using a turbid liquid, but various methods such as a method of appropriately combining these methods are possible.

FIG. 12 shows another method of forming a connection plug. This method differs from the conventional methods in that the metal plug 15 is formed after the back surface of the silicon substrate 11 is polished to form a through hole.

First, as shown in FIG. 12A, a mask pattern 12a made of Al is formed on a silicon substrate 10 having an element formed on its surface, and then the first mask pattern 12a is used as a mask. The hole 13 is formed by etching the interlayer insulating film 11 and the silicon substrate 10. After that, the mask pattern 12a is removed.

Next, as shown in FIG.
After the formation of the OG film 31, the FOX film 32 is formed on the entire surface so that the holes 13 are completely filled.

Next, as shown in FIG. 12C, the SOG film 31 and the FOX film 32 outside the hole 13 are removed by using, for example, a CMP method or an etch-back method.

Thereafter, the steps shown in FIGS. 5E to 5I are performed.

Next, as shown in FIG. 12D, after the FOX film 32 in the hole 13 is removed by using, for example, the CDE method,
As in the steps shown in FIGS. 4D and 5E, a metal plug 15 made of a metal film is buried in the hole 13.

In the case of the connection structure shown in FIG. 13, after the metal plug 15 is formed, a pad 33 and a metal ball 34 such as an Au ball are formed.

FIGS. 14 and 15 show still another method of forming a connection plug. This method differs from the conventional methods in that a metal plug 15 formed beforehand at a place different from the silicon substrate 10 is embedded in the hole 13.

First, a method for forming the metal plug 15 will be described.

First, as shown in FIG.
_A groove 36 is formed on the surface of the substrate 35 made of ₂ .

Next, a metal ball 37 is buried in the groove 36 as shown in FIG.

Finally, as shown in FIG. 14B, the metal balls 37 are melted by heat treatment to form the grooves 36.
A metal plug 15 made of a metal film is formed therein.

Next, a method of forming a connection plug using the metal plug 15 formed in advance as described above will be described.

First, as shown in FIG. 14C, the metal plug 15 is adhered to the adhesive film.

Next, as shown in FIG. 15D, the metal plug 15 adhered to the adhesive film 38 is taken out from the groove 36.

Next, as shown in FIG.
In the hole 13 of the silicon substrate 10 at the stage of the process (c),
The metal plug 15 bonded to the adhesive film 38 is embedded. Thereafter, the adhesive film 38 is removed.

Next, as shown in FIG. 15F, the metal plug 15 is fixed in the hole 13 by melting the metal plug 15 by heat treatment.

In the case of using such a metal plug 15 formed in advance on the substrate 15, a metal film to be the metal plug 4 is formed on the silicon substrate 10 by using a film forming method such as a sputtering method or a CVD method. The throughput is higher and the process temperature is lower than in the case of the forming method.

Here, the material of the substrate 35 is Si
Although O ₂ is selected, another material may be used as long as it does not react with the metal ball 37.

Incidentally, instead of the metal balls 37, a low-resistance conductive paste such as Au or Pd may be used. In this case, after the conductive paste is embedded in the groove 36 using a screen printing method, the conductive paste is sintered to form the metal plug 15.

Here, the conductive paste such as Au or Pd has a high sintering temperature, but there is no problem because the conductive paste is sintered on the substrate 35 which is different from the silicon substrate 10. Further, unlike the usual conductive paste, the conductive paste does not need to contain resin, glass, or the like.

Although the metal plug 15 is taken out of the groove 36 using the adhesive film 38, it may be taken out by other means such as tweezers.

Further, the metal plug 15 may be fixed in the hole 13 by forming an adhesive layer in the hole 13 in advance. Specifically, for example, SOG or FOX is applied in the hole 13 to form an adhesive layer, and then the metal plug 15 is embedded in the hole 13. Then, the adhesive layer is cured.

(Fifth Embodiment) FIG. 16 is a sectional view showing a method for forming a chip for a multichip semiconductor device according to a fifth embodiment of the present invention. 4 and 5 correspond to the chip for the multi-chip semiconductor device shown in FIGS.
The same reference numerals as in FIG. 5 are used, and detailed description is omitted.

This embodiment is different from the fourth embodiment in FIG.
After the step (i), as shown in FIG. 16A, the metal plug 15 is etched from the back surface of the silicon substrate 10 to form an unfilled portion in the through hole.

Next, as shown in FIG. 16B, after the metal plug 15 (the concave portion of the unfilled portion of the through hole) and the solder bump 8 are aligned, the metal plug 15 and the solder bump 8 are connected. .

Here, the alignment between the metal plug 15 and the solder bump 8 is preferably performed by image processing.
This is because on the screen, the difference between the light and dark portions in the unfilled portion and the light and dark portions in the other portion becomes clear, so that accurate positioning can be easily performed.

Further, since the side surface of the bump 8 comes into contact with the side surface of the through hole, the bump 8 is more firmly fixed than in the case where there is no concave portion in the unfilled portion.

Conversely, a convex structure in which the metal plug 15 protrudes from the through hole may be used. In this case, since the bump 8 does not contact the silicon substrate 10, contamination of the silicon substrate 10 by the bump 8 can be effectively prevented.

(Sixth Embodiment) FIG. 17 is a sectional view of a multichip semiconductor device according to a sixth embodiment of the present invention. Note that portions corresponding to those of the multi-chip semiconductor device in FIG. 1 are denoted by the same reference numerals as in FIG. Chip 1
_In FIGS. 1 and ₁₂ , the multilayer wiring layer 3, the insulating films 5, 7 and the pads 6 are omitted.

[0152] This embodiment is characterized in the provision of the heat radiation fins 39 on the chip 1 _1. The radiation fin 39 is fixed to the tip 1 ₁ by an adhesive 40. In addition,
Other fixing methods such as fixing by metallizing on an insulating film may be used.

According to the present embodiment, the heat radiation of the device can be made sufficiently high by the metal plug 4 and the heat radiation fan 39.

(Seventh Embodiment) FIG. 18 is a sectional view of a multichip semiconductor device according to a seventh embodiment of the present invention. Note that portions corresponding to those of the multi-chip semiconductor device in FIG. 1 are denoted by the same reference numerals as in FIG. In the figure, 7a denotes an insulating film, and 42 denotes a solder.

[0155] This embodiment is characterized in the provision of the dummy bump 8d for heat radiation between the chip 1 ₁ and the chip 1 _2.

[0156] The chip 1 ₁ and the chip 1 ₂ connected to the mechanical via dummy bumps 8d are not in electrical connection. Dummy bumps 8d is to connect the chip 1 ₁ and the chip 1 ₂ via a metal film (not shown), for example.

The material of the dummy bump 8d is, for example, a metal such as Au. Even if it is not a metal, a semiconductor or an insulator may be used as long as the material has good heat conductivity. Further, a filler may be used. If the dummy bumps 8d and the wiring bumps 8 are formed of the same material, these bumps can be formed at the same time, and an increase in the number of steps can be prevented.

Although the heat dissipation is improved only by the dummy bumps 8d, it is preferable to connect the dummy bumps 8d to the radiation fins in order to effectively enhance the heat dissipation.

(Eighth Embodiment) FIG. 19 is a diagram showing a method of manufacturing a multi-chip semiconductor device according to an eighth embodiment of the present invention.

In the method shown in FIG.
Although the solder bumps 8 are formed on the substrate, in the present embodiment, conversely,
Connection destination member 47 (for example, a chip having a metal plug,
A solder bump 8 is formed on a chip or a laminated wiring board having no metal plug, and the solder bump 8 is connected to the metal plug 4 protruding from the back surface of the silicon substrate 2.

Also in this case, the bumps 8 are
Therefore, the contamination of the silicon substrate 10 by the bumps 8 can be effectively prevented.

(Ninth Embodiment) FIG. 20 is a schematic diagram showing a multichip semiconductor device according to a ninth embodiment of the present invention.

Note that parts corresponding to those of the multi-chip semiconductor device of FIG. 1 are denoted by the same reference numerals as in FIG. Further, in the chip ₁ 1, 1 _2, 1 _3, a multilayer wiring layer 3 and the insulating films 5 and 7 and the pad 6 are omitted. Chip 1
₃ may or may not have the metal plug 4.

This embodiment is an example in which a TAB tape is used as a mounting member. In the figure, 43 is a plastic tape, and 44 is a lead terminal. In FIG. 21,
1 shows a schematic view of a conventional multi-chip semiconductor device using a TAB tape. From the figure, it can be seen that the planar area is larger than in the present embodiment.

According to the present embodiment, in addition to the effect that the chips can be stacked and the plane area can be reduced, it is possible to inspect all chips, some chips or each chip using the metal plug 4. it can.

[0166] If the inspection of the entire apparatus, in the state shown in FIG. 20, is performed by applying a test probe to the pads provided on the wiring layer of the chip 1 ₁ (not shown). Also, if the test of the chip 1 _1, 1 _2, after connecting the chip 1 _1, 1 _2, carried out by applying the test probes to the pads provided on the wiring layer of the chip 1 ₂ (not shown).

(Tenth Embodiment) FIG. 22 to FIG.
FIG. 21 is a diagram illustrating the method for manufacturing the multi-chip semiconductor device according to the tenth embodiment of the present invention.

First, according to a well-known method, FIG.
As shown in FIG.
After forming an OM memory cell and a peripheral element (not shown), a first interlayer insulating film 56 is formed.

In the figure, reference numeral 51 denotes a tunnel oxide film;
_F is a floating gate electrode, 53 is an insulating film between gate electrodes, 52
_C indicates a control gate electrode, 54 indicates a source diffusion layer, and 55 indicates a drain diffusion layer. Although a plurality of memory cells are actually formed, only one memory cell is shown in the figure for simplicity.

Next, as shown in FIG. 17A, after a contact hole is formed in the first interlayer insulating film 56, Ti.T
An iN laminated film 57 and a W bit line plug 58 are formed.

Specifically, first, a contact hole is formed, and then a Ti film and a TiN film are sequentially formed on the entire surface.
A W film is formed on the entire surface by using a blanket CVD method.
Finally, using a CMP method, a W film outside the contact hole,
The Ti film and the TiN film are removed.

Then, as shown in FIG. 22B, a mask pattern 5 made of, for example, Al is formed on the first interlayer insulating film 56.
9 and using the mask pattern 59 as a mask,
By etching the first interlayer insulating film 56 and the silicon substrate 50 in the region where the connection plug is formed, a hole 60 having a depth of 150 to 200 μm and a size of 100 μm × 100 μm is formed. After that, the mask pattern 59 is removed.

Next, as shown in FIG. 22C, a SiO ₂ film 61 covering the inside of the hole 60 is formed, and a polycrystalline silicon film 62 having a thickness of 500 nm as an adhesion film is formed thereon. A Ni film 63 as a metal plug is embedded in 60.

Specifically, after a 500 nm thick SiO ₂ film 61, a 500 nm thick polycrystalline silicon film 62, and a Ni film 63 are sequentially formed on the entire surface, a hole 60 is formed by CMP.
Extra surplus SiO ₂ film 61, polycrystalline silicon film 62, N
The i film 63 is removed.

The Ni film 63 is formed by embedding a Ni paste in the hole 60 using, for example, a screen printing method.
It is formed by sintering a Ni paste by heat treatment at 600 ° C.

Next, as shown in FIG. 23D, a bit line 64 and a first wiring layer 65 are formed according to a known method.

More specifically, for example, a 10 nm-thick Ti film serving as the bit line 64 and the first wiring layer 65, and a 10 nm-thick
TiN film, 400 nm thick AlCu film, 40 n thick
After forming a laminated film of m TiN films, the laminated film is formed by processing using photolithography and etching.

Next, as shown in FIG. 17D, a second interlayer insulating film 66 is formed, and a via hole is formed in the second interlayer insulating film 66. A second wiring layer 68 connected to the wiring layer 65 is formed.

The method of forming the second wiring layer 68 is the same as that of the first wiring layer 65. Further, as the plug 67, for example, a W film is used. Note that the second wiring layer in the memory cell area is omitted.

Next, as shown in FIG. 17D, a 450 nm thick passivation film covering the second wiring layer 68 is formed.
After the photosensitive polyimide film 69 of m is formed by using the plasma CVD method, an opening (pad hole) is formed on the second wiring layer 68 by using photolithography and etching. Thereafter, it is desirable that a probe be applied to a pad (not shown) to determine whether each chip formed on the wafer is good or bad.

Next, as shown in FIG. 23E, the back surface of the silicon substrate 50 is mechanically polished to expose the Ni film 63.

This polishing step is preferably performed after cutting the silicon substrate 50 from the wafer. This is because, as described above, uniform polishing is difficult in a wafer state. Thereafter, the damage caused by the polishing is removed by wet etching. Note that it is preferable that a shallow scribe line is previously formed on the front surface of the wafer so that chip division is automatically performed when the wafer is thinned by polishing the back surface.

Next, as shown in FIG. 23F, after forming an Au ball bump 70 on the second wiring layer 68, a solder 71 is formed on the Au ball bump 70 by using a transfer method. At this time, if a good chip is known in advance by probe measurement, the yield and production efficiency can be improved by forming the Au ball bump 70 only on the good chip.

Finally, as shown in FIG.
(Au ball bump 70) and Ni film (metal plug) 63
Then, the solder 71 and the Ni film (metal plug) 63 are connected to each other, and the silicon substrates 50 are connected to each other, thereby completing the EEPROM multi-chip semiconductor device. Thereafter, the electrical characteristics are evaluated, and if the stacked chips have a defect, the solder 71 is heated to the melt temperature to disconnect the chips and replace the defective chip with a non-defective chip.

In this embodiment, the NAND type EEP
The multi-chip semiconductor device of ROM was explained,
By the same method as in the present embodiment, a NOR type EEPROM
And a multi-chip semiconductor device of DRAM can also be manufactured. Furthermore, EEPR
A multi-chip semiconductor device of an information processing device such as a personal computer including an OM, a DRAM, or another semiconductor memory, or a combination thereof, and a CPU can also be manufactured.

[0186]

As described in detail above, the present invention (Claim 1,
According to 2), at least one chip has a structure in which a connection plug made of metal is formed in a through hole penetrating the semiconductor substrate and the interlayer insulating film, and the chip having this connection plug is connected to the connection plug. Since it is electrically connected to another chip via the semiconductor chip, a multi-chip semiconductor device having a small planar area, a simple structure, and a small thickness can be realized.

In the present invention (claims 3 to 7), as a chip for a multi-chip semiconductor device, a semiconductor substrate on which elements are formed, a through-hole penetrating the semiconductor substrate and an interlayer insulating film formed thereon are provided. A connection plug formed in a hole and made of metal for electrically connecting to another chip is used.

Therefore, by using the chip for a multichip semiconductor device having such a configuration, the multichip semiconductor device according to the present invention (claims 1 and 2) can be realized.

Further, in the present invention (claims 8 to 12), after forming a hole which penetrates the interlayer insulating film but does not penetrate the semiconductor substrate, the semiconductor substrate is receded from the back surface to form a through hole. Therefore, the through hole can be easily formed even if the original semiconductor substrate is thick.

Therefore, even if the semiconductor substrate is thick, the chip for a multichip semiconductor device according to the present invention (claims 3 to 7) can be easily formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a multi-chip semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a multichip semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view of a multi-chip semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a first-half process cross-sectional view showing a method for forming a chip for a multi-chip semiconductor device according to a fourth embodiment of the present invention;

FIG. 5 is a sectional view of the latter half of a process showing a method for forming a chip for a multi-chip semiconductor device according to a fourth embodiment of the present invention;

FIG. 6 is a sectional view showing a specific structure example of a multilayer wiring layer in a hole region;

FIG. 7 is a sectional view showing a specific example of the structure of a multilayer wiring layer in an element region.

FIG. 8 is a sectional view showing a through plug.

FIG. 9 is a process sectional view showing another method for forming a hole.

FIG. 10 is a sectional view showing another method of forming a metal plug.

FIG. 11 is a sectional view showing still another method for forming a metal plug.

FIG. 12 is a process sectional view showing another method for forming a connection plug.

FIG. 13 is a sectional view showing another connection structure of the multichip.

FIG. 14 is a process sectional view of the first half showing still another method of the connection plug.

FIG. 15 is a sectional view of a process in the latter half showing another method of connecting plugs;

FIG. 16 is a sectional view showing a method of forming a chip for a multi-chip semiconductor device according to a fifth embodiment of the present invention.

FIG. 17 is a sectional view of a multichip semiconductor device according to a sixth embodiment of the present invention.

FIG. 18 is a sectional view of a multichip semiconductor device according to a seventh embodiment of the present invention.

FIG. 19 is a view illustrating a method of manufacturing a multi-chip semiconductor device according to an eighth embodiment of the present invention.

FIG. 20 is a schematic view showing a multi-chip semiconductor device according to a ninth embodiment of the present invention.

FIG. 21 is a schematic view showing a conventional multi-chip semiconductor device using a TAB tape.

FIG. 22 is a process sectional view of the first half showing the method of manufacturing the multi-chip semiconductor device according to the tenth embodiment of the present invention;

FIG. 23 is a process sectional view of the latter half showing the method for manufacturing the multi-chip semiconductor device according to the tenth embodiment of the present invention;

FIG. 24 is a sectional view showing the method of manufacturing the multi-chip semiconductor device according to the tenth embodiment of the present invention.

FIG. 25 is a sectional view of a conventional multichip semiconductor device.

FIG. 26 is a sectional view of another conventional multi-chip semiconductor device.

FIG. 27 is a sectional view of still another conventional multi-chip semiconductor device.

[Explanation of symbols]

1 ₁ , 1 ₂ , 1 ₃ ... chip 2 ... silicon substrate 3 ... multilayer wiring layer 4 ... metal film (metal plug) 5 ... insulating film 6 ... pad 7 ... insulating film 7 a ... insulating film 8 ... solder bump (connection member) 8d: dummy bump 9: laminated wiring board (mounting member) 10: silicon substrate 11: first interlayer insulating film 11a: second interlayer insulating film 11b: third interlayer insulating film 11c: fourth interlayer insulating film 11n the n of the interlayer insulating film 12 ... mask pattern 12a ... mask pattern 13, 13 ₁ to 13 ₃ ... hole (through hole) 14 ... laminated insulating film (first insulating film) 15 ... metal film (metal plugs) 16 ... multilayer Wiring structure 17 Pad 18 SiO ₂ film (second insulating film) 19 Metal wiring 19 a First metal wiring 19 b Second metal wiring 20 a First metal wiring 20 b Second metal wiring 20 c … The third metal distribution DESCRIPTION OF SYMBOLS 21 ... Metal 22 ... Metal silicide film 23 ... Conductive paste 24 ... Metal particle 25 ... Silicon film 26 ... Metal silicide film 27 ... Silicon film 28 ... Ni grain 29 ... Nickel silicide film 30 ... Cap film 31 ... SOG film 32 ... FOX film 33 ... Pad 34 ... Metal ball 35 ... Substrate 36 ... Groove 37 ... Metal ball 38 ... Adhesive film 39 ... Heat radiation fin 40 ... Adhesive 41 ... Insulating film 42 ... Solder 43 ... Plastic tape 44 ... Lead terminal 45 ... Cap metal film 46 ... cap insulating film 47 ... connection of members 50 ... silicon substrate 51 ... tunnel oxide film 52 _F ... floating gate electrode 53 _C ... control gate electrode 53 ... gate insulating film 54 ... source diffusion layer 55 ... drain diffusion layer 56 ... First interlayer insulating film 57... Ti / TiN laminated film 58. Grayed 59 ... mask pattern 60 ... holes 61 ... SiO ₂ film 62 ... polycrystalline silicon film 63 ... Ni film 64 ... of the bit line 65 ... first wiring layer 66: second interlayer insulating film 67 ... plug 68 ... second Wiring layer 69: Polyimide film 70: Au ball bump

Claims (12)

[Claims] 1. A multi-chip semiconductor device comprising a plurality of chips having a semiconductor substrate on which elements are integrally formed on a surface thereof and an interlayer insulating film formed on the surface of the semiconductor substrate, wherein at least one chip comprises: A connection plug made of metal is formed in a through-hole penetrating the semiconductor substrate and the interlayer insulating film, and at least one chip having this connection plug is connected to another chip through the connection plug. A multi-chip semiconductor device, which is electrically connected to the semiconductor device. 2. A chip having the connection plug is electrically connected to at least one of chips directly above and below the chip via a connection member or a connection member and a mounting member. The multi-chip semiconductor device according to claim 1, wherein: 3. A semiconductor substrate having elements formed on the surface thereof, an interlayer insulating film formed on the surface of the semiconductor substrate, and a through hole formed through the interlayer insulating film and the semiconductor substrate. And a connection plug made of a metal for electrically connecting the chip to a multi-chip semiconductor device chip. 4. The connection plug comprises a metal plug provided in the through-hole and an insulating film provided between the metal plug and a side wall of the through-hole. The chip for a multichip semiconductor device according to claim 3. 5. A metal plug having a hollow portion provided in the through-hole, an insulating film provided between the metal plug and a side wall of the through-hole, and a connecting plug provided in the hollow portion. 4. The chip for a multi-chip semiconductor device according to claim 3, wherein the chip is provided with a low-stress film having a difference in thermal expansion coefficient from the semiconductor substrate smaller than that of the metal plug. 6. A connection plug comprising: a metal plug provided to a depth halfway of the through hole on the semiconductor substrate surface side; and an insulating film provided between the metal plug and a side wall of the through hole. 4. The multi-chip semiconductor device chip according to claim 3, further comprising: a cap film provided on the metal plug and filling the through hole. 7. A metal plug provided up to a depth halfway of the through hole on the semiconductor substrate surface side, wherein:
The metal plug and an insulating film provided between a side wall of the through hole and an unfilled portion of the through hole are provided with a connection member for electrically connecting to another chip. The chip for a multi-chip semiconductor device according to claim 3, wherein: 8. A step of integrally forming elements on the surface of the semiconductor substrate, a step of forming an interlayer insulating film on the surface of the semiconductor substrate, etching the interlayer insulating film and the semiconductor substrate,
Forming a hole that penetrates the interlayer insulating film and does not penetrate the semiconductor substrate; forming an insulating film having a thickness that does not fill the hole on a side wall and a bottom of the hole; A step of filling a metal as a metal plug in the covered hole, and a step of retracting the semiconductor substrate and the insulating film from the back surface of the semiconductor substrate to expose the metal plug at the bottom of the hole. A method for forming a chip for a multi-chip semiconductor device, comprising: 9. A step of integrating and forming elements on the surface of the semiconductor substrate; a step of forming an interlayer insulating film on the surface of the semiconductor substrate; etching the interlayer insulating film and the semiconductor substrate;
Forming a hole penetrating the interlayer insulating film and not penetrating the semiconductor substrate; forming a first insulating film having a thickness not filling the hole on a side wall and a bottom of the hole; Filling the inside of the hole with a second insulating film having a higher etching rate than the first insulating film; forming a connection hole in the interlayer insulating film and connecting to the element via the connection hole; Forming the semiconductor substrate and the first insulating film from the back surface of the semiconductor substrate to expose the second insulating film at the bottom of the hole; and forming the second insulating film in the hole. Selectively etching and removing the second insulating film, and then filling a metal as a metal plug in the hole covered with the first insulating film. Formation method. 10. A step of integrally forming an element on a surface of a semiconductor substrate; a step of forming an interlayer insulating film on the surface of the semiconductor substrate; and etching the interlayer insulating film and the semiconductor substrate;
Forming a hole penetrating the interlayer insulating film and not penetrating the semiconductor substrate; forming a first insulating film having a thickness not filling the hole on a side wall and a bottom of the hole; Filling a metal as a metal plug into the hole covered with the first insulating film; and removing the semiconductor substrate from the back surface of the semiconductor substrate until the first insulating film at the bottom of the hole is exposed. And selectively removing the semiconductor substrate on the bottom side of the hole until the first insulating film on the side wall of the hole is exposed above the first insulating film on the bottom of the hole. Etching; forming a second insulating film on the entire back surface of the semiconductor substrate on the bottom side of the hole; and forming the first and second insulating films until the metal plug on the bottom of the hole is exposed. And retract the semi-conductor on the bottom side of the hole. The back surface of the substrate, a method of forming the multi-chip semiconductor device chip, characterized in that it comprises a step of selectively leaving the second insulating film. 11. The semiconductor device according to claim 8, wherein said hole is formed before forming a wiring layer having the lowest melting point among wiring layers formed on said semiconductor substrate. 11. The method for forming a chip for a multi-chip semiconductor device according to any one of the above items 10. 12. The chip for a multi-chip semiconductor device according to claim 8, wherein the retreating of the semiconductor substrate is performed after the semiconductor substrate is cut out from a wafer. Formation method.