JP4537753B2 - Multilayer wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a circuit board with a built-in capacitor, and more particularly to a multilayer wiring board with a built-in capacitor in which the position and size of the capacitor can be arbitrarily provided on the circuit board.

  In recent years, in semiconductor chips, integrated circuit elements such as ICs and LSIs (hereinafter collectively referred to as LSIs) have been increased in density, and the operation speed has been increasing year by year. When the operating speed of the LSI increases, there is a problem that switching noise generated inside the semiconductor chip causes the LSI to malfunction. In order to reduce switching noise, it is effective to arrange a capacitor between the power supply bus line and the ground bus line.

  If the capacitors are arranged on the wiring board as external components, the connection distance between these components and the semiconductor chip becomes long and the wiring inductance increases, so that the effect of the capacitor becomes insufficient. For this reason, the capacitor is required to be as close to the LSI as possible, and is preferably formed directly on the semiconductor chip. However, in this case, the area of the semiconductor chip is increased, resulting in an increase in cost, and the manufacturing process is complicated and long. Therefore, there is a problem that the yield of the semiconductor chip itself is lowered due to a defective capacitor.

In order to cope with these problems, it has been proposed to incorporate a capacitor in an intermediate substrate (interposer or semiconductor chip carrier) used when a semiconductor chip is mounted on a wiring board (for example, Patent Document 1, (See Patent Document 2).
Alternatively, a method of incorporating a capacitor in a multilayer wiring layer stacked on a core substrate has been proposed (see, for example, Patent Document 3).
JP-A-8-148595 JP 2001-326298 A Japanese Patent Application Laid-Open No. 7-30258

However, the semiconductor device disclosed in Patent Document 1 shows a configuration in which a chip carrier made of glass ceramic having a thick film capacitor is connected to a base substrate, but it is difficult to make the dielectric layer thin. There was a limit to the characteristics of the capacitor. Patent Document 2 shows a configuration including an interposer made of a ceramic having a capacitor. However, the method using the interposer determines the material, thickness, capacitor position, size, etc. of the capacitor dielectric layer in advance. There was a problem that had to be decided.
In addition, since the circuit board with a built-in capacitor described in Patent Document 3 is embedded in the multilayer wiring layer, the size of the electrode is fixed, and the position and size of the capacitor are determined in advance. There is a problem that it is not possible to flexibly cope with a specification change, and there is a problem that a manufacturing process of a circuit board having a multilayer wiring with a built-in capacitor is long and a manufacturing yield is lowered.

  Therefore, the present invention has been made in consideration of such points, and the position, size, etc. of the capacitor can be flexibly changed according to the specification change, and the range of the material selection of the dielectric layer of the capacitor It is an object of the present invention to provide a multilayer wiring board with a built-in capacitor and a method for manufacturing the same, in which the manufacturing process of a circuit board with a built-in capacitor is shortened and the manufacturing yield is improved.

In order to solve the above-described problems, a multilayer wiring board according to the present invention includes a core board and a multilayer wiring board in which a wiring layer and an insulating layer are stacked on one surface of the core board. The thermal expansion coefficient in the XY direction is in the range of 2 to 20 ppm, and the core material for the core substrate is a core material selected from silicon, ceramics, glass, glass / epoxy composite material, and metal, and the core substrate is a conductive material A plurality of through-holes that are electrically connected to each other by the front and back , and a capacitor is provided on the other surface of the core substrate , and the capacitor is connected to the conductive material in the through-hole via an insulating layer. An upper electrode provided on the core substrate, a dielectric layer provided to cover at least part of the upper electrode, and a lower electrode provided to cover at least part of the dielectric layer; It is more configuration.

The multilayer wiring board according to the present invention is a multilayer wiring board in which a wiring layer and an insulating layer are laminated on one surface of the core substrate, and the thermal expansion coefficient in the XY direction of the core substrate is The core material for the core substrate is a core material selected from silicon, ceramics, glass, glass / epoxy composite material, and metal, and the core substrate is electrically connected to the front and back by a conductive material. An anodizable metal provided with a plurality of through holes and a capacitor on the other surface of the core substrate, the capacitor being connected to the conductive material in the through hole and provided on the core substrate And a lower electrode disposed so as to face the upper electrode through a dielectric layer made of the metal oxide .

  According to the present invention, the material of the dielectric layer constituting the capacitor is silicon oxide, silicon nitride, barium strontium titanate, tantalum pentoxide, lead zirconate titanate, strontium titanate, aluminum oxide, benzocyclobutene. It was set as the structure selected from either resin, a cardo resin, or a polyimide resin.

  Further, according to the present invention, the material of the wiring layer and the lower electrode is any one of Al, Cr, Cu, Ti, Pt, Ru, Ta, and W, and oxides and nitrides of these metals. And an alloy and a multilayer film made of any combination of the metal, oxide, nitride, alloy and polysilicon.

In the present invention, the thickness of the core substrate is in the range of 50 to 300 μm, and the opening diameter of the through hole is in the range of 10 to 300 μm.
In the present invention, a conductive material diffusion preventing layer is provided on the inner wall surface of the through hole, and the conductive material diffusion preventing layer is a titanium nitride thin film.
In the present invention, the through hole of the core material has an opening diameter in the range of 10 to 30 μm.

The method for manufacturing a multilayer wiring board according to the present invention includes: a core substrate; and a multilayer wiring substrate manufacturing method in which a wiring layer and an insulating layer are laminated on one surface of the core substrate. A step of forming a plurality of micropores in a core material selected from any of silicon, ceramics, glass, glass / epoxy composite material, and metal having an expansion coefficient in a range of 2 to 20 ppm; and conducting the micropores A step of making the material conductive, a step of forming a multilayer wiring layer by laminating a wiring layer and an insulating layer on the core substrate on the perforated side of the micropore, and the other of the core substrate provided with the micropore And polishing the surface to expose the fine holes made conductive by the conductive material to form a plurality of through holes for conducting the front and back of the core substrate, and a capacitor on the polished core substrate surface. Forming a process; Together with the step of forming the capacitor, forming an insulating layer on the core substrate surface to form an upper electrode so as to be connected to the conductive material in the through hole in the position for forming a capacitor on the insulating layer, Forming a wiring layer so as to connect with a conductive material in a through hole in a position where a capacitor is not formed, and forming a dielectric layer on the insulating layer so as to cover at least a part of the upper electrode; forming a lower electrode so as to cover at least a portion of the dielectric layer, and the like to organic configure.

The multilayer wiring board manufacturing method of the present invention is a method of manufacturing a multilayer wiring board in which a core substrate and a wiring layer and an insulating layer are laminated on one surface of the core substrate. The step of forming a plurality of micropores in the core material selected from any of silicon, ceramics, glass, glass / epoxy composite material, and metal, Forming a conductive layer with a conductive material, laminating a wiring layer and an insulating layer on the core substrate on the perforated side of the microhole, and forming a multilayer wiring layer, and a core substrate provided with the microhole And polishing the other surface of the core substrate to expose the fine holes made conductive by the conductive material to form a plurality of through holes that conduct the front and back of the core substrate, and to the polished core substrate surface Process for forming a capacitor , Have a step of forming the capacitor, an upper electrode made of anodic oxidizable metal and forming the core substrate surface, be a metal oxide surface of the upper electrode is anodized Forming a dielectric layer, a step of forming a lower electrode on the dielectric layer, and a wiring layer so as to connect the conductive material in the through hole at a position where a capacitor is formed and the upper electrode. and forming, and forming a wiring layer on the through-hole in a position that does not form a capacitor, and such that chromatic configure.

In addition, the present invention has a configuration in which a conductive substance diffusion prevention layer is formed on the inner wall surface of the fine hole after the formation of the fine hole having an opening diameter in the range of 10 to 300 μm. The formation method is the MO-CVD method.
Moreover, this invention was set as the structure which forms the said micropore so that an opening diameter may exist in the range of 10-30 micrometers.

Further, the present invention is configured such that the fine hole forming method is an ICP-RIE method or a sandblast method.
Further, the present invention is configured such that the step of making the micropores conductive with the conductive material is either a method of filling the micropores with a conductive paste or a method of filling the micropores with a conductive material by plating. It was.
Further, according to the present invention, the method of filling the conductive material by plating forms a base conductive thin film by a vacuum film formation method from the core material surface side where the fine holes are formed, and a part of the inner wall surface of the fine holes. A seed layer made of the underlying conductive thin film was formed, and the seed layer was used to deposit and fill a metal in the fine holes by electrolytic plating.

The method for manufacturing a multilayer wiring board according to the present invention includes: a core substrate; and a multilayer wiring substrate manufacturing method in which a wiring layer and an insulating layer are laminated on one surface of the core substrate. A step of forming a plurality of through holes in a core material selected from any one of silicon, ceramics, glass, glass / epoxy composite material, and metal having an expansion coefficient in a range of 2 to 20 ppm; and conducting the through holes Conducting the front and back of the core substrate as conductive by materials, forming a multilayer wiring layer by laminating a wiring layer and an insulating layer on one surface of the core substrate, and the other surface of the core substrate possess a step of forming a capacitor, a step of forming the capacitor, forming an insulating layer on the core substrate surface, connected to the conductive material in the through hole in a position to form a capacitor Forming an upper electrode on the insulating layer and forming a wiring layer so as to be connected to a conductive material in a through hole in a position where no capacitor is formed, and covering at least a part of the upper electrode wherein on the insulating layer to form a dielectric layer, forming a lower electrode so as to cover at least a portion of the dielectric layer, and the like to organic configured to.

The multilayer wiring board manufacturing method of the present invention is a method of manufacturing a multilayer wiring board in which a core substrate and a wiring layer and an insulating layer are laminated on one surface of the core substrate. A step of forming a plurality of through holes in a core material selected from any one of silicon, ceramics, glass, glass / epoxy composite material, and metal, and the through holes, Conducting the front and back of the core substrate with a conductive material, forming a multilayer wiring layer by laminating a wiring layer and an insulating layer on one surface of the core substrate, and the other of the core substrate 's forming a capacitor on the surface, have a step of forming the capacitor, an upper electrode made of anodic oxidizable metal and forming the core substrate surface, the surface of the upper electrode Forming a dielectric layer by polar oxidation to form a metal oxide; forming a lower electrode on the dielectric layer; electrically conductive material in a through hole at a position where a capacitor is to be formed; thereby forming a wiring layer so as to connect the electrodes, and forming a wiring layer on the through-hole in a position that does not form a capacitor, and such that chromatic configure.

  In the present invention, the step of making the through hole conductive with a conductive material and conducting the front and back of the core substrate includes forming a base conductive thin film from one side of the core substrate by a vacuum film formation method, A step of forming a seed layer made of the underlying conductive thin film on a part of the substrate, and a step of depositing and growing a metal from the seed layer into a through hole by electrolytic plating using the seed layer as a power feeding layer. The configuration was

In the present invention, after the through hole is formed, a conductive material diffusion preventing layer is formed on the inner wall surface of the through hole, and the method for forming the conductive material diffusion preventing layer is an MO-CVD method. The configuration was
In the present invention, the through hole is formed so as to have an opening diameter in a range of 10 to 30 μm.
In the present invention, the through hole is formed by an ICP-RIE method or a sand blast method.

In the present invention, by forming a capacitor as an internal circuit on one surface of the core substrate, the distance from the semiconductor chip is reduced, and there is no increase in impedance due to the extension of the power supply wiring. Switching noise can be reduced, the internal circuit can be stably operated at high speed, and an increase in chip size can be suppressed.
In addition, according to the multilayer wiring board with a built-in capacitor according to the present invention, the through hole filled with the conductive material is used as the upper electrode for the capacitor. Furthermore, since the capacitor is formed on one surface of the core substrate without being embedded, the material selection range of the capacitor dielectric layer can be widened.

The core board constituting the multilayer wiring board with a built-in capacitor of the present invention is made of a material having a small coefficient of thermal expansion, and the core board has a plurality of through holes which are electrically connected to each other by a conductive material. A multilayer wiring layer is formed on one surface of the substrate, and vias are formed in the wiring layer by a photolithography method and a plating method, so that wiring with a fine line width and a narrow pitch is possible. In addition, since the vias of the multilayer wiring layer can have a stack structure, high-density wiring is possible.
The multilayer wiring board of the present invention can be reduced in size and weight while having high performance electrical characteristics by miniaturization and densification, and thus can be used in various applications.

According to the method of manufacturing a multilayer wiring board with a built-in capacitor according to the present invention, since the conductive through hole filled with the conductive material is used as the upper electrode for the capacitor, the upper electrode forming step is not required, and the dielectric layer for the capacitor Since it also serves as an insulating layer, there is no need to provide an insulating layer on the surface of the core substrate, shortening the manufacturing process of the circuit board with a built-in capacitor and improving the manufacturing yield. It is done.
In addition, by providing the upper electrode on the core substrate so as to connect to the conductive material filled in the through hole, the position and size of the capacitor can be flexibly changed according to the specification change, and the capacitor is built in. The manufacturing method of the multilayer wiring board with a built-in capacitor in which the manufacturing process of the circuit board is shortened and the manufacturing yield is improved can be obtained. When anodizable metal is used for the upper electrode and this surface is anodized to form a dielectric layer, the process can be further simplified, and the multilayer wiring board with a built-in capacitor can be manufactured with improved manufacturing yield. A manufacturing method is obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment of multilayer wiring board)
FIG. 1 is a partial longitudinal sectional view schematically showing another embodiment of the multilayer wiring board of the present invention. In FIG. 1, a multilayer wiring substrate 101 includes a core substrate 102, and wiring 104 (104a, 104b, 104c, 104d) and an insulating layer 105 (105a, 105b, 105c) are laminated on one surface of the core substrate 102. A multilayer wiring layer 103 is formed. In addition, a dielectric layer 112 is provided on the other surface of the core substrate 102, and a capacitor 111 is formed. In the present invention, the surface on which the capacitor 111 is provided may be provided with not only the capacitor but also an inductor which is another passive component circuit.

  The core substrate 102 constituting the multilayer wiring substrate 101 is formed with a plurality of conductive through holes 107 that are electrically connected to each other by a conductive material 109. An insulating layer 108 is provided on the side of the core substrate 102 where the multilayer wiring layer 103 is formed and on the inner wall surface of the through hole 107. In the multilayer wiring layer 103 provided on one surface on the core substrate 102, each wiring 104 is connected via the insulating layer 105 through the conductive vias 106 (106 a, 106 b, 106 c). A conductive material 109 in a predetermined through hole 107 is connected. The wiring layer in the multilayer wiring layer 103 is a concept including the wiring 104 and the via 106.

  In the present invention, the core substrate 102 has a thermal expansion coefficient of 2 to 20 ppm in the XY direction (a plane parallel to the surface of the core substrate 102) in order to maintain the positional accuracy of the fine multilayer wiring layer 103 provided on the multilayer wiring substrate 101. Materials in the range are used. Such a core material 102 'can be selected from silicon, ceramics, glass, glass / epoxy composite material, and metal. In the above-described core material of the core substrate 102, silicon is suitable for fine processing and suitable for precise through hole processing. Ceramics, glass, and glass / epoxy composite materials have the advantage that they are relatively inexpensive, have excellent dimensional stability, and have little deformation during the manufacturing process. The above materials can be selected according to the desired characteristics. Is possible. Examples of the metal include 42 alloy and tungsten. Metal is excellent in conductivity of the substrate, but it is necessary to sufficiently insulate the surface after processing.

In the present invention, the thickness of the core substrate 102 is preferably used in the range of 50 to 300 μm. This is because if the thickness of the core substrate 102 is less than 50 μm, the mechanical strength is insufficient, and if it exceeds 300 μm, the characteristics of the capacitor 111 deteriorate.
For example, when the core material 102 ′ is silicon, the insulating layer 108 can be provided by subjecting the core material 102 ′ to thermal oxidation to form silicon oxide or the like. Further, an insulating layer 108 such as silicon oxide or silicon nitride may be provided on the surface of the core substrate 102 including the through hole 107 by using a vacuum film forming method such as a plasma CVD method. Further, a silicon oxide suspension or an insulating resin such as a benzocyclobutene resin, a cardo resin, or a polyimide resin is applied to the surface of the core substrate 102 including the sulfole 107 by a coating method. The insulating layer 108 can be formed by being cured.

The shape of the through hole 107 of the core substrate 102 of the present invention may be any of a straight shape having substantially the same opening diameter on the front and back sides, a tapered shape having an opening diameter at one end larger than the opening diameter at the other end, and the like.
The through hole 107 preferably has an opening diameter in the range of 10 to 300 μm. If the opening diameter of the through hole 107 is less than 10 μm, it becomes difficult to drill deep microholes and fill the conductive material, and if it exceeds 300 μm, the occupied area of the through hole becomes large, which is not preferable for high density. It is.

  Further, in the present invention, the opening diameter of the through hole 107 can be in the range of 10 to 100 μm, preferably 10 to 30 μm. In this case, as shown in FIG. It is preferable to provide a conductive material diffusion prevention layer 110 over the insulating layer 108. The conductive material diffusion preventing layer 110 prevents the conductive material 109 from diffusing into the core substrate 102, and even if the opening diameter is reduced and the pitch of the through holes 107 is reduced, the distance between adjacent through holes 107 is reduced. Is prevented from short circuiting. The conductive material diffusion preventing layer 110 is not particularly limited as long as it is a thin film that can prevent diffusion of the conductive material into the core substrate 102. For example, a thin film such as titanium nitride, titanium, or chromium is used. It can be. The thickness of the conductive substance diffusion preventing layer 110 can be set in the range of 10 to 50 nm, for example.

  The conductive material 109 used for the conductive through hole 107 of the core substrate 102 is filled with a known conductive paste such as copper paste or silver paste, or filled by electrolytic plating. Any of the metals such as copper, silver, gold, and nickel may be used. In particular, when a metal is used as the conductive material 109, thermal expansion of the conductive material in the through hole is small, and stress concentration on a wiring or the like provided on the core substrate can be prevented, which is preferable. When a metal is used as the conductive material 109, a base conductive thin film is formed on the inner wall of the through hole by a vacuum film-forming method such as CVD or an electroless plating method, and then copper, silver, gold or the like is formed by electrolytic plating. Alternatively, a method can be used in which conductive plating is performed with a conductive material such as nickel to make it conductive.

In the capacitor 111 according to the present invention, the conductive material 109 filled in the through hole 107 is used as the upper electrode 113 and the lower electrode 114 is provided via the dielectric layer 112. Therefore, at least the through hole 107 on the capacitor 111 side is provided. Is preferably filled with the conductive material 109, and more preferably filled with the conductive material 109 in the through hole 107.
In the present invention, the direction in which current flows between the upper electrode 113 and the lower electrode 114 is not limited, and the same applies to the embodiments described later.

In the present invention, the material of the dielectric layer 112 constituting the capacitor 111 is silicon oxide, silicon nitride, tantalum pentoxide, barium strontium titanate (SrBaTiO ₃ ), lead zirconate titanate (Pb, (Zr, Ti) O ₃ ), strontium titanate (SrTiO ₃ ), aluminum oxide, benzocyclobutene resin, cardo resin, or polyimide resin.
As the thickness of the dielectric layer 112, a film thickness of about 0.05 to several μm is used.

The material of the lower electrode 114 of the capacitor 111 provided on the dielectric layer 112 and the wiring layer 118 electrically connected to the through hole 107 is preferably selected from the following group, and is formed to a thickness of several μm.
-Any one metal of Al, Cr, Cu, Ti, Pt, Ru, Ta, W-Oxides (such as RuO), nitrides (such as TiN) and alloys of the above metals-The above metals and oxides , Nitrides, alloys, and multilayers composed of any combination of polysilicon (Cr / Cu, Ti / Pt two-layer film, Cr / Cu / Cr three-layer film, etc.)
Examples of metal alloys include Al containing several percent of Si or Cu.

The materials of the wiring 104 and the via 106 of the multilayer wiring layer 103 provided on the core substrate 102 are preferably selected from the following group.
-Any one metal of Al, Cr, Cu, Ti-Nitride (TiN, etc.) and alloys of the above metals-Multi-layer film (Cr / Cu of any combination of the above metals, nitrides and alloys) 2 layer film, Cr / Cu / Cr 3 layer film, etc.)
Examples of metal alloys include Al containing several percent of Si or Cu.

The insulating layer 105 of the multilayer wiring layer 103 is made of a photosensitive insulating material that can be thermoset at a solder reflow temperature of 250 ° C. or lower, and is preferably a benzocyclobutene resin, a cardo resin, or a polyimide resin. As a material.
Further, the multilayer wiring board of the present invention has a conductive material 109 filled in the through hole 107 on the surface of at least one surface of the core material 102 'as in the multilayer wiring board 101' shown in FIG. Further, the land 109a, 109b may be configured to protrude further. The lands 109a and 109b preferably protrude from the surface of the core substrate within a range of 5 to 15 μm. This is because if the protrusion is 5 μm or less, a sufficient area of the through hole conductor portion cannot be secured, while if it exceeds 15 μm, it becomes an obstacle to making the wiring board thinner. In the illustrated example, an insulating layer 105 'is provided on both sides in order to obtain a flat surface. The material of the insulating layer 105 ′ can be the same as that of the insulating layer 105 described above.

(Second Embodiment of Multilayer Wiring Board)
FIG. 4 is a partial longitudinal sectional view schematically showing another embodiment of the multilayer wiring board of the present invention. In FIG. 4, a multilayer wiring board 121 includes a core board 122, and wiring 124 (124a, 124b, 124c, 124d) and an insulating layer 125 (125a, 125b, 125c) are stacked on one surface of the core board 122. A multilayer wiring layer 123 is formed. In addition, a dielectric layer 132 is provided on the other surface of the core substrate 122, and a capacitor 131 is formed.

In the multilayer wiring layer 123 provided on one surface on the core substrate 122 constituting the multilayer wiring board 121, each wiring 124 is connected via the insulating layer 125 by the conductive via 126 (126a, 126b, 126c). Furthermore, the conductive material 129 in a predetermined through hole 127 of the core substrate 122 is connected. The wiring layer in the multilayer wiring layer 123 is a concept including the wiring 124 and the via 126.
Further, an insulating layer 128 is formed on the inner wall surface of the through hole 127 and the side of the core material 122 ′ where the multilayer wiring layer 123 is formed. The core substrate 122 and the multilayer wiring layer 123 are the same as the core substrate 102 and the multilayer wiring layer 103 constituting the multilayer wiring substrate 101 described above, and detailed description thereof is omitted.

  The capacitor 131 of the multilayer wiring board 121 is connected to the upper electrode 133 provided on the core substrate 122 so as to be connected to the conductive material 129 in the through hole 127, and the upper electrode 133 via the dielectric layer 132. It is comprised by the lower electrode 134 arrange | positioned so that it may oppose. The upper electrode 133 is smaller than the through hole 127, but the area of the upper electrode 133 is made larger than that of the through hole 127 by disposing an insulating layer in a portion where the insulating layer 128 of the core material 122 ′ is not formed. By increasing the size, a capacitor having a large capacitance can be formed. The multilayer wiring board 121 includes a wiring layer 138 that is electrically connected to the other through holes 127.

The materials of the upper electrode 133, the lower electrode 134, and the wiring layer 138 can be the same as those of the lower electrode 114 and the wiring layer 118 that constitute the multilayer wiring board 101 described above.
Also, the multilayer wiring board 121 may be provided with a conductive substance diffusion preventing layer on the inner wall surface of the through hole 127, as in the multilayer wiring board 101 shown in FIG.

Further, in the multilayer wiring board of the present invention, like the multilayer wiring board 121 'shown in FIG. 5, the conductive material 129 filled in the through hole 127 protrudes from the surface of the core material 122', The lands 129a and 129b may be configured.
The lands 129a and 129b preferably protrude from the surface of the core substrate within a range of 5 to 15 μm. This is because if the protrusion is 5 μm or less, a sufficient area of the through hole conductor portion cannot be secured, while if it exceeds 15 μm, it becomes an obstacle to making the wiring board thinner. In the illustrated example, the core substrate 122 is provided with insulating layers 125 ′ on both sides in order to obtain a flat surface.

(Third embodiment of multilayer wiring board)
FIG. 6 is a partial longitudinal sectional view schematically showing another embodiment of the multilayer wiring board of the present invention. In FIG. 6, a multilayer wiring board 141 includes a core substrate 142, and wiring 144 (144a, 144b, 144c, 144d) and an insulating layer 145 (145a, 145b, 145c) are stacked on one surface of the core substrate 142. A multilayer wiring layer 143 is formed. An insulating layer 155 is provided on the other surface of the core substrate 142, and a capacitor 151 is formed on the insulating layer 155.

  In the multilayer wiring layer 143 provided on one surface of the core substrate 142 constituting the multilayer wiring substrate 141, each wiring 144 is connected through the insulating layer 145 with conductive vias 146 (146a, 146b, 146c). Further, it is connected to a conductive material 149 in a predetermined through hole 147 of the core substrate 142. The wiring layer in the multilayer wiring layer 143 is a concept including the wiring 144 and the via 146.

In addition, an insulating layer 148 is formed on the inner wall surface of the through hole 147 and the side of the core material 142 ′ where the multilayer wiring layer 143 is formed. The core substrate 142 and the multilayer wiring layer 143 are the same as the core substrate 102 and the multilayer wiring layer 103 constituting the multilayer wiring substrate 101 described above, and detailed description thereof is omitted.
The capacitor 151 of the multilayer wiring substrate 141 includes an upper electrode 153 provided on the core substrate 142 via an insulating layer 155 so as to be connected to the conductive material 149 in the through hole 147, and at least the upper electrode The dielectric layer 152 is provided so as to cover a part thereof, and the lower electrode 154 is provided so as to cover at least a part of the dielectric layer 152. In addition, the multilayer wiring board 141 includes a wiring layer 158 that is electrically connected to another through hole 147.

The materials of the upper electrode 153, the lower electrode 154, and the wiring layer 158 can be the same as those of the lower electrode 114 and the wiring layer 118 that constitute the multilayer wiring board 101 described above.
Also, the multilayer wiring board 141 may be provided with a conductive substance diffusion preventing layer on the inner wall surface of the through hole 147, similarly to the multilayer wiring board 101 shown in FIG.

Further, in the multilayer wiring board of the present invention, like the multilayer wiring board 141 ′ shown in FIG. 7, the conductive material 149 filled in the through hole 147 protrudes from the surface of the core material 142 ′. The lands 149a and 149b may be configured.
The lands 149a and 149b preferably protrude from the surface of the core substrate within a range of 5 to 15 μm. This is because if the protrusion is 5 μm or less, a sufficient area of the through hole conductor portion cannot be secured, while if it exceeds 15 μm, it becomes an obstacle to making the wiring board thinner. In the illustrated example, the core substrate 142 includes an insulating layer 145 ′ on both sides in order to obtain a flat surface.

(Fourth Embodiment of Multilayer Wiring Board)
FIG. 8 is a partial longitudinal sectional view schematically showing another embodiment of the multilayer wiring board of the present invention. In FIG. 8, a multilayer wiring board 161 includes a core board 162, and wiring 164 (164a, 164b, 164c, 164d) and an insulating layer 165 (165a, 165b, 165c) are stacked on one surface of the core board 162. The multilayer wiring layer 163 thus formed is formed. A capacitor 171 is formed on the other surface of the core substrate 162.

In the multilayer wiring layer 163 provided on one surface of the core substrate 162 constituting the multilayer wiring substrate 161, each wiring 164 is connected via an insulating layer 165 with conductive vias 166 (166a, 166b, 166c). Further, it is connected to a conductive material 169 in a predetermined through hole 167 of the core substrate 162. The wiring layer in the multilayer wiring layer 163 is a concept including the wiring 164 and the via 166.
An insulating layer 168 is formed on the inner wall surface of the through hole 167 and the multilayer wiring layer 163 forming side of the core material 162 ′. Such a core substrate 162 and multilayer wiring layer 163 are the same as the core substrate 102 and multilayer wiring layer 103 constituting the multilayer wiring substrate 101 described above, and detailed description thereof will be omitted.

  The capacitor 171 of the multilayer wiring board 161 includes an upper electrode 173 connected to the conductive material 169 in the through hole 167 via the wiring layer 176, and a lower electrode facing the upper electrode 173 via the dielectric layer 172. 174 and a wiring layer 177 that connects the lower electrode 174 to the conductive material of the adjacent through-hole 167. The upper electrode 173 is disposed on the core material 162 ′ via the insulating layer 179. The multilayer wiring board 161 includes a wiring layer 178 that is electrically connected to another through hole 167.

The upper electrode 173 is made of an anodizable metal, and the dielectric layer 172 is made of a metal oxide obtained by oxidizing an anodizable metal. Examples of such anodizable metal include Ta, Al, Ti, and W.
The materials of the lower electrode 174 and the wiring layers 176, 177 and 178 can be the same as those of the lower electrode 114 and the wiring layer 118 constituting the multilayer wiring board 101 described above.
Also, the multilayer wiring board 161 may be provided with a conductive substance diffusion preventing layer on the inner wall surface of the through-hole 167, similarly to the multilayer wiring board 101 shown in FIG.

  Further, in the multilayer wiring board of the present invention, like the multilayer wiring board 161 'shown in FIG. 9, the conductive material 169 filled in the through hole 167 protrudes from the surface of the core material 162', The lands 169a and 169b may be configured. The lands 169a and 169b preferably protrude from the core substrate surface within a range of 5 to 15 μm. This is because if the protrusion is 5 μm or less, a sufficient area of the through hole conductor portion cannot be secured, while if it exceeds 15 μm, it becomes an obstacle to making the wiring board thinner. In the illustrated example, the core substrate 162 is provided with insulating layers 165 'on both sides in order to obtain a flat surface.

[Manufacturing method of multilayer wiring board]
Next, a method for manufacturing a multilayer wiring board according to the present invention taking the multilayer wiring board with a built-in capacitor shown in FIGS. 1 to 9 as an example will be described as first to sixth embodiments of the manufacturing method.
In the multilayer wiring board manufacturing method of the present invention, the core material is a material having a thermal expansion coefficient in the XY direction of 2 to 20 ppm, and silicon, ceramics, glass, glass / epoxy composite material, and metal are used. . The thickness of the core substrate is preferably used in the range of 50 to 300 μm, and the through hole preferably has an opening diameter in the range of 10 to 300 μm. In the present invention, the fine hole means a hole that does not penetrate the core material, and the through hole means a hole that penetrates the core substrate in the usual way.

As a method for forming fine holes in these core materials, drilling, laser processing using a carbon dioxide laser or YAG laser, dry etching processing, or sand blasting is used according to the material characteristics of the core material. However, dry etching processing by ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) method is preferable in terms of forming fine holes, and sand blast processing is preferable in terms of productivity.
When fine holes are formed by each of the above processing methods, in dry etching processing and sand blast processing, a method is used in which a mask pattern is formed on the processing surface side of the core material, and a hole is drilled using this mask pattern as a mask. It is done.

(First Embodiment of Manufacturing Method)
FIGS. 10A to 10D and FIGS. 11A to 11D are process diagrams showing a method of manufacturing a multilayer wiring board according to an example of the embodiment of the present invention shown in FIG. 1, where silicon is used for the core substrate. It is a suitable manufacturing method.

A predetermined mask pattern 180 is formed with a mask material on one surface of the core material 182 ′ to be the core substrate (FIG. 10A). Next, a fine hole 187 'is drilled to a predetermined depth in the core material 182' by ICP-RIE using the mask pattern 180 as a mask (FIG. 10B). As a mask material at the time of etching, a positive type photoresist using a normal novolac resin having dry etching resistance may be used, a silicon thin film such as silicon oxide or silicon nitride that can take an etching selection ratio with silicon, A metal thin film such as titanium or tungsten may be formed in advance and patterned by a photoetching method to be used as a mask material.
For etching, a commercially available ICP-RIE apparatus can be used. As the etching gas, a fluorine-based gas such as SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F _8, or the like can be used. Further, in order to increase the etching rate, it is possible to mix a small amount of oxygen or nitrogen within a range that does not affect the mask material.

Once the core material 182 'is drilled to a predetermined depth to provide the fine holes 187', the mask pattern 180 is then removed from the core material 182 '.
After the formation of the fine hole 187 'as described above, when the core material 182' is silicon or a metal that is a conductor, an insulating layer 188 is formed on the inner wall surface of the fine hole 187 'and the entire front and back surfaces of the core material 182'. (FIG. 10C).
For example, when the core material 182 'is silicon, an insulating layer of silicon oxide can be formed on the surface of the core material 182' including the fine holes 187 'by thermal oxidation. In addition, an insulating layer such as silicon oxide or silicon nitride can be formed on the surface of the core material 182 ′ by using a vacuum film formation method such as a plasma CVD method. Furthermore, an insulating layer can be formed by applying a silicon oxide suspension or an insulating resin such as a benzocyclobutene resin, a cardo resin, or a polyimide resin to the surface of the core material and thermally curing the coating. .

  As shown in FIG. 2, in the production of a multilayer wiring board having a conductive material diffusion prevention layer, for example, a conductive material is formed by plasma MO-CVD (Metal Organic-Chemical Vapor Deposition) or sputtering. A diffusion preventing layer can be formed. The conductive substance diffusion preventing layer can be a thin film such as titanium nitride, titanium, or chromium, and the thickness is preferably about 10 to 50 nm.

  Next, as shown in FIG. 10D, a conductive material 189 is filled into the fine holes 187 ′. As the conductive material 189 filled in the fine hole 187 ', a conductive paste such as a copper paste or a silver paste can be used, and the filling method into the fine hole 187' is as follows. Conductivity can be imparted by printing or the like followed by heat treatment. Further, a base conductive thin film is formed on the inner wall of the fine hole 187 'by a vacuum film-forming method such as sputtering or vapor deposition, or an electroless plating method to form a seed layer. Alternatively, conductive fine holes can be formed by performing embedded plating with a conductive material such as gold or nickel.

Next, a multilayer wiring layer 183 is formed on one surface of the core substrate 182 (FIG. 11A). As a process for forming the multilayer wiring layer 183, any of a subtractive method using etching or an additive method using selective plating can be used.
For example, first, the first wiring layer 184a is formed on the core material 182 ', and then a photosensitive resin to be an insulating layer is applied by a spinner coating method or the like, and a photomask for forming the via 186a is used. After exposure and development to form a pattern, the resin is cured by thermal curing to form the first insulating layer 185a. Examples of these photosensitive resins include benzocyclobutene resin, cardo resin, and polyimide resin.

  Next, wiring is formed by a semi-additive method. That is, a conductive thin film layer for a plating base is formed on the entire surface of the patterned insulating layer by a vacuum film forming method such as a sputtering method. The conductive thin film layer is provided with a metal such as Al, Cu, or Cr, for example, to a thickness of about 0.1 to 0.5 μm.

  Subsequently, a photosensitive resist for plating is applied with a spinner, exposed using a photomask having a wiring pattern, and developed to form a resist pattern. The thickness of the resist pattern varies depending on the desired plating metal thickness, line width, pitch, and plating metal, but about 1 to 10 μm is used. Subsequently, a conductor such as Cu is plated to a thickness of several μm on the resist opening by electrolytic plating to form a plated metal layer.

  Next, the resist is peeled off, and the exposed unnecessary conductive thin film layer for plating base other than the electroplated portion is removed by soft etching, so that the second wiring having the desired via 186a and wiring 184b is obtained. Get a layer.

  Further, in the case of a multilayer wiring, it is formed by repeating the above steps. That is, the next insulating layer 185b is formed, and then the next via 186b and the third wiring layer 184c are formed (FIG. 11A). FIG. 11A shows a build-up multilayer wiring layer 183 composed of three insulating layers.

  Next, the other surface of the core material 182 'is polished to expose the fine holes 187' to form a through hole 187 having a conductive material 189, and a core substrate 182 having a desired thickness is formed (FIG. 11B). . The core material can be polished by back grinding or polishing with a polishing apparatus or the like. In the case of sandblasting, since the through hole is a taper, the fine hole is exposed and filled with a predetermined opening diameter by polishing the surface with a small hole diameter to a certain thickness. A through hole having a conductive layer made of a conductive material can be formed.

Next, a dielectric layer 192 serving as a capacitor material is formed on the polished core substrate 182 (FIG. 11C). As the dielectric layer 192, silicon oxide or silicon nitride is formed by CVD, tantalum pentoxide, barium strontium titanate (SrBaTiO ₃ ), lead zirconate titanate (Pb, (Zr, Ti) O ₃ ), Obtained by masking strontium titanate (SrTiO ₃ ) and aluminum oxide and depositing them by vacuum evaporation or sputtering, or by sol-gel deposition, or by depositing benzocyclobutene resin, cardo resin, or polyimide resin It is done. The dielectric layer 192 on the through hole 187 connected to the wiring layer in the next step is previously provided with an opening by a method such as a photolithography method or a masking vapor deposition method.

Next, a wiring layer 198 is provided in a predetermined through hole in which an opening is provided in the dielectric layer 192, and a lower electrode 194 is provided on the dielectric layer 192 in the through hole in which no opening is provided. As a result, the conductive material 189 filled in the through hole 187 is used as the upper electrode 193, and the capacitor 191 including the lower electrode 194 is formed through the dielectric layer 192. The multilayer wiring layer 183 and the built-in wiring layer 183 are formed on the core substrate 182. A multilayer wiring board 181 having a capacitor 191 is obtained (FIG. 11D).
The materials of the lower electrode 194 and the wiring layer 198 can be the same as those of the lower electrode 114 and the wiring layer 118 described in the multilayer wiring board.

(Second Embodiment of Manufacturing Method)
12A to 12C are process diagrams showing a method of manufacturing the multilayer wiring board according to the example of the embodiment of the present invention shown in FIG. 4, which is a preferable manufacturing method when silicon is used for the core substrate.
In this embodiment, the process up to the step of manufacturing the core substrate 182 having the multilayer wiring layer 183 formed on one surface is performed in the same manner as in the first embodiment (FIGS. 10A to 11B).

Next, an upper electrode 193 is formed on the polished core substrate 182 so as to be connected to the conductive material 189 in the through hole 187 at a position where a capacitor is to be formed (FIG. 12A). The upper electrode 193 is made smaller than the through hole 187. However, the upper electrode 193 is made larger than the through hole 187 by forming a new insulating layer on the polished core material 182 ′ surface (the surface on which the insulating layer 188 is not formed) shown in FIG. 11B. Can do. Next, a dielectric layer 192 serving as a capacitor material is formed on the core substrate 182 so as to cover the upper electrode 193 (FIG. 12B). As the dielectric layer 192, silicon oxide or silicon nitride is formed by CVD, tantalum pentoxide, barium strontium titanate (SrBaTiO ₃ ), lead zirconate titanate (Pb, (Zr, Ti) O ₃ ), Obtained by masking strontium titanate (SrTiO ₃ ) and aluminum oxide and depositing them by vacuum evaporation or sputtering, or by sol-gel deposition, or by depositing benzocyclobutene resin, cardo resin, or polyimide resin It is done. The dielectric layer 192 on the through hole 187 connected to the wiring layer in the next step is previously provided with an opening by a method such as a photolithography method or a masking vapor deposition method.

Next, a wiring layer 198 is provided in a predetermined through hole in which an opening is provided in the dielectric layer 192, and a lower electrode 194 is provided on the dielectric layer 192 of the through hole in which no opening is provided to form a capacitor 191. To do. Thereby, the multilayer wiring board 181 having the multilayer wiring layer 183 and the built-in capacitor 191 on the core substrate 182 is obtained (FIG. 12C).
The materials of the upper electrode 193, the lower electrode 194, and the wiring layer 198 can be the same as those of the lower electrode 114 and the wiring layer 118 described in the multilayer wiring board.

(Third Embodiment of Manufacturing Method)
13A to 13C are process diagrams showing a method for manufacturing the multilayer wiring board according to the example of the embodiment of the present invention shown in FIG. 6, and are preferable when silicon is used for the core substrate.
Also in this embodiment, the process up to the step of manufacturing the core substrate 182 having the multilayer wiring layer 183 formed on one surface is performed in the same manner as in the first embodiment (FIGS. 10A to 11B).

  Next, the upper electrode 193 is formed on the polished core substrate 182 through the insulating layer 195 so as to be connected to the conductive material 189 in the through hole 187 at the position where the capacitor is formed, and at the position where the capacitor is not formed. A wiring layer 198 is formed on a certain through hole 187 (FIG. 13A). The insulating layer 195 is formed by applying a photosensitive resin to be an insulating layer by a spinner coating method or the like, exposing using a photomask for forming the upper electrode 193 and the wiring layer 198, developing, and forming a pattern. The resin can be cured by heat curing. Examples of these photosensitive resins include benzocyclobutene resin, cardo resin, and polyimide resin.

Next, a resist pattern 199 is formed so that desired positions of the upper electrode 193 and the core substrate 182 are exposed, and a dielectric layer 192 serving as a capacitor material is formed in the exposed portion (FIG. 13B). As the dielectric layer 192, silicon oxide or silicon nitride is formed by CVD, tantalum pentoxide, barium strontium titanate (SrBaTiO ₃ ), lead zirconate titanate (Pb, (Zr, Ti) O ₃ ), Obtained by masking strontium titanate (SrTiO ₃ ) and aluminum oxide and depositing them by vacuum evaporation or sputtering, or by sol-gel deposition, or by depositing benzocyclobutene resin, cardo resin, or polyimide resin It is done.

Next, the resist pattern 199 is removed, a resist pattern for a lower electrode is provided, a lower electrode 194 is provided on the dielectric layer 192, and a capacitor 191 is formed. Thereby, the multilayer wiring board 181 having the multilayer wiring layer 183 and the built-in capacitor 191 on the core substrate 182 is obtained (FIG. 13C).
The materials of the upper electrode 193, the lower electrode 194, and the wiring layer 198 can be the same as those of the lower electrode 114 and the wiring layer 118 described in the multilayer wiring board.

(Fourth Embodiment of Manufacturing Method)
14A to 14C and FIGS. 15A to 15C are process diagrams showing a method for manufacturing a multilayer wiring board according to an example of the embodiment of the present invention shown in FIG. 8, and when silicon is used for the core substrate. This is a suitable manufacturing method.
Also in this embodiment, the process up to the step of manufacturing the core substrate 182 having the multilayer wiring layer 183 formed on one surface is performed in the same manner as in the first embodiment (FIGS. 10A to 11B).

  Next, an insulating layer 199 is formed over the polished core substrate 182. A desired opening is provided in the insulating layer 199 so that the conductive material 189 in the through hole 187 is exposed. Next, an anodizable metal layer is formed on the insulating layer 199 to form the upper electrode 193 (FIG. 14A). Examples of the metal that can be anodized include Ta, Al, Ti, and W. Moreover, the thickness of the upper electrode 193 can be set, for example in the range of 0.1-10 micrometers. Next, a resist pattern 199 ′ is formed on the insulating layer 199 so that a desired portion (a portion where the dielectric layer is formed) of the upper electrode 193 is exposed (FIG. 14B). Thereafter, the upper electrode 193 is anodized. As a result, a dielectric layer 192 made of a metal oxide is formed on the upper electrode 193 (FIG. 14C). The thickness of the dielectric layer 192 can be set in the range of 0.05 to 1 μm. The conditions for anodization can be appropriately set in consideration of the thickness of the dielectric layer 192 to be formed, the material of the upper electrode 193, and the like. Next, a lower electrode 194 is formed on the dielectric layer 192 (FIG. 15A).

Next, the resist pattern 199 ′ is removed, and a wiring forming opening 195a for connecting the conductive material 189 in the desired through hole and the upper electrode 193, the conductive material 189 and the lower electrode 194 in the adjacent through hole, An insulating layer 195 having an opening 195c for forming a wiring layer is formed on the through hole 187 at a position where a capacitor is not formed, and an opening 195b for forming a wiring connecting the capacitors (FIG. 15B).
The insulating layer 195 is formed by applying a photosensitive resin to be an insulating layer by a spinner coating method or the like, exposing using a photomask for forming the upper electrode 193 and the wiring layer 198, developing, and forming a pattern. The resin can be cured by heat curing. Examples of these photosensitive resins include benzocyclobutene resin, cardo resin, and polyimide resin.

Then, wiring layers 196, 197, and 198 are provided to form a capacitor 191. Thereby, the multilayer wiring board 181 having the multilayer wiring layer 183 and the built-in capacitor 191 on the core substrate 182 is obtained (FIG. 15C).
The materials of the lower electrode 194 and the wiring layers 196, 197, and 198 can be the same as those of the lower electrode 114 and the wiring layer 118 described in the multilayer wiring board.

FIGS. 16A to 16C and FIGS. 17A to 17B are process diagrams showing another method for manufacturing the multilayer wiring board according to the example of the embodiment of the present invention shown in FIG. 8, and silicon is used for the core substrate. In this case, the production method is suitable.
Also in this embodiment, the process up to the step of manufacturing the core substrate 182 having the multilayer wiring layer 183 formed on one surface is performed in the same manner as in the first embodiment (FIGS. 10A to 11B).
Next, an insulating layer 199 is formed over the polished core substrate 182. A desired opening is provided in the insulating layer 199 so that the conductive material 189 in the through hole 187 is exposed. Next, a resist pattern 201 having an opening for forming an upper electrode is formed on the insulating layer 199, and a metal layer 193 ′ that can be anodized by a vacuum film forming method is formed on the resist pattern 201. An upper electrode 193 is formed on the insulating layer 199 exposed in the opening (FIG. 16A). Examples of the metal that can be anodized include Ta, Al, Ti, and W. Moreover, the thickness of the upper electrode 193 can be set, for example in the range of 0.1-10 micrometers.

Next, a resist pattern 202 is formed on the metal layer 193 ′ so that a desired portion (a portion where the dielectric layer is formed) of the upper electrode 193 is exposed (FIG. 16B). Thereafter, the upper electrode 193 is anodized. As a result, a dielectric layer 192 made of a metal oxide is formed on the upper electrode 193 (FIG. 16C). The thickness of the dielectric layer 192 can be set in the range of 0.05 to 1 μm. The conditions for anodization can be appropriately set in consideration of the thickness of the dielectric layer 192 to be formed, the material of the upper electrode 193, and the like.
Next, a metal layer 194 ′ is formed on the resist pattern 202 by a vacuum film formation method, and a lower electrode 194 is formed on the dielectric layer 192 (FIG. 17A). Next, by removing the resist pattern 201, unnecessary metal layer 193 ′, resist pattern 202, and metal layer 194 ′ are simultaneously removed (lifted off). As a result, a laminate including the upper electrode 193, the dielectric layer 192, and the lower electrode 194 is disposed at a desired position of the insulating layer 199 (FIG. 17B). Thereafter, the multilayer wiring board 181 (FIG. 17C) having the multilayer wiring layer 183 and the built-in capacitor 191 on the core substrate 182 is obtained by the same process as that of FIG.
The material of the lower electrode 194 (metal layer 194 ′) can be the same as that of the lower electrode 114 and the wiring layer 118 described in the multilayer wiring board.

(Fifth Embodiment of Manufacturing Method)
FIG. 18A to FIG. 18D and FIG. 19A to FIG. 19D illustrate the case where a through hole is formed by the sandblast method, and a predetermined mask pattern is formed on one surface of the core material 212 'for the core substrate. A fine hole 217 'is drilled in the core material 212' to a predetermined depth by sand blasting using this mask pattern 210 as a mask (FIG. 18A).

Next, the mask pattern 210 is removed from the core material 212 '(FIG. 18C). In the present embodiment, a case where glass as an insulator is used for the core material 212 'will be described as an example.
Next, the conductive material 219 is filled in the fine holes 217 ′ (FIG. 18D). As the conductive material 219 filled in the fine holes, a conductive paste such as a copper paste or a silver paste can be used, and filling into the fine holes is performed by screen printing or the like. Conductivity can be imparted by heat treatment. In addition, a base conductive thin film is formed on the inner wall of the fine hole by a vacuum film forming method such as sputtering or vapor deposition, or an electroless plating method, and this base conductive layer is used as a seed layer by electrolytic plating to form copper, silver, gold, nickel. It can also be set as a conduction | electrical_connection part by depositing conductive materials, such as.

  In the case of forming micropores by the sandblasting method, the micropores have a taper, so that the conductive material can be easily attached to the inner wall surface of the micropore from the surface having a large aperture diameter, and the micropore, that is, the through hole is formed. -The yield of the process for making the hole conductive is improved, the time is shortened, and stable production and production cost reduction are possible.

  Note that an insulating layer may be formed on the inner wall surface of the fine hole and one or both surfaces of the core material before filling the conductive material 219 into the fine hole. For example, when the core material is silicon, which is a semiconductor material, a silicon oxide film or a silicon nitride film is formed on the surface of the core material by using a vacuum film formation method such as a thermal oxidation method, a CVD method, or a sputtering method. be able to. In the case of a conductor such as metal, depending on the coating method, a silicon oxide suspension or an insulating resin such as benzocyclobutene resin, cardo resin, or polyimide resin is applied to the surface of the core material and thermally cured. Thus, an insulating layer can be formed in a necessary portion.

Next, as shown in FIG. 19A, a multilayer wiring layer 213 is formed on the surface of the core material 212 ′ on the side where the conductive material 219 is filled in the fine holes 217 ′. As a formation process of the multilayer wiring layer 213, any of a subtractive method using etching or an additive method using selective plating can be used.
For example, first, the first wiring layer 214a is formed on the core material 212 ', and then a photosensitive resin to be an insulating layer is applied by a spinner coating method or the like, and a photomask for forming the via 216a is used. After exposure and development to form a pattern, the resin is cured by thermal curing to form the first insulating layer 215a. Examples of these photosensitive resins include benzocyclobutene resin, cardo resin, and polyimide resin.

  Next, wiring is formed by a semi-additive method. That is, a conductive thin film layer for a plating base is formed on the entire surface of the patterned insulating layer by a vacuum film forming method such as a sputtering method. The conductive thin film layer is provided with a metal such as Al, Cu, or Cr, for example, to a thickness of about 0.1 to 0.5 μm.

  Subsequently, a photosensitive resist for plating is applied with a spinner, exposed using a photomask having a wiring pattern, and developed to form a resist pattern. The thickness of the resist pattern varies depending on the desired plating metal thickness, line width, pitch, and plating metal, but about 1 to 10 μm is used. Subsequently, a conductor such as Cu is plated to a thickness of several μm on the resist opening by electrolytic plating to form a plated metal layer.

  Next, the resist is peeled off and the exposed unnecessary conductive thin film layer for plating base other than the electroplated portion is removed by soft etching, and the second wiring having the desired via 216a and wiring 214b is obtained. Get a layer.

  Further, in the case of a multilayer wiring, it is formed by repeating the above steps. That is, the next insulating layer 215b is formed, and then the next via 216b and the third wiring 214 are formed (FIG. 19A). FIG. 19A shows a build-up multilayer wiring layer 213 composed of two insulating layers.

  Next, the other surface of the core material 212 ′ is polished to expose the fine holes 217 ′ to form a through hole 217 having a conductive material 219, thereby forming a core substrate 212 having a desired thickness (FIG. 19B). . The core material can be polished by back grinding or polishing with a polishing apparatus or the like. In the case of sandblasting, fine holes, i.e., through holes, are formed into a taper shape, so that a through hole having a conductive material can be formed by being exposed with a predetermined opening diameter.

Next, a dielectric layer 222 serving as a capacitor material is formed on the polished core substrate 212 (FIG. 19C). As the dielectric layer 222, silicon oxide or silicon nitride is formed by CVD, tantalum pentoxide, barium strontium titanate (SrBaTiO ₃ ), lead zirconate titanate (Pb, (Zr, Ti) O ₃ ), Obtained by masking strontium titanate (SrTiO ₃ ) and aluminum oxide and depositing them by vacuum evaporation or sputtering, or by sol-gel deposition, or by depositing benzocyclobutene resin, cardo resin, or polyimide resin It is done. The dielectric layer 222 on the through hole 217 connected to the wiring layer in the next step is previously provided with an opening by a method such as photolithography or masking vapor deposition.

Next, a wiring layer 228 is provided in a predetermined through hole in which an opening is provided in the dielectric layer 222, and a lower electrode 224 is provided on the dielectric layer 222 in the through hole in which no opening is provided to form a capacitor 221. To do. Thereby, the multilayer wiring board 211 having the multilayer wiring layer 213 and the built-in capacitor 221 on the core substrate 212 is obtained (FIG. 19D).
The process until the core substrate 212 having the multilayer wiring layer 213 formed on one surface is made in the same manner as in the above-described fifth embodiment, and then the same as in the above-described second to fourth embodiments. The capacitor may be formed by a method. Thereby, the multilayer wiring board of the aspect shown by FIG.4, FIG.6, FIG.8 can be manufactured.

(Sixth Embodiment of Manufacturing Method)
Another embodiment of the manufacturing method of the present invention will be described based on FIGS. 20A to 20E and FIGS. 21A to 21E.
20A to 20E and FIGS. 21A to 21E are process diagrams showing a method for manufacturing a multilayer wiring board according to an example of the embodiment of the present invention shown in FIG. 3, and are suitable when silicon is used for the core substrate. It is a simple manufacturing method.

First, as shown in FIG. 20A, a predetermined mask pattern 251 is formed with a mask material on one surface of the core material 232 ′.
Next, fine holes 237 'are drilled in the core material 232' to a predetermined depth by ICP-RIE using the mask pattern 251 as a mask (FIG. 20B). As a mask material at the time of etching, a positive type photoresist using a normal novolac resin having dry etching resistance may be used, a silicon thin film such as silicon oxide or silicon nitride that can take an etching selection ratio with silicon, A metal thin film such as titanium or tungsten may be formed in advance and patterned by a photoetching method to be used as a mask material.

For etching, a commercially available ICP-RIE apparatus can be used. As the etching gas, a fluorine-based gas such as SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F _8, or the like can be used. Further, in order to increase the etching rate, it is possible to mix a small amount of oxygen or nitrogen within a range that does not affect the mask material.

  After the fine holes 237 'are drilled into the core material 232' to a predetermined depth as described above, the mask pattern 251 is removed from the core material 232 ', and the other surface of the core material 232' is polished. Through holes 237 'are exposed on the surface of the core material 232' with a predetermined opening diameter to form a through hole 237 (FIG. 20C). The core material 232 'can be polished by back grinding, polishing, or the like. In this embodiment, silicon is used as a core material, and through holes 237 having substantially the same opening diameters on the front and back sides are obtained by polishing after trench etching.

  An insulating layer 238 is formed on both surfaces of the core material 232 'on which the through hole 237 is formed and on the inner wall surface of the through hole (FIG. 20D). For example, when the core material 232 ′ is silicon, the insulating layer 238 can be formed on the surface of the core material 232 ′ including the through holes 237 by thermal oxidation. In addition, an insulating layer such as silicon oxide or silicon nitride can be formed on the surface of the core material by using a vacuum film formation method such as a plasma CVD method. Furthermore, an insulating layer can be formed by applying a silicon oxide suspension or an insulating resin such as a benzocyclobutene resin, a cardo resin, or a polyimide resin to the surface of the core material and thermally curing the coating. .

  In addition, as shown in FIG. 2, in the production of a multilayer wiring board having a conductive material diffusion prevention layer, for example, a conductive material is formed by plasma MO-CVD (Metal Organic-Chemical Vapor Deposition) or sputtering. A diffusion preventing layer can be formed. The conductive substance diffusion preventing layer can be a thin film such as titanium nitride, titanium, or chromium, and the thickness is preferably about 10 to 50 nm.

After the insulating layer 238 is formed or after the insulating layer 238 and the conductive material diffusion preventing layer are formed, a dry film is laminated as a photosensitive resist on the front and back of the core material 232 ', and a desired through hole is formed. By exposing and developing with a photomask having a land diameter, a resist pattern 252 exposing the periphery of the through hole 237 and its opening is formed on the front and back surfaces of the core material 232 '(FIG. 20E).
Next, conductive paste is filled in the through hole and resist pattern opening as a conductive material 239 by a coating method such as screen printing (FIG. 21A). As the conductive paste, a conductive paste such as a copper paste or a silver paste can be used.

Subsequently, after the conductive paste is dried and cured, the conductive material 239 protruding from the surface of the resist pattern 252 on both the front and back surfaces is polished and removed, and the surface of the conductive material 239 and the surface of the resist pattern 252 are removed. Are on the same plane (FIG. 21B).
As a method of filling the through hole and resist pattern opening with the conductive material 239, a method using electrolytic plating may be used in addition to the method of filling the conductive paste. For example, a base conductive thin film is formed from one of the core materials 232 'by a vacuum film forming method, and a seed layer is formed in a part of the through hole 237 and a resist pattern opening. Thereafter, using this seed layer, metal can be deposited and filled in the through hole 237 and the resist pattern opening by electrolytic plating. As the seed layer, a conductive film such as copper having a thickness of 0.1 to 0.4 μm is preferable.

  Next, the resist 252 is peeled off, and the core substrate having the through holes 237 filled with the conductive material 239 having the lands 239 a and 239 b of the desired diameter formed on the front and back surfaces of the core material 232 ′ formed of the conductive material 239. 232 is formed (FIG. 21C). The heights of the lands 239a and 239b formed of a conductive material protruding from the through hole are defined by the resist thickness of the dry film resist, and the land diameter is defined by the size of the mask pattern.

In the manufacturing method of the present invention, the dry film resist prevents the problem that the wiring layer formed of copper, aluminum or the like provided on the surface of the core material 232 ′ in the previous step is oxidized during the drying and curing of the conductive paste. It also has an effect.
Next, an insulating layer 235 ′ is formed on one or both surfaces of the core substrate 232 so as to serve as a planarizing layer (FIG. 21D). As the insulating layer 235 ′, for example, a photosensitive resin such as benzocyclobutene resin, cardo resin, or polyimide resin is patterned by photolithography.

Next, a multilayer wiring layer is formed on one surface of the core substrate 232. Such a multilayer wiring layer can be formed according to the method described in the first embodiment of the manufacturing method described above.
Then, a capacitor is formed on the other surface of the core substrate 232 on which the multilayer wiring layer is formed by the method shown in FIGS. 11C and 11D described above to manufacture the multilayer wiring substrate 101 ′ of the present invention shown in FIG. can do.
Further, by forming a capacitor by the method shown in FIGS. 12A to 12C on the other surface of the core substrate 232 on which the multilayer wiring layer is formed as described above, the multilayer wiring board of the present invention shown in FIG. 121 'can be manufactured.

Further, by forming a capacitor by the method shown in FIGS. 13A to 13C on the other surface of the core substrate 232 on which the multilayer wiring layer is formed as described above, the multilayer wiring board of the present invention shown in FIG. 141 'can be manufactured.
Furthermore, the capacitor is formed on the other surface of the core substrate 232 on which the multilayer wiring layer is formed as described above by the method shown in FIGS. 14A to 14C and FIGS. 15A to 15C. The multilayer wiring board 161 'of the present invention can be manufactured.

Next, the present invention will be described in more detail by showing more specific examples.
Example 1
As a core material, a silicon substrate having a thickness of 300 μm was prepared, and a silicon nitride film having a thickness of 5 μm was formed on one surface of the core material by a plasma CVD method. Next, on the silicon nitride film, a positive type photoresist (Tokyo Ohka Kogyo Co., Ltd. OFPR-800) is applied, exposed and developed through a photomask for forming a through hole, thereby forming a resist pattern. Formed. Next, the silicon nitride exposed from the resist pattern was etched using CF ₄ as an etching gas, and then the resist was stripped with a special stripping solution to form a mask pattern of silicon nitride. The mask pattern was a circular opening having a diameter of 100 μm formed at a pitch of 150 to 500 μm.

Next, the silicon exposed from the mask pattern of the silicon nitride film was trench-etched to a depth of 250 μm using SF ₆ as an etching gas by an ICP-RIE apparatus to form fine holes.

Next, the silicon substrate in which the fine holes were formed was thermally oxidized to form an insulating layer made of a silicon oxide film and a silicon nitride film on the surface of the core material including the inner wall surface of the fine holes.
Next, a conductive material diffusion prevention layer made of titanium nitride and having a thickness of 10 nm was formed on the insulating layer by MO-CVD (Metal Organic-Chemical Vapor Deposition) using plasma.
Next, a copper paste was applied and filled in the fine holes by a screen printing method and cured (170 ° C., 20 minutes). Thereafter, the copper paste protruding from the surface of the core material was removed by polishing to obtain a core material in which the surface of the core material and the paste filled in the fine holes were flush with each other. The core material had a micropore diameter of 100 μm, and the inside of the micropore was filled with a conductive material.

  Next, a build-up multilayer wiring layer was formed on one surface of the core substrate by a semi-additive method. That is, by sputtering, a two-layer Cr / Cu film having a thickness of about 0.5 μm is formed on the entire surface of the substrate as a conductive thin film layer for plating, and then a liquid resist for plating (Tokyo Ohka Kogyo Co., Ltd.). LA900) was applied with a spinner, exposed using a photomask for the first layer wiring pattern, and developed to form a resist pattern having a thickness of 5 μm. Subsequently, Cu was plated on the resist opening to a thickness of 4 μm by electrolytic plating, and then the unnecessary Cr / Cu layer was removed by soft etching to form a first wiring layer.

  Next, a photosensitive benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) is formed by patterning as an insulating layer, and then a conductive thin film for plating under the entire surface of the substrate by sputtering. A layer was formed. The conductive thin film layer was provided with Cu to a thickness of about 0.5 μm.

  Subsequently, a liquid resist for plating (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied, exposed and developed using a photomask for the second layer wiring pattern, and a resist pattern having a thickness of 5 μm. Formed. Subsequently, Cu was plated on the resist opening to a thickness of 4 μm by electrolytic plating.

  Next, the resist is peeled off and the exposed conductive thin film layer for unnecessary plating base other than the electroplated portion is removed by soft etching to remove the second layer having a desired via and wiring pattern. A wiring layer was obtained.

  A third-layer wiring was formed in the same manner, and a patterned insulating layer was provided thereon to form a build-up multilayer wiring layer.

  Next, an adhesive tape was attached to the side on which the multilayer wiring layer was formed, and the silicon substrate was ground to a thickness of 200 μm with a diamond grinder to expose the fine holes, thereby forming a through hole. In this example, a substantially vertical through hole filled with a conductive material was obtained.

Next, a desired position (through hole opening connected to the wiring layer) on the polished core substrate was masked, and SrBaTiO ₃ was formed by sputtering using an RF magnetron sputtering apparatus and annealed. Thereby, the dielectric layer was formed except for the through-hole opening connected to the wiring layer. Subsequently, a Cu thin film (0.2 μm thick) was formed on the dielectric layer by sputtering, and Cu was electroplated to a thickness of 3 μm. This Cu film was patterned by photolithography. Thus, a wiring layer connected to the through hole and a lower electrode were formed. As a result, a multilayer wiring board having a capacitor composed of the lower electrode via the dielectric layer with the conductive material in the through hole not opened as the upper electrode was obtained.

  Next, the electrical characteristics of the multilayer wiring board according to the manufacturing method of the present invention were examined. By using the built-in capacitor as a decoupling capacitor, the capacitor was externally attached as an electronic component without reducing the mounting density. It was also confirmed that the switching noise can be greatly reduced.

(Example 2)
As a core material, a glass substrate having a thickness of 300 μm was prepared, and a photosensitive dry film resist (Tokyo BF 405 made by Tokyo Ohka Kogyo Co., Ltd.) was laminated on one surface of the core material. A mask pattern was formed by exposure and development through a photomask for formation. The mask pattern was a circular opening having a diameter of 150 μm formed at a pitch of 300 to 500 μm.

  Next, using this mask pattern as a mask, fine holes were drilled in the core material by sandblasting. The fine holes had a taper shape with an opening diameter of 150 μm, a depth of 250 μm, and an inner diameter of the bottom of 80 μm. Subsequently, the mask pattern was removed from the core material with acetone.

  Next, the copper paste is filled into the fine holes of the core material by a screen printing method, heat-treated at 170 ° C. for 20 minutes, and then the copper paste protruding from the surface of the core material is removed by polishing. The copper paste surface and the core material surface were made to be the same surface.

  Next, in the same manner as in Example 1, a build-up multilayer wiring layer was formed on one surface of the core substrate by a semi-additive method.

  Next, an adhesive tape was attached to the side on which the multilayer wiring layer was formed, and the glass substrate was ground to a thickness of 200 μm with a diamond grinder to expose fine holes, thereby forming a through hole. In this example, a tapered through hole filled with a conductive material was obtained.

Next, a photosensitive benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co., Ltd.) as a dielectric layer was applied onto the polished core material by a spinner coating method. Next, after exposure using a desired photomask, development and pattern formation, the resin was cured by thermal curing. As a result, an insulating layer having an opening for forming a wiring layer connected to the conductive material in the through hole was formed.
Next, a conductive thin film layer for plating base was formed on the entire surface of the substrate by sputtering. The conductive thin film layer was provided with Cu to a thickness of about 0.2 μm.

  Subsequently, a liquid resist for plating (LA900 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied with a spinner, exposed using a photomask having a wiring pattern, developed, and a resist pattern having a thickness of 5 μm was formed. Formed. Subsequently, Cu was plated on the resist opening to a thickness of 3 μm by electrolytic plating.

  Next, the resist was peeled off, and unnecessary conductive thin film layers for plating base other than the electroplated portions were removed by soft etching. Accordingly, the wiring layer connected to the conductive material in the through hole is provided, and the capacitor including the conductive material in the through hole that is not opened as the upper electrode and the lower electrode through the dielectric layer is provided. A multilayer wiring board was obtained.

  As a result of investigating the electrical characteristics of the multilayer wiring board according to the manufacturing method of the present invention, it was confirmed that switching noise can be significantly reduced by using the built-in capacitor as a decoupling capacitor, as in Example 1.

(Example 3)
A silicon substrate having a thickness of 625 μm was prepared as a core material, and silicon nitride was formed into a thickness of 5 μm on one surface of the core material by a plasma CVD method. Next, on the silicon nitride film, a positive type photoresist (Tokyo Ohka Kogyo Co., Ltd. OFPR-800) is applied, exposed and developed through a photomask for forming a through hole, thereby forming a resist pattern. Formed. Next, the silicon nitride exposed from the resist pattern was etched using CF ₄ as an etching gas, and the resist was stripped with a dedicated stripping solution to form a mask pattern of silicon nitride. The mask pattern was a circular opening having a diameter of 100 μm formed at a pitch of 150 to 500 μm.

Next, the silicon exposed from the mask pattern of the silicon nitride film was trench-etched to a depth of 350 μm using SF ₆ as an etching gas by an ICP-RIE apparatus.
Next, an adhesive tape was attached to the fine hole side, and the silicon substrate was ground to a thickness of 300 μm with a diamond grinder to obtain a through hole penetrating the fine hole. In this example, a substantially vertical through hole was obtained.

Next, the silicon substrate on which the through hole was formed was thermally oxidized to form an insulating layer made of a silicon oxide film and a silicon nitride film on the surface of the core material including the inner wall surface of the through hole.
Next, a conductive material diffusion prevention layer made of titanium nitride and having a thickness of 10 nm was formed on the insulating layer by MO-CVD (Metal Organic-Chemical Vapor Deposition) using plasma.

Next, a copper conductive thin film was formed on both surfaces of the core material by sputtering, and then electrolytic plating was performed to obtain a predetermined plating thickness, followed by pattern etching by a photolithography method to form a desired wiring.
Next, a dry film as a photosensitive resist is laminated on the front and back of the core material, exposed with a photomask having a land diameter of 150 μm as a desired through hole, developed, and A resist pattern exposing the periphery of the opening was formed on the front and back of the core material.

Next, the conductive holes of copper were filled in the through holes and the resist pattern openings by screen printing.
Subsequently, after the conductive paste is dried and cured (170 ° C., 20 minutes), the conductive paste protruding from the front and back resist surfaces is removed by double-side polishing, and the surface of the conductive paste is removed. And the resist surface were made to be the same surface.

  Next, the resist was peeled off. As a result, a core substrate having a through hole filled with the conductive paste having lands of a desired diameter formed on the front and back surfaces formed of the conductive paste was obtained. This core substrate has a through hole diameter of approximately 100 μm on both the front and back sides, and is electrically connected to the front and back by a conductive paste. The diameter was 150 μm, and both the front and back sides had a height of 10 μm from the core material surface.

Next, an insulating layer was formed to make the polished surface of the core substrate a flat surface. The insulating layer was formed by patterning a benzocyclobutene resin composition (Cycloten 4024 manufactured by Dow Chemical Co.) as a photosensitive resin.
A build-up multilayer wiring layer was formed in the same manner as in Example 3 on one surface of the core substrate flattened by the insulating layer as described above.

Next, a desired position (through-hole opening connected to the wiring layer) on the other surface of the core substrate was masked, and SrBaTiO ₃ was formed by sputtering using an RF magnetron sputtering apparatus and annealed. Thereby, the dielectric layer was formed except for the through-hole opening connected to the wiring layer. Subsequently, a Cu thin film (0.2 μm thick) was formed on the dielectric layer by sputtering, and Cu was electroplated to a thickness of 3 μm. This Cu film was patterned by photolithography. Thus, a wiring layer connected to the through hole and a lower electrode were formed. As a result, a multilayer wiring board having a capacitor composed of the lower electrode via the dielectric layer with the conductive material in the through hole not opened as the upper electrode was obtained.

  Next, the electrical characteristics of the multilayer wiring board according to the manufacturing method of the present invention were examined. By using the built-in capacitor as a decoupling capacitor, the capacitor was externally attached as an electronic component without reducing the mounting density. It was also confirmed that the switching noise can be greatly reduced.

  It can be applied to small semiconductor devices and various electronic devices that require high reliability.

It is a fragmentary longitudinal cross-sectional view which shows typically one Embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is a partial longitudinal cross-sectional view which shows typically other embodiment of the multilayer wiring board of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention. It is process drawing which shows other embodiment of the manufacturing method of the multilayer wiring board of this invention.

Explanation of symbols

101, 101 ', 121, 121', 141, 141 ', 161, 161', 181, 211 ... Multilayer wiring board 102, 122, 142, 162, 182, 212, 232 ... Core board 102 ', 122', 142 ', 162', 182 ', 212', 232 '... core material 103, 123, 143, 163, 183, 213 ... multilayer wiring layers 104, 124, 144, 164, 184a, 184b, 184c, 184d, 214a, 214b , 214c ... Wiring layers 105, 125, 145, 165, 185a, 185b, 185c, 215a, 215b ... Insulating layers 106, 126, 146, 166, 186a, 186b, 186c, 216a, 216b ... Vias 107, 127, 147, 167, 187, 217, 237 ... through hole 187 ', 2 7 ', 237' ... fine holes 109, 129, 149, 169, 189, 219, 239 ... conductive materials 111, 131, 151, 171, 191, 221 ... capacitors 112, 132, 152, 172, 192, 222 ... dielectrics Body layer 113, 133, 153, 173, 193, 223 ... Upper electrode 114, 134, 154, 174, 194, 224 ... Lower electrode

Claims (23)

In a multilayer wiring board formed by laminating a core substrate and a wiring layer and an insulating layer on one surface of the core substrate,
The thermal expansion coefficient in the XY direction of the core substrate is in the range of 2 to 20 ppm, and the core material for the core substrate is a core material selected from silicon, ceramics, glass, glass / epoxy composite material, metal,
The core substrate includes a plurality of through holes that are electrically connected to each other by a conductive material.
A capacitor is provided on the other surface of the core substrate ,
The capacitor includes an upper electrode provided on the core substrate via an insulating layer so as to be connected to the conductive material in the through hole, and a dielectric provided so as to cover at least a part of the upper electrode multi-layer wiring board to the layer, characterized that you have been composed of a lower electrode provided so as to cover at least a portion of the dielectric layer. In a multilayer wiring board formed by laminating a core substrate and a wiring layer and an insulating layer on one surface of the core substrate,
The thermal expansion coefficient in the XY direction of the core substrate is in the range of 2 to 20 ppm, and the core material for the core substrate is a core material selected from silicon, ceramics, glass, glass / epoxy composite material, metal,
The core substrate includes a plurality of through holes that are electrically connected to each other by a conductive material.
A capacitor is provided on the other surface of the core substrate ,
The capacitor includes an upper electrode made of an anodizable metal connected to the conductive material in the through hole and provided on the core substrate, and the upper electrode through a dielectric layer made of the metal oxide. multilayer wiring board characterized that you have been composed of a lower electrode disposed to face the. The material of the dielectric layer constituting the capacitor is silicon oxide, silicon nitride, barium strontium titanate, tantalum pentoxide, lead zirconate titanate, strontium titanate, aluminum oxide, benzocyclobutene resin, cardo resin, polyimide The multilayer wiring board according to claim 1 or 2 , wherein the multilayer wiring board is selected from any one of resins. The wiring layer and the lower electrode are made of any one of Al, Cr, Cu, Ti, Pt, Ru, Ta, W, oxides, nitrides, alloys of these metals, and the metals. , oxides, nitrides, according to any one of claims 1 to 3, characterized in that those selected from the group consisting of a multilayer film composed of any combination of alloy and polysilicon Multilayer wiring board. The thickness of the said core board | substrate is in the range of 50-300 micrometers, and the opening diameter of the said through hole is in the range of 10-300 micrometers, The one of the Claims 1 thru | or 4 characterized by the above-mentioned. Multilayer wiring board. The sul - E - multilayer wiring board according to any one of claims 1 to 5, characterized in that it comprises a electroconductive material diffusion barrier layer on the inner wall surface of the Le. The multilayer wiring board according to claim 6 , wherein the conductive material diffusion preventing layer is a titanium nitride thin film. The multilayer wiring board according to claim 6 or claim 7 opening diameter of Le is being in the range of 10 to 30 [mu] m - E - sul of the core material. In a manufacturing method of a multilayer wiring board formed by laminating a core substrate and a wiring layer and an insulating layer on one surface of the core substrate,
The core substrate has a thermal expansion coefficient in the XY direction of 2 to 20 ppm, and a plurality of fine holes are formed in the core material selected from silicon, ceramics, glass, glass / epoxy composite material, and metal. Process,
Making the micropores conductive with a conductive material;
Forming a multilayer wiring layer by laminating a wiring layer and an insulating layer on the core substrate on the perforated side of the fine holes;
Polishing the other surface of the core substrate provided with the fine holes, exposing the fine holes made conductive by the conductive material, and forming a plurality of through holes for conducting the front and back of the core substrate; ,
Have a, and forming a capacitor on a core substrate surface that is the polishing,
In the step of forming the capacitor, an insulating layer is formed on the core substrate surface, and an upper electrode is formed on the insulating layer so as to be connected to a conductive material in a through hole at a position where the capacitor is formed. Forming a wiring layer so as to connect with a conductive material in a through hole at a position not to be formed;
And characterized in that organic and forming a lower electrode so that the dielectric layer is formed on the insulating layer so as to cover at least a portion of the upper electrode covers at least a portion of the dielectric layer A method for manufacturing a multilayer wiring board. In a manufacturing method of a multilayer wiring board formed by laminating a core substrate and a wiring layer and an insulating layer on one surface of the core substrate,
The core substrate has a thermal expansion coefficient in the XY direction of 2 to 20 ppm, and a plurality of fine holes are formed in the core material selected from silicon, ceramics, glass, glass / epoxy composite material, and metal. Process,
Making the micropores conductive with a conductive material;
Forming a multilayer wiring layer by laminating a wiring layer and an insulating layer on the core substrate on the perforated side of the fine holes;
Polishing the other surface of the core substrate provided with the fine holes, exposing the fine holes made conductive by the conductive material, and forming a plurality of through holes for conducting the front and back of the core substrate; ,
Have a, and forming a capacitor on a core substrate surface that is the polishing,
The step of forming the capacitor includes the step of forming an upper electrode made of an anodizable metal on the core substrate surface;
Forming a dielectric layer by anodizing the surface of the upper electrode to form a metal oxide;
Forming a lower electrode on the dielectric layer;
Forming a wiring layer so as to connect the conductive material in the through hole at a position where the capacitor is formed and the upper electrode, and forming a wiring layer on the through hole where the capacitor is not formed; method for manufacturing a multilayer wiring board, characterized by chromatic. 11. The multilayer wiring board according to claim 9 , wherein a conductive material diffusion prevention layer is formed on an inner wall surface of the microhole after forming the microhole having an opening diameter in a range of 10 to 300 μm. Production method. 12. The method of manufacturing a multilayer wiring board according to claim 11 , wherein the conductive material diffusion preventing layer is formed by MO-CVD. Method for manufacturing a multilayer wiring board according to claim 11 or claim 12 wherein the micropores opening diameter and forming to be within the range of 10 to 30 [mu] m. The method for manufacturing a multilayer wiring board according to any one of claims 9 to 13 , wherein the method for forming the micropores is an ICP-RIE method or a sandblast method. A step of conducting a a conductive material fine pores 9 through claim, wherein the method of filling the conductive paste in the micropores, or is any of a method of filling a conductive material by plating micropores The manufacturing method of the multilayer wiring board of any one of Claim 14 . In the method of filling the conductive material by plating, a base conductive thin film is formed by vacuum film formation from the core material surface side where the fine holes are formed, and the base conductive thin film is formed on a part of the inner wall surface of the fine holes. 16. The method for manufacturing a multilayer wiring board according to claim 15 , wherein a seed layer is formed, and a metal is deposited and filled in the micropores by electrolytic plating using the seed layer. In a manufacturing method of a multilayer wiring board formed by laminating a core substrate and a wiring layer and an insulating layer on one surface of the core substrate,
The core substrate has a thermal expansion coefficient in the XY direction of 2 to 20 ppm, and a plurality of through holes are formed in the core material selected from silicon, ceramics, glass, glass / epoxy composite material, and metal. Process,
Making the through hole conductive with a conductive material and conducting the front and back of the core substrate;
Forming a multilayer wiring layer by stacking a wiring layer and an insulating layer on one surface of the core substrate;
Have a, and forming a capacitor on the other surface of the core substrate,
In the step of forming the capacitor, an insulating layer is formed on the core substrate surface, and an upper electrode is formed on the insulating layer so as to be connected to a conductive material in a through hole at a position where the capacitor is formed. Forming a wiring layer so as to connect with a conductive material in a through hole at a position not to be formed;
And characterized in that organic and forming a lower electrode so that the dielectric layer is formed on the insulating layer so as to cover at least a portion of the upper electrode covers at least a portion of the dielectric layer A method for manufacturing a multilayer wiring board. In a manufacturing method of a multilayer wiring board formed by laminating a core substrate and a wiring layer and an insulating layer on one surface of the core substrate,
The core substrate has a thermal expansion coefficient in the XY direction of 2 to 20 ppm, and a plurality of through holes are formed in the core material selected from silicon, ceramics, glass, glass / epoxy composite material, and metal. Process,
Making the through hole conductive with a conductive material and conducting the front and back of the core substrate;
Forming a multilayer wiring layer by stacking a wiring layer and an insulating layer on one surface of the core substrate;
Have a, and forming a capacitor on the other surface of the core substrate,
The step of forming the capacitor includes the step of forming an upper electrode made of an anodizable metal on the core substrate surface;
Forming a dielectric layer by anodizing the surface of the upper electrode to form a metal oxide;
Forming a lower electrode on the dielectric layer;
Forming a wiring layer so as to connect the conductive material in the through hole at a position where the capacitor is formed and the upper electrode, and forming a wiring layer on the through hole where the capacitor is not formed; method for manufacturing a multilayer wiring board, characterized by chromatic. The step of making the through hole conductive with a conductive material and conducting the front and back of the core substrate is formed by forming a base conductive thin film from one side of the core substrate by a vacuum film forming method, and forming the base on a part of the inner wall surface of the through hole. Forming a seed layer made of a conductive thin film;
The method of manufacturing a multilayer wiring board according to claim 17 , further comprising a step of depositing and growing a metal from the seed layer into a through hole by electrolytic plating using the seed layer as a power feeding layer. Method. After forming a through-hole, a method for manufacturing a multilayer wiring board according to any one of claims 17 to claim 19, characterized in that to form the electroconductive material diffusion barrier layer on the inner wall surface of the through hole. 21. The method of manufacturing a multilayer wiring board according to claim 20 , wherein the conductive material diffusion prevention layer is formed by MO-CVD. The method for manufacturing a multilayer wiring board according to claim 20 or 21 , wherein the through hole is formed so that an opening diameter is in a range of 10 to 30 µm. The method for producing a multilayer wiring board according to any one of claims 17 to 22 , wherein the through hole is formed by an ICP-RIE method or a sand blast method.

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