JP2001015928A - Multilayer printed wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multilayer printed wiring board having functions of capacitor in its build-up wiring layer and its manufacturing method. SOLUTION: An intermediate conductor circuit 16 is provided between adjacent conductor circuits formed in a build-up wiring layer, a dielectric layer 15 containing at least a high-inductivity material is formed between the intermediate conductor circuit 16 and one of the adjacent conductor circuits for imparting capacitor functions in the build-up wiring layer and the conductor layers are connected by via holes 25 and 26. In this way, an excellent power supply stability in a high-frequency area can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board having a build-up wiring layer, and more particularly to a multilayer printed wiring board having a dielectric layer having a capacitor function formed between conductive circuits formed in an interlayer resin insulating layer. We propose a printed wiring board.

[0002]

2. Description of the Related Art In recent years, as the frequency of a signal has been increased, it has been required that the material characteristics of a package substrate have a low dielectric constant and a low dielectric loss tangent. And the mainstream is shifting. Against this background, techniques relating to a printed wiring board using a resin substrate include, for example, Japanese Patent Publication No. 4-555.
There is one disclosed in Japanese Patent Application Publication No. 55-55. In this document, an interlayer resin insulating layer is formed using epoxy acrylate on a glass epoxy substrate on which an inner-layer conductor circuit is formed, and subsequently, an opening for forming a via hole is provided by using a photolithography method, and the surface thereof is formed. After providing a plating resist after roughening the outer layer, a plating method is used to form an outer conductor circuit and a via hole.

However, the surface of the interlayer resin insulation layer made of a resin such as epoxy acrylate and the surface of the conductor circuit must be roughened in order to ensure adhesion to the conductor circuit as a conductor. For this reason, when a high-frequency signal is propagated, there is a problem that the skin effect causes propagation only on the surface portion of the roughened conductor circuit, and noise is generated in the signal due to the unevenness of the surface.
This problem was particularly remarkable when a resin substrate having a lower dielectric constant and a lower dielectric loss tangent than a ceramic substrate was used.

[0004] Further, the resin substrate has a lower heat radiation property than the conductor substrate and the ceramic substrate, and thus easily stores heat. As a result, the diffusion speed of copper ions constituting the conductor circuit increases, causing migration and causing interlayer insulation. Was destroyed. Therefore, in order to solve the above-described problems, a resin such as a resin is applied on one side of a substrate by spin coating or the like, and a metal (chromium, A technique of providing nickel, titanium, etc.) has been proposed in JP-A-7-45948 and JP-A-7-94865.

[0005]

However, there is a strong demand for a smaller printed wiring board on which an IC is mounted, and to reduce the overall size of a device such as a mobile phone equipped with such a printed wiring board. In some situations, IC
Since the area for mounting electronic components such as resistors and capacitors other than chips is small, it is becoming increasingly difficult to mount those electronic components on a printed wiring board. The present invention has been made in order to solve the above-mentioned problems of the related art, and a main object of the present invention is to provide a multilayer printed wiring board in which a dielectric layer having a capacitor function is formed in a build-up wiring layer. It is in. Another object of the present invention is to propose a method by which such a multilayer printed wiring board can be advantageously manufactured.

[0006]

Means for Solving the Problems The inventors of the present invention have intensively studied for realizing the above-mentioned object, and as a result, have arrived at an invention having the following content as a gist configuration. (1) That is, in the multilayer printed wiring board of the present invention, a build-up wiring layer in which conductive layers and interlayer resin insulating layers are alternately laminated on an insulating substrate and the conductive layers are connected by via holes is formed. In the multilayer printed wiring board, an intermediate conductor layer is provided between adjacent inner and outer conductor layers, and at least a high dielectric material is interposed between any one of the adjacent conductor circuits and the intermediate conductor layer. A multilayer printed wiring board characterized by having a dielectric layer including the same. In such a multilayer printed wiring board, it is desirable that some via holes are connected to adjacent inner or outer conductor layers via a dielectric layer. Further, the high dielectric material is desirably formed of a high dielectric material composed of a perovskite compound represented by BaTiO ₃ or a mixture thereof with an organic material such as epoxy, polyphenylene ether (PPE), or polyimide.

(2) In the method of manufacturing a multilayer printed wiring board according to the present invention, a conductive layer and an interlayer resin insulating layer are alternately laminated on an insulating substrate, and the conductive layers are connected by via holes. In manufacturing a multilayer printed wiring board having an up wiring layer formed, at least the following steps (1) to (6) during the manufacturing process, that is, a step of forming a first conductive circuit on a first resin insulating layer; Forming a second resin insulation layer covering the first conductor circuit; forming an opening from the surface of the second resin insulation layer to the first conductor circuit; and forming at least a high dielectric property in the opening. Filling a dielectric substance containing a material to form a dielectric layer; forming a second conductive circuit covering the dielectric layer on a surface of the second resin insulating layer; The third resin covering the conductor circuit Forming the edge layer step, the third of the first from the surface of the resin insulating layer and the second
Forming openings each reaching the conductive circuit of the above, and forming a via hole for each of the openings.

In the above-mentioned method for manufacturing a multilayer printed wiring board, the dielectric layer is made of a high dielectric material made of a perovskite compound represented by BaTiO ₃ or a mixture thereof with an organic material such as epoxy, polyphenylene ether (PPE), or polyimide. Desirably formed from the body. Furthermore, the dielectric layer is formed by any one of a sputtering method, a vapor deposition method, a CVD method, a printing method, a film laminating method, a method using a roll coater, a method using a spin coater, or a method using a curtain coater. Preferably, it is formed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The multilayer printed wiring board of the present invention
An intermediate conductor circuit is provided between adjacent conductor circuits formed in the resin insulation layer in the build-up wiring layer, and a capacitor function is provided between any one of the adjacent conductor circuits and the intermediate conductor circuit. It is characterized in that a dielectric layer is formed. According to such a configuration, it is possible to obtain a multilayer printed wiring board having a stable power supply operation in a high frequency region.

In the above-mentioned multilayer printed wiring board, it is desirable that some via holes are connected to adjacent inner or outer conductor circuits via a dielectric layer. The dielectric layer is preferably formed of a high dielectric material made of a perovskite compound represented by BaTiO ₃ or a mixture thereof with an organic material such as epoxy, polyphenylene ether (PPE), or polyimide. The reason is that a stable dielectric constant can be obtained. The surface area and the thickness of the dielectric layer are desirably 1962.5 μm ² or more and 0.05 to 50 μm, respectively. The reason for this is to obtain a large capacity, and the lower limit is set for the thickness in order to prevent dielectric breakdown between layers.

As a method for forming the above dielectric layer, a sputtering method, a vapor deposition method, a CVD method, a printing method, a film laminating method, a method using a roll coater, a method using a spin coater, or a method using a curtain coater There is
From the viewpoint of cost, a method using a roll coater is most preferable.

Hereinafter, one method of manufacturing the multilayer printed wiring board of the present invention will be described. (1) First, a wiring board in which a copper pattern as an inner conductor circuit is formed on the surface of a resin board is manufactured. As the resin substrate, a resin substrate having inorganic fibers is desirable, specifically, a glass cloth epoxy substrate, a glass cloth polyimide substrate,
At least one selected from a glass cloth bismaleimide-triazine resin substrate and a glass cloth fluororesin substrate is preferred. The pattern formation of the inner-layer conductor circuit on the resin substrate is performed by etching a copper-clad laminate having copper foil on both surfaces of the resin substrate. Further, a through hole is formed in the substrate by a drill, and the wall surface of the through hole and the surface of the copper foil are subjected to electroless plating to form a through hole. Copper plating is preferable as the electroless plating. In the case of a substrate such as a fluororesin substrate, which has poor coverage of plating, surface modification such as treatment with a pretreatment liquid (trade name: tetra-etch) made of organometallic sodium or plasma treatment is performed.

Next, electrolytic plating is performed to thicken the pattern of the inner conductor circuit. Copper plating is preferable as the electrolytic plating. The inner wall of the through hole and the surface of the electrolytic plating film may be roughened. As the roughening process,
Examples include blackening (oxidation) -reduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, and treatment with copper-nickel-phosphorus needle-like alloy plating. Alternatively, a conductive paste may be filled in the through holes as necessary, and a conductive layer covering the conductive paste may be formed by electroless plating or electrolytic plating.

(2) A resin insulating layer is formed on both surfaces of the wiring board prepared in (1). This resin insulating layer functions as an interlayer resin insulating layer of the multilayer printed wiring board. This resin insulating layer is formed by applying an uncured liquid (uncured resin) or laminating a film-shaped resin by applying heat and pressure.

(3) Next, an opening from the surface of the resin insulating layer to the conductive circuit pattern of the inner layer is formed by laser irradiation. This opening is for forming a dielectric layer between two adjacent conductor layers as described later, and a laser beam used includes a carbon dioxide gas laser, an ultraviolet laser, an excimer laser and a UV laser. When a hole is formed by the carbon dioxide laser beam, a desmear process is performed.
This desmear treatment can be performed using an oxidizing agent composed of an aqueous solution such as chromic acid or permanganate, or may be treated with oxygen plasma, mixed plasma of CF ₄ and oxygen, corona discharge, or the like. . The surface can also be modified by irradiating ultraviolet rays using a low-pressure mercury lamp. In particular, the mixed plasma of CF ₄ and oxygen can introduce a hydrophilic group such as a hydroxyl group or a carbonyl group on the resin surface, and is easy to perform later CVD or PVD treatment.
It is advantageous.

(4) A dielectric material containing at least a high-dielectric material is filled into the opening for forming the dielectric layer formed in (3) above, so that the ohmic contact is made with the conductive circuit pattern of the inner layer. Forming a suitable dielectric layer. Here, BaTiO ₃ , which is a perovskite compound, is most suitable as the high dielectric material, and PZT, PLZT or BST can also be used. Further, a binary or ternary perovskite compound can also be used. Further, the dielectric layer can be formed from a mixture of the above-mentioned highly dielectric material and an epoxy resin, a polyimide resin or a polyphenylene ether resin. As such a mixture, BaTiO ₃
And an epoxy resin, a combination of BaTiO ₃ and a polyimide resin, and a combination of BaTiO ₃ and a polyphenylene ether resin.

The formation of the dielectric layer, in order to obtain a large capacity is preferably BaTiO _3, in terms of production cost, BaTiO ₃
Mixtures of epoxy and epoxy resins are preferred. As the dielectric paste, a mixture of a high dielectric material and a thermosetting resin is desirable.

The dielectric layer may be formed by filling a dielectric paste containing a high dielectric material into an opening by a printing method or the like, or by sputtering a high dielectric material, a vapor deposition method, or a CVD method.
It is formed directly in the opening using a method or the like. When forming a dielectric layer by a thin film of dielectric ceramics,
PVD methods such as sputtering and evaporation are advantageous.

(5) Next, a conductor layer (intermediate conductor layer) made of copper is formed on the surface of the resin insulation layer where the dielectric layer is exposed by PVD, CVD or plating, and an appropriate etching treatment is performed. Thus, a conductor circuit (intermediate conductor circuit) that makes ohmic contact with the dielectric layer is formed. Specific examples of the PVD method include vapor deposition methods such as sputtering and ion beam sputtering. In addition, as the CVD method, P which uses an organic metal (MO) such as allylcyclopentadiphenylpalladium, dimethylgold acetylacetate, tin tetramethylacrylonitrile, or dicobalt octacarbonylacrylonitrile as a supply material
Specific examples include E-CVD (Plasma Enhanced CVD).

(6) A resin insulating layer is formed in the same manner as in (2), covering the intermediate conductor circuit formed in (5).
This resin insulating layer is formed by applying an uncured liquid (uncured resin) or laminating a film-shaped resin by applying heat and pressure. (7) Further, an opening is provided from the surface of the resin insulating layer formed in (6) to the conductor circuit of the inner layer formed in (1), and an opening is formed to reach the intermediate conductor circuit formed in (5). Is provided. These openings are formed by the same laser irradiation as in the above process (3), but appropriate laser irradiation conditions are adopted according to the opening diameter and the depth. The former is
An opening for forming a via hole electrically connected to the conductor circuit of the inner layer, and the latter is an opening for forming a via hole electrically connected to the dielectric layer.

(8) Next, a thin conductor layer is provided by sputtering on the surface of the resin insulating layer formed in (6) and on the inner wall surface of the opening formed in (7). As the conductor layer, a copper layer is sputtered in consideration of adhesion to the conductor layer formed in the above step (5), oxidation prevention, or a function as a conductive layer for electrolytic plating. It is desirable to provide by. The thickness of the thin conductor layer is
It is desirable that the thickness be 1 μm or less. Further, an electroless plating layer of the same type may be formed on the conductor layer by sputtering. As the electroless plating, copper plating is optimal, and its thickness is desirably in the range of 0.1 to 3 μm. The reason for this is that etching can be removed without impairing the function of the electroplating performed later as a conductive layer.

(9) Next, a plating resist is formed on the conductor layer formed in the above (8). This plating resist is formed by laminating a photosensitive dry film, exposing, and developing. (10) Further, the conductor layer obtained in the above (6) is subjected to electrolytic plating using a plating lead to thicken the conductor layer to form a conductor circuit of an outer layer, and an opening for forming a via hole is formed. Each is filled with plating. The thickness of the electrolytic plating layer is preferably 5 to 30 μm. (11) After the electrolytic plating treatment in the above (10), the plating resist is peeled off. (12) If necessary, a copper layer is formed on the surface of the outer conductor circuit by a plating method, a PVD method or a CVD method,
Further, by repeating the steps (2) to (11), a multilayer printed wiring board is manufactured.

In the above description, the semi-additive method is employed as a method of forming a conductor circuit, but a full-additive method may be employed. In this fully additive method, after forming a thin conductor layer on the surface of the resin insulating layer by CVD or PVD processing, a photosensitive dry film is laminated or a liquid photosensitive resin is applied,
A plating resist is provided by exposure and development, and a thick conductor layer is formed by electroless plating to form a conductor circuit. Alternatively, after forming a plating resist on the surface of the resin insulating layer, a thin conductor layer is provided by CVD or PVD processing, and the conductor layer attached to the plating resist surface is removed by polishing or the like, or the plating resist itself is removed. , Electroless plating using this conductor layer as a catalyst,
Conductive circuits can also be formed.

Hereinafter, a detailed description will be given based on embodiments.

EXAMPLES (Example 1) (1) A BT resin copper-clad laminate (Mitsubishi Gas Co., Ltd.) in which 18 μm copper foils 2 are laminated on both sides of a 0.8 mm thick substrate 1 made of BT (bismaleimide triazine) resin Made of chemical,
Product name: HL830-0.8T12D) (Fig. 1 (a))
reference). First, the copper clad laminate was drilled (Fig. 1
(See (b)), and then a palladium-tin colloid was adhered, and electroless plating was performed with an electroless plating aqueous solution having the following composition under the following conditions to form a 0.7 μm electroless plating film on the entire surface of the substrate.

[Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions 30 minutes at 70 ° C liquid temperature

Further, electrolytic copper plating was performed with an electrolytic plating aqueous solution having the following composition under the following conditions to form an electrolytic copper plating film having a thickness of 15 μm (see FIG. 1C). [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Capparaside GL) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(2) The substrate on which a conductor layer (including through holes 3) made of an electroless plating film and an electrolytic plating film is formed on the entire surface is washed with water and dried, and then used as an oxidation bath (blackening bath). (20 g / l), NaClO ₂ (50 g / l), Na ₃ PO ₄
(15.0 g / l) aqueous solution and NaOH
(2.7 g / l) and a redox treatment using an aqueous solution of NaBH ₄ (1.0 g / l) to provide a roughened layer 4 on the entire surface of the conductor layer and the through hole.

(3) Next, the conductive paste 5 containing copper particles was filled in the through holes 3 by screen printing, dried and cured. Then, the conductive paste 5 protruding from the roughened layer 4 and the through hole 3 on the upper surface of the conductor is # 400
Was removed by belt sanding using a belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.), and buffing was performed to remove scratches due to the belt sanding, thereby flattening the substrate surface (see FIG. 1 (e)).

(4) An electroless copper plating film 6 having a thickness of 0.6 μm is formed by applying a palladium colloid catalyst according to a conventional method and then performing electroless plating on the substrate surface flattened in the above (3). (See FIG. 1 (f)).

(5) Next, electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 7 having a thickness of 15 μm, a portion to be a conductor circuit 9 is thickened, and the conductive hole filled in the through hole 3 is formed. Conductor layer (lid plating layer) 10 covering paste 5
Was formed. [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Capparaside GL) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(6) A commercially available photosensitive dry film is adhered to both sides of the substrate on which the portions to be the conductor circuits 9 and the conductor layers 10 are formed, a mask is placed, and exposure is performed at 100 mJ / cm ² .
The resist was developed with 0.8% sodium bicarbonate to form an etching resist 8 having a thickness of 15 μm (see FIG. 2A).

(7) Then, the plating film in the portion where the etching resist 8 is not formed is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and the plating resist 8 is stripped with 5% KOH. The conductor circuit 9 (hereinafter, this conductor circuit is referred to as “inner layer conductor circuit”) and the conductor layer 10 covering the conductive paste 5 (hereinafter, this conductor layer is simply referred to as “lid plating layer”) ) Was formed (see FIG. 2 (b)).

(8) Next, a 2.5 μm-thick roughened layer 11 made of a copper-nickel-phosphorus alloy is formed on the entire surface including the side surfaces of the inner conductor circuit 9 and the lid plating layer 10. A Sn layer having a thickness of 0.3 μm was provided on the surface of the passivation layer 11 (FIG.
(c)). The formation method is as follows. That is,
The substrate was acid degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a palladium catalyst. After activating this catalyst, copper sulfate 8 g / l and nickel sulfate 0.6 g / L, citric acid 15g /
1, sodium hypophosphite 29 g / l, boric acid 31 g / l,
Surfactant (Nissin Chemical Industries, Surfynol 465)
Plating is performed in an electroless plating bath having a pH of 9 consisting of a 0.1 g / l aqueous solution, and the inner conductor circuit 9 and the lid plating layer are plated.
A roughened layer 11 of a copper-nickel-phosphorus alloy was provided on the entire surface of 10.

(9) A 50 μm-thick thermosetting polyolefin resin sheet (manufactured by Sumitomo 3M, trade name: 15)
92) to a temperature of 50 to 180 ° C and a pressure of 10 kg / cm.
^The layers were laminated by heating and pressing at ² , and an interlayer resin insulating layer 12 made of a polyolefin-based resin was provided.

(10) Then, a carbon dioxide laser having a wavelength of 10.4 μm is used to form a resin insulating layer 12 made of polyolefin resin.
Further, an opening 14 for forming a dielectric layer having a diameter of 80 μm and a depth of 50 μm was provided (see FIG. 2D). The irradiation condition of the carbon dioxide laser for forming the opening 14 is such that the pulse energy is 8 to 13 m.
J, the pulse width is 10 ^-12 to 10 ^-4 s, the pulse interval is 1 ms or more, and the number of shots is 10 to 100. Furthermore, the surface of the desmear and polyolefin-based resin insulating layer was modified by plasma treatment with a mixed gas of CF ₄ and oxygen. By this modification, hydrophilic groups such as OH groups, carbonyl groups, and COOH groups were confirmed on the surface. The oxygen plasma processing conditions are power 800 W, 500 mTorr, and 20 minutes.

(11) Further, in the opening 14 for forming the dielectric layer, 75 BaTiO ₃ is added to polyphenylene ether (PPE).
% Of the dielectric paste is filled by a method using a roll coater to form a dielectric layer 15 so as to be in contact with the inner conductor circuit 9 via the roughened layer 11 (see FIG. 2 (e)). . (12) Next, sputtering using copper as a target,
The pressure was set to 0.6 Pa, the temperature was set to 80 ° C., the power was set to 200 W, and the time was set to 5 minutes, and the surface of the dielectric layer 15 formed in (11) and the surface of the resin insulating layer 12 made of polyolefin resin were formed. Form a copper sputter layer. The thickness of the thus formed copper sputtered layer was 0.1 μm. In addition, as a sputtering device, SV-45 manufactured by Japan Vacuum Engineering Co., Ltd.
40 was used.

(13) The copper sputter layer formed in the above (12) is subjected to an etching treatment, and a conductor circuit 16 is provided at a position corresponding to the dielectric layer 15 (hereinafter, this conductor circuit is referred to as an “outer layer conductor circuit”). To form (14) Further, similarly to the process of (9), a 50 μm-thick thermosetting polyolefin resin sheet (trade name: 1592, manufactured by Sumitomo 3M) covering the outer conductor circuit 16 formed in (13). ) The temperature while raising the temperature to 50-180 ℃
Lamination was performed by heating and pressing at 10 kg / cm ² , and a resin insulating layer 17 made of a polyolefin-based resin was provided (see FIG. 3A).

(15) Then, in the same manner as in the above (10),
Using a carbon dioxide gas laser with a wavelength of 10.4 μm, an opening 18 for forming a via hole with a diameter of 80 μm and a depth of 50 μm reaching the outer conductor circuit 16 from the surface of the resin insulation layer 17 made of polyolefin resin, and a through hole also from the surface of the resin insulation layer 17 An opening 19 for forming a via hole having a diameter of 80 μm and a depth of 50 μm reaching the lid plating layer 10 on the hole was provided (see FIG. 3B).

Further, the surface of the desmear and polyolefin resin insulating layer was modified by plasma treatment with a mixed gas of CF ₄ and oxygen. By this modification, hydrophilic groups such as OH groups, carbonyl groups, and COOH groups were confirmed on the surface. The oxygen plasma processing conditions were as follows: power 800W,
500 mTorr for 20 minutes. (16) Next, sputtering using copper as a target,
The process is performed under the conditions of a pressure of 0.6 Pa, a temperature of 80 ° C., a power of 200 W, and a time of 5 minutes to form a copper sputtered layer 20 on the surface of the resin insulating layer 17 and the inner wall surfaces of the openings 18 and 19. The thickness of the copper sputtered layer 20 thus formed was 0.1 μm (see FIG. 3 (c)). In addition, SV-4540 manufactured by Japan Vacuum Engineering Co., Ltd. was used as a sputtering apparatus.

(17) Further, a photosensitive dry film is stuck on the copper sputtered layer 20, a photomask film is mounted thereon, exposed at 100 mJ / cm ² , developed with 0.8% sodium carbonate, and processed to a thickness of 15 μm. The plating resist 21 was provided. Further, electrolytic copper plating is performed in accordance with the above process (1) to form an electrolytic copper plating film 22 having a thickness of 15 μm, the outer conductor circuit is thickened, and plating is performed in the via holes forming openings 18 and 19. Filling was performed (see FIG. 3 (d)).

(18) Further, after the plating resist 21 is peeled off with 5% KOH, the copper sputter layer 20 under the plating resist 21 is dissolved and removed by etching using a mixed solution of nitric acid and sulfuric acid / hydrogen peroxide. Then, an outer layer conductor circuit 24 composed of the electrolytic copper plating film 22 and the copper sputter layer 20, a via hole 25 connected to the lid plating layer 10 on the through hole and a via hole 26 connected to the intermediate conductor circuit 16 are formed, A dielectric layer 15 having a capacitor function was formed between the inner conductor circuit 9 and the intermediate conductor circuit 16 (FIG. 3E).
reference). (19) Further, by repeating the processes (8) to (10) and (12) to (18), a via hole 27 is formed on the outer layer conductor circuit 24 and the via hole 26, and the via hole 27 is formed. A multilayer printed wiring board having the outermost conductive circuit 28 formed in the same plane as the filled electrolytic copper plating layer was obtained (see FIG. 4A).

(20) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of an epoxy group of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku) of 60% by weight dissolved in DMDG, 15.0 g of 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, 1.6 g of imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), polyvalent acrylic monomer as a photosensitive monomer (Nippon Kayaku, R
604) 3 g, similarly polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, DPE6A) 1.5 g, dispersion antifoaming agent (manufactured by San Nopco,
S-65) of 0.71 g, and 2 g of benzophenone (Kanto Chemical) as a photoinitiator was added to the mixture.
0.2 of Michler's ketone (Kanto Chemical) as photosensitizer
g was added to obtain a solder resist composition whose viscosity was adjusted to 2.0 Pa · s at 25 ° C. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm and the rotor No.
In the case of 4, 6 rpm, the rotor No. 3 was used.

(21) The multilayer wiring board obtained in the above (19) was sandwiched between a pair of application rolls of a roll coater in an upright state, and a solder resist composition was applied to a thickness of 20 μm. (22) Next, after performing a drying treatment at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, respectively, the substrate was exposed to ultraviolet light of 1000 mJ / cm ² ,
DMTG development processing was performed. In addition, 1 hour at 80 ° C, 1 hour at 100 ° C
Heat treatment at 120 ° C. for 1 hour and 150 ° C. for 3 hours to form a solder resist layer (opening diameter: 200 μm) with a part of the upper surface of the via hole, land, and grid-like power supply layer (opening diameter: 200 μm) 30) formed.

(23) Next, the substrate on which the solder resist layer 30 was formed was subjected to electroless electrolysis (pH = 5) consisting of an aqueous solution of nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g / l. It was immersed in a nickel plating solution for 20 minutes to form a nickel plating layer 31 having a thickness of 5 μm at the opening. Further, the substrate was treated with 2 g of potassium potassium cyanide /
l, ammonium chloride 75 g / l, sodium citrate 50
g / l, immersed in an electroless gold plating solution consisting of an aqueous solution of sodium hypophosphite 10 g / l at 93 ° C. for 23 seconds to form a gold plating layer 32 having a thickness of 0.03 μm on the nickel plating layer 31. did.

(24) A solder paste is printed on the opening of the solder resist layer 30 and reflowed at 200 ° C. to form a solder bump 33.
(See FIG. 4 (b)).

As a result of examining the capacitance of the formed dielectric layer for the printed wiring board manufactured according to the above embodiment,
A capacity of 750 pF was confirmed in the 500 holes, and the stability to temperature was also confirmed to be good.

[0047]

According to the multilayer printed wiring board of the present invention,
An intermediate conductor circuit is provided between adjacent conductor circuits in the build-up wiring layer, and a dielectric layer containing at least a high dielectric material is formed between the intermediate conductor circuit and any of the adjacent conductor circuits. Since the capacitor function can be provided in the layer, there is an effect that excellent power supply stability in a high frequency region can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1F are views showing a part of a manufacturing process of a multilayer printed wiring board according to the present invention.

2 (a) to 2 (e) are views showing a part of a manufacturing process of a multilayer printed wiring board according to the present invention.

FIGS. 3 (a) to 3 (e) are views showing a part of the manufacturing process of the multilayer printed wiring board according to the present invention.

FIGS. 4 (a) and (b) are views showing a part of a manufacturing process of a multilayer printed wiring board according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 substrate 2 copper foil 3 through hole 4, 11 roughened layer 5 filler 7, 18 electrolytic copper plating 8 etching resist 9 conductor circuit (inner conductor circuit) 10 conductor layer 12 resin insulation layer (polyolefin resin layer) 14 dielectric Layer forming opening 15 Dielectric layer 16 Intermediate conductor circuit 17 Resin insulation layer (polyolefin resin layer) 18, 19 Via hole forming opening 20 Copper sputter layer 21 Plating resist 22 Electrolytic copper plating 24 Conductor circuit (Outer layer conductor circuit) 25, 26, 27 Via hole 28 Conductor circuit (Outer layer conductor circuit) 30 Solder resist layer 31 Nickel plating layer 32 Gold plating layer 33 Solder bump

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H01G 4/33 H01G 4/06 102 F term (Reference) 4E351 AA01 BB03 BB33 CC06 DD04 DD43 DD48 GG06 5E082 AB03 BC14 BC39 EE05 EE37 FF14 FG03 FG04 FG26 FG34 FG42 FG46 JJ15 JJ21 MM05 MM06 5E346 AA06 AA12 AA13 AA15 AA23 AA32 AA43 BB01 BB16 BB20 CC21 CC31 CC33 DD02 DD07 DD22 DD32 GG17 GG23 GG17 GG17 GG33 GG17 GG17 GG33

Claims (6)

[Claims] 1. A multilayer printed wiring board comprising a build-up wiring layer in which conductive layers and interlayer resin insulating layers are alternately laminated on an insulating substrate, and the conductive layers are connected by via holes. An intermediate conductor layer is provided between the two conductor layers, and between one of the adjacent conductor circuits and the intermediate conductor layer,
A multilayer printed wiring board comprising a dielectric layer containing at least a high dielectric material. 2. The printed wiring board according to claim 1, wherein a part of the via hole is connected to an adjacent conductor layer via the dielectric layer. 3. The method according to claim 1, wherein the dielectric layer is formed of a high dielectric material composed of a perovskite compound represented by BaTiO ₃ or a mixture thereof with an organic material such as epoxy, polyphenylene ether (PPE), or polyimide. The multilayer printed wiring board according to claim 1, wherein: 4. When manufacturing a multilayer printed wiring board in which conductive layers and interlayer resin insulating layers are alternately laminated on an insulating substrate and a build-up wiring layer in which the conductive layers are connected by via holes is formed. During the manufacturing process, at least the following steps, namely, a step of forming a first conductive circuit on the first resin insulating layer, and forming a second resin insulating layer covering the first conductive layer Forming an opening reaching the first conductive circuit from the surface of the second resin insulating layer, filling the opening with a dielectric substance containing at least a high dielectric material, and forming a dielectric layer on the opening. Forming; forming a second conductor circuit covering the dielectric layer on the surface of the second resin insulation layer; forming a third resin insulation layer covering the second conductor circuit Step, from above the surface of the third resin insulating layer 1st and 2nd
Forming an opening reaching each of the conductive circuits, and forming a via hole in each of the openings. 5. The method according to claim 1, wherein the dielectric layer is formed of a high dielectric material made of a perovskite compound represented by BaTiO ₃ or a mixture thereof with an organic material such as epoxy, polyphenylene ether (PPE), or polyimide. The method for producing a multi-printed wiring board according to claim 4, wherein: 6. The dielectric layer is formed by a sputtering method, a vapor deposition method,
6. The method according to claim 4, wherein the film is formed by any one of a VD method, a printing method, a film laminating method, a method using a roll coater, a method using a spin coater, and a method using a curtain coater. A method for producing the multilayer printed wiring board according to the above.