JP2001015931A - Multilayer printed wiring board and manufacture thereof - Google Patents

Multilayer printed wiring board and manufacture thereof

Info

Publication number
JP2001015931A
JP2001015931A JP18741899A JP18741899A JP2001015931A JP 2001015931 A JP2001015931 A JP 2001015931A JP 18741899 A JP18741899 A JP 18741899A JP 18741899 A JP18741899 A JP 18741899A JP 2001015931 A JP2001015931 A JP 2001015931A
Authority
JP
Japan
Prior art keywords
resin
wiring board
printed wiring
multilayer printed
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18741899A
Other languages
Japanese (ja)
Other versions
JP4197805B2 (en
Inventor
Touto O
東冬 王
Koji Sekine
浩司 関根
Motoo Asai
元雄 浅井
Kenichi Shimada
憲一 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP18741899A priority Critical patent/JP4197805B2/en
Priority to MYPI99004184A priority patent/MY139405A/en
Priority to EP08160500A priority patent/EP1978796B1/en
Priority to DE69938854T priority patent/DE69938854D1/en
Priority to KR1020067014992A priority patent/KR100675615B1/en
Priority to DE69941937T priority patent/DE69941937D1/en
Priority to DE69934130T priority patent/DE69934130T2/en
Priority to EP06115385A priority patent/EP1699280B1/en
Priority to EP08157080A priority patent/EP1968368A3/en
Priority to EP07110630A priority patent/EP1830616B1/en
Priority to EP07108839A priority patent/EP1893006B1/en
Priority to PCT/JP1999/005266 priority patent/WO2000019789A1/en
Priority to DE69942468T priority patent/DE69942468D1/en
Priority to EP08160963A priority patent/EP1978797B1/en
Priority to KR1020067014991A priority patent/KR100776865B1/en
Priority to EP06115382A priority patent/EP1699279B8/en
Priority to KR1020067014993A priority patent/KR100673910B1/en
Priority to DE69943397T priority patent/DE69943397D1/en
Priority to EP06115377A priority patent/EP1727409B1/en
Priority to EP99943468A priority patent/EP1119227B1/en
Priority to EP06115380A priority patent/EP1699278B1/en
Priority to KR1020017003881A priority patent/KR100697640B1/en
Priority to US09/806,203 priority patent/US7535095B1/en
Priority to DE69939913T priority patent/DE69939913D1/en
Priority to EP07110631A priority patent/EP1830617B1/en
Publication of JP2001015931A publication Critical patent/JP2001015931A/en
Priority to US11/188,886 priority patent/US7504719B2/en
Priority to US12/146,165 priority patent/US8020291B2/en
Priority to US12/146,105 priority patent/US8030577B2/en
Priority to US12/146,204 priority patent/US8006377B2/en
Priority to US12/146,212 priority patent/US8018045B2/en
Application granted granted Critical
Publication of JP4197805B2 publication Critical patent/JP4197805B2/en
Priority to US12/409,683 priority patent/US8533943B2/en
Priority to US12/409,670 priority patent/US7994433B2/en
Priority to US12/420,469 priority patent/US8093507B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To prevent generation of signal delay and signal error by forming multilayer printed wiring board comprising wiring circuits on the substrate and cyclo-olefin resin insulating layers laminated in order, and connecting these wiring circuits by means of via holes. SOLUTION: A copper stuck laminate is formed with copper foil laminated on both sides of a substrate 1. Then, a via hole 9 is formed in the substrate 1 and lower layer conductive circuits 4 as inner copper pattern are formed on both sides of the substrate 1. Roughening surfaces 4a and 9a are formed all over the lower layer conductive circuits 4 and then resin filler 10 mainly consisting of cycloolefin resin is filled among the lower layer conductive circuits 4 or in the via hole 9. This laminates the cycloolefin resin with vacuum compression bonding to form the interlayer resin insulation layer 2 consisting of cycloolefin resin.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、誘電率が低く、剛
性等の機械的特性に優れるシクロオレフィン系樹脂から
なる層間樹脂絶縁層を有する多層プリント配線板および
その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board having an interlayer resin insulating layer made of a cycloolefin resin having a low dielectric constant and excellent mechanical properties such as rigidity, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】いわゆる多層ビルドアップ配線基板と呼
ばれる多層プリント配線板は、セミアディティブ法等に
より製造されており、コアと呼ばれる0.6〜1.5m
m程度のガラスクロス等で補強された樹脂基板の上に、
銅等による導体回路と層間樹脂絶縁層とを交互に積層す
ることにより作製される。この多層プリント配線板の層
間樹脂絶縁層を介した導体回路間の接続は、バイアホー
ルにより行われている。
2. Description of the Related Art A multilayer printed wiring board called a so-called multilayer build-up wiring board is manufactured by a semi-additive method or the like.
m on a resin substrate reinforced with glass cloth, etc.
It is manufactured by alternately laminating a conductor circuit made of copper or the like and an interlayer resin insulating layer. The connection between the conductor circuits via the interlayer resin insulation layer of the multilayer printed wiring board is performed by via holes.

【0003】従来、ビルドアップ多層プリント配線板
は、例えば、特開平9−130050号公報等に開示さ
れた方法により製造されている。すなわち、まず、銅箔
が貼り付けられた銅貼積層板に貫通孔を形成し、続いて
無電解銅めっき処理を施すことによりスルーホールを形
成する。続いて、基板の表面を導体パターン状にエッチ
ング処理して導体回路を形成し、この導体回路の表面に
無電解めっきやエッチング等により粗化面を形成し、そ
の粗化面を有する導体回路上に層間樹脂絶縁層を形成し
た後、露光、現像処理を行うか、レーザ処理によりバイ
アホール用開口を形成し、その後、UV硬化、本硬化を
経て層間樹脂絶縁層を形成する。
Conventionally, build-up multilayer printed wiring boards have been manufactured by a method disclosed in, for example, Japanese Patent Application Laid-Open No. 9-130050. That is, first, a through-hole is formed in the copper-clad laminate on which the copper foil is stuck, and then a through-hole is formed by performing an electroless copper plating process. Subsequently, the surface of the substrate is etched into a conductor pattern to form a conductor circuit, and a roughened surface is formed on the surface of the conductor circuit by electroless plating, etching, or the like. After forming an interlayer resin insulation layer, an exposure and development process is performed, or a via hole opening is formed by laser processing, and then the interlayer resin insulation layer is formed through UV curing and main curing.

【0004】さらに、層間樹脂絶縁層に粗化形成処理を
施した後、形成された粗化面に薄い無電解めっき膜を形
成し、この無電解めっき膜上にめっきレジストを形成し
た後、電解めっきにより厚付けを行い、めっきレジスト
剥離後にエッチングを行って、下層の導体回路とバイア
ホールにより接続された導体回路を形成する。
Further, after a roughening treatment is performed on the interlayer resin insulating layer, a thin electroless plating film is formed on the formed roughened surface, a plating resist is formed on the electroless plating film, and then an electrolytic plating film is formed. Thickening is performed by plating, and etching is performed after the plating resist is stripped to form a conductive circuit connected to the lower conductive circuit by a via hole.

【0005】これを繰り返した後、最外層として導体回
路を保護するためのソルダーレジスト層を形成し、ソル
ダーレジスト層に開口を形成し、開口部分の導体層にめ
っき等を施してパッドとした後、半田バンプを形成する
ことにより、ビルドアップ多層プリント配線板を製造す
る。
After repeating this, a solder resist layer for protecting the conductor circuit is formed as an outermost layer, an opening is formed in the solder resist layer, and the conductor layer in the opening is plated or the like to form a pad. Then, a build-up multilayer printed wiring board is manufactured by forming solder bumps.

【0006】しかしながら、このようにして製造した多
層プリント配線板では、層間樹脂絶縁層にエポキシ樹
脂、アクリル樹脂等の混合物を使用しているため誘電率
がGHz領域において、3.5以上と高い。そのため、
GHz帯域の高周波数信号を用いたLSIチップ等を搭
載すると、層間樹脂絶縁層が高誘電率であることに起因
して、信号遅延や信号エラーが発生しやすくなってしま
うという問題があった。
However, the multilayer printed wiring board manufactured in this manner has a high dielectric constant of 3.5 or more in the GHz region because a mixture of an epoxy resin, an acrylic resin, and the like is used for the interlayer resin insulating layer. for that reason,
When an LSI chip or the like using a high-frequency signal in the GHz band is mounted, there is a problem that signal delay or signal error is likely to occur due to the high dielectric constant of the interlayer resin insulating layer.

【0007】[0007]

【発明が解決しようとする課題】そこで、このような問
題を解決するために、線状のポリオレフィン系樹脂を層
間樹脂絶縁層として用いたプリント配線板が提案されて
いる。このプリント配線板では、層間樹脂絶縁層の誘電
率は低下するものの、層間樹脂絶縁層自体が柔らかすぎ
るため、形成された導体回路が層間樹脂絶縁層中に沈み
やすく、その結果、導体回路同士の接続に問題が発生し
やすく、プリント配線板の信頼性が低いという問題があ
った。
In order to solve such a problem, a printed wiring board using a linear polyolefin resin as an interlayer resin insulating layer has been proposed. In this printed wiring board, although the dielectric constant of the interlayer resin insulating layer decreases, the interlayer resin insulating layer itself is too soft, so that the formed conductor circuit easily sinks in the interlayer resin insulating layer, and as a result, There is a problem that a connection problem easily occurs and the reliability of the printed wiring board is low.

【0008】また、上記線状ポリオレフィン樹脂を用い
て層間樹脂絶縁層を形成する際には、樹脂シートを導体
回路上に圧着、ラミネートすることにより層間樹脂絶縁
層を形成していたが、フィルムが柔らすぎるため、その
取扱いが難しいという問題もあった。
When forming an interlayer resin insulation layer using the linear polyolefin resin, the interlayer resin insulation layer is formed by pressing and laminating a resin sheet on a conductor circuit. There was also a problem that handling was difficult because it was too soft.

【0009】本発明は、このような従来技術の問題点を
解決するためになされたものであり、その目的は、誘電
率や誘電正接が小さく、GHz帯域の高周波信号を用い
た場合にも信号遅延や信号エラーが発生しにくく、ま
た、剛性等の機械的特性にも優れるため、導体回路同士
の接続の信頼性が高い層間樹脂絶縁層を有する多層プリ
ント配線板およびその製造方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and has as its object to reduce the dielectric constant and the dielectric loss tangent even when a high-frequency signal in the GHz band is used. Provided is a multilayer printed wiring board having an interlayer resin insulating layer with high reliability in connection between conductor circuits because the delay and signal errors are less likely to occur and excellent in mechanical properties such as rigidity, and a method of manufacturing the same. It is in.

【0010】[0010]

【課題を解決するための手段】本発明者らは、上記目的
の実現に向け鋭意研究した結果、シクロオレフィン系樹
脂、なかでも、熱硬化性のシクロオレフィン系樹脂を層
間樹脂絶縁層に用いることにより、上記した低誘電率、
低誘電正接等の電気的特性や剛性等の機械的特性につい
ても、その要求特性を充分に満足する層間樹脂絶縁層を
形成することができることを見いだし、以下に示す内容
を要旨構成とする本発明に想到した。
Means for Solving the Problems The inventors of the present invention have conducted intensive studies for realizing the above object, and have found that cycloolefin resins, particularly thermosetting cycloolefin resins, are used for the interlayer resin insulating layer. By the low dielectric constant described above,
With regard to the electrical characteristics such as low dielectric loss tangent and the mechanical characteristics such as rigidity, the present inventors have found that an interlayer resin insulating layer can be formed which sufficiently satisfies the required characteristics, and the present invention which has the following contents as a summary configuration I thought.

【0011】即ち、本発明の多層プリント配線板は、基
板上に導体回路と樹脂絶縁層とが順次形成され、これら
導体回路がバイアホールを介して接続されてなる多層プ
リント配線板において、上記樹脂絶縁層は、シクロオレ
フィン系樹脂からなることを特徴とする。
That is, the multilayer printed wiring board of the present invention is a multilayer printed wiring board in which a conductive circuit and a resin insulating layer are sequentially formed on a substrate, and these conductive circuits are connected via via holes. The insulating layer is made of a cycloolefin-based resin.

【0012】上記多層プリント配線板において、上記シ
クロオレフィン系樹脂は、2−ノルボルネン、5−エチ
リデン−2−ノルボルネンまたはこれらの誘導体からな
る単量体の単独重合体または共重合体であることが望ま
しい。また、上記樹脂絶縁層の1GHzにおける誘電率
は、3以下であり、誘電正接は、0.01以下であるこ
とが望ましい。また、上記シクロオレフィン系樹脂は、
熱硬化性シクロオレフィン系樹脂であることが望まし
い。
In the multilayer printed wiring board, the cycloolefin resin is preferably a homopolymer or a copolymer of a monomer comprising 2-norbornene, 5-ethylidene-2-norbornene or a derivative thereof. . The dielectric constant of the resin insulating layer at 1 GHz is preferably 3 or less, and the dielectric loss tangent is preferably 0.01 or less. Further, the cycloolefin-based resin,
A thermosetting cycloolefin-based resin is desirable.

【0013】また、本発明の多層プリント配線板の製造
方法は、基板上に導体回路と樹脂絶縁層とが順次形成さ
れ、これら導体回路がバイアホールを介して接続されて
なる多層プリント配線板の製造方法において、基板上に
形成された導体回路上に、シクロオレフィン系樹脂から
なるフィルムを真空圧着ラミネートすることにより、層
間樹脂絶縁層を形成することを特徴とする。
Further, according to the method of manufacturing a multilayer printed wiring board of the present invention, a conductive circuit and a resin insulating layer are sequentially formed on a substrate, and these conductive circuits are connected via via holes. The manufacturing method is characterized in that an interlayer resin insulating layer is formed by laminating a film made of a cycloolefin-based resin on a conductor circuit formed on a substrate by vacuum compression bonding.

【0014】上記多層プリント配線板の製造方法におい
て、基板上に形成された導体回路上に、シクロオレフィ
ン系樹脂から層間樹脂絶縁層を形成した後、上記層間樹
脂絶縁層にレーザ光を照射することによりバイアホール
用開口を形成することが望ましい。
In the above method for manufacturing a multilayer printed wiring board, an interlayer resin insulating layer is formed from a cycloolefin resin on a conductor circuit formed on a substrate, and then the interlayer resin insulating layer is irradiated with laser light. It is desirable to form an opening for a via hole.

【0015】[0015]

【発明の実施の形態】本発明の多層プリント配線板は、
基板上に導体回路と樹脂絶縁層とが順次形成され、これ
ら導体回路がバイアホールを介して接続されてなる多層
プリント配線板において、上記樹脂絶縁層は、シクロオ
レフィン系樹脂からなることを特徴とする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The multilayer printed wiring board of the present invention
In a multilayer printed wiring board in which a conductor circuit and a resin insulation layer are sequentially formed on a substrate and these conductor circuits are connected via via holes, the resin insulation layer is made of a cycloolefin resin. I do.

【0016】このような本発明の多層プリント配線板に
よれば、上記層間樹脂絶縁層がシクロオレフィン系樹脂
により構成されているので、エポキシ樹脂等からなる層
間樹脂絶縁層と比べて誘電率や誘電正接が大きく低下
し、信号伝搬の遅延や信号の電送損失等に起因する信号
エラーを防止することができる。
According to such a multilayer printed wiring board of the present invention, since the interlayer resin insulating layer is made of a cycloolefin resin, the dielectric constant and the dielectric constant are higher than those of the interlayer resin insulating layer made of epoxy resin or the like. The tangent is greatly reduced, and signal errors due to signal propagation delay, signal transmission loss, etc. can be prevented.

【0017】また、上記シクロオレフィン系樹脂は、機
械的特性、特に剛性が高いため、しっかりとした層間樹
脂絶縁層の上に導体回路を形成することができ、そのた
め、導体回路同士の接続信頼性を充分に確保することが
できる。
Further, since the cycloolefin resin has high mechanical properties, particularly high rigidity, a conductor circuit can be formed on a firm interlayer resin insulating layer, and therefore, the connection reliability between the conductor circuits can be improved. Can be sufficiently secured.

【0018】また、上記シクロオレフィン系樹脂は、導
体回路との密着性にも優れるため、層間樹脂絶縁層が導
体回路から剥離するのを防止することができ、剥離に起
因する層間樹脂絶縁層のクラックの発生等も防止するこ
とができる。さらに、上記シクロオレフィン系樹脂は、
吸水率も小さいため、導体回路間の電気絶縁性が高くな
り、信頼性も向上する。
Further, since the cycloolefin-based resin has excellent adhesion to the conductor circuit, the interlayer resin insulation layer can be prevented from peeling off from the conductor circuit, and the interlayer resin insulation layer caused by the peeling can be prevented. Cracks can also be prevented. Further, the cycloolefin-based resin,
Since the water absorption is small, the electrical insulation between the conductor circuits is increased, and the reliability is also improved.

【0019】上記シクロオレフィン系樹脂の種類は特に
限定されるものではないが、1GHzにおける誘電率
は、3.0以下であり、誘電正接は、0.01以下であ
ることが望ましい。上記誘電率は、2.4〜2.7がよ
り好ましい。このような低誘電率のものを使用すること
により、信号伝搬の遅延や信号の電送損失等に起因する
信号エラーを防止することができる。
The type of the cycloolefin resin is not particularly limited, but the dielectric constant at 1 GHz is preferably 3.0 or less and the dielectric loss tangent is preferably 0.01 or less. The dielectric constant is more preferably 2.4 to 2.7. By using such a material having a low dielectric constant, it is possible to prevent a signal error due to a delay in signal propagation, a signal transmission loss, and the like.

【0020】また、上記シクロオレフィン系樹脂は、2
−ノルボルネン、5−エチリデン−2−ノルボルネンま
たはこれらの誘導体からなる単量体の単独重合体または
共重合体であることが望ましい。上記誘導体としては、
上記2−ノルボルネン等のシクロオレフィンに、架橋を
形成するためのアミノ基や無水マレイン酸残基あるいは
マレイン酸変性したもの等が結合したもの等が挙げられ
る。上記共重合体を合成する場合の単量体としては、例
えば、エチレン、プロピレン等が挙げられる。
The above cycloolefin-based resin is
It is preferably a homopolymer or a copolymer of monomers composed of -norbornene, 5-ethylidene-2-norbornene or a derivative thereof. As the above derivatives,
Examples thereof include those in which an amino group for forming a crosslink, a maleic anhydride residue, or a maleic acid-modified one is bonded to the cycloolefin such as 2-norbornene. Examples of monomers for synthesizing the copolymer include ethylene and propylene.

【0021】上記シクロオレフィン系樹脂は、上記した
樹脂の2種以上の混合物であってもよく、シクロオレフ
ィン系樹脂以外の樹脂を含むものであってもよい。ま
た、上記シクロオレフィン系樹脂が共重合体でなる場合
には、ブロック共重合体であってもよく、ランダム共重
合体であってもよい。
The cycloolefin resin may be a mixture of two or more of the above resins, or may contain a resin other than the cycloolefin resin. When the cycloolefin-based resin is a copolymer, it may be a block copolymer or a random copolymer.

【0022】また、上記シクロオレフィン系樹脂は、熱
硬化性シクロオレフィン系樹脂であることが望ましい。
加熱を行って架橋を形成させることにより、より剛性が
高くなり、機械的特性が向上するからである。上記シク
ロオレフィン系樹脂のガラス転移温度(Tg)は、13
0〜200℃であることが望ましい。
The cycloolefin resin is preferably a thermosetting cycloolefin resin.
This is because by performing the heating to form the crosslinks, the rigidity is further increased and the mechanical properties are improved. The glass transition temperature (Tg) of the cycloolefin resin is 13
Desirably, the temperature is 0 to 200 ° C.

【0023】上記シクロオレフィン系樹脂は、既に樹脂
シート(フィルム)として成形されたものを使用しても
よく、単量体もしくは一定の分子量を有する低分子量の
重合体が、キシレン、シクロヘキサン等の溶剤に分散し
た未硬化溶液の状態であってもよい。また、樹脂シート
の場合には、いわゆるRCC(RESIN COATE
D COPPER:樹脂付銅箔)を用いてもよい。
As the cycloolefin-based resin, those already formed as a resin sheet (film) may be used, and a monomer or a low-molecular-weight polymer having a constant molecular weight may be used as a solvent such as xylene or cyclohexane. It may be in the state of an uncured solution dispersed in. In the case of a resin sheet, a so-called RCC (RESIN COATE
D COPER: resin-coated copper foil).

【0024】上記シクロオレフィン系樹脂は、フィラー
等を含まないものであってもよく、水酸化アルミニウ
ム、水酸化マグネシウム、リン酸エステル等の難燃剤を
含むものであってもよい。
The cycloolefin resin may not contain a filler or the like, or may contain a flame retardant such as aluminum hydroxide, magnesium hydroxide, or a phosphate.

【0025】次に、このようなシクロオレフィン系樹脂
を用いた多層プリント配線板の製造方法について説明す
る。
Next, a method of manufacturing a multilayer printed wiring board using such a cycloolefin resin will be described.

【0026】(1) まず、樹脂基板の表面に下層導体回路
を有する配線基板を作製する。樹脂基板としては、無機
繊維を有する樹脂基板が望ましく、具体的には、例え
ば、ガラス布エポキシ基板、ガラス布ポリイミド基板、
ガラス布ビスマレイミド−トリアジン樹脂基板、ガラス
布フッ素樹脂基板等が挙げられる。また、上記樹脂基板
の両面に銅箔を貼った銅張積層板を用いてもよい。
(1) First, a wiring board having a lower conductive circuit on the surface of a resin substrate is manufactured. As the resin substrate, a resin substrate having inorganic fibers is desirable, specifically, for example, a glass cloth epoxy substrate, a glass cloth polyimide substrate,
A glass cloth bismaleimide-triazine resin substrate, a glass cloth fluororesin substrate, and the like can be given. Further, a copper-clad laminate in which copper foil is stuck on both surfaces of the resin substrate may be used.

【0027】通常、この樹脂基板にドリルで貫通孔を設
け、該貫通孔の壁面および銅箔表面に無電解めっきを施
してスルーホールを形成する。無電解めっきとしては銅
めっきが好ましい。さらに、銅箔の厚付けのために電気
めっきを行ってもよい。この電気めっきとしては銅めっ
きが好ましい。この後、スルーホール内壁等に粗化処理
を施し、スルーホールを樹脂ペースト等で充填し、その
表面を覆う導電層を無電解めっきもしくは電気めっきに
て形成してもよい。
Usually, a through hole is formed in the resin substrate by a drill, and a through hole is formed by applying electroless plating to the wall surface of the through hole and the surface of the copper foil. Copper plating is preferred as the electroless plating. Further, electroplating may be performed for thickening the copper foil. Copper plating is preferred as the electroplating. Thereafter, the inner wall of the through-hole may be subjected to a roughening treatment, the through-hole may be filled with a resin paste or the like, and the conductive layer covering the surface may be formed by electroless plating or electroplating.

【0028】上記粗化処理の方法としては、例えば、黒
化(酸化)−還元処理、有機酸と第二銅錯体の混合水溶
液によるスプレー処理、Cu−Ni−P針状合金めっき
による処理等が挙げられる。上記工程を経て、基板上の
全面に形成された銅のベタパターン上にフォトリソグラ
フィーの手法を用いてエッチングレジストを形成し、続
いて、エッチングを行うことにより、下層導体回路を形
成する。この後、必要により、導体回路の形成により、
エッチングされ、凹部となった部分に樹脂等を充填して
もよい。 (2) 次に、形成された下層導体回路に、必要により粗化
処理を施す。粗化処理の方法としては、上記した方法、
すなわち、黒化(酸化)−還元処理、有機酸と第二銅錯
体の混合水溶液によるスプレー処理、Cu−Ni−P針
状合金めっきによる処理等が挙げられる。また、下層導
体回路に粗化処理を施さず、下層導体回路が形成された
基板を樹脂成分を溶解した溶液に浸漬することにより、
下層導体回路の表面に樹脂からなる層を形成し、その上
に形成する層間樹脂絶縁層との密着性を確保してもよ
い。
Examples of the method of the above-mentioned roughening treatment include blackening (oxidation) -reduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, and treatment with Cu-Ni-P needle-like alloy plating. No. Through the above steps, an etching resist is formed on the solid copper pattern formed on the entire surface of the substrate by using a photolithography technique, and then etching is performed to form a lower conductive circuit. Thereafter, if necessary, by forming a conductor circuit,
A portion which has been etched and becomes a concave portion may be filled with a resin or the like. (2) Next, the formed lower conductor circuit is subjected to a roughening treatment if necessary. As the method of the roughening treatment, the method described above,
That is, a blackening (oxidation) -reduction treatment, a spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, a treatment with Cu-Ni-P needle-like alloy plating, and the like can be given. Also, by immersing the substrate on which the lower conductor circuit is formed in a solution in which the resin component is dissolved, without subjecting the lower conductor circuit to a roughening treatment,
A layer made of a resin may be formed on the surface of the lower conductive circuit, and adhesion to the interlayer resin insulating layer formed thereon may be ensured.

【0029】(3) 次に、上記(2) で作製した下層導体回
路を有する配線基板の両面に、上記シクロオレフィン系
樹脂からなる層間樹脂絶縁層を形成する。この層間樹脂
絶縁層は、シクロオレフィン系樹脂形成用の未硬化液を
塗布した後、加熱等により硬化させる方法により、また
は、樹脂シートを加熱下に真空圧着ラミネートすること
により形成するが、取扱いが簡単なことから、樹脂シー
トをラミネートする方法が好ましい。この場合の加熱条
件としては、100〜180℃、0.5〜20分が好ま
しい。
(3) Next, an interlayer resin insulating layer made of the cycloolefin resin is formed on both surfaces of the wiring board having the lower conductive circuit prepared in the above (2). This interlayer resin insulating layer is formed by applying an uncured liquid for forming a cycloolefin-based resin and then curing it by heating or the like, or by laminating a resin sheet under vacuum with heating. For simplicity, a method of laminating a resin sheet is preferable. The heating conditions in this case are preferably 100 to 180 ° C. and 0.5 to 20 minutes.

【0030】(4) 次に、層間樹脂絶縁層にレーザ光を照
射することにより、バイアホール用開口を設ける。この
とき、使用されるレーザ光としては、例えば、炭酸ガス
(CO 2 )レーザ、紫外線レーザ、エキシマレーザ等が
挙げられるが、これらのなかでは、エキシマレーザや短
パルスの炭酸ガスレーザが好ましい。
(4) Next, a laser beam is applied to the interlayer resin insulation layer.
By irradiation, a via hole opening is provided. this
When the laser light used is, for example, carbon dioxide
(CO Two ) Laser, ultraviolet laser, excimer laser, etc.
Of these, excimer lasers and short
A pulsed carbon dioxide laser is preferred.

【0031】エキシマレーザは、バイアホール用開孔を
形成する部分に貫通孔が形成されたマスク等を用いるこ
とにより、一度に多数のバイアホール用開孔を形成する
ことができ、また、短パルスの炭酸ガスレーザは、開口
内の樹脂残りが少なく、開口周縁の樹脂に対するダメー
ジが小さいからである。マスクの貫通孔は、レーザ光の
スポット形状を真円にするために、真円である必要があ
り、上記貫通孔の径は、0.1〜2mm程度が望まし
い。
The excimer laser can form a large number of via holes at once by using a mask or the like in which a through hole is formed in a portion where the via holes are formed. This is because the carbon dioxide gas laser has a small amount of resin remaining in the opening and little damage to the resin at the periphery of the opening. The through hole of the mask needs to be a perfect circle in order to make the spot shape of the laser beam a perfect circle, and the diameter of the through hole is desirably about 0.1 to 2 mm.

【0032】レーザ光にて開口を形成した場合、特に炭
酸ガスレーザを用いた場合には、デスミア処理を行うこ
とが望ましい。上記デスミア処理は、クロム酸、過マン
ガン酸塩等の水溶液からなる酸化剤を使用して行うこと
ができる。また、酸素プラズマ、CF4 と酸素の混合プ
ラズマやコロナ放電等で処理してもよい。また、低圧水
銀ランプを用いて紫外線を照射することにより、表面改
質することもできる。
When the opening is formed by a laser beam, particularly when a carbon dioxide gas laser is used, desmearing is preferably performed. The desmear treatment can be performed using an oxidizing agent composed of an aqueous solution such as chromic acid and permanganate. Alternatively, the treatment may be performed using oxygen plasma, a mixed plasma of CF 4 and oxygen, corona discharge, or the like. The surface can also be modified by irradiating ultraviolet rays using a low-pressure mercury lamp.

【0033】(5) 層間樹脂絶縁層は、特に粗化処理等を
行うことなく、その上に金属層を形成してもよく、プラ
ズマ処理するか、または、酸等で処理することにより、
その表面を粗化した後、金属層を形成してもよい。プラ
ズマ処理を行った場合には、上層として形成する導体回
路と層間樹脂絶縁層との密着性を確保するために、層間
樹脂絶縁層との密着性に優れたNi、Ti、Pd等の金
属を中間層として形成してもよい。上記金属からなる中
間層は、スパッタリング等の物理的蒸着法(PVD)に
より形成することが望ましく、その厚さは、0.1〜
2.0μm程度であることが望ましい。
(5) The interlayer resin insulating layer may be formed with a metal layer thereon without performing any particular roughening treatment or the like, and may be subjected to plasma treatment or treatment with an acid or the like.
After roughening the surface, a metal layer may be formed. When the plasma treatment is performed, a metal such as Ni, Ti, Pd, etc. having excellent adhesion to the interlayer resin insulation layer is used to secure the adhesion between the conductor circuit formed as the upper layer and the interlayer resin insulation layer. It may be formed as an intermediate layer. The intermediate layer made of the metal is desirably formed by physical vapor deposition (PVD) such as sputtering.
It is desirable to be about 2.0 μm.

【0034】(6) 上記工程の後、金属からなる薄膜層を
形成する。この薄膜層の材質は、銅または銅−ニッケル
合金が好ましい。この薄膜層は、物理的蒸着法(PVD
法)や化学蒸着法(CVD法)により形成することもで
き、無電解めっきを施すことにより形成することもでき
る。上記PVD法としては、例えば、スパッタリング、
イオンビームスパッタリング等が挙げられ、上記CVD
法としては、有機金属を供給材料とするPE−CVD
(Plasma Enhanced CVD)法等が挙
げられる。
(6) After the above steps, a thin film layer made of metal is formed. The material of the thin film layer is preferably copper or a copper-nickel alloy. This thin film layer is formed by physical vapor deposition (PVD).
Method), a chemical vapor deposition method (CVD method), or an electroless plating. As the PVD method, for example, sputtering,
Ion beam sputtering, etc .;
The method is PE-CVD using organic metal as a feed material.
(Plasma Enhanced CVD) method.

【0035】この薄膜の膜厚は、0.1〜5μmが好ま
しい。このような膜厚とするのは、後に行う電気めっき
の導電層としての機能を損なうことなく、エッチング除
去できるようにするためである。なお、この薄膜の形成
工程は必須ではなく、省略することもできる。
The thickness of this thin film is preferably from 0.1 to 5 μm. The thickness is set so that the film can be removed by etching without impairing the function as a conductive layer in electroplating performed later. The step of forming the thin film is not essential and can be omitted.

【0036】(7) 上記(6) で形成した無電解めっき膜上
にめっきレジストを形成する。このめっきレジストは、
感光性ドライフィルムをラミネートした後、露光、現像
処理を行うことにより形成される。
(7) A plating resist is formed on the electroless plating film formed in (6). This plating resist
After laminating a photosensitive dry film, it is formed by performing exposure and development processing.

【0037】(8) 次に、層間樹脂絶縁層上に形成された
金属薄膜をめっきリードとして電気めっきを行い、導体
回路を厚付けする。電気めっき膜の膜厚は、5〜30μ
mが好ましい。この時、バイアホール用開口を電気めっ
きで充填してフィルドビア構造としてもよい。
(8) Next, electroplating is performed using the thin metal film formed on the interlayer resin insulating layer as a plating lead to thicken the conductor circuit. Electroplating film thickness is 5-30μ
m is preferred. At this time, the via hole opening may be filled with electroplating to form a filled via structure.

【0038】(9) 電気めっき膜を形成した後、めっきレ
ジストを剥離し、めっきレジストの下に存在していた無
電解めっき膜と上記中間層とをエッチングにより除去
し、独立した導体回路とする。上記電気めっきとして
は、銅めっきを用いることが望ましい。エッチング液と
しては、例えば、硫酸−過酸化水素水溶液、過硫酸アン
モニウム、過硫酸ナトリウム、過硫酸カリウム等の過硫
酸塩水溶液、塩化第二鉄、塩化第二銅の水溶液、塩酸、
硝酸、熱希硫酸等が挙げられる。また、前述した第二銅
錯体と有機酸とを含有するエッチング液を用いて、導体
回路間のエッチングと同時に粗化面を形成してもよい。
(9) After forming the electroplating film, the plating resist is peeled off, and the electroless plating film existing under the plating resist and the intermediate layer are removed by etching to form an independent conductor circuit. . It is desirable to use copper plating as the electroplating. Examples of the etchant include sulfuric acid-hydrogen peroxide aqueous solution, ammonium persulfate, sodium persulfate, persulfate aqueous solution such as potassium persulfate, ferric chloride, aqueous solution of cupric chloride, hydrochloric acid,
Nitric acid, hot dilute sulfuric acid and the like can be mentioned. Alternatively, a roughened surface may be formed simultaneously with etching between conductor circuits using an etching solution containing the above-described cupric complex and an organic acid.

【0039】(10)この後、上記(2) 〜(9) の工程を繰り
返して上層の上層導体回路を設け、最上層にソルダーレ
ジスト層を設け、該ソルダーレジスト層を開口してハン
ダバンプを設けることにより、例えば、片面3層の6層
両面多層プリント配線板を得る。以下、実施例をもとに
説明する。
(10) Thereafter, the above steps (2) to (9) are repeated to provide an upper conductor circuit of an upper layer, a solder resist layer is provided on the uppermost layer, and a solder bump is provided by opening the solder resist layer. Thereby, for example, a six-layer double-sided multilayer printed wiring board having three layers on one side is obtained. Hereinafter, description will be made based on embodiments.

【0040】[0040]

【実施例】(実施例1) (1) 厚さ1mmのガラスエポキシ樹脂またはBT(ビス
マレイミド−トリアジン)樹脂からなる基板1の両面に
18μmの銅箔8がラミネートされている銅貼積層板を
出発材料とした(図1(a)参照)。まず、この銅貼積
層板をドリル削孔し、続いてめっきレジストを形成した
後、この基板に無電解銅めっき処理を施してスルーホー
ル9を形成し、さらに、銅箔を常法に従いパターン状に
エッチングすることにより、基板の両面に内層銅パター
ン(下層導体回路)4を形成した。
EXAMPLES (Example 1) (1) A copper-clad laminate in which 18 μm copper foil 8 is laminated on both surfaces of a substrate 1 made of a glass epoxy resin or a BT (bismaleimide-triazine) resin having a thickness of 1 mm. It was used as a starting material (see FIG. 1 (a)). First, the copper-clad laminate is drilled, and then a plating resist is formed. Then, the substrate is subjected to an electroless copper plating process to form through holes 9, and the copper foil is patterned in a conventional manner. Then, an inner copper pattern (lower conductive circuit) 4 was formed on both surfaces of the substrate.

【0041】(2) 下層導体回路4を形成した基板を水洗
いし、乾燥した後、エッチング液を基板の両面にスプレ
イで吹きつけて、下層導体回路4の表面とスルーホール
9のランド表面と内壁とをエッチングすることにより、
下層導体回路4の全表面に粗化面4a、9aを形成した
(図1(b)参照)。エッチング液として、イミダゾー
ル銅(II)錯体10重量部、グリコール酸7重量部、塩
化カリウム5重量部およびイオン交換水78重量部を混
合したものを使用した。
(2) The substrate on which the lower conductive circuit 4 is formed is washed with water and dried, and then an etching solution is sprayed on both surfaces of the substrate by spraying, so that the surface of the lower conductive circuit 4 and the land surface of the through hole 9 and the inner wall are formed. And by etching
The roughened surfaces 4a and 9a were formed on the entire surface of the lower conductor circuit 4 (see FIG. 1B). A mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water was used as an etching solution.

【0042】(3) シクロオレフィン系樹脂を主成分とす
る樹脂充填剤10を、基板の両面に印刷機を用いて塗布
することにより、下層導体回路4間またはスルーホール
9内に充填し、加熱乾燥を行った。即ち、この工程によ
り、樹脂充填剤10が下層導体回路4の間あるいはスル
ーホール9内に充填される(図1(c)参照)。
(3) A resin filler 10 containing a cycloolefin resin as a main component is applied to both sides of the substrate by using a printing machine to fill the space between the lower-layer conductor circuits 4 or the inside of the through hole 9 and heat the resin. Drying was performed. That is, by this step, the resin filler 10 is filled between the lower conductor circuits 4 or in the through holes 9 (see FIG. 1C).

【0043】(4) 上記(3) の処理を終えた基板の片面
を、ベルト研磨紙(三共理化学社製)を用いたベルトサ
ンダー研磨により、下層導体回路4の表面やスルーホー
ル9のランド表面に樹脂充填剤10が残らないように研
磨し、ついで、上記ベルトサンダー研磨による傷を取り
除くためのバフ研磨を行った。このような一連の研磨を
基板の他方の面についても同様に行った。そして、充填
した樹脂充填剤10を加熱硬化させた(図1(d)参
照)。
(4) One surface of the substrate after the treatment of the above (3) is subjected to belt sanding using a belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) to form the surface of the lower conductor circuit 4 and the land surface of the through hole 9 Was polished so that the resin filler 10 did not remain, and then buffed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Then, the filled resin filler 10 was cured by heating (see FIG. 1D).

【0044】このようにして、スルーホール9等に充填
された樹脂充填剤10の表層部および下層導体回路4上
面の粗化層4aを除去して基板両面を平滑化し、樹脂充
填剤10と下層導体回路4の側面とが粗化面4aを介し
て強固に密着し、またスルーホール9の内壁面と樹脂充
填剤10とが粗化面9aを介して強固に密着した配線基
板を得た。
In this manner, the surface layer portion of the resin filler 10 filled in the through holes 9 and the like and the roughened layer 4a on the upper surface of the lower conductor circuit 4 are removed to smooth both surfaces of the substrate, and the resin filler 10 and the lower layer are removed. A wiring board was obtained in which the side surfaces of the conductive circuit 4 were firmly adhered through the roughened surface 4a, and the inner wall surface of the through hole 9 was tightly adhered to the resin filler 10 through the roughened surface 9a.

【0045】(5) 次に、上記(4) の処理を終えた基板の
両面に、上記(2) で用いたエッチング液と同じエッチン
グ液をスプレイで吹きつけ、一旦平坦化された下層導体
回路4の表面とスルーホール9のランド表面とをエッチ
ングすることにより、下層導体回路4の全表面に粗化面
4a、9aを形成した(図2(a)参照)。
(5) Next, the same etching solution as the etching solution used in (2) is sprayed onto both surfaces of the substrate after the treatment in (4), and the lower conductor circuit once flattened is sprayed. By etching the surface of the lower conductor circuit 4 and the land surface of the through hole 9, roughened surfaces 4a and 9a were formed on the entire surface of the lower conductor circuit 4 (see FIG. 2A).

【0046】(6) 次に、上記工程を経た基板の両面に、
厚さ50μmの熱硬化型シクロオレフィン系樹脂シート
を温度50〜150℃まで昇温しながら圧力5kg/c
2 で真空圧着ラミネートし、シクロオレフィン系樹脂
からなる層間樹脂絶縁層2を設けた(図2(b)参
照)。真空圧着時の真空度は、10mmHgであった。
(6) Next, on both surfaces of the substrate having undergone the above steps,
A pressure of 5 kg / c while heating a thermosetting type cycloolefin resin sheet having a thickness of 50 μm to a temperature of 50 to 150 ° C.
Vacuum compression lamination was performed at m 2 to provide an interlayer resin insulating layer 2 made of a cycloolefin-based resin (see FIG. 2B). The degree of vacuum during vacuum compression was 10 mmHg.

【0047】(7) 次に、波長10.4μmのCO2 ガス
レーザにて、ビーム径5mm、トップハットモード、パ
ルス幅50μ秒、マスクの穴径0.5mm、3ショット
の条件でシクロオレフィン系樹脂からなる層間樹脂絶縁
層2に直径80μmのバイアホール用開口6を設けた
(図2(c)参照)。この後、酸素プラズマを用いてデ
スミア処理を行った。
(7) Next, using a CO 2 gas laser having a wavelength of 10.4 μm, the cycloolefin resin was used under the conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 50 μsec, a mask hole diameter of 0.5 mm, and three shots. A via hole opening 6 having a diameter of 80 μm was formed in the interlayer resin insulating layer 2 made of (see FIG. 2C). Thereafter, a desmear treatment was performed using oxygen plasma.

【0048】(8) 次に、日本真空技術株式会社製のSV
−4540を用いてプラズマ処理を行い、層間樹脂絶縁
層2の表面を粗化した(図2(d)参照)。この際、不
活性ガスとしてはアルゴンガスを使用し、電力200
W、ガス圧0.6Pa、温度70℃の条件で、2分間プ
ラズマ処理を実施した。
(8) Next, SV manufactured by Japan Vacuum Engineering Co., Ltd.
Plasma treatment was performed using −4540 to roughen the surface of the interlayer resin insulating layer 2 (see FIG. 2D). At this time, argon gas was used as the inert gas, and the power was 200
Plasma treatment was performed for 2 minutes under the conditions of W, gas pressure 0.6 Pa, and temperature 70 ° C.

【0049】(9) 次に、同じ装置を用い、内部のアルゴ
ンガスを交換した後、Ni−Cu合金をターゲットにし
たスパッタリングを、気圧0.6Pa、温度80℃、電
力200W、時間5分間の条件で行い、Ni−Cu合金
層12をポリオレフィン系層間樹脂絶縁層2の表面に形
成した。このとき、形成されたNi−Cu合金層12の
厚さは0.2μmであった(図3(a)参照)。
(9) Next, after replacing the argon gas inside using the same apparatus, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., a power of 200 W, and a time of 5 minutes. Under the conditions, the Ni—Cu alloy layer 12 was formed on the surface of the polyolefin-based interlayer resin insulating layer 2. At this time, the thickness of the formed Ni—Cu alloy layer 12 was 0.2 μm (see FIG. 3A).

【0050】(10)上記処理を終えた基板の両面に、市販
の感光性ドライフィルムを貼り付け、フォトマスクフィ
ルムを載置して、100mJ/cm2 で露光した後、
0.8%炭酸ナトリウムで現像処理し、厚さ15μmの
めっきレジスト3のパターンを形成した(図3(b)参
照)。
(10) A commercially available photosensitive dry film is adhered to both surfaces of the substrate after the above treatment, a photomask film is placed, and after exposure at 100 mJ / cm 2 ,
It was developed with 0.8% sodium carbonate to form a pattern of the plating resist 3 having a thickness of 15 μm (see FIG. 3B).

【0051】(11)次に、以下の条件で電気めっきを施し
て、厚さ15μmの電気めっき膜13を形成した(図3
(c)参照)。なお、この電気めっき膜13により、後
述する工程で導体回路5となる部分の厚付けおよびバイ
アホール7となる部分のめっき充填等が行われたことに
なる。なお、電気めっき水溶液中の添加剤は、アトテッ
クジャパン社製のカパラシドHLである。
(11) Next, electroplating was performed under the following conditions to form an electroplating film 13 having a thickness of 15 μm (FIG. 3).
(C)). This means that the electroplating film 13 has been used to thicken the portion that will be the conductor circuit 5 and fill the portion that will be the via hole 7 with plating in the steps described later. The additive in the electroplating aqueous solution is Capparaside HL manufactured by Atotech Japan.

【0052】 〔電気めっき水溶液〕 硫酸 2.24 mol/l 硫酸銅 0.26 mol/l 添加剤 19.5 ml/l 〔電気めっき条件〕 電流密度 1 A/dm2 時間 65 分 温度 22±2 ℃[Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l [electroplating conditions] current density 1 A / dm 2 hours 65 minutes temperature 22 ± 2 ° C

【0053】(12)ついで、めっきレジスト3を5%Na
OHで剥離除去した後、そのめっきレジスト3の下に存
在していたNi−Cu合金層12を硝酸および硫酸と過
酸化水素との混合液を用いるエッチングにて溶解除去
し、電気銅めっき膜13等からなる厚さ16μmの導体
回路5(バイアホール7を含む)を形成した(図3
(d)参照)。
(12) Then, the plating resist 3 is made of 5% Na
After stripping and removing with OH, the Ni—Cu alloy layer 12 existing under the plating resist 3 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the electrolytic copper plating film 13 is removed. The conductor circuit 5 (including the via hole 7) having a thickness of 16 μm and the like was formed (FIG. 3).
(D)).

【0054】(13)続いて、上記(5) 〜(13)の工程を、繰
り返すことにより、さらに上層の導体回路を形成した。
(図4(a)〜図5(b)参照)。
(13) Subsequently, the above steps (5) to (13) were repeated to form a further upper layer conductive circuit.
(See FIGS. 4A to 5B).

【0055】(14)次に、ジエチレングリコールジメチル
エーテル(DMDG)に60重量%の濃度になるように
溶解させた、クレゾールノボラック型エポキシ樹脂(日
本化薬社製)のエポキシ基50%をアクリル化した感光
性付与のオリゴマー(分子量:4000)46.67重
量部、メチルエチルケトンに溶解させた80重量%のビ
スフェノールA型エポキシ樹脂(油化シェル社製、商品
名:エピコート1001)15重量部、イミダゾール硬
化剤(四国化成社製、商品名:2E4MZ−CN)1.
6重量部、感光性モノマーである多官能アクリルモノマ
ー(日本化薬社製、商品名:R604)3重量部、同じ
く多価アクリルモノマー(共栄化学社製、商品名:DP
E6A)1.5重量部、分散系消泡剤(サンノプコ社
製、商品名:S−65)0.71重量部を容器にとり、
攪拌、混合して混合組成物を調製し、この混合組成物に
対して光重合開始剤としてベンゾフェノン(関東化学社
製)2.0重量部、光増感剤としてのミヒラーケトン
(関東化学社製)0.2重量部を加えて、粘度を25℃
で2.0Pa・sに調整したソルダーレジスト組成物
(有機樹脂絶縁材料)を得た。なお、粘度測定は、B型
粘度計(東京計器社製、DVL−B型)で60rpmの
場合はローターNo.4、6rpmの場合はローターN
o.3によった。
(14) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight was used. 46.67 parts by weight of an oligomer for imparting properties (molecular weight: 4000), 15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, and 15 parts by weight of an imidazole curing agent ( (Shikoku Chemicals, trade name: 2E4MZ-CN)
6 parts by weight, 3 parts by weight of polyfunctional acrylic monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), which is a photosensitive monomer, and polyvalent acrylic monomer (trade name: DP, manufactured by Kyoei Chemical Co., Ltd.)
E6A) 1.5 parts by weight and 0.71 part by weight of a dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) in a container,
A mixed composition was prepared by stirring and mixing, and 2.0 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a photopolymerization initiator and Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixed composition. Add 0.2 parts by weight and adjust viscosity to 25 ° C
To obtain a solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s. The viscosity was measured with a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) when the rotor No. was 60 rpm. Rotor N at 4,6 rpm
o. According to 3.

【0056】(15)次に、多層配線基板の両面に、上記ソ
ルダーレジスト組成物を20μmの厚さで塗布し、70
℃で20分間、70℃で30分間の条件で乾燥処理を行
った後、ソルダーレジスト開口部のパターンが描画され
た厚さ5mmのフォトマスクをソルダーレジスト層に密
着させて1000mJ/cm2 の紫外線で露光し、DM
TG溶液で現像処理し、200μmの直径の開口を形成
した。そして、さらに、80℃で1時間、100℃で1
時間、120℃で1時間、150℃で3時間の条件でそ
れぞれ加熱処理を行ってソルダーレジスト層を硬化さ
せ、はんだパッド部分が開口した、その厚さが20μm
のソルダーレジスト層(有機樹脂絶縁層)14を形成し
た。
(15) Next, the above-mentioned solder resist composition is applied to both sides of the multilayer wiring board in a thickness of 20 μm,
After performing a drying process under the conditions of 20 ° C. for 20 minutes and 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer, and an ultraviolet ray of 1000 mJ / cm 2 is applied. Exposure with DM
Development was performed with a TG solution to form an opening having a diameter of 200 μm. Then, at 80 ° C. for 1 hour, and at 100 ° C. for 1 hour.
The solder resist layer was cured by performing a heat treatment under the conditions of 1 hour at 120 ° C. and 3 hours at 150 ° C., and the solder pad portion was opened, and the thickness was 20 μm.
Of the solder resist layer (organic resin insulating layer) 14 was formed.

【0057】(16)次に、ソルダーレジスト層(有機樹脂
絶縁層)14を形成した基板を、塩化ニッケル(2.3
×10-1mol/l)、次亜リン酸ナトリウム(2.8
×10 -1mol/l)、クエン酸ナトリウム(1.6×
10-1mol/l)を含むpH=4.5の無電解ニッケ
ルめっき液に20分間浸漬して、開口部に厚さ5μmの
ニッケルめっき層15を形成した。さらに、その基板を
シアン化金カリウム(7.6×10-3mol/l)、塩
化アンモニウム(1.9×10-1mol/l)、クエン
酸ナトリウム(1.2×10-1mol/l)、次亜リン
酸ナトリウム(1.7×10-1mol/l)を含む無電
解めっき液に80℃の条件で7.5分間浸漬して、ニッ
ケルめっき層15上に、厚さ0.03μmの金めっき層
16を形成した。
(16) Next, a solder resist layer (organic resin
The substrate on which the insulating layer (14) was formed was coated with nickel chloride (2.3).
× 10-1mol / l), sodium hypophosphite (2.8
× 10 -1mol / l), sodium citrate (1.6 ×
10-1mol / l) and pH = 4.5
Immersion in a plating solution for 20 minutes, and a 5 μm thick
A nickel plating layer 15 was formed. In addition, the board
Potassium gold cyanide (7.6 × 10-3mol / l), salt
Ammonium iodide (1.9 × 10-1mol / l), quenched
Sodium acid (1.2 × 10-1mol / l), phosphorus hypophosphite
Sodium acid (1.7 × 10-1mol / l)
Immerse in a plating solution at 80 ° C for 7.5 minutes,
0.03 μm thick gold plating layer on the Kell plating layer 15
No. 16 was formed.

【0058】(17)この後、ソルダーレジスト層14の開
口にはんだペーストを印刷して、200℃でリフローす
ることによりはんだバンプ(はんだ体)17を形成し、
はんだバンプ17を有する多層配線プリント基板を製造
した(図5(c)参照)。
(17) Thereafter, a solder paste is printed on the openings of the solder resist layer 14 and reflowed at 200 ° C. to form solder bumps (solder bodies) 17.
A multilayer wiring printed board having the solder bumps 17 was manufactured (see FIG. 5C).

【0059】得られた多層プリント配線板について、誘
電率、誘電正接及びピール強度を測定し、128℃で4
8時間の加熱処理試験、及び、−55℃〜125℃で1
000回のヒートサイクル試験を実施した。そして、上
記加熱処理試験の後、及び、ヒートサイクル試験の後に
は、層間樹脂絶縁層と下層導体回路との剥離、バイアホ
ール部分の抵抗変化率を測定した。結果を下記の表1に
示した。
The dielectric constant, dielectric loss tangent, and peel strength of the obtained multilayer printed wiring board were measured.
Heat treatment test for 8 hours and 1 at -55 ° C to 125 ° C
000 heat cycle tests were performed. Then, after the heat treatment test and after the heat cycle test, peeling between the interlayer resin insulating layer and the lower conductive circuit and the resistance change rate of the via hole portion were measured. The results are shown in Table 1 below.

【0060】(実施例2)(5) の工程における導体回路
のエッチングを行わず、(8) の工程における層間樹脂絶
縁層の粗化処理も行わなかった以外は、上記実施例1と
同様にして、多層プリント配線板を製造した。そして、
得られた多層プリント配線板について、実施例1と同様
の試験及び評価を行った。結果を下記の表1に示した。
(Example 2) In the same manner as in Example 1 except that the conductor circuit was not etched in the step (5) and the interlayer resin insulating layer was not roughened in the step (8). Thus, a multilayer printed wiring board was manufactured. And
The same tests and evaluations as in Example 1 were performed on the obtained multilayer printed wiring board. The results are shown in Table 1 below.

【0061】(比較例1)層間樹脂絶縁層を形成するた
めの樹脂として、熱硬化型線状ポリオレフィン系樹脂
(住友3M社製、商品名:1592)を用いた以外は、
実施例1と同様にして多層プリント配線板を製造した。
そして、得られた多層プリント配線板について、実施例
1と同様の試験及び評価を行った。結果を下記の表1に
示した。
(Comparative Example 1) A thermosetting linear polyolefin resin (manufactured by Sumitomo 3M, trade name: 1592) was used as a resin for forming an interlayer resin insulating layer.
A multilayer printed wiring board was manufactured in the same manner as in Example 1.
Then, the same tests and evaluations as in Example 1 were performed on the obtained multilayer printed wiring board. The results are shown in Table 1 below.

【0062】[0062]

【表1】 [Table 1]

【0063】上記表1の結果より明らかなように、実施
例の多層プリント配線板は、加熱試験やヒートサイクル
試験を行った後も、導体回路とバイアホールとの間の抵
抗変化率は小さく、導体回路と層間樹脂絶縁層との剥離
は見られなかったのに対し、比較例の多層プリント配線
板は、抵抗変化率が大きいか、または、試験後に剥離が
発生していた。
As is clear from the results shown in Table 1, the multilayer printed wiring board of the example has a small resistance change ratio between the conductor circuit and the via hole even after the heating test and the heat cycle test. While no peeling was observed between the conductor circuit and the interlayer resin insulating layer, the multilayer printed wiring board of the comparative example had a large rate of change in resistance or peeled off after the test.

【0064】[0064]

【発明の効果】以上説明したように本発明の多層プリン
ト配線板は、層間樹脂絶縁層として、シクロオレフィン
系樹脂を使用しているので、誘電率や誘電正接が小さ
く、そのためにGHz帯域の高周波信号を用いた場合に
も、信号遅延や信号エラーが発生しにくく、また、剛性
等の機械的特性に優れるため、導体回路同士の接続の信
頼性が高く、導体回路と層間樹脂絶縁層をとの密着性に
も優れる。
As described above, the multilayer printed wiring board of the present invention uses a cycloolefin resin as the interlayer resin insulating layer, so that the dielectric constant and the dielectric loss tangent are small. Even when signals are used, signal delays and signal errors are unlikely to occur, and mechanical properties such as rigidity are excellent, so the reliability of the connection between conductor circuits is high, and the conductor circuits and interlayer resin insulation layers should be used. Also has excellent adhesion.

【0065】また、本発明の多層プリント配線板の製造
方法は、導体回路上にシクロオレフィン系樹脂シートを
ラミネートすることにより層間樹脂絶縁層を形成するの
で、溶剤等を用いる必要がなくなり、製造工程が簡易化
され、容易に多層プリント配線板を製造することができ
る。
In the method for manufacturing a multilayer printed wiring board according to the present invention, the interlayer resin insulating layer is formed by laminating a cycloolefin-based resin sheet on a conductive circuit, so that it is not necessary to use a solvent or the like, and Is simplified, and a multilayer printed wiring board can be easily manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(d)は、本発明の多層プリント配線
板の製造工程の一部を示す縦断面図である。
FIGS. 1A to 1D are longitudinal sectional views showing a part of a manufacturing process of a multilayer printed wiring board according to the present invention.

【図2】(a)〜(d)は、本発明の多層プリント配線
板の製造工程の一部を示す縦断面図である。
FIGS. 2A to 2D are longitudinal sectional views showing a part of a manufacturing process of the multilayer printed wiring board of the present invention.

【図3】(a)〜(d)は、本発明の多層プリント配線
板の製造工程の一部を示す縦断面図である。
FIGS. 3A to 3D are longitudinal sectional views showing a part of a manufacturing process of the multilayer printed wiring board of the present invention.

【図4】(a)〜(c)は、本発明の多層プリント配線
板の製造工程の一部を示す縦断面図である。
FIGS. 4A to 4C are longitudinal sectional views showing a part of a manufacturing process of the multilayer printed wiring board of the present invention.

【図5】(a)〜(c)は、本発明の多層プリント配線
板の製造工程の一部を示す縦断面図である。
FIGS. 5A to 5C are longitudinal sectional views showing a part of a manufacturing process of the multilayer printed wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 層間樹脂絶縁層 3 めっきレジスト 4 下層導体回路 4a 粗化面 5 上層導体回路 6 バイアホール用開口 7 バイアホール 8 銅箔 9 スルーホール 9a 粗化面 10 樹脂充填剤 12 Ni−Cu合金層 13 電気めっき膜 14 ソルダーレジスト層 15 ニッケルめっき膜 16 金めっき膜 17 はんだバンプ Reference Signs List 1 substrate 2 interlayer resin insulating layer 3 plating resist 4 lower conductive circuit 4a roughened surface 5 upper conductive circuit 6 opening for via hole 7 via hole 8 copper foil 9 through hole 9a roughened surface 10 resin filler 12 Ni-Cu alloy layer 13 Electroplating film 14 Solder resist layer 15 Nickel plating film 16 Gold plating film 17 Solder bump

───────────────────────────────────────────────────── フロントページの続き (72)発明者 浅井 元雄 岐阜県揖斐郡揖斐川町北方1−1 イビデ ン株式会社大垣北工場内 (72)発明者 島田 憲一 岐阜県揖斐郡揖斐川町北方1−1 イビデ ン株式会社大垣北工場内 Fターム(参考) 5E346 AA06 AA12 AA15 AA23 AA43 BB01 CC08 CC32 CC37 CC54 DD02 DD03 DD17 DD24 DD33 DD47 EE33 EE35 EE38 FF14 GG15 GG17 GG27 GG28 HH05 HH06 HH07 HH11  ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Motoo Asai 1-1, Ibigawa-cho, Ibi-gun, Gifu Prefecture Inside the Ogaki-Kita Plant of Ibid Co., Ltd. (72) Inventor Kenichi Shimada 1-1, Ibigawa-cho, Ibi-gun, Gifu Prefecture F-term in Ogaki Kita Plant (reference) 5E346 AA06 AA12 AA15 AA23 AA43 BB01 CC08 CC32 CC37 CC54 DD02 DD03 DD17 DD24 DD33 DD47 EE33 EE35 EE38 FF14 GG15 GG17 GG27 GG28 HH05 HH06 HH07 HH11

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 基板上に導体回路と樹脂絶縁層とが順次
形成され、これら導体回路がバイアホールを介して接続
されてなる多層プリント配線板において、前記樹脂絶縁
層は、シクロオレフィン系樹脂からなることを特徴とす
る多層プリント配線板。
1. A multilayer printed wiring board in which a conductive circuit and a resin insulating layer are sequentially formed on a substrate and these conductive circuits are connected via via holes, wherein the resin insulating layer is made of a cycloolefin resin. A multilayer printed wiring board, comprising:
【請求項2】 前記樹脂絶縁層の1GHzにおける誘電
率は、3.0以下であり、誘電正接は、0.01以下で
ある請求項1記載の多層プリント配線板。
2. The multilayer printed wiring board according to claim 1, wherein the dielectric constant of the resin insulating layer at 1 GHz is 3.0 or less, and the dielectric loss tangent is 0.01 or less.
【請求項3】 前記シクロオレフィン系樹脂は、2−ノ
ルボルネン、5−エチリデン−2−ノルボルネンまたは
これらの誘導体からなる単量体の単独重合体または共重
合体である請求項1または2記載の多層プリント配線
板。
3. The multilayer according to claim 1, wherein the cycloolefin-based resin is a homopolymer or a copolymer of a monomer composed of 2-norbornene, 5-ethylidene-2-norbornene, or a derivative thereof. Printed wiring board.
【請求項4】 前記シクロオレフィン系樹脂は、熱硬化
性シクロオレフィン系樹脂である請求項1〜3のいずれ
かに記載の多層プリント配線板。
4. The multilayer printed wiring board according to claim 1, wherein the cycloolefin-based resin is a thermosetting cycloolefin-based resin.
【請求項5】 基板上に導体回路と樹脂絶縁層とが順次
形成され、これら導体回路がバイアホールを介して接続
されてなる多層プリント配線板の製造方法において、基
板上に形成された導体回路上に、シクロオレフィン系樹
脂からなるフィルムを真空圧着ラミネートすることによ
り、層間樹脂絶縁層を形成することを特徴とする多層プ
リント配線板の製造方法。
5. A method for manufacturing a multilayer printed wiring board, comprising: forming a conductive circuit and a resin insulating layer on a substrate in order, and connecting the conductive circuits through via holes. A method for producing a multilayer printed wiring board, wherein an interlayer resin insulating layer is formed by laminating a film made of a cycloolefin-based resin under vacuum.
【請求項6】 基板上に形成された導体回路上に、シク
ロオレフィン系樹脂から層間樹脂絶縁層を形成した後、
前記層間樹脂絶縁層にレーザ光を照射することによりバ
イアホール用開口を形成する請求項5記載の多層プリン
ト配線板の製造方法。
6. After forming an interlayer resin insulating layer from a cycloolefin resin on a conductive circuit formed on a substrate,
6. The method for manufacturing a multilayer printed wiring board according to claim 5, wherein a via hole opening is formed by irradiating the interlayer resin insulating layer with laser light.
JP18741899A 1998-09-28 1999-07-01 Multilayer printed wiring board and manufacturing method thereof Expired - Fee Related JP4197805B2 (en)

Priority Applications (33)

Application Number Priority Date Filing Date Title
JP18741899A JP4197805B2 (en) 1999-07-01 1999-07-01 Multilayer printed wiring board and manufacturing method thereof
MYPI99004184A MY139405A (en) 1998-09-28 1999-09-27 Printed circuit board and method for its production
EP06115380A EP1699278B1 (en) 1998-09-28 1999-09-28 Multilayer printed wiring board and method for producing the same
EP06115377A EP1727409B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
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DE69934130T DE69934130T2 (en) 1998-09-28 1999-09-28 PRINTED PCB AND METHOD FOR THE PRODUCTION THEREOF
EP06115385A EP1699280B1 (en) 1998-09-28 1999-09-28 Multilayer printed wiring board and method for producing the same
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EP07108839A EP1893006B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
PCT/JP1999/005266 WO2000019789A1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
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KR1020067014993A KR100673910B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
EP08160500A EP1978796B1 (en) 1998-09-28 1999-09-28 Multilayer printed wiring board and method for producing the same
KR1020067014992A KR100675615B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
DE69941937T DE69941937D1 (en) 1998-09-28 1999-09-28 Multilayer printed circuit board and manufacturing method therefor
EP99943468A EP1119227B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
KR1020017003881A KR100697640B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
US09/806,203 US7535095B1 (en) 1998-09-28 1999-09-28 Printed wiring board and method for producing the same
DE69939913T DE69939913D1 (en) 1998-09-28 1999-09-28 Printed circuit board and method of manufacture
EP07110631A EP1830617B1 (en) 1998-09-28 1999-09-28 Multilayer printed wiring board and method for producing the same
DE69943397T DE69943397D1 (en) 1998-09-28 1999-09-28 Multilayer printed circuit board and method for its production
US11/188,886 US7504719B2 (en) 1998-09-28 2005-07-26 Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same
US12/146,212 US8018045B2 (en) 1998-09-28 2008-06-25 Printed circuit board
US12/146,105 US8030577B2 (en) 1998-09-28 2008-06-25 Printed wiring board and method for producing the same
US12/146,204 US8006377B2 (en) 1998-09-28 2008-06-25 Method for producing a printed wiring board
US12/146,165 US8020291B2 (en) 1998-09-28 2008-06-25 Method of manufacturing a printed wiring board
US12/409,683 US8533943B2 (en) 1998-09-28 2009-03-24 Printed wiring board and method for producing the same
US12/409,670 US7994433B2 (en) 1998-09-28 2009-03-24 Printed wiring board and method for producing the same
US12/420,469 US8093507B2 (en) 1998-09-28 2009-04-08 Printed wiring board and method for producing the same

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