JP2001168529A - Multilayer printed wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board together with its manufacturing method wherein the arrangement density of through holes is raised with less thickness. SOLUTION: A through hole 36 formed in a core substrate 30 comprises a first electrolytic plating layer 24, an electroless plating film 26, and a second electrolytic plating layer 28. The through hole 36 is formed by plate-filling, so the strength of the core substrate 30 is raised and warping is less easy to be generated. Thus, the core substrate can be thinner, and the heat-radiation characteristic of a multilayer printed wiring board is raised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board which can be used for a package substrate on which electronic components such as IC chips are mounted, and more particularly to a multilayer printed wiring board and a multilayer printed wiring formed by building up an interlayer resin insulating layer on a core substrate. It also relates to a method for manufacturing a plate.

[0002]

2. Description of the Related Art Conventionally, build-up multilayer printed wiring boards have been manufactured, for example, by the method disclosed in Japanese Patent Application Laid-Open No. Hei 9-130050. That is, an interlayer resin insulating layer is laminated on a core substrate in which a through hole is formed, and a circuit pattern is formed on the interlayer resin insulating layer. By repeating this, a build-up multilayer printed wiring board is obtained.

[0003]

At present, when a through hole is formed in a core substrate, a through hole is formed by a drill. For this reason, 300 μm is the minimum limit of the diameter of the through hole, and the density of the through hole cannot be increased beyond the value determined by the drill diameter. For this reason, a method of drilling through holes in the core substrate using a laser has been studied. However, since the core substrate has a thickness of about 1 mm, it was difficult to form fine through holes.

On the other hand, in a multilayer printed wiring board used as a package substrate, it is necessary to efficiently radiate heat generated in an IC chip. Here, the multilayer printed wiring board is formed by laminating an interlayer resin insulating layer and a wiring layer of several tens of μm on a core substrate made of a laminated resin plate of about 1 mm.
Therefore, the core substrate occupies most of the thickness of the multilayer printed wiring board. That is, the core substrate increases the thickness of the multilayer printed wiring board and causes a decrease in thermal conductivity.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer printed wiring board capable of increasing the arrangement density of through holes and reducing the thickness thereof, and the multilayer printed wiring board. An object of the present invention is to provide a method for manufacturing a plate.

[0006]

In order to solve the above-mentioned problems, a first aspect of the present invention is a multilayer printed wiring board in which an interlayer resin insulating layer is built up on a core substrate provided with through holes. The technical feature is that the through holes are filled with a first metal layer formed by electrolytic plating, a metal film formed by electroless plating, sputtering or vapor deposition, and a second metal layer formed by electrolytic plating.

According to the first aspect, since the through hole is formed by filling with plating, a via hole for connection can be formed on the through hole, and the wiring density of the via hole can be increased. In addition, through-holes, electrolytic plating,
Since the electroless plating and the electrolytic plating are filled, insufficient filling in the through holes is eliminated.

A second aspect of the present invention is a method for manufacturing a multilayer printed wiring board, comprising at least the following steps (A) to (E): (A) Forming a metal layer on one surface Forming a non-through hole reaching the metal layer by a laser in the resin insulating layer thus formed; (B) flowing a current through the metal layer to the non-through hole of the resin insulating layer through the metal layer to form a first metal by electrolytic plating; Filling a layer; (C) forming a metal film on the surface of the resin insulating layer opposite to the metal layer: (D) passing a current through a non-through hole of the resin insulating layer via the metal film. Filling a second metal layer by electrolytic plating; (E) forming a land of a through hole by etching the metal layer and the metal film of the resin insulating layer.

According to the second aspect, since the through holes are formed by laser, the through holes having a diameter of 50 to 250 μm can be formed, so that the wiring density can be improved. Since the through holes are formed by plating and filling, the strength of the core substrate is increased, and warpage is less likely to occur. For this reason, the core substrate can be formed thin, and the heat dissipation of the multilayer printed wiring board can be improved. Since the through holes are filled by electrolytic plating, insufficient filling in the through holes is eliminated.
Furthermore, since the second metal layer is formed in the through hole after the metal film serving as the land of the through hole is formed, the land does not peel off, and the reliability of the through hole can be improved. Further, since the connection reliability is high, the land can be formed thin, the smoothness of the upper interlayer resin insulating layer can be improved, and peeling and cracking of the interlayer resin insulating layer can be prevented.

According to a third aspect of the present invention, in the second aspect, the method further comprises a step of forming a metal layer on the resin insulating layer by electroless plating, sputtering or vapor deposition.

According to the third aspect, when the metal layer is formed by electroless plating, the metal layer can be formed at low cost. When formed by sputtering, a thin metal layer having high adhesion can be formed. When formed by vapor deposition, a thin metal layer can be formed.

According to a fourth aspect, in the second or third aspect,
In the step of forming a metal film on the surface of the resin insulation layer opposite to the metal layer, a technical feature is that electroless plating, sputtering, or vapor deposition is used.

According to the fourth aspect, when the metal film is formed by electroless plating, the metal film can be formed at low cost. When formed by sputtering, a thin metal film having high adhesion can be formed. When formed by vapor deposition, a thin metal film can be formed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] The structure of a multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIG. In the multilayer printed wiring board of the first embodiment, a conductor circuit 34 is formed on the upper and lower surfaces of a core substrate 30, and interlayer resin insulation layers 50, 50 are provided on the conductor circuit 34. Via holes 60 and conductor circuits 58 are provided in the lower interlayer resin insulation layer 50. On the lower interlayer resin insulation layer 50 on the upper surface side, an upper interlayer resin insulation layer 150 in which a via hole 160 is formed is arranged. The upper interlayer resin insulation layer 150 on the upper surface side and the lower interlayer resin insulation layer 50 on the lower surface side
Is provided with a solder resist layer 70 on the surface thereof.

On the upper surface of the multilayer printed wiring board 10, a solder bump 76U for connection to an IC chip is provided in an opening 71U of the solder resist layer 70. On the other hand, the opening 71D of the solder resist layer 70 is formed on the bottom of the package substrate.
Are provided with solder bumps 76D for connection to the daughter board.

The solder bumps (76U) are formed on the interlayer resin insulation layer (1).
It is connected to the through-hole 36 via the via hole 160 formed in 50 and the via hole 60 formed in the interlayer resin insulating layer 50. On the other hand, the solder bump 76D
Are via holes 60 formed in interlayer resin insulation layer 50.
Is connected to the through-hole 36 via the.

The through hole 3 formed in the core substrate 30
6 denotes a first electrolytic plating layer 24 and an electroless plating film 26
And the second electrolytic plating layer 28. Through hole 3
Since 6 is formed by filling with plating, the strength of the core substrate 30 is increased, and warpage hardly occurs. For this reason, the core substrate can be formed thin, and the heat dissipation of the multilayer printed wiring board can be improved. Further, since the through hole 36 is formed by filling the first electrolytic plating layer 24, the electroless plating film 26, and the second electrolytic plating layer 28, insufficient filling in the through hole is eliminated.

As will be described later, in the multilayer printed wiring board of the first embodiment, since the through holes 36 are formed by a laser, the through holes 36 having a fine diameter can be arranged at a narrow pitch, and high integration is achieved. are doing.

The multilayer printed wiring board 10 shown in FIG.
Will be described with reference to the drawings.

(1) Epoxy resin, BT (bismaleimide triazine) resin on glass cloth and aramid cloth,
A substrate 30 impregnated with a polyimide resin, an olefin resin, and a polyphenol ether resin is used as a starting material (FIG. 1A). The thickness of the substrate 30 is 20 to 800 μm
Is good, and 100 to 500 μm is particularly preferable. This is because the thickness as a core substrate can be maintained and a non-through hole can be easily formed by laser. Here, the core material is used by impregnating the resin. Alternatively, a resin having no core material or a resin having a reinforcing resin layer laminated thereon may be used.

(2) A metal layer 22 having a thickness of 6 to 20 μm is formed on the lower surface of the substrate 30 by sputtering (FIG. 1).
(B)). For the metal layer 22, copper, nickel, chromium, cobalt, aluminum, or the like can be used. In particular, copper or an alloy mainly containing copper is preferable because it is inexpensive and has low electric resistance. Here, sputtering that has excellent adhesion to the resin substrate 30 and can be formed thinly is used. Instead, inexpensive electroless plating or vapor deposition that can form a thin metal layer at low cost can be used. Electroless plating, electroless plating, sputtering, and electrolytic plating can also be performed after evaporation.
Further, a copper-clad laminate in which a copper foil is laminated can be used as the core substrate. Here, the metal layer 22
Is preferably in the range of 6 to 20 μm, particularly 8 to 15 μm.
The range of μm is preferred. With this thickness, the strength can be maintained and there is no warpage, and the laser energy can be absorbed when forming a non-through hole in the substrate 30 as described later.

(3) Next, the substrate 30 is irradiated with a carbon dioxide laser from the surface on which the metal layer 22 is not formed, and a non-through hole 32 reaching the metal layer 22 is formed (FIG. 1C). Here, the diameter of the non-through hole is preferably 50 to 250 μm, and particularly preferably 75 to 150 μm.
A pitch of 400 to 600 μm in the range of μm is preferred. The smaller diameter of the non-through hole 32 is desirable for increasing the wiring density, but the yield decreases in inverse proportion to the radius. Here, the non-through holes 32 are
It is also possible to form a hole for each hole, and a mask having a through hole can be placed on the substrate 30 to form a non-through hole collectively. Here, a carbon dioxide laser which is inexpensive and has a large output is used, but excimer, UV, YAG or the like can be used instead, or a mixture of these can be used.

Thereafter, the non-through hole 32 is formed with an acid or an oxidizing agent.
Desmear processing inside. Here, the inner wall of the non-through hole 32 may be further smoothed by performing a plasma treatment such as oxygen, tetrachloride, or nitrogen, a corona treatment, or a dry treatment such as a UV treatment.

(4) Next, after the film 23 is brought into close contact with the metal film 20, the substrate 30 is immersed in an electrolytic copper plating solution, a current is passed through the metal layer 22, and the first The plating layer 24 is formed (FIG. 1D). The first electrolytic plating layer is desirably copper plating having a low electric resistance.
It is also possible to use chromium, cobalt, aluminum and the like.

(5) A metal film 26 having a thickness of 0.1 to 10 μm is formed on the upper surface of the substrate 30 by electroless plating (FIG. 2A). For the metal layer, copper, nickel, chromium, cobalt, aluminum, or the like can be used. In particular, copper or an alloy mainly containing copper is preferable because it is inexpensive and has low electric resistance. Instead of electroless plating, sputtering or vapor deposition having excellent adhesion to the substrate 30 made of resin can be used. Here, the thickness of the metal film 26 is 0.1 to 1
A range of 0 μm is preferable, and within this range, a circuit can be formed by etching. In particular, the range of 0.5 to 5 μm is preferable.

(6) The substrate 30 is immersed in an electrolytic copper plating solution,
An electric current flows through the metal film 26 and the second
The plated layer 28 is filled to form a through hole 36 (FIG. 2).
(B)). Electroplating is desirably the same metal as the first plating layer. Further, as described above with reference to FIG. 7, it is desirable that the height H1 of the first plating layer 24 and the height H2 of the second plating layer 28 are substantially the same. Note that, in order to smooth the surface of the second plating layer 28,
It is also possible to perform etching, buffing, belt sander, jet scrub polishing for blowing abrasive grains, and the like.

(7) After the film 23 is peeled off, a predetermined pattern of an etchant resist is applied and patterned.
While forming the conductor circuit 34 on the surface of the core substrate 30,
A land 36a is formed in the through hole 36 (FIG. 2).
(C)). The shape of the land is preferably circular or elliptical, but may be square or rectangular. The land 36a is desirably 1.00 to 1.25 times the through hole diameter. The thickness H3 of the land 36a and the conductor circuit is desirably as thin as possible in order to achieve smoothness of the upper interlayer resin insulation layer.

In the multilayer printed wiring board of the first embodiment,
Since the second plating layer 28 is formed in the through hole after the metal film 26 serving as the land 36a of the through hole 36 is formed, the land 36a formed of the metal film 26 does not peel off. Can be enhanced. Further, since the connection reliability is high, the land can be formed thin, and the smoothness of the upper interlayer resin insulating layer formed in a step described later can be improved, and peeling and cracking of the interlayer resin insulating layer can be prevented. Can be prevented.

(8) The substrate on which the conductor circuit 34 and the land 36a are formed is washed with water and dried, and then an etching solution is sprayed on both surfaces of the substrate by spraying, so that the surface of the lower conductor circuit 34 and the land 36a of the through hole 36 are formed. By etching the surface, the roughened surface 34
β and 36β were formed on the land 36a of the through hole 36 (see FIG. 2D). As an etching solution, a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water is used.

In this embodiment, the roughened surface is formed by etching in the step (1), but a roughened layer may be formed by electroless plating instead. In this case, the substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution composed of palladium chloride and an organic acid to form P
After the catalyst was activated and the catalyst was activated, copper sulfate was added.
2 × 10 ⁻² mol / l, nickel sulfate 3.9 × 10
⁻³ mol / l, complexing agent 5.4 × 10 ⁻² mol / l,
Sodium hypophosphite 3.3 × ¹⁰ -1 mol / l, boric acid ^{5.0 × 10 - 1 mol / l} , the surfactant (Nisshin Chemical Industry Co., Sir Feel 465) 0.1g / l, PH =
Immersion in an electroless plating solution consisting of
By vibrating vertically and horizontally at a rate of once per second, C is applied to the surface of the land 36a of the conductor circuit 34 and the through hole 36.
A coating layer of a needle-shaped alloy made of u-Ni-P and a roughened layer 42 are provided. A metal layer such as Sn, Pb, or Ni may be provided on the surface of the roughened layer.

(9) Next, on both sides of the substrate having undergone the above steps,
A pressure of 5 kg / c while heating a thermosetting type cycloolefin resin sheet having a thickness of 50 μm to a temperature of 50 to 150 ° C.
Vacuum compression lamination is performed at m ² to provide an interlayer resin insulating layer 50 made of a cycloolefin-based resin (see FIG. 3A). The degree of vacuum at the time of vacuum pressing is adjusted to 10 mmHg.

(10) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 15 μs, a mask hole diameter of 0.5 mm, and three shots, a via hole opening 48 having a diameter of 80 μm is provided in the interlayer resin insulating layer 50 made of cycloolefin resin (see FIG. 3B). Thereafter, desmear treatment is performed using oxygen plasma.

(11) Next, S manufactured by Japan Vacuum Engineering Co., Ltd.
Plasma treatment was performed using V-4540 to roughen the surface of the interlayer resin insulating layer 50 (see FIG. 3C). At this time, argon gas was used as the inert gas, and electric power 2
Plasma treatment was performed for 2 minutes under the conditions of 00 W, a gas pressure of 0.6 Pa, and a temperature of 70 ° C.

(12) Next, after replacing the argon gas inside using the same apparatus, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C.
The operation was performed under the conditions of a power of 200 W and a time of 5 minutes to form a Ni—Cu alloy layer 52 on the surface of the polyolefin-based interlayer resin insulating layer 50. At this time, the formed Ni—Cu alloy layer 5
The thickness of Sample No. 2 was 0.2 μm (see FIG. 4A).

(13) A commercially available photosensitive dry film is adhered to both surfaces of the substrate after the above treatment, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
Developing with 0.8% sodium carbonate, a pattern of a plating resist 54 having a thickness of 15 μm was formed (FIG. 4B).
reference).

(14) Next, electroplating was performed under the following conditions to form an electroplating film 56 having a thickness of 15 μm (FIG. 4).
(C)). This means that the electroplating film 56 has been used to thicken the portion that will become the conductor circuit 58 and fill the portion that will become the via hole 60 with plating in the steps described later. The additive in the electroplating aqueous solution is Capparaside HL manufactured by Atotech Japan.

[Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l [electroplating conditions] current density 1 A / dm ² hours 65 minutes temperature 22 ± 2 ° C

(15) Then, the plating resist 54 is changed to 5% N
After stripping and removing with aOH, the Ni—Cu alloy layer 52 existing under the plating resist 54 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the electrolytic copper plating film 56 is removed. A conductor circuit 58 (including the via hole 60) having a thickness of 16 μm and the like was formed (see FIG. 5A).

(16) Subsequently, the above steps (10) to (16) are repeated to further increase the interlayer resin insulation layer 50 on the upper surface side.
Then, an upper interlayer resin insulation layer 150, a conductor circuit 158, and a via hole 160 were formed (see FIG. 5B).

(17) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was sensitized with 50% of epoxy groups being acrylated. 46.67 parts by weight of an oligomer for imparting property (molecular weight: 4000), 15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, and 15 parts by weight of an imidazole curing agent ( (Shikoku Chemicals, trade name: 2E4MZ-CN)
6 parts by weight, 3 parts by weight of polyfunctional acrylic monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), which is a photosensitive monomer, and polyvalent acrylic monomer (trade name: DP, manufactured by Kyoei Chemical Co., Ltd.)
E6A) 1.5 parts by weight and 0.71 part by weight of a dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) in a container,
A mixed composition was prepared by stirring and mixing, and 2.0 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a photopolymerization initiator and Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixed composition. Add 0.2 parts by weight and adjust viscosity to 25 ° C
To obtain a solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s. The viscosity was measured with a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) when the rotor No. was 60 rpm. Rotor N at 4,6 rpm
o. According to 3.

(18) Next, the above-mentioned solder resist composition is applied to both surfaces of the multilayer wiring board in a thickness of 20 μm,
After performing a drying process under the conditions of 20 ° C. for 20 minutes and 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer, and an ultraviolet ray of 1000 mJ / cm ² is applied. Exposure with DM
Development was performed with a TG solution to form an opening 71U having a diameter of 200 μm on the upper surface and an opening 71D having a diameter of 500 μm on the lower surface. Then, the solder resist layer is further heated at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours to cure the solder resist layer.
A solder resist layer (organic resin insulating layer) 70 having a thickness of 20 μm and an opening in the solder pad portion was formed (FIG. 6A). The through-hole may be press-bonded with a semi-cured resin film, and a solder pad may be provided by exposure and development or laser.

(19) Next, a solder resist layer (organic resin
The substrate on which the insulating layer (70) is formed is coated with nickel chloride (2.3).
× 10^-1mol / l), sodium hypophosphite (2.8
× 10 ^-1mol / l), sodium citrate (1.6 ×
10^-1mol / l) and pH = 4.5
Immersion in a plating solution for 20 minutes, and a thickness of 5 μm
Was formed (FIG. 6B). Sa
Furthermore, the substrate is made of potassium potassium cyanide (7.6 × 10^-3
mol / l), ammonium chloride (1.9 × 10 ^-1mo
1 / l), sodium citrate (1.2 × 10^-1mol
/ L), sodium hypophosphite (1.7 x 10^-1mol
/ L) for 7.5 minutes at 80 ° C in an electroless plating solution containing
To a thickness of 0.03 on the nickel plating layer 72.
A gold plating layer 74 of μm was formed.

(20) Thereafter, solder paste is printed on the openings 71U and 71D of the solder resist layer 70,
Solder bump (solder body) by reflowing at ℃
76U and 76D are formed to complete the multilayer printed wiring board 10 (see FIG. 7).

[Second Embodiment] Next, a multilayer printed wiring board according to a second embodiment of the present invention and a method for manufacturing the same will be described. FIG. 12 shows a cross section of a multilayer printed wiring board according to the second embodiment applied to a package substrate. The multilayer printed wiring board according to the second embodiment is similar to the first embodiment described above with reference to FIG. However, in the first embodiment, the solder bumps 76D
However, in the second embodiment, the conductive connection pins 7
8 are provided.

A method for manufacturing the multilayer printed wiring board according to the second embodiment will be described. The method of forming the core substrate includes the steps (1) to (8) of the first embodiment described above with reference to FIGS.
Therefore, the description is omitted.

First, the production of a resin film for an interlayer resin insulation layer will be described. 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent: 469, Epicoat 1001 manufactured by Yuka Shell Epoxy Co.), 40 parts by weight of cresol novolak type epoxy resin (epoxy equivalent: 215, epicron N-673 manufactured by Dainippon Ink & Chemicals, Inc.), triazine 30 parts by weight of a structure-containing phenol novolak resin (phenolic hydroxyl equivalent: 120, phenolite KA-7052 manufactured by Dainippon Ink and Chemicals, Inc.) was dissolved by heating in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha while stirring, The terminal epoxidized polybutadiene rubber (Denalex R manufactured by Nagase Kasei Kogyo Co., Ltd.)
(45EPT), 1.5 parts by weight of a pulverized product of 2-phenyl-4,5-bis (hydroxymethyl) imidazole, 2 parts by weight of finely divided silica, and 0.5 part by weight of a silicon-based antifoaming agent, A resin composition was prepared. The resulting epoxy resin composition is applied on a 38 μm-thick PET film using a roll coater so that the thickness after drying becomes 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to form an interlayer resin. A resin film for an insulating layer was produced.

(9) On both sides of the substrate 30 shown in FIG.
A resin film for an interlayer resin insulation layer, which was slightly larger than the substrate, was placed on the substrate, and a pressure of 4 kgf / cm ² and a temperature of 80 were applied.
After temporarily compressing and cutting at 10 ° C. for 10 seconds, the interlayer resin insulating layer 50 was formed by pasting using a vacuum laminator apparatus by the following method (see FIG. 8A). That is, a resin film for an interlayer resin insulating layer is formed on a substrate by applying a vacuum of 0.5 Torr and a pressure of 4 k.
The final compression bonding was performed under the conditions of gf / cm ² , a temperature of 80 ° C., and a compression bonding time of 60 seconds, followed by heat curing at 170 ° C. for 30 minutes.

(10) On the interlayer resin insulation layer 50, a thickness of 1.
A mask 49 having a through-hole 49a of 2 mm is placed. Then, using a CO ₂ gas laser having a wavelength of 10.4 μm, under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 5.0 μsec, a diameter of a through hole of a mask of 1.0 mm, and one shot, an interlayer resin insulating layer was formed. A via hole opening 48 having a diameter of 80 μm was formed in 50 (see FIG. 8B).

(11) The substrate 30 having the via hole opening 48 formed therein is immersed in a solution containing 60 g / l of permanganic acid at 80 ° C. for 10 minutes, and the epoxy resin particles existing on the surface of the interlayer resin insulation layer 50 are immersed. Is dissolved and removed to form an interlayer resin insulating layer 50 including the inner wall of the via hole opening 48.
Was made rough (see FIG. 8C).

(12) Next, the substrate after the above treatment was immersed in a neutralizing solution (manufactured by Shipley) and washed with water. Further, by applying a palladium catalyst to the surface of the substrate which has been subjected to the surface roughening treatment (roughening depth: 3 μm), catalyst nuclei are attached to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48. Was.

(13) Next, the substrate is immersed in an aqueous solution of electroless copper plating having the following composition, and has a thickness of 0.6 to 3.
An electroless copper plating film 51 of 0 μm was formed (FIG. 9A).
reference). [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 40 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(14) A commercially available photosensitive dry film is affixed to the electroless copper plating film 51, and a mask is placed thereon.
Exposure was performed at mJ / cm ² , and a development treatment was performed with a 0.8% aqueous sodium carbonate solution to provide a plating resist 54 having a thickness of 30 μm (see FIG. 9B).

(15) Next, the substrate was washed with water at 50 ° C., degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions to give a thickness of 20 μm. Was formed (see FIG. 9C). [Electroplating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, Capparaside HL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

(16) After the plating resist 54 is peeled and removed with 5% NaOH, the electroless plating film 51 under the plating resist 54 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. A conductor circuit (including the via hole 60) 58 having a thickness of 18 μm and including the copper plating film 51 and the electrolytic copper plating film 56 was formed (see FIG. 10A).

(17) The roughening of the conductor circuit 34 of the first embodiment
By performing the same treatment as in (8), a roughened surface 62 was formed with an etching solution containing a cupric complex and an organic acid (see FIG. 10B).

(18) By repeating the above steps (9) to (17), an interlayer resin insulating layer 160, a conductor circuit 158 and a via hole 160 are formed above the interlayer resin insulating layer 50 on the upper surface to form a multilayer wiring. A plate was obtained (see FIG. 10 (C)).

(19) Next, the same solder resist composition as that of the first embodiment is applied to both surfaces of the multilayer wiring board at a thickness of 20 μm, and the coating is performed at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes. After performing the drying process, a 5 mm-thick photomask on which the pattern of the solder resist opening is drawn is brought into close contact with the solder resist layer, exposed to ultraviolet light of 1000 mJ / cm ² , developed with a DMTG solution, and developed with a 71 mg opening. 7
1D was formed. And further at 80 ° C. for 1 hour, 10
The solder resist layer is cured by performing heat treatment at 0 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to form a solder resist pattern layer 70 having an opening and a thickness of 20 μm. It was formed (FIG. 11A).
As the solder resist composition, a commercially available solder resist composition can be used.

(20) Next, as in the first embodiment, the opening 71
A nickel plating layer 72 having a thickness of 5 μm is formed on each of the U and 71D.
A gold plating layer 74 of μm was formed (FIG. 11B).

(20) Thereafter, a solder paste containing tin-lead is printed in the opening 71U of the solder resist layer 70 on the surface of the substrate on which the IC chip is to be mounted, and the solder resist layer 70 on the other surface is printed. After printing a solder paste containing tin-antimony in the opening 71D, the solder bump 76U was provided on the upper surface by performing reflow at 200 ° C. Then, the conductive connection pins 78 were provided on the lower surface, and a printed circuit board was manufactured (see FIG. 12).

Third Embodiment FIG. 13 shows a cross section of a multilayer printed wiring board according to a third embodiment. In the third embodiment,
The configuration is the same as that of the first embodiment. However, in the multilayer printed wiring board according to the third embodiment, the interlayer resin insulating layer 50 and the interlayer resin insulating layer 150 are composed of the upper adhesive 57 and the lower adhesive 55 having the following compositions, and are applied in a liquid state. After that, an opening is provided by exposure and development processing. A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
Parts by weight, epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) with an average particle size of 1.0 μm, 7.2 parts by weight, average particle size
After mixing 0.59 μm of 3.09 parts by weight,
30 parts by weight of MP was added, and the mixture was stirred and mixed with a bead mill to obtain. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), and 1.5 parts by weight of NMP are mixed with stirring. I got it.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
After mixing 14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, and the mixture was stirred and mixed with a bead mill. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), 1.5 parts by weight of NMP I got it.

[Comparative Example 1] The multilayer printed wiring board of Comparative Example 1 has the same configuration as that of the first embodiment. However, in the first embodiment, the plating is filled in the through holes 36, whereas in Comparative Example 1, a resin filler is filled.

First to Third Embodiments, Comparative Example 1, Comparative Example 2
Heat cycle test (-65 ° C / 3 minutes +130
FIG. 14 shows the results obtained by performing 1000 cycles at a cycle of ° C./3 minutes. In the first, second, and third embodiments, warpage and disconnection did not occur even after the heat cycle, but in Comparative Example 1, warpage occurred.
The amount of warpage was measured by placing the substrate on a flat base and measuring the end of the substrate with a measuring instrument.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, and 1D are manufacturing process diagrams of a multilayer printed wiring board according to a first embodiment of the present invention.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B and 3C show a first embodiment of the present invention.
It is a manufacturing process figure of the multilayer printed wiring board concerning an embodiment.

FIGS. 4A, 4B and 4C show a first embodiment of the present invention.
It is a manufacturing process figure of the multilayer printed wiring board concerning an embodiment.

FIGS. 5A and 5B are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 6A and 6B are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

8 (A), 8 (B), and 8 (C) show a second embodiment of the present invention.
It is a manufacturing process figure of the multilayer printed wiring board concerning an embodiment.

FIGS. 9A, 9B and 9C show a second embodiment of the present invention.
It is a manufacturing process figure of the multilayer printed wiring board concerning an embodiment.

FIGS. 10A, 10B, and 10C are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 11A and 11B are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 12 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 13 is a sectional view of a multilayer printed wiring board according to a third embodiment of the present invention.

FIG. 14 is a table showing the results of a heat cycle test.

[Explanation of symbols]

 Reference Signs List 22 metal layer 24 first electrolytic plating layer 26 electroless plating film 28 second electrolytic plating layer 30 resin substrate 32 through hole 34 conductive circuit 36 via hole 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist layer 76U, 76D Solder bump

Continued on the front page F term (reference) 4K024 AA09 AB03 AB04 AB08 AB15 AB17 BA12 BB11 BC10 DA10 FA05 GA16 4K044 AA06 AA16 AB02 AB08 BA06 BA08 BA21 BB04 BB05 BB10 BC14 CA13 CA15 CA18 5E317 AA07 AA11 AA24 BB02 CC33 CC12 CC12 CD05 CD15 CD25 CD27 CD32 GG09 GG14 5E346 AA02 AA12 AA15 AA26 AA32.

Claims (4)

[Claims] 1. A multilayer printed wiring board in which an interlayer resin insulating layer is built up on a core substrate provided with a through hole, wherein the through hole of the core substrate is formed by a first electrode formed by electrolytic plating.
A multilayer printed wiring board characterized by being filled with a metal layer, a metal film formed by electroless plating, sputtering or vapor deposition, and a second metal layer formed by electrolytic plating. 2. A method of manufacturing a multilayer printed wiring board, comprising at least the following steps (A) to (E): (A) forming a resin insulating layer having a metal layer on one surface; Forming a non-through hole to the metal layer with a laser; (B) filling the first metal layer by electrolytic plating by passing an electric current through the metal layer to the non-through hole of the resin insulating layer; C) a step of forming a metal film on the surface of the resin insulation layer opposite to the metal layer: (D) passing a current through the metal film to a non-through hole of the resin insulation layer and electrolytic plating to form a second metal layer And (E) etching the metal layer and the metal film of the resin insulating layer to form lands for through holes. 3. The method for manufacturing a multilayer printed wiring board according to claim 2, further comprising a step of forming a metal layer on said resin insulating layer by electroless plating, sputtering or vapor deposition. 4. The multilayer printed wiring board according to claim 2, wherein in the step of forming a metal film on the surface of the resin insulating layer opposite to the metal layer, electroless plating, sputtering or vapor deposition is used. Production method.