JP4760447B2 - Method for manufacturing thin-film electronic components - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film electronic component.

Conventionally, as a method of manufacturing a thin film electronic component in which a thin film electronic device such as a thin film capacitor is formed on a substrate, a thin film electronic device such as a thin film capacitor is formed on the surface of the substrate, and then a through hole for forming a conductive through hole is formed. A method including a step of drilling holes using a laser is known (for example, Patent Document 1). In the case of this method, in order to avoid destruction of the thin film electronic device due to excessive energy supply, generally, a laser is irradiated from the back surface of the substrate on which the thin film electronic device is formed to form a through hole in the substrate.
JP 2001-358248 A

  However, in the conventional method, the positional accuracy when irradiating the laser from the back surface is not always sufficient, and a part of the thin film electronic element is destroyed by the laser, which causes a short circuit in the thin film electronic component. there were.

  Then, an object of this invention is to provide the manufacturing method of the thin film electronic component which can obtain the thin film electronic component in which generation | occurrence | production of the short circuit was fully prevented.

Method of manufacturing a thin film electronic component of the present invention, a thin film electronic device forming step of forming on the first main surface side of the substrate having a thin film electronic device having an electrode layer of the first and second main surfaces, thin film electronic forming an opening in the element, and the alignment mark formation step of forming an alignment mark corresponding to the thin film electronic device on the second main surface, communicated with respect to the opening, a through hole penetrating through the base plate second A through-hole forming step formed by drilling from the main surface side, and a conductive through-hole forming step of forming a conductive through-hole by attaching a conductive material to the inner surface of the through-hole. Furthermore, the manufacturing method of this invention is equipped with the grinding | polishing process of grind | polishing a 2nd main surface before a through-hole formation process.

In the step of forming the opening in the thin film electronic element, an embodiment of forming an opening penetrating the thin film electronic element can be employed.

  According to the manufacturing method of the present invention, the back surface (second main surface) of the substrate is polished before the through hole forming step, and the alignment mark corresponding to the thin film electronic element is formed on the back surface of the substrate. When the through hole is formed, the position of the alignment mark can be clearly recognized optically. As a result, the through hole can be formed with high positional accuracy, and as a result, a thin film electronic component in which occurrence of a short circuit is sufficiently prevented can be obtained.

  The substrate is preferably a ceramic substrate because of its excellent heat resistance, insulation and mechanical strength. In the present invention, the ceramic substrate refers to a substrate obtained using a non-metallic inorganic material and undergoing processes such as molding and firing.

  In the polishing step, it is preferable to polish the second main surface until Rz is 500 nm or less. Thereby, the effect of preventing the occurrence of a short circuit becomes more remarkable.

  According to the manufacturing method of the present invention, it is possible to obtain a thin film electronic component in which occurrence of a short circuit is sufficiently prevented.

  Hereinafter, preferred embodiments of the present invention will be described in detail. However, the present invention is not limited to the following embodiments. In the description of the drawings, the same or corresponding elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a flowchart showing a method of manufacturing a thin film electronic component according to this embodiment. In the present embodiment, a thin film electronic element forming step S1 for forming a thin film electronic element having an electrode layer on the first main surface side of the substrate having the first and second main surfaces, and on the second main surface An alignment mark forming step S2 for forming an alignment mark corresponding to the thin film electronic element, a through hole forming step S3 for forming a through hole penetrating the substrate and the electrode layer by drilling from the second main surface side, A conductive through hole forming step S4 for forming a conductive through hole by attaching a conductive material to the inner surface. The embodiment further includes a polishing step S10 for polishing the second main surface of the substrate, and the polishing step S10 is performed at a stage before the thin film electronic element forming step S1. Polishing process S10 should just be before through-hole formation S3.

  2, 3, 4 and 5 are schematic cross-sectional views showing a method of manufacturing a thin film electronic component according to the present embodiment. In the present embodiment, a thin film electronic component including a substrate and a thin film capacitor as a thin film electronic element formed on the substrate is manufactured. First, a substrate 10 (thickness 0.35 mm) is prepared ((a) of FIG. 2), and the first main surface 10a and the second main surface 10b of the substrate 10 are polished by a precision polishing method using an abrasive. Then, the respective surfaces are smoothed ((b) in FIG. 2, polishing step). At this time, polishing is performed until the maximum height on each main surface (the sum of the height from the average line to the highest peak on the roughness curve and the depth from the lowest valley) to Rz (JIS B0601: 2001) is 500 nm or less. It is preferable to polish until Rz is 50 nm or less.

After polishing, the first main surface 10a, which is the surface on which the thin film capacitor is formed, is covered with an insulating film 12 (film thickness: 10 μm) ((c) in FIG. 2). The insulating film 12 is made of SiO ₂ and can be formed by a method such as plasma CVD or chemical solution deposition (CSD). The insulating film 12 is polished to a thickness of 2 to 3 μm by a chemical mechanical polishing method (CMP). The maximum height Rz of the surface of the insulating film 12 after polishing is about 10 nm.

Next, as shown in FIGS. 3D to 3G, the thin film capacitor 40 is formed on the first main surface 10a side of the substrate 10 (thin film electronic element forming step). In this step, first, an adhesion layer 14 (film thickness: 10 nm) made of TiO ₂ and a lower electrode layer 15 (film thickness: 100 nm) made of Pt are formed in this order on the insulating film 12 by these sputtering methods. Is patterned by photolithography so that an opening 14a is formed at a predetermined position ((d) of FIG. 3). The adhesion layer 14 is formed by RF sputtering using a TiO ₂ target. The lower electrode layer 15 is formed by depositing Pt by DC sputtering. For the adhesion layer 14 and the lower electrode layer 15, for example, a photoresist pattern is formed on the lower electrode layer 15, an opening 14 a is formed by dry milling using argon in this state, and an organic solvent and an oxygen ashing device are used. The photoresist pattern is removed for patterning. Note that heat treatment of the adhesion layer 14 before the formation of the lower electrode layer 15 suppresses generation of hillocks in the lower electrode layer 15.

  The opening 14 a is a groove having an annular plane shape, and extends from the upper surface of the lower electrode layer 15 to the upper surface of the insulating film 12 through the lower electrode layer 15 and the adhesion layer 14. Inside the opening 14a, the island part 20 separated from the main part 21 of the laminated structure including the adhesion layer 14 and the lower electrode layer 15 remains. The island part 20 has a circular planar shape.

  Subsequently, as shown in FIG. 3E, a dielectric layer 16 having a high dielectric constant is formed on the lower electrode layer 15. The dielectric layer 16 is made of BST (strontium barium titanate). The dielectric layer 16 fills the opening 14 a and contacts the insulating film 12. The dielectric layer 16 is patterned using a photolithography method so that a plurality of openings 16a and 16b are formed. The openings 16a and 16b have a circular planar shape. The opening 16 a is aligned with the island part 20. For this reason, the surface of the island part 20 is exposed from the opening 16a. The opening 16 b is formed on the main portion 21 of the adhesion layer 14 and the lower electrode layer 15. For this reason, a part of surface of the main part 21 is exposed from the opening 16b. The patterning by the photolithography method is performed by, for example, forming a photoresist pattern on the dielectric layer 16 and performing etching using buffered hydrofluoric acid (an aqueous solution of a mixture of hydrogen fluoride and ammonium fluoride) in that state. , 16b, and the photoresist pattern is removed using an organic solvent.

  Thereafter, as shown in FIG. 3F, an upper electrode layer 18 (thickness: 100 nm) covering the dielectric layer 16 is formed by depositing Pt by DC sputtering. The upper electrode layer 18 fills the openings 16 a and 16 b of the dielectric layer 16 and is in contact with the lower electrode layer 15. In the upper electrode layer 18, an opening 18 a is formed above the main portion 21 of the lower electrode layer 15 and the adhesion layer 14. The opening 18 a is a groove having an annular planar shape, and extends from the upper surface of the upper electrode layer 18 to the upper surface of the dielectric layer 16 through the upper electrode layer 18. Inside the opening 18a, an island portion 22 that is separated from the main portion 23 of the upper electrode layer 18 remains. The island part 22 has a circular planar shape.

  The main portion 23 of the upper electrode layer 18 fills the opening 16 a of the dielectric layer 16 and contacts the lower electrode layer 15 in the island portion 20. As a result, the island part 20 and the main part 23 function as one capacitor electrode layer 31. Further, the island portion 22 of the upper electrode layer 18 fills the opening 16 b of the dielectric layer 16 and contacts the lower electrode layer 15 in the main portion 21. As a result, the island part 22 and the main part 21 function as one capacitor electrode layer 32. The capacitor electrode layers 31 and 32 are electrically insulated from each other through the dielectric layer 16. Thus, the thin film capacitor 40 having a structure in which the dielectric layer 16 is sandwiched between the two capacitor electrode layers 31 and 32 in which the openings 50 and 51 are formed is formed on the first main surface 10a side of the substrate 10. Formed.

  In the thin film capacitor 40, an opening 50 penetrating the capacitor electrode layer 31 and an opening 51 penetrating the capacitor electrode layer 32 are formed ((g) of FIG. 3). The openings 50 and 51 extend from the upper surface of the upper electrode layer 18 to the upper surface of the insulating film 12. Openings 50 and 51 have a circular cross section. The openings 50 and 51 are formed in the same manner as the opening 14a and the like by using a photolithography method.

  Then, an alignment mark 70 (film thickness: 25 μm) made of Cr is formed on the second main surface 10b of the substrate 10 ((h) in FIG. 4, alignment mark forming step). The alignment mark 70 is formed as follows, for example. First, a Cr film is formed on the second main surface 10b by sputtering, and a photoresist layer covering the Cr film is formed. Then, the photoresist layer is exposed using a mask aligner that can expose the second main surface side at a position corresponding to the position of the thin film capacitor 40 on the first main surface 10a side. After the exposure, the photoresist is developed, and the exposed portion of the Cr film is removed by wet etching or the like and patterned. The alignment mark 70 is formed by removing the photoresist layer using an organic solvent after patterning. As will be understood by those skilled in the art, an alignment mark 70 reflecting the position of the thin film capacitor 40 is formed with extremely high accuracy by patterning through a step of exposing the photoresist layer while recognizing the position of the thin film capacitor 40. Is done.

  In the present embodiment, the alignment mark 70 is formed on the second main surface 10b of the first main surface 10a opposite to the portion where the thin film capacitor 40 is not formed. An alignment mark may be formed on the opposite side of the portion where the thin film capacitor 40 is formed, but there are many design restrictions such as the need to arrange so as to avoid a conductive through hole. From the viewpoint of improving the yield, etc., it is preferable to form the alignment mark 70 at a position as in this embodiment.

  Next, as shown in FIG. 4I, passivation films 24 and 25 made of polyimide are formed on the surface of the thin film capacitor 40 opposite to the substrate 10 and on the second main surface 10b. The passivation film 24 is patterned so as to cover the upper electrode layer 18 and to form an opening 24 a aligned with the openings 50 and 51. The passivation film 25 is patterned so as to cover the second main surface 10 b and to form an opening 25 a disposed immediately below the openings 50 and 51. Specifically, for example, positive photosensitive polyimide is applied to each surface, exposed using a mask aligner, developed with an alkaline solution, and then heat treated in nitrogen at 350 ° C. for 1 hour. It is formed by curing photosensitive polyimide.

  Subsequently, as shown in FIG. 4J, a through hole 52 that penetrates the substrate 10, the insulating film 12, and the capacitor electrode layer 31, and a through hole that penetrates the substrate 10, the insulating film 12, and the capacitor electrode layer 32. 53 is formed (through hole forming step). The through hole 52 is formed to communicate with the opening 50 and has a substantially circular cross section. In the present embodiment, the through hole 52 has a substantially equal diameter up to the opening 50 portion, but may have a smaller diameter at the opening 50 portion. Similarly, the through hole 53 is formed so as to communicate with the opening 51 and has a substantially circular cross section. In the present embodiment, the through hole 53 has substantially the same diameter up to the opening 51.

  The through holes 52 and 53 are drilled from the second major surface 10b while aligning using the alignment mark 70 using a method such as laser drilling or micro drilling. Since the alignment mark 70 is formed by accurately reflecting the position of the thin film capacitor 40 as described above, by positioning the perforation based on the position of the alignment mark 70, the openings 50 and 51 in the thin film capacitor 40 are positioned. It is possible to form a through hole that communicates. And since the 2nd main surface 10b is smooth | blunted by grinding | polishing as mentioned above, the position of the alignment mark 70 is recognized optically clearly, and perforation with a high positional accuracy is attained by this.

  For example, when using laser drilling, the laser beam is irradiated to the second main surface 10b of the substrate 10 through the opening 25a of the passivation film 25, and the hole is dug. These holes are formed substantially perpendicular to the second main surface 10 b of the substrate 10, penetrate the insulating film 12, and communicate with the openings 50 and 51. Thus, the through holes 52 and 53 are formed.

The following are typical laser drilling equipment and conditions.
・ Laser model: UV LASER μ VIA DRILL model 5320 manufactured by ESI
・ Light source: UV-YAG
・ Processing method: Spiral method (irradiates the laser spirally from the center of the opening to the outermost periphery)
・ Laser output: 2.8W
・ Number of shots: 100 shots

  The reason why the second main surface 10b is irradiated with laser light is to prevent damage to the thin film capacitor 40 formed on the first main surface 10a. In general, in laser drilling, the energy of laser light is attenuated by the substrate, and therefore the energy of laser light tends to be higher on the incident light side than on the outgoing light side. For this reason, when laser light is irradiated to the 1st main surface 10a, possibility that damage to the thin film capacitor 40 will become high.

  Next, after the residue deposited in the through holes 52 and 53 at the time of laser irradiation is removed by ultrasonic treatment in an organic solvent, the through holes 52 and 53 are filled with a conductive material, Conductive through holes 54 and 55 extending from the other side to the other side are formed ((k) in FIG. 5, conductive through hole forming step). Examples of the conductive material include silver and copper. The conductive material may completely fill the through holes 52 and 53, or may only adhere to the inner surfaces of the through holes 52 and 53. The conductive through holes 54 and 55 are in contact with the first and second capacitor electrode layers 31 and 32, respectively, and have electrical continuity between these electrode layers.

  Subsequently, a Ti layer 26 (film thickness: 5 nm) and a Cu layer 27 (film thickness: 200 nm) are sequentially formed on the passivation films 24 and 25 as plating seed layers by RF sputtering. Then, a photoresist pattern layer 28 is formed so that a portion of the Cu layer 27 to be plated is exposed ((l) in FIG. 5).

  A Cu plating layer 41 and a SnPb plating layer 42 are formed in this order by electroplating using the photoresist pattern layer 28 as a mask. The SnPb plating layer 42 is a layer that functions as a bump for mounting, and the height of the SnPb plating layer 42 on the first main surface 10a side is larger than the height of the SnPb plating layer 42 on the second main surface 10b side. It has become. After plating, the photoresist pattern layer 28 is removed with an organic solvent, and the Ti layer 26 and the Cu layer 27 are removed by dry milling using argon ((m) in FIG. 5).

  As described above, the thin film electronic component 100 having the thin film capacitor 40 is obtained. The thin film electronic component 100 is used by removing the substrate 10 where the alignment mark 70 is formed.

  Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples.

A plurality of thin film capacitors were actually fabricated by the same method as in the above embodiment. At this time, an alumina substrate that was polished under conditions such that Rz after polishing of the second main surface 10b had a value as shown in Table 1 was used. The composition of the dielectric layer was Ba _0.7 Sr _0.3 TiO ₃ . Table 1 shows an average value of deviation values (position deviation) from a predetermined position of the laser emission hole position and a ratio (short ratio) of a thin film capacitor in which a short circuit occurs.

  As shown in Table 1, in the comparative example in which the polishing was not performed, the alignment marks were not well-viewed, so the positional deviation was large, the short-circuit rate was 100%, and a short circuit occurred in all the manufactured thin film capacitors. On the other hand, in the example using the polished substrate, the positional deviation decreased, and a decrease in the short-circuit rate was recognized accordingly. In particular, in Examples 1 to 6 using the substrate in which the second main surface was polished until Rz was 500 nm or less, the effect of preventing a short circuit was remarkably exhibited.

It is a flowchart which shows the manufacturing method of the thin film capacitor which concerns on embodiment. It is a schematic sectional drawing which shows the manufacturing method of the thin film capacitor which concerns on embodiment. It is a schematic sectional drawing which shows the manufacturing method of the thin film capacitor which concerns on embodiment. It is a schematic sectional drawing which shows the manufacturing method of the thin film capacitor which concerns on embodiment. It is a schematic sectional drawing which shows the manufacturing method of the thin film capacitor which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 10a ... 1st main surface, 10b ... 2nd main surface, 12 ... Insulating film, 14 ... Lower electrode layer, 16 ... Dielectric layer, 18 ... Upper electrode layer, 20 ... Island part, 31, 32 ... capacitor electrode layer, 40 ... thin film capacitor, 50, 51 ... opening, 52, 53 ... through hole, 54, 55 ... conduction through hole, 70 ... alignment mark, 100 ... thin film electronic component.

Claims (4)

Forming a thin film electronic device having an electrode layer on the first main surface side of the substrate having the first and second main surfaces;
Forming an opening in the thin film electronic device;
An alignment mark forming step of forming an alignment mark corresponding to the thin film electronic element on the second main surface side;
Communicated with respect to the opening, a through hole forming step of forming a through hole penetrating through the base plate by drilling from the second main surface side,
A conductive through hole forming step of forming a conductive through hole by attaching a conductive material to the inner surface of the through hole, and
The manufacturing method of a thin film electronic component provided with the grinding | polishing process of grind | polishing a said 2nd main surface before the said through-hole formation process.   The method for manufacturing a thin film electronic component according to claim 1, wherein in the step of forming an opening in the thin film electronic element, an opening penetrating the thin film electronic element is formed.   The method of manufacturing a thin film electronic component according to claim 1, wherein the substrate is a ceramic substrate.   The method of manufacturing a thin film electronic component according to any one of claims 1 to 3, wherein in the polishing step, the second main surface is polished until Rz is 500 nm or less.

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