JP4196351B2 - Film capacitor manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a film capacitor, and more particularly to a method for manufacturing a film capacitor characterized by a configuration for reducing the inductance of a decoupling capacitor for an electronic device that transmits a high-frequency signal such as a high-end server. Is.

  In recent years, macro LSIs and other digital LSIs have become faster and consume less power, and there has been a need to improve the performance of decoupling capacitors to suppress rapid fluctuations in LSI load impedance and fluctuations in power supply voltage. In addition, there is a demand for stable LSI operation in the high-frequency region of the GHz band of high-speed operation digital LSIs.

  In order to prevent such malfunction of the LSI due to power supply voltage fluctuations and high frequency noise, it is necessary to mount a decoupling capacitor, that is, a bypass capacitor as close as possible to the LSI chip.

See FIG.
FIG. 9 is a schematic configuration diagram of an electronic circuit device on which a conventional decoupling capacitor and an LSI are mounted. The LSI chip 71 is mounted on a circuit wiring board 74 provided with a multilayer wiring layer, and is located in the vicinity of the LSI chip 71. A chip capacitor 73 to be a decoupling capacitor is mounted, and one terminal of the chip capacitor 73 is connected to the ground line 76 and the other terminal is connected to the power terminal 72 of the LSI chip 71. Connect to.

  However, in the case of the method of mounting a decoupling capacitor on the surface of the circuit wiring board 74 as shown in FIG. 9, the wiring between the chip capacitor 73 and the LSI chip 71 is unavoidable. Due to the parasitic inductance associated with the wiring layer, there is a limit to the effect of suppressing fluctuations in power supply voltage and the effect of absorbing high-frequency ripple for high-speed operation LSIs.

  Therefore, in order to suppress fluctuations in the power supply voltage, reduction of equivalent series resistance (ESR) and equivalent series inductance (ESL) is required for the capacitor. In particular, an increase in inductance due to wiring routing is a major cause of deterioration of the high-frequency characteristics of the decoupling capacitor, and therefore reduction of equivalent series inductance (ESL) becomes more important.

  Therefore, a circuit board with a built-in capacitor, a ceramic circuit board with a dielectric film formed on the surface (see, for example, Patent Document 1), etc. have been proposed, whereby a decoupling capacitor is arranged immediately below the LSI chip, It is intended to minimize the wiring route from the LSI power supply and the ground terminal to the capacitor.

  Further, since it has been proposed to use an interposer type capacitor substrate separately from the circuit substrate to minimize the connection distance between the LSI chip and the decoupling capacitor, an example will be described with reference to FIG.

See FIG.
FIG. 10 is a schematic configuration diagram of an electronic circuit device in which an LSI is mounted via an interposer type capacitor substrate. A signal terminal of the LSI chip 81 is provided on the circuit wiring board 83 via a through via provided on the capacitor board 82. Connected to the signal line 86.
On the other hand, the power supply terminal and the ground terminal of the LSI chip 81 are respectively connected to the power supply line 84 and the ground line 85 via vias connected to one of a pair of solid electrode layers constituting a decoupling capacitor provided on the capacitor substrate 82. Is done.
Japanese Patent Laid-Open No. 4-211191

However, in the case of the above-mentioned capacitor built-in substrate, since a high temperature of about 700 ° C. is required for firing the high dielectric material, there is a problem that the base material constituting the circuit substrate and the manufacturing process thereof are limited.
In addition, as the number of capacitor layers increases, there is a problem that the manufacturing yield decreases and the manufacturing cost increases.

On the other hand, in the case of an interposer type capacitor substrate, there are some terminals of an LSI chip that exceed several thousand, such as a high-end server, and in order to support such an LSI chip, a small diameter and a small pitch. Although an interposer substrate is required, there is a problem that manufacturing becomes difficult as the via diameter becomes smaller and the pitch becomes smaller.
For example, when the capacitor substrate is manufactured using the green sheet method, the pitch of through vias is limited to 100 to 200 μm.

  A thin film capacitor is desirable for lowering the impedance of the capacitor substrate, that is, lowering ESL. However, leakage current due to pinholes and the like becomes a problem as the layer becomes thinner. Although necessary, there is a problem that it becomes difficult to manufacture a low-defect through-via substrate with the progress of thinning.

  Accordingly, an object of the present invention is to provide a low-inductance film-like capacitor having through-vias having a minute diameter and a minute pitch.

Here, means for solving the problems in the present invention will be described with reference to FIG.
See Figure 1
(1) The present invention relates to a method of manufacturing a film capacitor having electrodes provided on the front and back surfaces and vias electrically connected to the electrodes, on the substrate 1, the first resin insulating layer 8, the power wiring Also, a solid electrode layer 2 provided with holes through which the vias 5 and 6 necessary for the conduction of the signal wiring are provided, a solid material provided with holes through which the vias 6 and 7 necessary for the conduction of the dielectric material layer 3, the ground wiring and the signal wiring are passed. After forming at least one cycle of the film capacitor composed of the electrode layer 4 and the second resin insulation layer, the first resin insulation layer 8 and the substrate 1 are irradiated by irradiating the laser beam 9 from the back surface of the substrate 1. A method for producing a film capacitor, wherein the interface side is evaporated and peeled off from the substrate 1.

  Thus, by using a film-like capacitor without using the green sheet method as an interposer type capacitor, the semiconductor manufacturing technology can be diverted, thereby having a thin dielectric material layer 3, In addition, it is possible to realize a low-inductance film-like capacitor having through vias 6 having a minute diameter and a minute pitch.

  In particular, when manufacturing a film capacitor, a thin film capacitor is formed with high precision and reproducibility using semiconductor manufacturing technology by using the substrate 1 having a smooth surface and the first resin insulating layer 8 provided. In addition, by peeling from the substrate 1 after formation, the capacitor substrate is not thickened.

  In addition, by using a dry process in which the interface side of the resin insulating layer 8 with the substrate 1 is evaporated by laser ablation and the substrate 1 is peeled off, the peeling process of the substrate 1 is simplified, and like a wet process, There is no possibility that the dielectric material layer 3, the electrode pad, and the like are attacked by the chemical solution.

  Moreover, by applying a high dielectric film having a perovskite structure used in semiconductor ferroelectric memory or the like as the dielectric material layer 3, a thin film having a high dielectric constant can be formed free of pinholes. Thus, a large capacity can be realized even with only one dielectric material film.

(2) Further, in the present invention, after removing the first resin insulating layer 8 carbonized in the step of forming the dielectric material layer 3 after the substrate 1 is peeled off in the above (1), a new resin insulating layer is formed. It is provided.
In this way, the first resin insulating layer 8 that is partially carbonized and unsuitable as a protective insulating layer is removed in the heating step when forming the dielectric material layer 3, so that the capacitor substrate Reliability can be improved.

(3) Further, in the method for manufacturing a film capacitor according to the present invention, after the Cr adhesion layer is selectively formed only on the peripheral portion of the glass substrate, the Cr adhesion layer is selectively formed on the glass substrate. Necessary for the conduction of the first resin insulation layer made of polyimide, the solid electrode layer with holes for passing the vias necessary for the conduction of the power supply wiring and signal wiring, the dielectric material layer having the perovskite structure, the ground wiring and the signal wiring A film-like capacitor is formed by forming a solid electrode layer having a hole through which a simple via passes and a second resin insulating layer made of polyimide, and then irradiating a laser beam from the back surface of the glass substrate. Evaporate the inner part of the Cr adhesion layer in FIG. 1, remove the outer part of the evaporated part, and then apply a film capacitor to the remaining part. Characterized by peeling from the glass substrate.

  According to the present invention, a solid substrate having a smooth surface is used, and a film capacitor for decoupling is produced using a semiconductor manufacturing technique, so that a low-defect film capacitor having a high-density through via is obtained. Therefore, the equivalent series inductance (ESL) can be reduced, so that power supply voltage fluctuations and high-frequency noise in the high-frequency region associated with high-speed digital LSIs can be effectively reduced. It greatly contributes to improving the reliability of LSI operation or high-density mounting.

  The present invention is necessary for conduction of a solid electrode layer, a dielectric material layer, a ground wiring, and a signal wiring provided with a hole through which a first resin insulating layer, a via necessary for the conduction of the power supply wiring and the signal wiring are passed on the substrate. After forming at least one period of a solid electrode layer with holes for passing through holes and a film-like capacitor made of the second resin insulation layer, the substrate side interface of the first resin insulation layer is evaporated by laser light irradiation. And peeled from the substrate.

Here, the first embodiment of the present invention will be described with reference to FIGS. 2 to 6. First, the manufacturing process of the first embodiment of the present invention will be described with reference to FIGS.
In addition, each figure is principal part sectional drawing of a film-like capacitor | condenser.
See Figure 2
First, a polyimide resin is applied on the sapphire substrate 11, cured by heating, and further heated to 700 ° C. to form a carbonized polyimide layer 12 having a thickness of, for example, 10 μm. The lower solid electrode layer 13 is formed by sequentially depositing a Ti film having a thickness of, for example, 0.1 μm and a Pt film having a thickness of 0.2 μm.

Next, a resist is coated on the entire surface, exposed and developed to form a resist pattern 14 having a recess for forming a buried insulating layer for insulating and isolating the power supply via, and then formed on the entire surface by sputtering. A SiO ₂ film 15 having a thickness of, for example, 0.5 μm is deposited, and the SiO ₂ film deposited in the recess is used as the buried insulating layer 16.

Next, the resist pattern 14 is removed, and the SiO ₂ film 15 deposited thereon is lifted off at the same time. Then, a resist is applied to the entire surface, exposed and developed again, so that a signal through via and a ground via are formed. After forming a resist pattern 17 having a recess 18 for forming a buried insulating layer that insulates the substrate, the exposed portion of the lower solid electrode layer 12 is etched away using the resist pattern 17 as a mask, thereby being surrounded by the recess 18. A part of the signal through via and the ground via are formed.

Next, again, a buried insulating layer 20 is formed by depositing an SiO ₂ film 19 having a thickness of, for example, 0.8 μm on the entire surface by sputtering, and insulating and separating the through via and the via from the SiO ₂ film deposited in the recess 18. And

See Figure 3
Next, the resist pattern 17 is removed, and the SiO ₂ film 19 deposited thereon is simultaneously lifted off to leave the buried insulating layer 20.

Next, a high dielectric constant film 21 made of (Ba, Sr) TiO ₃ , that is, BST is formed on the entire surface by using a sol-gel method.
As a manufacturing process of the high dielectric constant film 21, a mixed solution in which each alkoxide of Sr, Ba, Ti is mixed is applied by spin coating, for example, at 2000 rpm for 30 seconds, and then dried at, for example, 120 ° C. for 10 minutes. Then, pre-baking is performed at 300 ° C. for 10 minutes, and this process is repeated, for example, four times, and then, for example, main baking is performed for 60 minutes in a high-temperature oxygen atmosphere at 700 ° C. Is crystallized as a perovskite oxide, for example, to form a BST film having a total thickness of 400 nm.
Incidentally, the relative dielectric constant of the BST film thus formed was 500, and the loss was 2% or less.

Next, the high dielectric film 21 is etched away until the tops of the buried insulating layer 16 and the buried insulating layer 20 are exposed by etching back using buffered hydrofluoric acid of NH ₄ F: HF = 6: 1. To do.

Next, a resist is coated on the entire surface, exposed and developed to form a resist pattern 22 having openings corresponding to the inner ends of the buried insulating layer 16 and the buried insulating layer 20, that is, openings corresponding to through vias and vias. Then, the high dielectric film 21 exposed using the resist pattern 22 as a mask is etched using NH ₄ F: HF = 6: 1 buffered hydrofluoric acid to form a recess 23 that becomes a via hole.

See Figure 4
Next, after removing the resist pattern 22, the upper solid electrode layer that fills the recess 23 by sequentially depositing, for example, a 0.1 μm thick Ti film and a 0.2 μm thick Pt film by sputtering again. 24 is formed.

  Next, a resist pattern 25 having an opening coinciding with the top of the buried insulating layer 16 for forming the buried insulating layer 16 and the signal through via is again provided by applying a resist to the entire surface, exposing and developing. Then, the upper solid electrode layer 24 exposed using the resist pattern 25 as a mask is selectively removed by etching to form a recess 26.

  Next, after removing the resist pattern 25, a polyimide resin is applied to the entire surface, and is cured by heating to form a polyimide layer 27 having a thickness of, for example, 10 μm. By developing, a resist pattern 28 having an opening corresponding to each through via and each via is provided, and the exposed polyimide layer 27 is selectively removed by etching using the resist pattern 28 as a mask.

  Next, after removing the resist pattern 28, a sputtering method is used again to successively deposit, for example, a 0.05 μm Cr film, a 2 μm Ni film, and a 0.2 μm Au film, The electrode pads 30 and 32 connected to the through vias are formed by the photo-etching process, and the electrode pads 29 and 31 connected to the vias are formed.

See Figure 5
Next, by irradiating laser light 33 from the back surface of the sapphire substrate 11 using an excimer laser, the adhesive force with the sapphire substrate 11 is reduced by laser ablation that evaporates the polyimide layer 12 on the interface side of the sapphire substrate 11.

  Next, the film capacitor laminate is peeled from the sapphire substrate 11.

Next, the polyimide layer 12 in contact with the sapphire substrate 11 is selectively removed using a plasma etching method.
That is, the polyimide layer 12 is exposed to a high temperature state of 700 ° C. for about 1 hour and partially carbonized, so that it is not suitable as a protective insulating layer.

  Next, the electrode pads 36 and 38 connected to the through vias are formed through the polyimide layer 34, and the electrode pads 35 and 37 connected to the vias are formed, thereby completing the basic configuration of the film capacitor.

See FIG.
FIG. 6 is a schematic cross-sectional view of a mounting structure using the film capacitor formed by the above process. The ground terminal 41 of the LSI chip 40 includes the electrode pad 35 and the electrode pad 29 provided on the film capacitor 39. The power supply terminal 42 of the LSI chip 40 is connected to the power supply line 46 provided on the mounting circuit board 45 via the electrode pad 37 and the electrode pad 31, while being connected to the ground line 47 provided on the mounting circuit board 45. It will act as a decoupling capacitor.

  The signal terminals 43 and 44 provided on the LSI chip 40 are connected to the signal lines 48 and 49 via the electrode pad 36 and the electrode pad 30 connected to the insulated through vias, or the electrode pad 38 and the electrode pad 32, respectively. Is done.

  Thus, in Example 1 of the present invention, a solid substrate with a smooth surface and a polyimide layer is used, and a film capacitor is formed using a semiconductor manufacturing process. It becomes possible to manufacture a film capacitor having a low defect with high accuracy and good reproducibility.

Next, Example 2 of the present invention will be described with reference to FIG. 7, but since the film-like capacitor multilayer structure itself is exactly the same as Example 1 described above, description of similar parts is omitted.
See FIG.
First, after selectively providing the Cr adhesion layer 52 only on the periphery of the glass substrate 51, a polyimide resin is applied to the entire surface, and the polyimide layer 53 having a thickness of 10 μm is formed by heating and curing. Thereafter, The electrode pads 29 to 32 are formed in the same process as in the first embodiment.
In this case, the Cr adhesion layer 52 may be selectively deposited using a resist mask, or the central portion may be selectively etched away after a Cr film is deposited on the entire surface. It is.

Next, the laser light 54 is irradiated only from the back surface of the glass substrate 51 or the film capacitor side to the vicinity of the inner end of the Cr adhesion layer 52 using a YAG laser or a CO ₂ laser, so that the film capacitor multilayer structure of the irradiated portion is obtained. It is made to evaporate so that the outer peripheral part of the thick broken line is only the resin layer.

Next, the film capacitor laminated structure is peeled off from the glass substrate 51.
In this case, since the adhesive force between the glass substrate 51 and the polyimide layer 53 is weak, it can be easily separated by performing laser scribing so that the polyimide layer 53 in close contact with the Cr adhesive layer 52 is cut off. Become.

  Thereafter, after the polyimide layer 53 is removed, the film capacitor having the same structure as that of the first embodiment can be manufactured by performing the subsequent process of FIG.

  In this way, by using an adhesion improving layer such as Cr, it can be applied when a combination having poor adhesion is used as an insulating layer such as a substrate and a polyimide layer. The range of choices can be expanded.

Next, Embodiment 3 of the present invention will be described with reference to FIG.
See FIG.
First, after a polyimide layer 12 having a thickness of 10 μm is formed on the sapphire substrate 11, for example, a 0.05 μm Cr film, a 2 μm Ni film, and a 0.2 μm Au film are formed on the entire surface by sputtering. A film is sequentially deposited, and then electrode pads 36 and 38 for connection to signal through vias by an ordinary photoetching process, electrode pad 37 for connection to power supply vias, and connection to ground vias. An electrode pad 35 is formed.

  Next, again, a polyimide resin is applied to the entire surface and cured by heating to form a polyimide layer 65 having a thickness of, for example, 10 μm. Then, via holes reaching the electrode pads 35 to 38 are again formed by a normal photoetching process. Then, a lower solid electrode layer 13 for filling a via hole is formed on the entire surface by sequentially depositing a Ti film having a thickness of, for example, 0.1 μm and a Pt film having a thickness of 0.2 μm using a sputtering method.

Thereafter, a film-like capacitor multilayer structure is formed by performing the same processes as in FIGS. 2 to 4. In this case, a high dielectric made of a BST film formed by a sol-gel method as a dielectric film is used. A SiN film 66 is formed by sputtering instead of the film.
In this way, after forming the film-like capacitor multilayer structure, the laser beam 33 is irradiated from the back surface of the sapphire substrate 11 using an excimer laser, and the adhesion between the sapphire substrate 11 and the polyimide layer 12 is lowered.

  Next, the film capacitor laminated structure is peeled from the sapphire substrate 11 together with the polyimide layer 12.

  Next, the polyimide capacitor 12 is chemically removed by etching to obtain a film capacitor.

  In the third embodiment of the present invention, since all film forming steps and patterning steps are performed on the hard sapphire substrate 11, the pattern accuracy is improved.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made.
For example, in the first and second embodiments of the present invention, the BST film is used as the high dielectric film. However, the present invention is not limited to the BST film, and Bi such as an SBT (SrBi ₂ Ta ₂ O ₉ ) film is used. Other high dielectric constant films such as a system layered perovskite oxide or PZT film may be used.

  In addition, the manufacturing method of such a high dielectric film is not limited to the sol-gel method, and a sputtering method, a MOVPE method, or a MOD (Metal Organic Decomposition) method may be used.

For example, when a high dielectric film is formed by a sputtering method, a (Pb, Zr) TiO ₃ target is used, for example, Ar: O ₂ = 36 sccm: 4 sccm is passed, and the degree of vacuum in the film formation chamber is 0.5 Pa. In this state, a power of 120 W is applied and a PZT film having a thickness of 200 nm may be formed over 10 hours.

  In each of the above embodiments, polyimide resin is used as the base layer of the film capacitor. However, it is not limited to polyimide resin, and other organic insulating layers such as epoxy resin and fluorinated polyimide resin are used. It is good.

  In Example 3 described above, since the polyimide layer 65 constituting a part of the base layer of the film capacitor is formed before the dielectric film is formed, the dielectric film can be formed at a low temperature. Although a SiN film is used, it is not necessarily limited to a SiN film. In this case, a film that is exposed to a high temperature atmosphere and deteriorates to some extent or a high dielectric film may be used. It is desirable to use an insulating film with higher heat resistance instead of polyimide resin.

  In each of the above embodiments, the counter electrode constituting the film-like capacitor is constituted by a two-layer structure of an upper solid electrode layer and a lower solid electrode layer to form a single-layer capacitor. It is also possible to provide a capacitor having a multilayer structure by providing more than one layer.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 4 of Example 1 of this invention. It is explanatory drawing of the mounting structure using the film-shaped capacitor of Example 1 of this invention. It is explanatory drawing of the manufacturing process of Example 2 of this invention. It is explanatory drawing of the manufacturing process of Example 3 of this invention. It is explanatory drawing of the mounting structure of the conventional decoupling capacitor. It is explanatory drawing of the mounting structure using the conventional interposer type capacitor substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Solid electrode layer 3 Dielectric material layer 4 Solid electrode layer 5 Via 6 Via 7 Via 8 Resin insulating layer 9 Laser beam 11 Sapphire substrate 12 Polyimide layer 13 Lower solid electrode layer 14 Resist pattern 15 SiO ₂ film 16 Embedded insulation Layer 17 resist pattern 18 recess 19 SiO ₂ film 20 buried insulating layer 21 high dielectric film 22 resist pattern 23 recess 24 upper solid electrode layer 25 resist pattern 26 recess 27 polyimide layer 28 resist pattern 29 electrode pad 30 electrode pad 31 electrode pad 32 Electrode Pad 33 Laser Light 34 Polyimide Layer 35 Electrode Pad 36 Electrode Pad 37 Electrode Pad 38 Electrode Pad 39 Film Capacitor 40 LSI Chip 41 Ground Terminal 42 Power Terminal 43 Signal Terminal 44 Signal Terminal 45 Mounting Circuit Board 6 Power line 47 Ground line 48 Signal line 49 Signal line 51 Glass substrate 52 Cr adhesion layer 53 Polyimide layer 54 Laser light 65 Polyimide layer 66 SiN film 71 LSI chip 72 Power supply terminal 73 Chip capacitor 74 Circuit wiring board 75 Power supply line 76 Ground line 81 LSI chip 82 Capacitor board 83 Circuit wiring board 84 Power supply line 85 Ground line 86 Signal line

Claims (3)

In the method of manufacturing a film capacitor having electrodes provided on the front and back surfaces and vias electrically connected to the electrodes, vias necessary for conduction of the first resin insulating layer, the power supply wiring, and the signal wiring on the substrate A film electrode capacitor comprising a solid electrode layer for providing a hole for passing through, a solid electrode layer for providing a hole for passing a via necessary for conduction of the dielectric material layer, ground wiring and signal wiring, and a second resin insulating layer After forming at least one cycle, the interface side of the first resin insulation layer with the substrate is evaporated by irradiating a laser beam from the back surface of the substrate, and the film-like capacitor is peeled off from the substrate. Production method. 2. The film capacitor according to claim 1, wherein after the substrate is peeled , the first resin insulating layer carbonized in the dielectric material layer forming step is removed, and then a new resin insulating layer is provided. Manufacturing method. After selectively forming the Cr adhesion layer only on the periphery of the glass substrate, the first resin insulation layer made of polyimide, the power supply wiring, and the signal wiring are formed on the glass substrate on which the Cr adhesion layer is selectively formed. Solid electrode layer provided with a hole for passing a via necessary for conduction, a dielectric material layer having a perovskite structure, a solid electrode layer provided with a hole for passing a via necessary for conduction of ground wiring and signal wiring, and polyimide Forming a film capacitor composed of the second resin insulation layer, and then irradiating a laser beam from the back surface of the glass substrate to evaporate the inner part of the Cr adhesion layer in the film capacitor, The outside of the evaporated part is removed, and then the film capacitor is peeled off from the glass substrate for the remaining part. Method for producing a film-shaped capacitor to.

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