JP2006041512A - Method of manufacturing integrated-circuit chip for multi-chip package, and wafer and chip formed by the method thereof - Google Patents

Method of manufacturing integrated-circuit chip for multi-chip package, and wafer and chip formed by the method thereof Download PDF

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Publication number
JP2006041512A
JP2006041512A JP2005204665A JP2005204665A JP2006041512A JP 2006041512 A JP2006041512 A JP 2006041512A JP 2005204665 A JP2005204665 A JP 2005204665A JP 2005204665 A JP2005204665 A JP 2005204665A JP 2006041512 A JP2006041512 A JP 2006041512A
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Japan
Prior art keywords
hole
connection electrode
chip
integrated circuit
semiconductor
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JP2005204665A
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Japanese (ja)
Inventor
In-Young Lee
仁榮 李
Sung-Min Sim
成▲ミン▼ 沈
Togen Cho
東鉉 張
Hyun-Soo Chung
顯秀 鄭
Young-Hee Song
永僖 宋
Myeong-Soon Park
明洵 朴
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020040058689A external-priority patent/KR100575591B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2006041512A publication Critical patent/JP2006041512A/en
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  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing integrated-circuit chips for a multi-chip package which can simplify the manufacturing process and reduce the manufacturing cost and process time. <P>SOLUTION: The integrated-circuit chip comprises a semiconductor substrate, having upper and lower surfaces which extend to outer edges and having at least one first contact pad on the upper surface contiguous to the outer edge, an electrically insulating region which is formed on the outer edge side of the semiconductor substrate and in which a through hole is formed, and a contact electrode that fills the through hole and is electrically connected to the first contact pad. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、集積回路チップの製造方法に関し、さらに詳細にはマルチチップパッケージ用集積回路チップの製造方法に関するものである。   The present invention relates to a method for manufacturing an integrated circuit chip, and more particularly to a method for manufacturing an integrated circuit chip for a multichip package.

一般に、マルチチップパッケージ技術には、水平に配設された集積回路チップ、一つの直接回路パッケージやモジュールに垂直に積層された集積回路チップ等がある。こうしたマルチチップパッケージ技術は、携帯電話等のような小型製品の集積回路の集積度を高めることができる。   In general, the multi-chip package technology includes an integrated circuit chip disposed horizontally, an integrated circuit chip stacked vertically on one direct circuit package or module, and the like. Such multi-chip package technology can increase the degree of integration of integrated circuits of small products such as mobile phones.

集積回路チップの貫通孔（penetrant aperture）内に配線プラグを有するマルチチップパッケージ技術として、従来技術文献が知られている。上記配線プラグは、一つの集積回路パッケージに垂直に積層された複数個のチップを電気的に接続するものである。また、貫通孔（through hole）を有するマルチチップパッケージ技術の他の例として、別の従来技術文献が挙げられる（例えば、特許文献１及び２参照）。
米国特許第６、４２９、０９６号明細書 米国特許第６、５６６、２３２号明細書 Prior art documents are known as a multichip package technology having a wiring plug in a penetrant aperture of an integrated circuit chip. The wiring plug is for electrically connecting a plurality of chips stacked vertically on one integrated circuit package. Another example of a multi-chip package technology having a through hole is another prior art document (see, for example, Patent Documents 1 and 2).
US Pat. No. 6,429,096 US Pat. No. 6,566,232

一方、印刷回路基板等の基板上に集積回路チップの集積度を高めるための他のパッケージ技術として、チップスケールパッケージ技術が知られている。チップスケールパッケージ技術は、小型の形態因子を有して集積回路チップとほぼ同じ大きさのパッケージを用いて集積度を向上させるものである。チップスケールパッケージの条件のうち、共通に求められるのは、パッケージの大きさが半導体チップの大きさより約１．２倍以内でなければならない点である。チップスケールパッケージ技術として、また別の従来技術文献に知られるが、ここに、チップスケールパッケージの一形態であるウエハレベルチップスケールパッケージが開示されている。ウエハレベルチップスケールパッケージは、集積回路チップが印刷回路基板に向けて実装されることにより、下部充填材（underfill）を使用せずソルダボールを介してチップパッドと基板パッドとを接合させる。また、電気的接続のために、ボンディングワイヤやインターポーザーを用いないことが、その他のボールグリッドアレイ技術と異なる。このようなウエハレベルパッケージは、集積回路と印刷回路基板との間のインダクタンスを最小化できるとともに、パッケージの大きさをが減少し、かつ製造の手間を省くため熱伝導性を向上させることができる。チップスケールパッケージのさらに他の形態として、さらにまた別の従来技術文献が知られるが、半導体基板に貫通孔をあけた後、基板の下面を除去して貫通孔を露出させる構造が開示されている（例えば、特許文献３及び４参照）。
米国特許第６、７７４、４７５号明細書 韓国特許公開番号第２００３−００２３０４０号 On the other hand, a chip scale package technique is known as another package technique for increasing the degree of integration of an integrated circuit chip on a substrate such as a printed circuit board. The chip scale package technology improves the degree of integration by using a package having a small form factor and almost the same size as an integrated circuit chip. A common requirement among chip scale package conditions is that the size of the package must be within about 1.2 times the size of the semiconductor chip. As a chip scale package technique, which is known in another prior art document, a wafer level chip scale package which is one form of the chip scale package is disclosed. In the wafer level chip scale package, the integrated circuit chip is mounted on the printed circuit board, and the chip pad and the substrate pad are bonded via the solder ball without using the underfill. Also, the use of bonding wires and interposers for electrical connection is different from other ball grid array technologies. Such a wafer level package can minimize the inductance between the integrated circuit and the printed circuit board, reduce the size of the package, and improve the thermal conductivity to save manufacturing effort. . Still another prior art document is known as yet another form of the chip scale package. However, a structure is disclosed in which a through hole is formed in a semiconductor substrate and then the lower surface of the substrate is removed to expose the through hole. (For example, refer to Patent Documents 3 and 4).
US Pat. No. 6,774,475 Korean Patent Publication No. 2003-0023040

図１は、電気的に接続されている第１集積回路チップ１０ａ及び第２集積回路チップ１０ｂが垂直に積層された積層パッケージ２０を示す断面図である。積層パッケージ２０は、上記特許文献４の図１２に示されたチップ積層パッケージと類似している。第１チップ１０ａは、第１貫通孔１７ａが形成されている第１半導体基板１２ａを有し、第１貫通孔１７ａは、基板１２ａの上面から下面に貫通している。第１不活性層１３ａが基板の上面に形成され、不活性層１３ａに第１チップパッド１１ａを露出させる孔が形成されている。第１絶縁層１８ａが、不活性層１３ａ上に形成され第１貫通孔１７ａの側壁まで及んでいる。第１金属層２１ａが、第１チップパッド１１ａ上に形成されチップパッド１１ａと電気的に接続する。図示したように、第１金属層２１ａは、第１絶縁層１８ａ上に形成され第１貫通孔１７ａ内部に延びている。第１電極金属層２２ａが、第１貫通孔１７ａを充填して形成され、第１金属層２１ａにより第１チップパッド１１ａと電気的に接続する。   FIG. 1 is a cross-sectional view showing a stacked package 20 in which a first integrated circuit chip 10a and a second integrated circuit chip 10b that are electrically connected are stacked vertically. The stacked package 20 is similar to the chip stacked package shown in FIG. The first chip 10a has a first semiconductor substrate 12a in which a first through hole 17a is formed, and the first through hole 17a penetrates from the upper surface to the lower surface of the substrate 12a. A first inactive layer 13a is formed on the upper surface of the substrate, and a hole for exposing the first chip pad 11a is formed in the inactive layer 13a. The first insulating layer 18a is formed on the inactive layer 13a and extends to the side wall of the first through hole 17a. The first metal layer 21a is formed on the first chip pad 11a and is electrically connected to the chip pad 11a. As illustrated, the first metal layer 21a is formed on the first insulating layer 18a and extends into the first through hole 17a. The first electrode metal layer 22a is formed by filling the first through hole 17a, and is electrically connected to the first chip pad 11a by the first metal layer 21a.

同様に、第２チップ１０ｂもまた第２貫通孔１７ｂが形成されている第２半導体基板１２ｂを有し、第２貫通孔１７ｂは、基板１２ｂの上面から下面に貫通する。第２不活性層１３ｂが、基板１２ｂの上面に形成され不活性層１３ｂに第２チップパッド１１ｂを露出させる開口が形成されている。第２絶縁層１８ｂが、不活性層１３ｂ上に形成され第２貫通孔１７ｂの側壁まで及んでいる。第２金属層２１ｂが、第２チップパッド１１ｂ上に形成されチップパッド１１ｂと電気的に接続する。すなわち、第２金属層２１ｂは、第２絶縁層１８ｂ上に形成され第２貫通孔１７ｂ内部に延びている。第２電極金属層２２ｂが、第２貫通孔１７ｂを充填して形成され、第２金属層２１ｂにより第２チップパッド１１ｂと電気的に接続する。   Similarly, the second chip 10b also has a second semiconductor substrate 12b in which a second through hole 17b is formed, and the second through hole 17b penetrates from the upper surface to the lower surface of the substrate 12b. The second inactive layer 13b is formed on the upper surface of the substrate 12b, and an opening for exposing the second chip pad 11b is formed in the inactive layer 13b. The second insulating layer 18b is formed on the inactive layer 13b and extends to the side wall of the second through hole 17b. The second metal layer 21b is formed on the second chip pad 11b and is electrically connected to the chip pad 11b. That is, the second metal layer 21b is formed on the second insulating layer 18b and extends into the second through hole 17b. The second electrode metal layer 22b is formed by filling the second through hole 17b, and is electrically connected to the second chip pad 11b by the second metal layer 21b.

第１集積回路チップ１０ａ及び第２集積回路チップ１０ｂが電気的に接続する同時に、第１チップパッド１１ａ及び第２チップパッド１１ｂも電気的に接続する。この電気的相互接続は、第１電極金属層２２ａと第２電極金属層２２ｂとを電気的に接続する第１金属バンプ２４ａ（例えば、ソルダボール）からなる。第２金属バンプ２４ｂは、第２電極金属層２２ｂと下部とに位置されるチップ、パッケージまたは印刷回路基板（図示せず）を電気的に接続する。   At the same time that the first integrated circuit chip 10a and the second integrated circuit chip 10b are electrically connected, the first chip pad 11a and the second chip pad 11b are also electrically connected. This electrical interconnection consists of a first metal bump 24a (for example, a solder ball) that electrically connects the first electrode metal layer 22a and the second electrode metal layer 22b. The second metal bump 24b electrically connects a chip, a package, or a printed circuit board (not shown) positioned on the second electrode metal layer 22b and the lower part.

集積回路、複数個のチップパッド及び不活性層（図１の１３ａ、１３ｂ）から構成される一つの半導体ウエハ（図示せず）において、第１集積回路チップ１０ａ及び第２集積回路チップ１０ｂが形成されることは当業者にとって自明である。レーザードリルリング方法を用いて半導体ウエハに第１貫通孔１７ａ及び第２貫通孔１７ｂが形成される。貫通孔を形成した後、不活性層上に貫通孔の側壁に沿って絶縁層（図１の１８ａ、１８ｂ）が形成される。チップパッドが露出するように絶縁層がパターニングされる。次いで、絶縁層上に金属層（図１の２１ａ、２１ｂ）及び電極金属層（図１の２２ａ、２２ｂ）が順に形成される。電極金属層は貫通孔を充填する程度に、十分な厚さで形成される。そして、半導体ウエハは、裏面の一部を除去して薄膜化する。このような薄膜工程には、研削方法、研磨方法及び湿式エッチング方法などが挙げられる。薄膜工程によって貫通孔内の電極金属層が露出される。   The first integrated circuit chip 10a and the second integrated circuit chip 10b are formed on one semiconductor wafer (not shown) including an integrated circuit, a plurality of chip pads, and an inactive layer (13a and 13b in FIG. 1). It will be obvious to those skilled in the art. A first through hole 17a and a second through hole 17b are formed in the semiconductor wafer using a laser drilling method. After forming the through hole, an insulating layer (18a and 18b in FIG. 1) is formed along the side wall of the through hole on the inert layer. The insulating layer is patterned so that the chip pad is exposed. Next, a metal layer (21a and 21b in FIG. 1) and an electrode metal layer (22a and 22b in FIG. 1) are sequentially formed on the insulating layer. The electrode metal layer is formed with a sufficient thickness to fill the through hole. Then, the semiconductor wafer is thinned by removing a part of the back surface. Examples of such a thin film process include a grinding method, a polishing method, and a wet etching method. The electrode metal layer in the through hole is exposed by the thin film process.

しかしながら、レーザードリルリング方法を用いて半導体ウエハに貫通孔を形成する従来の製造工程は、貫通孔を一つずつ順に形成しているため工程時間がかる。また、ドリルリング方法は、半導体ウエハを損傷させる恐れがあり、一定した形状の貫通孔を期待し難い。例えば、不規則な形の貫通孔が形成されると、電極金属層に電気的絶縁のような欠陥が発生することがある。従って、集積度を高めるための集積回路チップを積層する従来技術の他にも、半導体ウエハ及び半導体チップに貫通孔を形成する方法を向上させる技術が求められる。   However, the conventional manufacturing process in which the through holes are formed in the semiconductor wafer using the laser drilling method takes a long time because the through holes are formed one by one in order. Further, the drilling method may damage the semiconductor wafer, and it is difficult to expect a through hole having a constant shape. For example, when an irregularly shaped through hole is formed, a defect such as electrical insulation may occur in the electrode metal layer. Therefore, in addition to the conventional technique of stacking integrated circuit chips for increasing the degree of integration, a technique for improving the method of forming a through hole in a semiconductor wafer and a semiconductor chip is required.

本発明の目的は、製造工程を単純化し、かつ製造コスト及び工程時間を短縮できるマルチチップパッケージ用集積回路チップの製造方法を提供することにある。   An object of the present invention is to provide a method for manufacturing an integrated circuit chip for a multichip package, which can simplify the manufacturing process and reduce the manufacturing cost and the process time.

本発明の実施形態による半導体チップは、外縁絶縁層に貫通孔が形成され積層マルチチップパッケージに信頼性のある相互接続孔を備える。本実施形態において、外縁まで延びる上面と下面を有する半導体基板を備え、半導体基板の上面に外縁に隣接して延びている少なくとも一つの第１接触パッドを備えている。この電気絶縁領域は、半導体基板の外縁に形成され、半導体基板の全周を取り囲んで少なくとも一つの貫通孔を含む。上記貫通孔は、電気絶縁領域の垂直に貫通して形成され、半導体基板の外縁と実質的に平行した縦軸を有する。また、接続電極を備えるが、該接続電極は、貫通孔を貫通して第１接触パッドと電気的に接続する。電気絶縁層の下面は、半導体基板の下面と同一平面上に、電気絶縁層の上面は、半導体基板の上面上に位置することにより、貫通孔の高さが半導体基板の厚さより大きく形成される。特に、電気的絶縁層は、外縁を取り囲んで半導体基板を覆っている不活性層の上に延びている。   A semiconductor chip according to an embodiment of the present invention includes a through hole formed in an outer edge insulating layer and a reliable multi-chip package having a reliable interconnect hole. In this embodiment, a semiconductor substrate having an upper surface and a lower surface extending to the outer edge is provided, and at least one first contact pad extending adjacent to the outer edge is provided on the upper surface of the semiconductor substrate. The electrically insulating region is formed at the outer edge of the semiconductor substrate and surrounds the entire periphery of the semiconductor substrate and includes at least one through hole. The through hole is formed perpendicularly to the electrically insulating region and has a vertical axis substantially parallel to the outer edge of the semiconductor substrate. Moreover, although a connection electrode is provided, this connection electrode penetrates a through-hole and is electrically connected with a 1st contact pad. The lower surface of the electrical insulating layer is on the same plane as the lower surface of the semiconductor substrate, and the upper surface of the electrical insulating layer is positioned on the upper surface of the semiconductor substrate, so that the height of the through hole is formed larger than the thickness of the semiconductor substrate. . In particular, the electrically insulating layer extends over an inactive layer that surrounds the outer edge and covers the semiconductor substrate.

本発明の実施形態による半導体チップは、貫通孔が形成された電気絶縁領域によって画定される周辺端部を有する。半導体チップは、外縁まで延びている上面と下面とを有する半導体基板を備え、半導体基板の外縁に電気絶縁領域が形成される。電気絶縁領域に貫通孔が形成され、該貫通孔は接続電極で充填される。半田バンプは、貫通孔の底面に隣接して延びた接続電極の一部と電気的に接続する。   A semiconductor chip according to an embodiment of the present invention has a peripheral edge defined by an electrically insulating region in which a through hole is formed. The semiconductor chip includes a semiconductor substrate having an upper surface and a lower surface extending to the outer edge, and an electrically insulating region is formed on the outer edge of the semiconductor substrate. A through hole is formed in the electrically insulating region, and the through hole is filled with a connection electrode. The solder bump is electrically connected to a part of the connection electrode extending adjacent to the bottom surface of the through hole.

本発明の他の実施形態による集積回路チップ製造方法は、複数個の接触パッドを有する半導体ウエハに複数個の十字溝を形成する段階を含む。十字溝が、電気絶縁層で充填され、電気絶縁層がパターニングされ溝に少なくとも第１貫通孔及び第２貫通孔を形成する。第１貫通孔及び第２貫通孔は、各々第１接続電極及び第２接続電極で充填される。そして、半導体ウエハは、複数個の集積回路チップに分離される。このダイシング工程は、電気絶縁層を十字溝の位置と一致する十字形態に切断することからなる。   An integrated circuit chip manufacturing method according to another embodiment of the present invention includes forming a plurality of cross grooves in a semiconductor wafer having a plurality of contact pads. The cross groove is filled with an electrical insulating layer, and the electrical insulating layer is patterned to form at least a first through hole and a second through hole in the groove. The first through hole and the second through hole are filled with the first connection electrode and the second connection electrode, respectively. Then, the semiconductor wafer is separated into a plurality of integrated circuit chips. This dicing process consists of cutting the electrical insulating layer into a cross shape that matches the position of the cross groove.

本発明の他の実施形態において、ダイシング工程に先立ち、半導体ウエハの下部を除去することにより、第１貫通チップ接続電極及び第２貫通チップ接続電極と電気絶縁層とを露出させる段階を含む。第１貫通孔及び第２貫通孔を充填する段階は、第１貫通孔及び第２貫通孔を含む金属基底層を電気絶縁層に形成した後、該金属基底層を電気メッキ電極にして第１貫通チップ接続電極及び第２貫通チップ接続電極を第１貫通孔及び第２貫通孔の中に電気メッキする段階を含む。金属基底層は、第１貫通チップ接続電極及び第２接続電極をエッチングマスクとして用いてエッチングする。   In another embodiment of the present invention, prior to the dicing process, the lower portion of the semiconductor wafer is removed to expose the first through-chip connection electrode, the second through-chip connection electrode, and the electrical insulating layer. In the step of filling the first through hole and the second through hole, a metal base layer including the first through hole and the second through hole is formed on the electrical insulating layer, and then the first metal base layer is used as an electroplating electrode. Electroplating the through-chip connecting electrode and the second through-chip connecting electrode into the first through-hole and the second through-hole. The metal base layer is etched using the first through-chip connection electrode and the second connection electrode as an etching mask.

以下、添付図面を参照しながら本発明の実施形態をさらに詳細に説明する。   Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

本明細書と図面に開示された本発明の実施形態などは理解を助けるための特定例を提示したに過ぎず、本発明の範囲を限定するものではない。ここに開示された実施形態の他にも本発明の技術的思想に基づき他の変形例を実施可能であることが自明である。また、図面に示した層や領域の厚さは、明確な説明のために誇張され得る。ある層を他の層や基板上に位置させるとき、これは、他の層や基板の上部に直接位置させることもでき、中間に他の層を介在させることもできることを意味する。一方、図面において、同一構成部分には同一符号を付す。   The embodiments of the present invention disclosed in the present specification and the drawings are merely examples for assisting understanding, and do not limit the scope of the present invention. In addition to the embodiments disclosed herein, it is obvious that other modifications can be implemented based on the technical idea of the present invention. In addition, the thickness of layers and regions illustrated in the drawings can be exaggerated for the sake of clarity. When one layer is positioned on another layer or substrate, this means that it can be positioned directly on top of the other layer or substrate, and another layer can be interposed in between. On the other hand, in the drawings, the same components are denoted by the same reference numerals.

図２乃至図１４を参照しながら本発明の実施形態における集積回路チップ製造方法について説明する。図２によれば、半導体ウエハ３０は、半導体基板３２（例えば、シリコン基板）を備え、かつ第１面３５を有する。図３乃至図１４によれば、半導体ウエハ３０を十字スクライブレーン３６に沿ってダイシングして、半導体ウエハから複数個の個別半導体チップ３４を形成する。   The integrated circuit chip manufacturing method according to the embodiment of the present invention will be described with reference to FIGS. According to FIG. 2, the semiconductor wafer 30 includes a semiconductor substrate 32 (for example, a silicon substrate) and has a first surface 35. 3 to 14, the semiconductor wafer 30 is diced along the cross scribe lane 36 to form a plurality of individual semiconductor chips 34 from the semiconductor wafer.

図３は、図２の半導体ウエハ３０の一部を示す平面図である。図４は、図３の４−４´線に沿って切断した断面図である。特に、図３は、スクライブレーン３６により集積回路素子が互いに分離される隣接集積回路素子の抹消部を示している。各集積回路素子は、第１面３５に接触パッド３１を含む。接触パッド３１は、図示の集積回路素子のそれぞれの一面に沿って形成されている。本発明の他の実施形態において、他のパッド（図示せず）が集積回路素子の他の一面に形成され得る。図４において、不活性層３３が半導体ウエハ３０の第１面３５を覆っている。パッド３１は、アルミニウムまたは銅からなり、不活性層３３は、シリコン酸化物、シリコン窒化物及びシリコン窒酸化物等の電気絶縁物質からなる。不活性層３３は、比較的厚い電気絶縁物質から形成され、金属化、相互接続、層間絶縁層及び能動素子（図示せず）等の多重下層を覆う。図４は、最終ウエハダイシング段階が行われた後、最終的に構成される個々の半導体チップ３４の二つの基板３２の間に形成されているスクライブレーン３６を示す。   FIG. 3 is a plan view showing a part of the semiconductor wafer 30 of FIG. 4 is a cross-sectional view taken along line 4-4 ′ of FIG. In particular, FIG. 3 shows an erasure part of adjacent integrated circuit elements in which the integrated circuit elements are separated from each other by a scribe lane 36. Each integrated circuit element includes a contact pad 31 on the first surface 35. The contact pad 31 is formed along one surface of each of the illustrated integrated circuit elements. In other embodiments of the present invention, other pads (not shown) may be formed on the other side of the integrated circuit element. In FIG. 4, the inactive layer 33 covers the first surface 35 of the semiconductor wafer 30. The pad 31 is made of aluminum or copper, and the inactive layer 33 is made of an electrically insulating material such as silicon oxide, silicon nitride, or silicon nitride oxide. The inactive layer 33 is formed from a relatively thick electrical insulating material and covers multiple underlayers such as metallization, interconnects, interlayer insulating layers and active devices (not shown). FIG. 4 shows a scribe lane 36 formed between two substrates 32 of individual semiconductor chips 34 that are finally constructed after the final wafer dicing step has been performed.

図５及び図６に示すように、スクライブレーン３６に沿って一連の深さを有する十字溝３７が形成されている。これらの溝３７の幅は、スクライブレーン３６の幅とほぼ同一で、図１２に示すように、これらの溝３７の深さは、ウエハ切断前に除去される半導体ウエハ３０の裏面３９の量と相関関係にある。本発明の実施形態において、溝３７の深さは、約３０〜４０ミクロンで形成される。これらの溝３７は、ウエハ切断技術及び/又はウエハエッチング技術を用いて形成される。それから、比較的厚い電気絶縁層３８が半導体ウエハ３０の第１面上にブランケット層（blanket layer）として形成される。図６に示すように、電気絶縁層３８は、溝３７を充填して基板３２間の空間を完全に満たす。電気絶縁層３８はシリコン酸化層またはポリイミド層から形成される。   As shown in FIGS. 5 and 6, a cross groove 37 having a series of depths is formed along the scribe lane 36. The width of these grooves 37 is substantially the same as the width of the scribe lane 36. As shown in FIG. 12, the depth of these grooves 37 is the amount of the back surface 39 of the semiconductor wafer 30 to be removed before cutting the wafer. There is a correlation. In an embodiment of the present invention, the depth of the groove 37 is formed at about 30-40 microns. These grooves 37 are formed using a wafer cutting technique and / or a wafer etching technique. A relatively thick electrical insulation layer 38 is then formed on the first surface of the semiconductor wafer 30 as a blanket layer. As shown in FIG. 6, the electrically insulating layer 38 fills the groove 37 and completely fills the space between the substrates 32. The electrically insulating layer 38 is formed from a silicon oxide layer or a polyimide layer.

図７を参照すれば、電気絶縁層３８を選択的に除去することにより、スクライブレーン３６内に複数個の貫通孔４１が形成され、接触パッド３１を露出させる。貫通孔４１を通して溝３７の底面が露出されている。電気絶縁層３８の除去段階は、フォトリソグラフィエッチング方法によって行われる。これにより、垂直な側壁と一定の直径を有する貫通孔が形成される。貫通孔の直径は、１０〜５０ミクロンである。電気絶縁層３８は、基板との接着力に優れ、後続工程の間に分離及び／または絶縁層３８の剥離を防ぐことができる。しかも、エッチング段階が、全ウエハ３０に一括的に行われるため、貫通孔４１を一度に形成し、それと同時に接合パッド３１を露出させることから、工程時間を短縮することができる。   Referring to FIG. 7, by selectively removing the electrical insulating layer 38, a plurality of through holes 41 are formed in the scribe lane 36 to expose the contact pads 31. The bottom surface of the groove 37 is exposed through the through hole 41. The step of removing the electrical insulating layer 38 is performed by a photolithography etching method. As a result, a vertical side wall and a through hole having a constant diameter are formed. The diameter of the through hole is 10 to 50 microns. The electrically insulating layer 38 has excellent adhesion to the substrate and can prevent separation and / or peeling of the insulating layer 38 during subsequent processes. In addition, since the etching step is performed on all the wafers 30 at once, the through holes 41 are formed at the same time and the bonding pads 31 are exposed at the same time, so that the process time can be shortened.

貫通孔４１の形成後に、ウエハ３０上に金属基底層４２が形成される。図８に示すように、この金属基底層４２は、露出した接合パッド３１の上面と接し、かつ貫通孔４１の底面と側壁に沿って形成されている。下層の電気絶縁層３８との優れた接着特性を有しなければならない金属基底層４２は、スパッタリング方法で形成され、約０．０５〜１ミクロンの厚さを有する。本発明の実施形態において、金属基底層４２は、二つまたはそれ以上の金属層の組み合わせからなるが、第１金属層は、クロム、チタンまたは電気絶縁層３８との接着力に優れた金属層などを用い、第２金属層は、金、銅、ニッケル、パラジウム、白金または後から形成される接続電極との接着力に優れた金属層などが用いられる。   After the formation of the through hole 41, the metal base layer 42 is formed on the wafer 30. As shown in FIG. 8, the metal base layer 42 is in contact with the exposed upper surface of the bonding pad 31 and is formed along the bottom surface and the side wall of the through hole 41. The metal base layer 42, which must have excellent adhesion properties with the underlying electrical insulating layer 38, is formed by a sputtering method and has a thickness of about 0.05 to 1 micron. In the embodiment of the present invention, the metal base layer 42 is composed of a combination of two or more metal layers, and the first metal layer is a metal layer having excellent adhesion to chromium, titanium, or the electrical insulating layer 38. As the second metal layer, gold, copper, nickel, palladium, platinum, or a metal layer having excellent adhesive force with a connection electrode formed later is used.

図９乃至図１１を参照すれば、フォトレジスト物質層が形成され、これをパターニングして複数個の開口５２を有するフォトレジストマスク５１を形成している。これらの開口５２は、接触パッド３１上の金属基底層４２とそれに対応する貫通孔４１を露出させる。図１０に示すように、フォトレジストマスク５１内にそれぞれの開口５２を完全に充填する電極金属層４３が形成されている。電極金属層４３は、金属基底層４２をメッキ電極として用いる電気メッキ方法または他の選択的蒸着方法から形成される。電極金属層４３は、金、銅、ニッケル、パラジウム、白金及びその合金または適宜な高伝導物質等からなる。図１１に示すように、フォトレジストマスク５１が除去されることにより金属基底層４２の一部が露出される。露出した金属基底層４２は、電極金属層４３をエッチングマスクとして用いるエッチング段階によって選択的に除去される。該エッチング段階により、電気絶縁層３８が露出するとともに電極金属層４３が電気的に絶縁されるようになる。   9 to 11, a photoresist material layer is formed and patterned to form a photoresist mask 51 having a plurality of openings 52. These openings 52 expose the metal base layer 42 on the contact pads 31 and the corresponding through holes 41. As shown in FIG. 10, an electrode metal layer 43 that completely fills each opening 52 is formed in the photoresist mask 51. The electrode metal layer 43 is formed by an electroplating method using the metal base layer 42 as a plating electrode or other selective vapor deposition method. The electrode metal layer 43 is made of gold, copper, nickel, palladium, platinum, an alloy thereof, or an appropriate highly conductive material. As shown in FIG. 11, a part of the metal base layer 42 is exposed by removing the photoresist mask 51. The exposed metal base layer 42 is selectively removed by an etching step using the electrode metal layer 43 as an etching mask. The etching step exposes the electrical insulating layer 38 and electrically insulates the electrode metal layer 43.

図１２を参照すれば、ウエハ薄膜段階により、電極金属層４３の一部が露出されている。ウエハ薄膜段階は、研磨ホイール５３を用いて半導体ウエハ３０の裏面３９を除去する。半導体ウエハ３０の裏面３９の薄膜段階は、研磨方法の他にも湿式エッチング方法が用いられる。薄膜段階により、半導体ウエハ３０の裏面３９が実質的に減ることになるが、具体的に、薄膜段階前に、７００ミクロンだった半導体ウエハの厚さが薄膜の後、約１００ミクロン（または、それ以下）となる。従って、貫通孔４１及び溝３７との深さが、約１００ミクロンより大きく電極金属層４３の露出を保障するとともに、電極金属層４３とそれに対応する金属基底層４２とは、接触パッド３１から半導体ウエハ３０裏面３９に至る高伝導性電気通路を提供できるようになる。   Referring to FIG. 12, a part of the electrode metal layer 43 is exposed at the wafer thin film stage. In the wafer thin film stage, the back surface 39 of the semiconductor wafer 30 is removed using the polishing wheel 53. In addition to the polishing method, a wet etching method is used for the thin film stage on the back surface 39 of the semiconductor wafer 30. Although the thin film step substantially reduces the backside 39 of the semiconductor wafer 30, the thickness of the semiconductor wafer, which was 700 microns before the thin film step, is about 100 microns (or less) after the thin film. The following. Accordingly, the depth of the through hole 41 and the groove 37 is larger than about 100 microns to ensure the exposure of the electrode metal layer 43, and the electrode metal layer 43 and the corresponding metal base layer 42 are formed from the contact pad 31 to the semiconductor. It becomes possible to provide a highly conductive electrical path to the back surface 39 of the wafer 30.

図１３及び図１４に示すように、ウエハ薄膜工程に続いて、紫外線接着テープ等の接着テープ５４を半導体ウエハ３０の裏面３９全体に貼付ける段階が行われる。接着テープ５４を貼付けることにより、ウエハ切断工程等の後続工程での半導体ウエハ３０の状態を維持することができる。そして、切断機５５でスクライブレーン３６に沿って半導体ウエハ３０を切断して、複数個の個別集積回路チップ６０に分離させる。   As shown in FIGS. 13 and 14, following the wafer thin film process, a step of applying an adhesive tape 54 such as an ultraviolet adhesive tape to the entire back surface 39 of the semiconductor wafer 30 is performed. By sticking the adhesive tape 54, the state of the semiconductor wafer 30 in a subsequent process such as a wafer cutting process can be maintained. Then, the semiconductor wafer 30 is cut along the scribe lane 36 by the cutting machine 55 and separated into a plurality of individual integrated circuit chips 60.

図１５を参照すれば、図３乃至図１４に示した方法によって形成された集積回路チップ６０ａ、６０ｂを積層した積層パッケージ７０は、第１金属バンプ４５ａを用いて上部チップ６０ａの上部接続電極４３ａと下部チップ６０ｂの下部接続電極４３ｂとが電気的に接続されている構造を有する。そして、積層パッケージ７０は、第２金属バンプ４５ｂを用いて印刷回路基板（図示せず）に実装されかつ電気的に接続する。よって、第２金属バンプ４５ｂは、積層パッケージ７０の接続端子としての役割を果たす。第１金属バンプ４５ａ及び第２金属バンプは、電気メッキ方法または金属バンプ形成方法で形成される。   Referring to FIG. 15, the stacked package 70 in which the integrated circuit chips 60a and 60b formed by the method shown in FIGS. 3 to 14 are stacked is formed by using the first metal bump 45a and the upper connection electrode 43a of the upper chip 60a. And the lower connection electrode 43b of the lower chip 60b are electrically connected. The stacked package 70 is mounted on and electrically connected to a printed circuit board (not shown) using the second metal bump 45b. Therefore, the second metal bump 45 b serves as a connection terminal for the stacked package 70. The first metal bump 45a and the second metal bump are formed by an electroplating method or a metal bump forming method.

なお、本明細書と図面に開示された本発明の実施形態は理解を助けるために特定例を提示したに過ぎず、本発明の範囲を限定するものではない。ここに開示された実施形態の他にも本発明の技術的思想に基づき他の変形例が実施可能であることは自明である。   It should be noted that the embodiments of the present invention disclosed in this specification and the drawings are merely provided as specific examples to help understanding, and do not limit the scope of the present invention. It is obvious that other modified examples can be implemented based on the technical idea of the present invention in addition to the embodiments disclosed herein.

チップスケールパッケージ技術が用いられる、従来技術の集積回路チップが積層された積層パッケージを示す断面図である。It is sectional drawing which shows the laminated package on which the integrated circuit chip of the prior art was laminated | stacked using the chip scale package technique. 図３乃至図１４に示す方法に従って製造された半導体ウエハの平面図である。FIG. 15 is a plan view of a semiconductor wafer manufactured according to the method shown in FIGS. 3 to 14. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 本発明の実施形態における集積回路チップ製造方法の段階別の構造を示す断面図である。It is sectional drawing which shows the structure according to the step of the integrated circuit chip manufacturing method in embodiment of this invention. 図３乃至図１４に示した方法による集積回路チップの積層パッケージを示す断面図である。FIG. 15 is a cross-sectional view showing a stacked package of integrated circuit chips by the method shown in FIGS. 3 to 14.

符号の説明Explanation of symbols

３０ 半導体ウエハ
３１ 接触パッド
３２ 基板
３３ 不活性層
３４ 半導体チップ
３５ 第１面
３６ スクライブレーン
３７ 溝
３８ 電気絶縁層
３９ 裏面
４１ 貫通孔
４２ 金属基底層
４３ 電極金属層
４３ａ 上部接続電極
４３ｂ 下部接続電極
４５ 金属バンプ
４５ａ 第１金属バンプ
５１ フォトレジストマスク
５２ 開口
５３ 研磨ホイール
５４ 接着テープ
５５ 切断機
６０ 集積回路チップ
６０ａ 集積回路チップ
７０ 積層パッケージ
DESCRIPTION OF SYMBOLS 30 Semiconductor wafer 31 Contact pad 32 Substrate 33 Inactive layer 34 Semiconductor chip 35 1st surface 36 Scribe lane 37 Groove 38 Electrical insulation layer 39 Back surface 41 Through-hole 42 Metal base layer 43 Electrode metal layer 43a Upper connection electrode 43b Lower connection electrode 45 Metal bump 45a First metal bump 51 Photoresist mask 52 Opening 53 Polishing wheel 54 Adhesive tape 55 Cutting machine 60 Integrated circuit chip 60a Integrated circuit chip 70 Stacked package

Claims (20)

外縁まで延びる上下面を有し、前記上面から前記外縁に隣接して少なくとも一つの第１接触パッドが形成されている半導体基板と、
貫通孔が形成され、前記半導体基板の前記外縁に画成されている電気絶縁領域と、
前記貫通孔を貫通し、かつ前記第１接触パッドと電気的に接続する接続電極と、
を備えることを特徴とする半導体チップ。 A semiconductor substrate having an upper and lower surface extending to an outer edge, wherein at least one first contact pad is formed adjacent to the outer edge from the upper surface;
An electrically insulating region having a through hole formed therein and defined at the outer edge of the semiconductor substrate;
A connection electrode penetrating the through hole and electrically connected to the first contact pad;
A semiconductor chip comprising: 前記電気絶縁層の下面は、前記半導体基板の下面と共面である、請求項１に記載の半導体チップ。   The semiconductor chip according to claim 1, wherein a lower surface of the electrical insulating layer is coplanar with a lower surface of the semiconductor substrate. 前記貫通孔の高さは、前記半導体基板の厚さより大きい、請求項１に記載の半導体チップ。   The semiconductor chip according to claim 1, wherein a height of the through hole is larger than a thickness of the semiconductor substrate. 前記貫通孔の縦軸は、前記半導体基板の外縁と実質的に平行である、請求項３に記載の半導体チップ。   The semiconductor chip according to claim 3, wherein a vertical axis of the through hole is substantially parallel to an outer edge of the semiconductor substrate. 前記上面に形成され、かつ前記第１接触パッドを露出する開口を有する不活性層をさらに備え、
前記電気絶縁領域は、前記半導体基板の外縁を取り囲んで前記不活性層まで延びる、請求項１に記載の半導体チップ。 An inert layer formed on the upper surface and having an opening exposing the first contact pad;
The semiconductor chip according to claim 1, wherein the electrically insulating region surrounds an outer edge of the semiconductor substrate and extends to the inactive layer. 前記電気絶縁領域は、前記半導体基板の上面と前記接続電極との間に形成される、請求講５に記載の半導体チップ。   The semiconductor chip according to claim 5, wherein the electrically insulating region is formed between an upper surface of the semiconductor substrate and the connection electrode. 前記電気絶縁領域の外縁は、前記半導体チップの外縁である、請求項１に記載の 半導体チップ。   The semiconductor chip according to claim 1, wherein an outer edge of the electrically insulating region is an outer edge of the semiconductor chip. 外縁まで延びる上下面を有する半導体基板と、
前記半導体基板の外縁に形成され、かつ前記半導体基板の厚さより大きい高さの貫通孔を有する電気絶縁領域と、
前記貫通孔を貫通する接続電極と、
前記貫通孔の底面に隣接して形成される接続電極と電気的に接続する半田バンプと、
を備えることを特徴とする半導体チップ。 A semiconductor substrate having upper and lower surfaces extending to the outer edge;
An electrically insulating region formed at an outer edge of the semiconductor substrate and having a through-hole having a height larger than the thickness of the semiconductor substrate;
A connection electrode penetrating the through hole;
A solder bump electrically connected to a connection electrode formed adjacent to the bottom surface of the through hole;
A semiconductor chip comprising: 前記電気絶縁領域の外縁は、前記半導体チップの外縁である、請求項８に記載の半導体チップ。   The semiconductor chip according to claim 8, wherein an outer edge of the electrically insulating region is an outer edge of the semiconductor chip. 複数個の接触パッドを有する半導体ウエハに複数個の十字溝を形成する段階と、
前記十字溝を電気絶縁層で充填する段階と、
前記電気絶縁層をパターニングして前記十字溝に第１貫通孔及び第２貫通孔を形成する段階と、
前記第１貫通孔及び第２貫通孔を、第１接続電極及び第２接続電極で充填する段階と、
前記溝の位置と一致する十字形態にして前記電気絶縁層を切断することにより前記半導体ウエハをダイシングする段階と、
を含むことを特徴とする複数個の集積回路チップを製造する方法。 Forming a plurality of cross grooves in a semiconductor wafer having a plurality of contact pads;
Filling the cross groove with an electrically insulating layer;
Patterning the electrical insulating layer to form a first through hole and a second through hole in the cross groove;
Filling the first through hole and the second through hole with a first connection electrode and a second connection electrode;
Dicing the semiconductor wafer by cutting the electrical insulation layer into a cross shape that matches the position of the groove;
A method of manufacturing a plurality of integrated circuit chips. 前記ダイシング段階に先立ち、前記半導体ウエハの裏面を除去する段階が行われることにより、前記１貫通チップ接続電極及び第２貫通チップ接続電極と電気絶縁層とを露出する請求項１０に記載の複数個の集積回路チップを製造する方法。   11. The plurality of claim 10, wherein a step of removing a back surface of the semiconductor wafer is performed prior to the dicing step, thereby exposing the first through-chip connection electrode, the second through-chip connection electrode, and the electrical insulating layer. Method of manufacturing an integrated circuit chip. 前記第１貫通孔及び第２貫通孔を充填する段階は、
前記電気絶縁層上に形成され、かつ前記第１貫通孔及び第２貫通孔に沿って金属基底層を被覆する段階と、
前記第１貫通チップ接続電極及び第２貫通チップ接続電極を、前記第１貫通孔及び第２貫通孔の内へ電気メッキする段階と、
前記第１接続電極及び第２接続電極をエッチングマスクとして用いて前記金属基底層をエッチングする段階と、
を含む、請求項１１に記載の複数個の集積回路チップを製造する方法。 Filling the first through hole and the second through hole comprises:
Covering the metal base layer along the first through hole and the second through hole formed on the electrical insulating layer;
Electroplating the first through chip connection electrode and the second through chip connection electrode into the first through hole and the second through hole; and
Etching the metal base layer using the first connection electrode and the second connection electrode as an etching mask;
12. A method of manufacturing a plurality of integrated circuit chips according to claim 11, comprising: 前記第１貫通孔及び第２貫通孔を充填する段階は、
前記電気絶縁層上に形成され、かつ前記第１貫通孔及び第２貫通孔に沿って金属基底層を被覆する段階と、
前記第１貫通チップ接続電極及び第２貫通チップ接続電極を、前記第１貫通孔及び第２貫通孔に電気メッキする段階と、
前記第１接続電極及び第２接続電極をエッチングマスクとして用いて前記金属基底層を蝕刻する段階と、
を含む、請求項１０に記載の複数個の集積回路チップを製造する方法。 Filling the first through hole and the second through hole comprises:
Covering the metal base layer along the first through hole and the second through hole formed on the electrical insulating layer;
Electroplating the first through-chip connection electrode and the second through-chip connection electrode on the first through-hole and the second through-hole; and
Etching the metal base layer using the first connection electrode and the second connection electrode as an etching mask;
A method of manufacturing a plurality of integrated circuit chips as claimed in claim 10. 前記電気メッキ段階は、電気メッキ電極として前記金属基底層を用いて前記第１貫通電極及び第２貫通電極の中へ前記第１貫通チップ接続電極及び第２貫通チップ接続電極を電気メッキすることを含む、請求項１３に記載の複数個の集積回路チップを製造する方法。   The electroplating step includes electroplating the first through-chip connecting electrode and the second through-chip connecting electrode into the first through-electrode and the second through-electrode using the metal base layer as an electroplating electrode. A method of manufacturing a plurality of integrated circuit chips as claimed in claim 13. 前記電気メッキ段階に先立ち、前記金属基底層上の電気メッキマスクをパターニングする段階を行う、請求項１４に記載の複数個の集積回路チップを製造する方法。   15. The method of manufacturing a plurality of integrated circuit chips according to claim 14, wherein a step of patterning an electroplating mask on the metal base layer is performed prior to the electroplating step. 半導体基板に溝を形成する段階と、
前記溝を電気絶縁領域で充填する段階と、
前記電気絶縁領域に第１貫通孔及び第２貫通孔を形成する段階と、
前記第１貫通孔及び第２貫通孔を第１接続電極及び第２接続電極で充填する段階と、
前記半導体基板の裏面を除去することにより、前記電気絶縁領域、前記第１接続電極及び第２接続電極を露出させる段階と、
前記第１接続電極及び第２接続電極の間で前記電気絶縁領域を切断することにより前記半導体ウエハを、第１半導体チップ及び第２半導体チップに分離する段階と、
を含むことを特徴とする複数個の集積回路チップを製造する方法。 Forming a groove in a semiconductor substrate;
Filling the groove with an electrically insulating region;
Forming a first through hole and a second through hole in the electrically insulating region;
Filling the first through hole and the second through hole with a first connection electrode and a second connection electrode;
Exposing the electrically insulating region, the first connection electrode and the second connection electrode by removing a back surface of the semiconductor substrate;
Separating the semiconductor wafer into a first semiconductor chip and a second semiconductor chip by cutting the electrically insulating region between the first connection electrode and the second connection electrode;
A method of manufacturing a plurality of integrated circuit chips. 前記第１貫通孔及び第２貫通孔を充填する段階は、
前記第１貫通孔及び第２貫通孔の中へ前記第１接続電極及び第２接続電極を電気メッキする段階を含む、請求項１６に記載の複数個の集積回路チップを製造する方法。 Filling the first through hole and the second through hole comprises:
The method of manufacturing a plurality of integrated circuit chips according to claim 16, comprising electroplating the first connection electrode and the second connection electrode into the first through hole and the second through hole. 半導体ウエハに複数個の十字溝を形成する段階と、
前記十字溝を電気絶縁層で充填する段階と、
前記半導体ウエハの裏面を除去して、十字形態を有する前記電気絶縁層の表面を露出させる段階と、
前記十字形態の地点において、前記電気絶縁層を切断することにより前記半導体ウエハを電気絶縁エッジを有する複数個の集積回路チップにダイシングする段階と、
を含むことを特徴とする複数個の集積回路チップを製造する方法。 Forming a plurality of cross grooves in a semiconductor wafer;
Filling the cross groove with an electrically insulating layer;
Removing the back surface of the semiconductor wafer to expose the surface of the electrical insulating layer having a cross shape;
Dicing the semiconductor wafer into a plurality of integrated circuit chips having electrically insulating edges by cutting the electrically insulating layer at the point of the cross shape;
A method of manufacturing a plurality of integrated circuit chips. 前記半導体ウエハの裏面除去段階に先立ち、前記電気絶縁層に複数個の貫通孔を形成する段階と、
前記複数個の貫通孔をそれに対応する複数個の接続電極で充填する段階と、
を含む、請求項１８に記載の複数個の集積回路チップを製造する方法。 Prior to the backside removal step of the semiconductor wafer, forming a plurality of through holes in the electrical insulating layer;
Filling the plurality of through holes with a plurality of corresponding connection electrodes;
19. A method of manufacturing a plurality of integrated circuit chips according to claim 18, comprising: 前記半導体ウエハの裏面除去段階は、前記半導体ウエハの裏面を除去することにより前記電気絶縁層の表面と複数個の接続電極とを露出させる段階を含む、請求項１９に記載の複数個の集積回路チップを製造する方法。
20. The plurality of integrated circuits of claim 19, wherein the step of removing the back surface of the semiconductor wafer includes the step of exposing the surface of the electrical insulating layer and the plurality of connection electrodes by removing the back surface of the semiconductor wafer. A method of manufacturing a chip.
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