JP4700642B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a structure of a semiconductor device in which a plurality of semiconductor chips are stacked on an interposer, and a resin is filled between the semiconductor chips (functional chips), and a manufacturing method thereof.

  FIG. 1 shows a cross-sectional structure of a conventional semiconductor device in which a plurality of semiconductor chips having through wirings are stacked. Through wirings 102 are formed in the plurality of functional chip substrates 121 and are electrically connected to the internal integrated circuit. The plurality of functional chip substrates 121 are electrically connected to each other through metal bumps 115. An insulating resin 104 is filled between the functional chip substrates 121 for the purpose of improving mechanical strength. The plurality of functional chip groups 105 are mounted on electrode portions 108 of a mounting mounting chip (interposer) 107 having a through wiring 106 via metal bumps 109. A solder terminal 111 for mounting a wiring board is formed on the mounting surface 110 opposite to the chip mounting surface of the interposer 107.

  1 to 4 show a process of forming a conventional semiconductor chip (121). First, in step (1-1), the element wiring layer 112 and the protective layer 113 are formed on the semiconductor substrate 114 by steps such as sputtering, photolithography, plating, and etching.

  Next, in step (1-2), surface metal bumps 115 connected to the element wiring layer 112 are formed on the semiconductor substrate 114. Subsequently, in step (1-3), a support substrate 116 such as glass is attached to the surface of the semiconductor substrate 114. Thereafter, in step (1-4), the back surface of the semiconductor substrate 114 is cut to a thickness of about several tens of microns. In addition, the figure of (1-4) shows the state which reversed the figure of (1-3).

  Next, in step (1-5), a through hole 117 connected to a predetermined position of the element wiring layer 112 is formed by photolithography, etching, or the like. Thereafter, an oxide film is formed by thermal oxidation, and a barrier and a seed layer are formed by sputtering or CVD. Subsequently, in step (1-6), a photosensitive resist 118 such as a dry film is attached on the semiconductor substrate 114, and thereafter an opening is formed on the through hole 117 by a photolithography process.

  Next, in step (1-7), after electroplating, the photosensitive resist 118 and unnecessary barrier and seed layers are etched to form the through wiring 119. Subsequently, in step (1-8), after the dicing tape 120 is attached to the semiconductor substrate 114, the support substrate 116 is peeled off.

  Thereafter, in step (1-9), the semiconductor substrate 114 is diced. Thereafter, the dicing tape 120 is removed to form individual semiconductor chips 121 with through wiring. These semiconductor chips 121 are stacked on the interposer 107 as in the semiconductor chip 121 of FIG. 1, and the insulating resin 104 is filled between the interposer 107 and the lowermost semiconductor chip. The filled resin 104 moves upward (penetrates) and fills the gaps of all the semiconductor chips.

  At present, in order to thinly process a semiconductor chip laminated on the interposer 107 (50 microns or less), the conventional semiconductor device manufactured by the process shown in FIGS. 1 to 4 has various films formed on the chip. The warp occurs in the semiconductor chip due to the stress. In particular, when the number of stacked semiconductor chips increases, the warpage stress of the semiconductor chips is accumulated, and the overall warpage increases. Further, when the lamination condition is inappropriate, the warping stress is further increased. If the warpage of the semiconductor chip becomes large, there is a possibility that the bump bonding portion around the chip is destroyed.

  The warpage (deformation) of the semiconductor chip starts when the support is removed (wafer state) and remains warped even after dicing into individual pieces. The warped semiconductor chip is sucked and flattened by a jig and stacked.

Further, since the insulating resin 104 is filled from between the interposer 107 and the lowermost semiconductor chip, the filling property of the insulating resin becomes worse as the number of stacked chips increases. As a result, there are problems such as unfilling and generation of voids. Japanese Patent Application Laid-Open No. 2004-288721 discloses a technique for suppressing the generation of voids in an insulating resin.
JP 2004-288721 A

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a structure of a semiconductor device capable of reducing or suppressing deformation (warping) of a semiconductor chip stacked on an interposer and a method for manufacturing the same. And

  It is another object of the present invention to provide a structure of a semiconductor device and a manufacturing method that contribute to improving the filling property of an insulating resin between a plurality of stacked semiconductor chips.

  To achieve the above object, a semiconductor device according to a first aspect of the present invention includes an interposer; a plurality of semiconductor chips (functional chips) stacked on the interposer; and an insulation filled between the semiconductor chips. An adhesive resin portion. The semiconductor chip includes: a semiconductor substrate; a through wiring penetrating the semiconductor substrate; a connection bump connected to the through wiring and electrically connected to another semiconductor chip; and the through wiring is electrically And a plurality of dummy bumps provided outside the connection bumps.

  The semiconductor device manufacturing method according to the second aspect of the present invention is applied to a semiconductor device manufacturing method in which a plurality of semiconductor chips are stacked on an interposer and an insulating resin is filled between the semiconductor chips. The Then, each of the semiconductor chips is manufactured by a step of forming a through wire on a semiconductor substrate; a step of forming a connection bump connected to the through wire; and a step of forming the connection bump in the same step as the formation of the connection bump. And a step of forming a plurality of dummy bumps electrically independent from the through wiring on the outside.

  The semiconductor device manufacturing method according to the third aspect of the present invention is applied to a semiconductor device manufacturing method in which a plurality of semiconductor chips are stacked on an interposer and an insulating resin is filled between the semiconductor chips. Here, the manufacturing of each of the semiconductor chips includes the step of forming a through wiring on a semiconductor substrate; the step of forming a connection bump connected to the through wiring; and the same step as the formation of the connection bump. Forming a plurality of dummy bumps electrically independent from the through wiring on the outside; forming a plurality of through holes along dicing lines on the semiconductor substrate; dicing along the through holes And a step of forming individual semiconductor chips. Then, a plurality of notches are formed on the side of the semiconductor chip by the dicing. Furthermore, after laminating the semiconductor chip on the interposer, the insulating resin is injected from the direction in which the plurality of notches are formed.

  According to the present invention configured as described above, the presence of the reinforcing dummy bumps improves the bonding strength between the stacked semiconductor chips and reduces the warping stress of the semiconductor chips. Thereby, destruction of a bump junction part can be prevented.

  Further, in the semiconductor device according to the present invention, since the insulating resin is transmitted between the dummy bumps through the dummy bumps, the filling efficiency of the insulating resin is improved. Furthermore, according to the method for manufacturing a semiconductor device according to the third aspect of the present invention, the insulating resin is efficiently filled into the inside of the semiconductor chip stacked body by capillary action from the notch formed in the side surface of the semiconductor chip.

  FIG. 5 shows a cross-sectional structure of a semiconductor device according to the present invention in which a plurality of semiconductor chips having through wirings are stacked. Through wirings 202 are formed in the plurality of functional chip substrates 221 and are electrically connected to the internal integrated circuit. The plurality of functional chip substrates 221 are electrically connected to each other through metal bumps 203. Insulating resin 204 is filled between functional chip substrates 221 for the purpose of improving mechanical strength. The plurality of functional chip groups 205 are mounted on electrode portions 208 of a mounting mounting chip (interposer) 207 having through wirings 206 via metal bumps 209. On the mounting surface 210 opposite to the chip mounting surface of the interposer 207, solder terminals 211 for mounting the substrate are formed.

  The thickness of the semiconductor chip 221 is about 20 μm to 100 μm. On the other hand, the thickness of the interposer 207 is about 200 μm to 400 μm. In this embodiment, for example, the thickness of the semiconductor chip 221 is 50 μm, and the thickness of the interposer 207 is 300 μm. Thus, by increasing the thickness of the interposer 107, the warp of the semiconductor chip 221 stacked on the interposer 107 can be reduced.

  In addition to the metal bump 203, a plurality of dummy bumps 230 are formed on each semiconductor chip 221 outside the metal bump 203. The dummy bumps 230 are formed around the outer periphery (outer edge) of the semiconductor chip 221. The dummy bumps 230 are electrically independent from the internal integrated circuit and other semiconductor chips, unlike the metal bumps 203 that are electrically connected to the internal integrated circuit and other semiconductor chips.

  7 to 9 show a process of forming a semiconductor chip (221) applied to the semiconductor device according to the first embodiment of the present invention. First, in step (2-1), the element wiring layer 212 and the protective layer 213 are formed on the semiconductor substrate 214 by steps such as sputtering, photolithography, plating, and etching.

  Next, in step (2-2), surface metal bumps 215a and dummy bumps 215b connected to the element wiring layer 212 are formed on the semiconductor substrate 214 in the same step. At this time, the dummy bumps 215b are preferably formed in the vicinity of the chip edge as shown in FIG.

  Subsequently, in step (2-3), a support substrate 216 such as glass is attached to the surface of the semiconductor substrate 214. Thereafter, in step (2-4), the back surface of the semiconductor substrate 214 is cut to a thickness of about several tens of microns. In addition, the figure of (2-4) shows the state which reversed the figure of (2-3).

  Next, in step (2-5), a through hole 217 connected to a predetermined position of the element wiring layer 212 is formed by photolithography, etching, or the like. Thereafter, an oxide film is formed by thermal oxidation, and a barrier and a seed layer are formed by sputtering or CVD. Subsequently, in step (2-6), a photosensitive resist 218 such as a dry film is attached on the semiconductor substrate 214, and thereafter, an opening 217a is formed on the through hole 217 by a photolithography process. When the opening 217a is formed on the through hole 217, the opening 217b is also formed at a position corresponding to the dummy bump 215b.

  Next, in step (2-7), after electroplating, the photosensitive resist 218 and unnecessary barrier and seed layers are etched to form through wirings 219. Subsequently, in the step (2-8), after attaching 220 to the dicing tape on the semiconductor substrate 214, the support substrate 216 is peeled off.

  Next, in step (2-9), dicing is performed on the semiconductor substrate 214. Thereafter, the dicing tape 210 is removed to form individual semiconductor chips 221 with through wiring.

  The semiconductor chip 221 manufactured as described above is stacked on the interposer 207 like the semiconductor chip 221 of FIG. At this time, the stacked semiconductor chips 221 and the semiconductor chips 221 and the interposer 207 are connected not only by the metal bumps 215a (204) but also by the dummy bumps 215b (203), so that the connection strength can be improved. It should be noted that the formation position and the number of dummy bumps are preferably close to the edge of the semiconductor chip without obstructing the formation of the metal bumps.

  After stacking the semiconductor chips 221 one by one on the interposer 107, the filler 400 is used to fill the insulating resin 104 between the interposer 107 and the lowermost semiconductor chip 221. This is shown in FIG. The filled resin 104 moves upward (penetrates) and fills the gaps of all the semiconductor chips. In the present embodiment, since the dummy bumps are formed on each semiconductor chip, the resin is satisfactorily filled between the semiconductor chips through the dummy bumps. This is presumably because when the surface tension of the resin is lowered, the resin is likely to wet and spread on the solid surface.

  FIG. 10 shows a cross-sectional structure of a semiconductor device according to the second embodiment of the present invention in which a plurality of semiconductor chips having through wirings are stacked. Through wirings 302 are formed in the plurality of functional chip substrates 321 and are electrically connected to the internal integrated circuit. The plurality of functional chip substrates 321 are electrically connected to each other through metal bumps 303. Insulating resin 304 is filled between functional chip substrates 321 for the purpose of improving mechanical strength. The plurality of functional chips 305 are mounted on electrode portions 308 of a mounting mounting chip (interposer) 307 having through wirings 306 via metal bumps 309. On the mounting surface 310 opposite to the chip mounting surface of the interposer 307, solder terminals 311 for mounting the substrate are formed.

  The thickness of the semiconductor chip 221 is about 20 μm to 100 μm. On the other hand, the thickness of the interposer 207 is about 200 μm to 400 μm. In this embodiment, for example, the thickness of the semiconductor chip 221 is 50 μm, and the thickness of the interposer 207 is 300 μm. Thus, by increasing the thickness of the interposer 107, the warp of the semiconductor chip 221 stacked on the interposer 107 can be reduced.

  In addition to the metal bumps 203, a plurality of dummy bumps 330 are formed on each semiconductor chip 321 outside the metal bumps 303. The dummy bumps 330 are formed around the outer periphery (outer edge) of the semiconductor chip 221.

  FIG. 11 is a plan view showing the structure of a semiconductor chip applied to a semiconductor device according to the second embodiment of the present invention. FIG. 12 is an explanatory view showing the structure of the main part of a semiconductor chip applied to the semiconductor device according to the second embodiment of the present invention. Cutouts 301 a are formed on the two side surfaces (sides) of the semiconductor chip 321. The positional relationship between the notch 301a and the dummy bump 330 can be as shown in FIGS. In the case of (A), dummy bumps 330 are formed inside notches 301 a formed at substantially equal intervals on the edge portion of the semiconductor substrate 314. In the case of (B), dummy bumps 330 are formed between the notches 301 a formed at substantially equal intervals on the edge portion of the semiconductor substrate 314.

  13 to 15 show a manufacturing process of the semiconductor chip 321 applied to the semiconductor device according to the second embodiment of the present invention. First, in step (3-1), the element wiring layer 312 and the protective layer 313 are formed on the semiconductor substrate 314 by steps such as sputtering, photolithography, plating, and etching.

  Next, in step (3-2), surface metal bumps 315a and dummy bumps 315b connected to the element wiring layer 312 are formed on the semiconductor substrate 314 in the same step. At this time, the dummy bumps 315b are preferably formed near the chip edge as shown in FIGS.

  Subsequently, in step (3-3), a support substrate 316 such as glass is attached to the surface of the semiconductor substrate 314. Thereafter, in the step (3-4), the back surface of the semiconductor substrate 314 is cut to a thickness of about several tens of microns. In addition, the figure of (3-4) shows the state which reversed the figure of (3-3).

  Next, in step (3-5), a through hole 317 connected to a predetermined position of the element wiring layer 312 is formed by photolithography, etching, or the like. At the same time, a plurality of through-holes 311 that are several tens of microns wider than the dicing width are formed on the dicing line using a photomask pattern.

  Thereafter, an oxide film is formed by thermal oxidation, and a barrier and a seed layer are formed by sputtering or CVD. Subsequently, in step (3-6), a photosensitive resist 318 such as a dry film is attached onto the semiconductor substrate 314, and thereafter an opening 317a is formed on the through hole 317 by a photolithography process. When the opening 317a is formed on the through hole 317, the opening 317b is also formed at a position corresponding to the dummy bump 315b.

  Next, in step (3-7), after electroplating, the photosensitive resist 318 and unnecessary barriers and seed layers are etched to form through wirings 319. Subsequently, in step (3-8), the dicing tape 320 is attached on the semiconductor substrate 314, and then the support substrate 316 is peeled off.

  Here, FIG. 16 shows a state of the wafer 10 on which semiconductor chips are formed. When the state before dicing is viewed in plan, it can be seen that through-holes 311 are formed on the two side surfaces (sides) of each chip formation region 342 as shown in FIG. FIG. 17 is an enlarged view of a range X surrounded by a broken-line circle in FIG.

  The position of the through hole 311 with respect to the chip formation region 342 basically corresponds to the resin injection location in the semiconductor device. Therefore, it is possible to form the through hole on one side surface (one side) or three side surfaces (three sides) of the chip formation region 342. It is also possible to form the through-hole 311 over the entire periphery of the chip formation region 342 and fill the resin from one side surface (side), two side surfaces, or three side surfaces. However, if the resin is filled (injected) from all four side surfaces (four sides) of the semiconductor chip, there is no possibility of air escape between the stacked semiconductor chips, which may cause voids.

  Next, dicing is performed on the semiconductor substrate 314 in step (3-9). At this time, the dicing cutter passes over the line in which the through holes 311 are arranged. Thereafter, the dicing tape 310 is removed to form individual semiconductor chips 321 with through wiring. When the state after dicing is viewed in plan, it can be seen that notches 311a are formed on the two side surfaces (sides) of each chip 321 as shown in FIG. FIG. 18 corresponds to a range X surrounded by a broken-line circle in FIG.

  The semiconductor chips 321 manufactured as described above are sequentially stacked on the interposer 307 as shown in FIGS. Here, as shown in FIGS. 20 and 21, after the semiconductor chips 321 are stacked one by one on the interposer 107, the filler 400 is used to insulate from the interposer 107 and the lowermost semiconductor chip 321. Resin 104 is filled. In this embodiment, since the plurality of notches 311a are formed on the side surface of the semiconductor chip 321 stacked in a plurality of stages, the filling property of the insulating resin 304 is improved. That is, the resin 304 can easily enter the inside of the chip due to capillary action. The filled resin 304 moves (penetrates) upward and fills the gaps of all the semiconductor chips.

  In this embodiment, since the dummy bumps 330 (315b) are provided on each semiconductor chip 321, the resin is well filled between the semiconductor chips through the dummy bumps 330 (315b). This is presumably because when the surface tension of the resin is lowered, the resin is likely to wet and spread on the solid surface.

  Here, the physical properties of the insulating resin and the shape and size of the notch 311a will be considered. The capillary phenomenon due to the notch 311a formed on the side surface of the semiconductor chip is affected by the physical properties of the resin injected therefrom and the shape and size of the notch 311a. The insulating resin is usually determined in terms of viscosity (viscosity) and the size of filler particles contained in consideration of the upper and lower chip intervals (about 20 μm) of the stacked semiconductor chips. FIG. 19 shows a variation of the notch shape on the side surface of the semiconductor chip applicable to the present invention. In the second embodiment, (A) is adopted.

  For example, when the upper and lower chip intervals of the semiconductor chips stacked on the interposer are 20 μm, the viscosity of the filled insulating resin (epoxy resin) is 9 Pas, and the size of the filler particles contained is an average of 0.3 μm (maximum 1 μm). In such a situation, the width W of the notch formed on the side surface of the semiconductor chip is approximately equal to the upper and lower chip intervals in order to satisfactorily exhibit the capillary phenomenon due to the notch (inject resin efficiently) ( 20 μm) or less is preferable. Moreover, it is preferable that the space | interval D of the notch formed at substantially the same space | interval shall be 20-40 micrometers. This is because the mechanical strength at the side surface of the semiconductor chip is insufficient when the distance D is 20 μm or less. The dicing width (dicing blade width) is about 40-50 μm.

  As mentioned above, although the Example of this invention was described, this invention is not limited to these Examples at all, It can change in the category of the technical idea shown by the claim.

FIG. 1 is a cross-sectional view showing the structure of a conventional semiconductor device in which a plurality of semiconductor chips are stacked. FIG. 2 is a partial cross-sectional view showing a reference example of a manufacturing process of a semiconductor device. FIG. 3 is a partial cross-sectional view showing a reference example of a manufacturing process of a semiconductor device. FIG. 4 is a partial cross-sectional view showing a reference example of a manufacturing process of a semiconductor device. FIG. 5 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention formed by laminating a plurality of semiconductor chips. FIG. 6 is a plan view showing the structure of a semiconductor chip applied to the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the present invention. FIG. 8 is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the present invention. FIG. 9 is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the present invention. FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention formed by stacking a plurality of semiconductor chips. FIG. 11 is a plan view showing the structure of a semiconductor chip applied to a semiconductor device according to the second embodiment of the present invention. FIG. 12 is an explanatory view showing the structure of the main part of a semiconductor chip applied to the semiconductor device according to the second embodiment of the present invention. FIG. 13 is a partial cross-sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. FIG. 14 is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to the second example of the present invention. FIG. 15 is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to the second example of the present invention. FIG. 16 is an explanatory view showing a semiconductor wafer used for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 17 is an explanatory view (plan view) showing the state of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 18 is an explanatory view (plan view) showing the state of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 19 is an enlarged plan view showing an example of a notch shape on the chip side surface of the semiconductor device applicable to the second embodiment of the present invention. FIG. 20 is an explanatory view (plan view) showing the state of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 21 is an explanatory view showing the state of the manufacturing process (resin filling) of the semiconductor device according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 104 Insulating resin 107 Interposer 211 Through-hole 211a Notch 221,321 Semiconductor chip

Claims (13)

With an interposer;
A plurality of semiconductor chips having internal integrated circuits stacked on the interposer;
An insulating resin portion filled between the semiconductor chips,
The semiconductor chip includes: a semiconductor substrate; a through wiring penetrating the semiconductor substrate; a connection bump connected to the through wiring and electrically connected to another semiconductor chip; the internal integrated circuit and the other semiconductor A semiconductor device comprising a plurality of dummy bumps that are electrically independent of a chip and provided outside the connection bumps.   The semiconductor device according to claim 1, wherein the dummy bump is provided in the vicinity of an outer peripheral portion of the semiconductor chip.   3. The semiconductor device according to claim 1, wherein each of the plurality of semiconductor chips has a plurality of notches recessed inward on at least a side side into which an insulating resin is injected.   4. The semiconductor device according to claim 3, wherein the opening width of the notch is set to a size such that the insulating resin is guided between the semiconductor chips by capillary action.   5. The semiconductor device according to claim 3, wherein an opening width of the notch is set to be approximately equal to an interval between upper and lower chips of the plurality of stacked semiconductor chips.   6. The semiconductor device according to claim 1, wherein the interposer is thicker than each of the plurality of semiconductor chips. In a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked on an interposer and an insulating resin is filled between the semiconductor chips.
Each of the semiconductor chips is manufactured by forming a through-wiring on a semiconductor substrate; forming a connection bump connected to the through-wiring; and outside the connection bump in the same process as the formation of the connection bump. And a step of forming a plurality of dummy bumps electrically independent from the through wiring.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the dummy bump is provided in the vicinity of an outer peripheral portion of the semiconductor chip.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the interposer is thicker than each of the plurality of semiconductor chips. In a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked on an interposer and an insulating resin is filled between the semiconductor chips.
Each of the semiconductor chips is manufactured by forming a through-wiring on a semiconductor substrate; forming a connection bump connected to the through-wiring; and outside the connection bump in the same process as the formation of the connection bump. Forming a plurality of dummy bumps electrically independent from the through wiring; forming a plurality of through holes along dicing lines on the semiconductor substrate; and dicing along the through holes to individually Forming a semiconductor chip of
A plurality of notches are formed on the side of the semiconductor chip by the dicing,
After the semiconductor chip is stacked on the interposer, the insulating resin is injected from the direction in which the plurality of notches are formed.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the opening width of the notch is set to a size such that the insulating resin is guided between the semiconductor chips by a capillary phenomenon.   12. The method of manufacturing a semiconductor device according to claim 10, wherein an opening width of the notch is set to be approximately equal to an interval between upper and lower chips of the stacked semiconductor chips. The method of manufacturing a semiconductor device according to claim 10, wherein the interposer is thicker than each of the plurality of semiconductor chips.

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