JP2008270354A - Manufacturing method of three-dimensional semiconductor device, manufacturing method of substrate product, substrate product, and three-dimensional semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of three-dimensional semiconductor device for easily forming interlayer wirings formed of metal materials, a manufacturing method of substrate product, a substrate product, and a three-dimensional semiconductor device. <P>SOLUTION: The manufacturing method comprises a step to form a hole 82 having the bottom on the front surface 80a of a silicon substrate 80, a step to embed the hole 82 with a sacrifice material 85, a step to form an integrated circuit for forming an integrated circuit layer 90 on the front surface 80a of the silicon substrate 80, a step for exposing a part of the sacrifice material 85 from the rear surface 80b of the silicon substrate 80 through the hole 82 by thinning the silicon substrate 80 from the rear surface 80b of the silicon substrate 80, a step to form an interlayer wiring by removing the sacrifice material 85 and embedding a metal material, and a step to stack the silicon substrate 80 on the other substrate to electrically connect a circuit of the integrated circuit layer 90 to a circuit of the other substrate via the interlayer wiring. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a three-dimensional semiconductor device, a method for manufacturing a substrate product, a substrate product, and a three-dimensional semiconductor device.

  There has been proposed a three-dimensional semiconductor device having a structure in which a plurality of silicon substrates having integrated circuits formed on the surface thereof are thinned and stacked. Such a three-dimensional semiconductor device contributes to further integration of IC chips. In addition, when integrating arithmetic processing circuits and memories having different dimensions such as gate lengths, the arithmetic processing circuit and the memory are formed on separate silicon substrates, and these silicon substrates are overlapped to electrically connect each other. By connecting, the process can be simplified as compared with the case where the arithmetic processing circuit and the memory are formed on a single silicon substrate.

  Conventionally, in such a three-dimensional semiconductor device, wire bonding is used for electrical connection between the substrates. However, in the connection method by wire bonding, the peripheral portion of the substrate that becomes a space for wire bonding needs to be exposed when viewed from the stacking direction, and the area of the upper layer substrate becomes smaller as the number of stacked layers increases. In addition, a signal delay occurs due to the inductance of the wire, which hinders high-speed operation of the integrated circuit. Recently, in order to solve these problems, use of interlayer wiring (via) penetrating each substrate has been studied.

As a method for forming the interlayer wiring, the following method has been proposed. That is, it is a method described in Non-Patent Document 1, in which (1) a bottomed hole (hole) is formed on the surface of the silicon substrate, (2) an insulating film is formed on the inner surface of this hole, and (3 (4) Polycrystalline silicon used as an interlayer wiring is buried in this hole, (4) An integrated circuit is formed on the surface of the silicon substrate, and (5) The silicon substrate is thinned from the back side until the polycrystalline silicon is exposed. To penetrate.
M. Kawano et al., “A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer”, International Electron Devices Meeting (IEDM) 2006, program No. 21.5

  In the above-described method for forming the interlayer wiring, since the hole for the interlayer wiring and the insulating film are formed before the silicon substrate is thinned, the wafer-like silicon substrate is easily handled and the process is facilitated. However, in this method, an integrated circuit is formed in a state where a material for an interlayer wiring is embedded in a silicon substrate. However, when forming the integrated circuit, a high-temperature heat treatment is performed to add impurities to the semiconductor. Therefore, it is necessary to select a material that can withstand the temperature rise during the heat treatment as the interlayer wiring material, and for example, polycrystalline silicon is used instead of a metal such as copper. However, polycrystalline silicon has a higher resistivity than metal and hinders high-speed operation of integrated circuits.

  As another method, (1) an integrated circuit is formed on the surface of the silicon substrate, (2) the silicon substrate is thinned from the back surface side, and (3) a through hole is formed by etching the silicon substrate from the back surface side. (4) An insulating film is formed on the inner surface of the through hole, and (5) a metal to be an interlayer wiring is embedded in the through hole. In this method, after forming an integrated circuit on a silicon substrate, an interlayer wiring material is embedded in the silicon substrate. Therefore, a metal such as copper can be used as the interlayer wiring material, and the interlayer wiring can have a low resistivity. However, since the through hole for the interlayer wiring is formed after the silicon substrate is thinned, it is difficult to chuck and transport the thinned silicon substrate. There is also a method of attaching to a thin glass substrate with an adhesive, but since the heat-resistant temperature of the adhesive is limited to about 150 ° C, it is difficult to form an insulating film such as a silicon oxide film on the sidewall that requires high temperature It is. Further, when performing dry etching for drilling, a loss of bias power occurs in the glass substrate, and it is difficult to realize etching at high speed and high anisotropy.

  The present invention has been made in view of the above-described problems, and a method for manufacturing a three-dimensional semiconductor device, a method for manufacturing a substrate product, a substrate product, and a three-dimensional semiconductor capable of easily forming an interlayer wiring made of metal. The purpose is to provide a device.

  In order to solve the above-described problems, a manufacturing method of a three-dimensional semiconductor device according to the present invention includes a hole forming step of forming a bottomed hole on a surface of a substrate, a filling step of filling a hole with a sacrificial material, and a sacrificial material Forming an integrated circuit having a wiring pattern in contact with the substrate on the surface of the substrate and thinning the substrate from the back surface of the substrate, thereby penetrating the hole and exposing a part of the sacrificial material from the back surface of the substrate. A thinning process, a wiring forming process for forming an interlayer wiring penetrating the substrate by removing a sacrificial material and embedding a metal material; and stacking the substrate on another substrate, and an integrated circuit and a circuit on the other substrate, And a laminating step for electrically connecting the two through an interlayer wiring.

  In this method of manufacturing a three-dimensional semiconductor device, an integrated circuit is formed in a state where a sacrificial material is embedded at a location where an interlayer wiring penetrating the substrate is formed. Note that the sacrificial material may be any material that can withstand heat treatment in forming the integrated circuit and can be selectively removed in the wiring formation step. After the substrate is thinned, the sacrificial material is removed and a metal material is embedded to form an interlayer wiring that penetrates the substrate. That is, since the interlayer wiring is formed after the integrated circuit is formed, a metal can be used as the wiring material, and the interlayer wiring can have a low resistivity. In addition, since the hole for embedding the wiring material is formed before the thinning step, the substrate can be easily chucked and transported. Therefore, according to the above-described method for manufacturing a three-dimensional semiconductor device, an interlayer wiring made of metal can be easily formed.

  The three-dimensional semiconductor device manufacturing method may further include an insulating film forming step for forming an insulating film on the inner surface of the hole between the hole forming step and the embedding step. In this case, it is preferable that the substrate is a silicon substrate and the insulating film is a silicon oxide film. Generally, when an insulating film (especially a silicon oxide film) is formed on the inner surface of a fine hole formed in the substrate, it is preferable that the insulating film is uniformly formed on the inner surface as the temperature is increased. However, in the latter method described in the [Background Art] column, for example, an insulating film is formed on the inner surface of the through hole after the substrate is thinned. When the insulating film is formed on the thinned substrate, however, Requires that the substrate be attached to some support material. And when sticking a board | substrate to a support material, adhesive agents, such as resin, are used, but such an adhesive agent generally has low heat resistance. Therefore, it is difficult to raise the temperature sufficiently when forming the insulating film, and it is difficult to uniformly form the insulating film on the inner surface of the minute hole. On the other hand, according to the manufacturing method described above, since the insulating film on the inner surface of the hole can be formed before the thinning step, there is no need to bond the substrate to the support material, and the temperature is sufficiently high when forming the insulating film. The insulating film can be formed uniformly.

  The three-dimensional semiconductor device manufacturing method includes a first portion in which the hole formed in the hole forming step extends from the surface of the substrate in the thickness direction of the substrate, and a second portion having a larger inner diameter than the first portion. It is good also as having. In the above three-dimensional semiconductor device manufacturing method, the hole is penetrated by thinning the substrate from the back surface (thinning step). At this time, since the hole has the first and second portions described above, the inner diameter on the back surface side of the penetrated hole becomes larger than the inner diameter on the front surface side. That is, in the subsequent wiring formation step, the diameter of the interlayer wiring on the back surface of the substrate becomes larger than the diameter of the interlayer wiring on the surface of the substrate. Therefore, when the back surface of the substrate is bonded to another substrate in the stacking process, the alignment accuracy between the substrate and the other substrate can be relaxed.

  In the method for manufacturing a three-dimensional semiconductor device, the sacrificial material may include at least one of polycrystalline silicon and silicon germanium. Accordingly, the hole can be suitably filled with a material that can withstand heat treatment in forming the integrated circuit and can be selectively removed in the wiring formation process.

  In addition, a method for manufacturing a substrate product according to the present invention includes an integrated circuit having a hole forming step of forming a bottomed hole on the surface of the substrate, a filling step of filling the hole with a sacrificial material, and a wiring pattern in contact with the sacrificial material Forming an integrated circuit on the surface of the substrate, thinning the substrate from the back surface of the substrate, thereby thinning the hole to penetrate and exposing a part of the sacrificial material from the back surface of the substrate, and a sacrificial material And a wiring formation step of forming an interlayer wiring penetrating the substrate by removing and embedding a metal material.

  In this method of manufacturing a substrate product, an integrated circuit is formed in a state where a sacrificial material is embedded at a location where an interlayer wiring penetrating the substrate is formed. After the substrate is thinned, the sacrificial material is removed and a metal material is embedded to form an interlayer wiring that penetrates the substrate. That is, since the interlayer wiring is formed after the integrated circuit is formed, a metal can be used as the wiring material, and the interlayer wiring can have a low resistivity. In addition, since the hole for embedding the wiring material is formed before the thinning step, the substrate can be easily chucked and transported. Therefore, according to the above-described method for manufacturing a substrate product, an interlayer wiring made of metal can be easily formed.

  The substrate product according to the present invention includes a substrate, an integrated circuit provided on the surface of the substrate, and an interlayer wiring penetrating the substrate, and the interlayer wiring forms a bottomed hole on the surface of the substrate, After the hole is filled with the sacrificial material and an integrated circuit having a wiring pattern in contact with the sacrificial material is formed on the surface of the substrate, the substrate is thinned from the back surface of the substrate to penetrate the hole, and a part of the sacrificial material from the back surface of the substrate It is characterized by being formed by exposing the substrate, removing the sacrificial material, and embedding a metal material.

  In this substrate product, since the interlayer wiring is formed after the integrated circuit is formed, a metal can be used as a wiring material, and the interlayer wiring can have a low resistivity. In addition, since the hole for embedding the interlayer wiring is formed before the substrate is thinned, the substrate can be easily chucked and transported. Therefore, according to the first substrate product, the interlayer wiring made of metal can be easily formed.

  The substrate product may be characterized in that the sacrificial material includes at least one of polycrystalline silicon and silicon germanium. This makes it possible to suitably fill the hole with a material that can withstand heat treatment when the integrated circuit is formed and can be selectively removed.

  The substrate product may be characterized in that the diameter of the interlayer wiring on the back surface of the substrate is larger than the diameter of the interlayer wiring on the surface of the substrate. In such a substrate product, a bottomed hole having a first portion extending from the surface of the substrate in the thickness direction of the substrate and a second portion having an inner diameter larger than the first portion is formed on the surface of the substrate. By doing so, it is easily formed. According to the second substrate product having such a configuration, the accuracy of alignment between the substrate product and the other substrate can be relaxed when the substrate product is bonded to the other substrate.

  The substrate product may further include an insulating film between the substrate and the interlayer wiring. In this case, it is preferable that the substrate is a silicon substrate and the insulating film is a silicon oxide film. As described above, when an insulating film (especially a silicon oxide film) is formed on the inner surface of a fine hole formed in the substrate, it is preferable that the insulating film is uniformly formed on the inner surface as the temperature is increased. In the first or second substrate product described above, by forming the insulating film on the inner surface of the hole before thinning the substrate, it is not necessary to adhere the substrate to the support material when forming the insulating film. The temperature can be raised sufficiently, and this insulating film can be formed uniformly.

  The three-dimensional semiconductor device according to the present invention is formed by stacking any of the above-mentioned substrate products on another substrate, and electrically connecting the integrated circuit and the circuit on the other substrate via an interlayer wiring. It is characterized by that. According to this three-dimensional semiconductor device, an interlayer wiring made of metal can be easily formed by providing any of the above-described substrate products.

  According to the method for manufacturing a three-dimensional semiconductor device, the method for manufacturing a substrate product, the substrate product, and the three-dimensional semiconductor device according to the present invention, an interlayer wiring made of metal can be easily formed.

  Hereinafter, embodiments of a method for manufacturing a three-dimensional semiconductor device, a method for manufacturing a substrate product, a substrate product, and a three-dimensional semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a side sectional view showing a configuration of an embodiment of a three-dimensional semiconductor device according to the present invention. A three-dimensional semiconductor device 1 shown in FIG. 1 includes a build-up substrate 20 and a plurality of substrate products 10 stacked on the build-up substrate 20. In addition, as an application example of such a three-dimensional semiconductor device 1, for example, a plurality of types of memory circuits such as flash memory and RAM formed on different substrates are stacked in the thickness direction of the substrate and configured as one chip. Or a large-capacity memory chip by stacking a single type of memory circuit in the thickness direction of the substrate, or an arithmetic processing circuit and a memory circuit formed on different substrates in the thickness direction of the substrate. For example, they are stacked and electrically connected to each other. Specifically, it is suitable for a combination of a logic portion of a microprocessor used in a personal computer or a server and an SRAM cache memory, a combination of a graphic processor and a DRAM, or the like.

  FIG. 2 is a side sectional view showing the configuration of one substrate product 10. As shown in FIG. 2, the substrate product 10 includes a substrate 30, an integrated circuit layer 40, and interlayer wiring 50.

  The substrate 30 is a thin film substrate having a front surface 30a and a back surface 30b intersecting with the stacking direction of the three-dimensional semiconductor device 1, and is made of, for example, silicon (Si). The thickness of the substrate 30 is, for example, 3 [μm] to 100 [μm]. The substrate 30 is formed by grinding a silicon wafer having a thickness of about 700 [μm] into a thin film by CMP (Chemical Mechanical Polishing) in a manufacturing process described later.

  The integrated circuit layer 40 is a layer in which a plurality of semiconductor elements 41 such as transistors and a wiring pattern 42 for connecting the plurality of semiconductor elements 41 to each other or another circuit are formed. The plurality of semiconductor elements 41 are formed side by side on the surface 30a of the substrate 30, and are covered with a lower layer portion of an insulating layer 43 made of a silicon oxide film. The wiring pattern 42 is mainly composed of a low resistivity metal such as copper (Cu), aluminum (Al), gold (Au), or silver (Ag). The wiring pattern 42 is mainly embedded in the upper layer portion of the insulating layer 43. A part of the wiring pattern 42 is exposed from the insulating layer 43, and bumps (electrodes) 60 are provided on the exposed part. As a constituent material of the bump 60, for example, gold (Au), copper (Cu), tin (Sn), silver (Ag), or an alloy of tin and silver is preferable.

  The other part of the wiring pattern 42 extends from the upper layer portion of the integrated circuit layer 40 to the lower layer portion close to the substrate 30 and is electrically connected to the interlayer wiring 50. Note that a portion of the wiring pattern 42 disposed in the lower layer portion of the integrated circuit layer 40 has a barrier metal film 42 a, and this barrier metal film 42 a is composed of copper, aluminum, gold, which mainly constitute the wiring pattern 42. The metal is disposed between the metal such as silver and the insulating layer 43 to prevent the metal from diffusing into the insulating layer 43.

  The interlayer wiring 50 is a wiring penetrating between the front surface 30 a and the back surface 30 b of the substrate 30. The interlayer wiring 50 according to the present embodiment includes a main part 50a made of a metal such as copper, gold, aluminum, silver, and tungsten (W), and a barrier metal film 50b disposed between the main part 50a and the substrate 30. Has been. The main portion 50a extends in the thickness direction of the substrate 30, one end on the front surface 30a side is electrically connected to the wiring pattern 42 via the barrier metal film 50b, and the other end on the back surface 30b side is on the back surface 30b. Is exposed from. In addition, the interlayer wiring 50 of the present embodiment has a diameter-enlarged portion 52 having a diameter larger than that of a portion extending from the surface 30 a of the substrate 30 in the thickness direction of the substrate 30. The enlarged diameter portion 52 corresponds to an exposed portion of the interlayer wiring 50 on the back surface 30b. Therefore, the diameter of the interlayer wiring 50 on the back surface 30 b of the substrate 30 is larger than the diameter of the interlayer wiring 50 on the front surface 30 a of the substrate 30.

Further, when the substrate 30 has conductivity, it is preferable to provide an insulating film 70 between the interlayer wiring 50 and the substrate 30 as in the present embodiment. The insulating film 70 is formed, for example, by oxidizing the inner surface of the hole of the substrate 30 on which the interlayer wiring 50 is formed. When the substrate 30 is a silicon substrate, the insulating film 70 is a silicon oxide film (SiO ₂ ). In addition, an insulating film 71 is preferably provided also on the back surface 30 b of the substrate 30. The insulating film 71 is formed using an insulating material such as a silicon oxide film (SiO ₂ ), but may be formed using a material different from the insulating film 70. The interlayer wiring 50 is also exposed from the insulating film 71.

  Refer to FIG. 1 again. The three-dimensional semiconductor device 1 is configured by stacking a plurality of substrate products 10 having the above-described structure in the thickness direction. And the integrated circuit (semiconductor element 41) of each board | substrate product 10 joins the bump 60 provided in the other board | substrate product 10 with respect to the interlayer wiring 50 exposed from the back surface 30b of one board | substrate product 10. Are electrically connected to each other. Further, the interlayer wiring 50 of the lowermost substrate product 10 is electrically connected to a circuit (not shown) of the build-up substrate 20 via bumps 61 provided on the build-up substrate 20. In FIG. 1, the shapes and arrangements of the semiconductor elements 41 and the wiring patterns 42 are similarly depicted in the respective substrate products 10, but the shapes and arrangements of the semiconductor elements 41 and the wiring patterns 42 are mutually different in the respective substrate products 10. It may be different. Therefore, the position where the interlayer wiring 50 is formed on the substrate 30 may be different for each substrate product 10.

  Next, the method for manufacturing the three-dimensional semiconductor device 1 according to the present embodiment will be described with reference to FIGS. Prior to manufacturing the three-dimensional semiconductor device 1, a silicon substrate (silicon wafer) 80 shown in FIG. 3 is prepared. The silicon substrate 80 is made of a silicon single crystal and is sliced into a plate having a thickness of about 700 [μm] having a front surface 80a and a back surface 80b.

<Hole formation process>
As shown in FIG. 4, a silicon oxide film 81 is formed on the surface 80 a of the silicon substrate 80. The silicon oxide film 81 is a film that serves as an etching mask when holes for later-described interlayer wiring are formed by etching. The silicon oxide film 81 is formed by a chemical vapor deposition method such as plasma CVD. Note that a film made of another material (for example, a silicon nitride film) may be formed instead of the silicon oxide film 81 as long as it functions as an etching mask when the silicon substrate 80 is etched.

  Subsequently, as shown in FIG. 5, an opening 81a is formed in the silicon oxide film 81 by using a general photolithography technique. That is, a resist film is applied and formed on the silicon oxide film 81, and the resist film is exposed and developed using a photomask, thereby forming an opening corresponding to the opening 81a in the resist film. By etching the silicon oxide film 81 through the resist mask formed in this way, an opening 81 a is formed in the silicon oxide film 81. At this time, the opening 81a is formed in accordance with the position of the interlayer wiring 50 shown in FIGS. Thereafter, the resist mask is removed.

Subsequently, as shown in FIG. 6, a bottomed hole 82 in which an interlayer wiring material is embedded in a subsequent process is formed in the surface 80 a of the silicon substrate 80. First, anisotropic etching is performed on the silicon substrate 80 through the opening 81a of the silicon oxide film 81 formed in the previous step. As the anisotropic etching, for example, reactive ion etching (RIE) is suitable. At this time, for example, a mixed gas of HBr gas and SF ₆ gas may be used as the etching gas. By this anisotropic etching, a first portion 82a extending from the surface 80a of the silicon substrate 80 in the thickness direction in the hole 82 is formed.

In general, when Si is anisotropically etched using HBr and SF ₆ , a protective film 83 made of a silicon odor oxide film is formed on the side wall by the reaction of an etching product or a gas released from the mask. If the formation of the protective film is insufficient due to the etching conditions, it is possible to actively form the protective film 83 by introducing a gas containing Si such as silane and a gas containing oxygen such as N ₂ O. is there. At this time, by adjusting the bias condition for the substrate, the bottom portion of the hole is exposed and a protective film is formed only on the side wall. After forming the protective film, isotropic etching is performed on the silicon substrate 80. For example, plasma etching is suitable as the isotropic etching. At this time, for example, a gas containing fluorine (SF ₆ gas or the like) may be used as the etching gas. By this isotropic etching, the silicon substrate 80 is isotropically etched from the bottom of the first portion 82a, and the second portion 82b of the hole 82 is formed. The second portion 82 b has a larger inner diameter than the first portion 82 a in the hole 82 and constitutes the bottom of the hole 82. Thereafter, the silicon oxide film 81 and the protective film 83 are removed from the silicon substrate 80 (FIG. 7). For removing the silicon oxide film 81 and the protective film 83, for example, wet etching using NH ₄ F as an etchant is suitable. The hole 82 formed in this way has a depth of 20 [micrometers] from the surface 80a, an inner diameter of the first portion 82a of, for example, 5 [micrometers], and an inner diameter of the second portion. The maximum is 20 [micrometers].

<Insulating film formation process>
Subsequently, as shown in FIG. 8, an insulating film (silicon oxide film) 84 is formed on the surface 80 a of the silicon substrate 80 and the inner surface of the hole 82. The insulating film 84 places the silicon substrate 80 in a high temperature environment such as 900 ° C. to 1000 ° C., for example, and supplies oxygen or a mixed gas of oxygen and hydrogen to thermally oxidize the surface 80 a of the silicon substrate 80 and the inner surface of the hole 82. Good. At this time, the reason why the treatment is performed at a high temperature as described above is to make the insulating film 84 uniformly formed on the inner surface of the fine hole 82.

<Embedding process>
Subsequently, as shown in FIG. 9, the hole 82 of the silicon substrate 80 is filled with a sacrificial material 85. The sacrificial material 85 may be a material that can withstand heat treatment of a semiconductor in an integrated circuit formation process described later and can be selectively removed from the insulating film 84 in a wiring formation process described later. As such a material, for example, a material mainly containing at least one of polycrystalline silicon (polysilicon) and silicon germanium (SiGe) is suitable. In this embedding process, for example, silicon germanium (SiGe) is deposited as the sacrificial material 85 on the surface 80a of the silicon substrate 80 by the CVD method, and the hole 82 is embedded. At this time, a portion of the sacrificial material 85 embedded in the second portion 82 b of the hole 82 becomes an enlarged diameter portion 85 a having a larger diameter than the other portion of the sacrificial material 85. A void (cavity) 85b may be formed inside the sacrificial material 85 embedded in the hole 82 (especially the second portion 82b), but there is no problem.

  Subsequently, a portion of the sacrificial material 85 deposited on the surface 80a of the silicon substrate 80 is removed. Thereafter, the portion of the insulating film 84 deposited on the surface 80a of the silicon substrate 80 is removed. As a method for removing these portions, for example, chemical mechanical polishing (CMP) is suitable. By this step, as shown in FIG. 10, the sacrificial material 85 is exposed from the opening of the hole 82 on the surface 80 a of the silicon substrate 80.

<Integrated circuit formation process>
Subsequently, as shown in FIG. 11, an integrated circuit layer 90 including an integrated circuit is formed on the surface 80 a of the silicon substrate 80. First, a process called a FEOL (Front End of Line), which is centered on a process of forming a plurality of semiconductor elements 86 such as transistors, is performed. That is, various semiconductor layers (for example, a p-type semiconductor layer or an n-type semiconductor layer formed by adding impurities to a predetermined region of the surface 80a of the silicon substrate 80), a gate insulating film, various electrodes, etc. Form. When forming an n-type semiconductor layer or a p-type semiconductor layer, after implanting impurity ions through a photoresist, heat treatment (annealing) is performed to bond the impurity ions to silicon atoms. The silicon substrate 80 is placed in a high temperature environment such as 800 ° C. to 1000 ° C., for example. After forming the semiconductor element 86, a lower layer portion of the insulating layer 87 is formed by depositing a silicon oxide film so as to cover the semiconductor element 86.

  Subsequently, a process called BEOL (Back End of Line), centering on wiring formation after transistor formation, is performed. In this process, a wiring pattern 88 in contact with the sacrificial material 85 is formed. That is, an opening is formed in a portion covering the sacrificial material 85 in the insulating layer 87 formed earlier, and the end face of the sacrificial material 85 is exposed. Then, after forming a barrier metal film 88a on the side and bottom surfaces of the opening, a wiring portion 88b that fills the opening and connects to an electrode of a predetermined semiconductor element 86 is formed. Thereafter, a wiring pattern 88 embedded in the insulating layer 87 is formed by covering wiring layers such as the wiring portions 88c and 88d with an insulating material while being laminated on the wiring portion 88b as necessary. The wiring portions 88b to 88d are preferably formed mainly from a low resistivity metal such as copper (Cu), aluminum (Al), gold (Au), or silver (Ag). Through the above steps, an integrated circuit including a plurality of semiconductor elements 86 and wiring patterns 88 is formed.

  After forming the insulating layer 87 and the wiring pattern 88, an opening is formed at a predetermined position of the insulating layer 87 to expose a part of the wiring pattern 88. For example, gold (Au), copper (Cu), tin (Sn), A bump 89 mainly including silver (Ag) or an alloy of tin and silver is formed.

  The holes 82 and the bumps 89 of the silicon substrate 80 in which the sacrificial material 85 is embedded may be arranged side by side in the thickness direction of the silicon substrate 80 as shown in FIG. 11, or as shown in FIG. The silicon substrate 80 may be disposed at different positions as viewed from the thickness direction. The bump 89 is formed in accordance with the position of the interlayer wiring of another substrate product arranged on the substrate product.

<Thinning process>
Subsequently, the silicon substrate 80 is thinned (thinned) from the back surface 80 b of the silicon substrate 80. Before the thinning, as shown in FIG. 13, the surface 80 a side of the silicon substrate 80, that is, the upper surface of the integrated circuit layer 90 is attached to a glass support material 92 through an adhesive layer 91. As the support member 92, a plate-like member having a flat surface 92a is used, and as the adhesive constituting the adhesive layer 91, a material that can be peeled off by UV irradiation or heat treatment is suitable.

  Subsequently, the back surface 80b of the silicon substrate 80 is polished by grinding until the silicon substrate 80 has a certain thickness (thickness that does not expose the sacrificial material 85, for example, 40 [micrometers]). Next, the back surface 80b of the silicon substrate 80 is polished by chemical mechanical polishing (CMP). As shown in FIG. 14, this chemical mechanical polishing (CMP) is preferably stopped when the insulating film 84 formed at the bottom of the hole 82 appears on the back surface 80b.

Subsequently, dry etching such as plasma etching is performed on the back surface 80b of the silicon substrate 80, and the silicon substrate 80 is further thinned. At this time, for example, SF ₆ may be used as the reactive gas. As a result, the insulating film 84, which is a silicon oxide film, is not etched, and only the silicon substrate 80 is selectively etched. This etching may be stopped in the middle of the second portion 82b of the hole 82 (preferably, the position where the inner diameter of the second portion 82b is maximized). By this step, as shown in FIG. 15, the hole 82 penetrates the silicon substrate 80, and the enlarged diameter portion 85 a of the sacrificial material 85 is exposed from the back surface 80 b of the silicon substrate 80.

<Wiring formation process>
Subsequently, as shown in FIG. 16, a silicon oxide film 93 is formed on the back surface 80 b of the silicon substrate 80. The silicon oxide film 93 is a film that serves as an etching mask when the sacrificial material 85 is removed by etching in a later step. The silicon oxide film 93 is formed by a chemical vapor deposition method such as plasma CVD. Note that a film made of another material (for example, a silicon nitride film) may be formed instead of the silicon oxide film 93 as long as it functions as an etching mask when the sacrificial material 85 is etched.

  Subsequently, as shown in FIG. 17, chemical mechanical polishing (CMP) is performed on the silicon oxide film 93 to flatten the surface on the back surface 80 b side of the silicon substrate 80. At this time, the enlarged diameter portion 85a of the sacrificial material 85 is polished halfway to expose the sacrificial material 85 from the insulating film 84 and to form a lower end surface 85c of the sacrificial material 85. At this time, since the diameter of the lower end surface 85c is equal to the diameter of the enlarged diameter portion 85a, the area of the lower end surface 85c is larger than the area of the upper end surface 85d of the sacrificial material 85.

Subsequently, the sacrificial material 85 is removed from the silicon substrate 80 by etching the exposed sacrificial material 85. As etching at this time, for example, plasma etching is suitable. As the etching gas, for example, a gas containing fluorine (SF ₆ gas or the like) is preferable. However, the insulating film 84 and the silicon oxide film 93 are not etched and only the sacrificial material 85 is etched. If it is. By this etching, the sacrificial material 85 is removed from the silicon substrate 80, and a through hole 94 penetrating between the front surface 80a and the back surface 80b of the silicon substrate 80 is formed as shown in FIG. The through hole 94 has a first portion 94a extending in the thickness direction from the front surface 80a of the silicon substrate 80, and a second portion having an inner diameter larger than that of the first portion 94a and opening toward the back surface 80b of the silicon substrate 80. Part 94b.

  Subsequently, as shown in FIG. 19, a barrier metal film 95 is formed on the inner surface of the through hole 94. As the barrier metal film 95, for example, titanium nitride (TiN) is suitable, and as the method for forming the barrier metal film 95, for example, a CVD method or a PVD method is suitable. The thickness of the barrier metal film 95 is, for example, 300 [nm]. At this time, the barrier metal film 95 is also formed on the surface of the silicon oxide film 93 and the surface of the wiring pattern 88 facing the through hole 94.

  Subsequently, as illustrated in FIG. 20, the metal film 96 is formed on the back surface 80 b of the silicon substrate 80, and the through hole 94 is embedded with the metal material that forms the metal film 96. As the metal film 96, for example, copper (Cu), gold (Au), aluminum (Al), silver (Ag), tungsten (W), or the like is suitable. As a method for depositing these metals, for example, a physical vapor deposition (PVD) method is suitable. Specifically, the silicon substrate 80 is placed in a container filled with a vacuum or an inert gas, a metal vapor deposition source placed in the container is heated and scattered, and deposited on the back surface 80b of the silicon substrate 80. Let

  Subsequently, the barrier metal film 95 and the metal film 96 formed on the back surface 80b of the silicon substrate 80 are removed by chemical mechanical polishing (CMP). Thereby, as shown in FIG. 21, an interlayer wiring 98 constituted by the main portion 97 and the barrier metal film 95 disposed between the main portion 97 and the silicon substrate 80 is completed. That is, the interlayer wiring 98 penetrates between the front surface 80a and the back surface 80b of the silicon substrate 80, one end on the front surface 80a side is electrically connected to the wiring pattern 88, and the other end on the back surface 80b side. Are exposed from the silicon substrate 80 and the silicon oxide film 93. Further, the interlayer wiring 98 has an enlarged diameter portion 99, and the enlarged diameter portion 99 has a diameter larger than that of the portion extending from the surface 80a of the silicon substrate 80 in the thickness direction. Since this enlarged diameter portion 99 corresponds to an exposed portion of the interlayer wiring 98 on the back surface 80 b, the diameter of the interlayer wiring 98 on the back surface 80 b of the silicon substrate 80 is larger than the diameter of the interlayer wiring 98 on the front surface 80 a of the silicon substrate 80. ing. Thus, the substrate product 100A having the configuration shown in FIG. 2 is completed.

<Lamination process>
Subsequently, as shown in FIG. 22, the substrate product 100 </ b> A is mounted on the build-up substrate 101. At this time, the relative position between the buildup substrate 101 and the substrate product 100A is adjusted so that the position of the bump 102 provided on the buildup substrate 101 and the position of the interlayer wiring 98 of the substrate product 100A coincide. Then, the bumps 102 are melted by heating or the like to bond the bumps 102 and the interlayer wiring 98, thereby electrically connecting the integrated circuit of the substrate product 100 </ b> A and the circuit on the build-up substrate 101 through the interlayer wiring 98. Connecting. Thereafter, the support material 92 bonded to the substrate product 100A via the adhesive layer 91 is removed from the substrate product 100A (FIG. 23).

  Then, as shown in FIG. 24, the substrate product 100B manufactured by the same method as the substrate product 100A is stacked on the surface side of the substrate product 100A. At this time, the relative positions of the substrate product 100A and the substrate product 100B are adjusted so that the positions of the bumps 89 provided on the substrate product 100A coincide with the positions of the interlayer wiring 98 of the substrate product 100B. Then, the bumps 89 of the substrate product 100A are melted by heating or the like, and the bumps 89 and the interlayer wiring 98 of the substrate product 100B are joined to electrically connect the integrated circuits of the substrate products 100A and 100B to each other. Connecting. Thereafter, the support member 92 bonded to the substrate product 100B via the adhesive layer 91 is removed from the substrate product 100B. In this way, a predetermined number of substrate products are sequentially stacked and joined together. And the three-dimensional semiconductor device provided with the structure shown in FIG. 1 is obtained by cut | disconnecting the laminated product formed in this way in chip shape. Further, the order may be reversed, and each substrate product may be cut into chips and then stacked sequentially.

  The effect by the board | substrate product demonstrated above, a three-dimensional semiconductor device, and those manufacturing methods is demonstrated. In the manufacturing method according to the present embodiment, the integrated circuit layer 90 is formed in a state where the sacrificial material 85 (FIG. 10) is embedded in a portion where the interlayer wiring 98 penetrating the silicon substrate 80 is formed. Then, after the silicon substrate 80 is thinned (FIG. 15), the sacrificial material 85 is removed (FIG. 18) and a metal material (metal film 96) is embedded to form an interlayer wiring 98 penetrating the silicon substrate 80 (see FIG. 18). FIG. 21). Thus, since the interlayer wiring 98 is formed after the integrated circuit layer 90 is formed, it is necessary to use a material that can withstand high temperatures when forming the semiconductor element 86 of the integrated circuit layer 90 as the constituent material of the interlayer wiring 98. There is no. Therefore, a metal can be used as a constituent material of the interlayer wiring 98, and the interlayer wiring 98 can have a low resistivity. Further, since the hole 82 (FIG. 7) for embedding the interlayer wiring 98 is formed before the thinning step, a via having a favorable processed shape can be formed at a high speed by reactive ion etching. Therefore, according to the manufacturing method of this embodiment, the substrate product manufactured by the manufacturing method, and the three-dimensional semiconductor device, the interlayer wiring 98 made of metal can be easily formed.

  A method is also known in which a plurality of substrates on which integrated circuits are formed are stacked and then an interlayer wiring (through hole) is formed so as to penetrate the plurality of substrates. However, according to the manufacturing method of this embodiment, Compared with such a system, the degree of freedom of arrangement of the interlayer wiring can be remarkably improved. Further, the hole 82 can be formed narrower and deeper than the method of forming the through hole for the interlayer wiring after the substrate is thinned.

  Further, as in this embodiment, the insulating film forming step (FIG. 8) for forming the insulating film 84 on the inner surface of the hole 82 is replaced with the hole forming step (FIGS. 4 to 7) and the embedding step (FIGS. 9 and 10). ) Is preferably provided. In this case, the substrate 80 is preferably a silicon substrate and the insulating film 84 is preferably a silicon oxide film. In general, when an insulating film 84 of silicon oxide is formed on the inner surface of a fine hole 82 formed in the silicon substrate 80, the insulating film 84 is more uniformly formed on the inner surface as the temperature is increased. . However, as described in the [Means for Solving the Problems] column, when the insulating film is formed on the inner surface of the through hole after the substrate is thinned, an adhesive such as a resin is used when the substrate is attached to the support material. However, such an adhesive generally has low heat resistance. Therefore, it is difficult to raise the temperature sufficiently when forming the insulating film, and it is difficult to uniformly form the insulating film on the inner surface of the minute hole. On the other hand, according to the manufacturing method according to the present embodiment, the insulating film 84 on the inner surface of the hole 82 can be formed before the thinning step (FIGS. 14 and 15), so that the silicon substrate 80 is bonded to the support material. This is not necessary, and the temperature can be sufficiently increased when forming the insulating film 84, and the insulating film 84 can be uniformly formed on the inner surface of the hole 82.

  Further, as in this embodiment, the hole 82 formed in the hole forming step (FIGS. 4 to 7) includes a first portion 82a extending in the thickness direction from the surface 80a of the silicon substrate 80, and a first portion. It is preferable to have the 2nd part 82b whose internal diameter is larger than 82a. Since the hole 82 has the first portion 82a and the second portion 82b, the inner diameter on the back surface 80b side of the hole 82 after the thinning step (FIGS. 14 and 15) is larger than the inner diameter on the surface 80a side. growing. That is, in the subsequent wiring formation process (FIGS. 16 to 21), the diameter of the interlayer wiring 98 on the back surface 80b side is larger than the diameter of the interlayer wiring 98 on the front surface 80a side. Therefore, when the back side of the substrate product is bonded to another substrate in the stacking step (FIGS. 22 to 24), the accuracy of alignment between the substrate product and the other substrate can be relaxed.

  In addition, as in the present embodiment, the sacrificial material 85 preferably includes at least one of polycrystalline silicon and silicon germanium. Thus, the hole 82 can be suitably filled with a material that can withstand heat treatment when forming the integrated circuit and can be selectively removed in the wiring formation step (FIGS. 16 to 21).

  The three-dimensional semiconductor device manufacturing method, the substrate product manufacturing method, the substrate product, and the three-dimensional semiconductor device according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, in the above-described embodiment, polycrystalline silicon and silicon germanium are exemplified as examples of the sacrificial material. However, as the sacrificial material, gas is not generated even at a high temperature when forming a semiconductor element, and etching with a silicon oxide film is selected. Other materials may be used as long as there is a property. Examples of such other materials include carbon and tungsten. Silicon germanium is not limited to a single crystal structure, and may have an amorphous structure.

It is side surface sectional drawing which shows the structure of one Embodiment of the three-dimensional semiconductor device by this invention. It is side surface sectional drawing which shows the structure of a board | substrate product. It is a figure which shows the silicon substrate used in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the hole formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the hole formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the hole formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the hole formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the insulating film formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the embedding process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the embedding process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the integrated circuit formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the integrated circuit formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the thinning process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the thinning process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the thinning process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the wiring formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the wiring formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the wiring formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the wiring formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the wiring formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the wiring formation process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the lamination process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the lamination process in the manufacturing method of a three-dimensional semiconductor device. It is a figure which shows the lamination process in the manufacturing method of a three-dimensional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Three-dimensional semiconductor device 10, 100A, 100B ... Substrate product, 20, 101 ... Build-up substrate, 30 ... Substrate, 40, 90 ... Integrated circuit layer, 41, 86 ... Semiconductor element, 42, 88 ... Wiring pattern , 42a, 50b, 88a, 95 ... barrier metal film, 43, 87 ... insulating layer, 50, 98 ... interlayer wiring, 52 ... enlarged diameter part, 60, 61, 89, 102 ... bump, 70, 71, 84 ... insulating 80, silicon substrate, 81, 93 ... silicon oxide film, 82 ... hole, 82a ... first part, 82b ... second part, 83 ... protective film, 85 ... sacrificial material, 91 ... adhesive layer, 92 ... support material, 94 ... through hole, 96 ... metal film.

Claims (12)

A hole forming step of forming a bottomed hole on the surface of the substrate;
Embedding the hole with a sacrificial material;
Forming an integrated circuit having a wiring pattern in contact with the sacrificial material on the surface of the substrate; and
A thinning step of thinning the substrate from the back surface of the substrate to penetrate the hole and to expose a part of the sacrificial material from the back surface of the substrate;
A wiring forming step of forming an interlayer wiring penetrating the substrate by removing the sacrificial material and embedding a metal material;
A stacking step of stacking the substrate on another substrate, and electrically connecting the integrated circuit and the circuit on the other substrate via the interlayer wiring. Production method.   The method for manufacturing a three-dimensional semiconductor device according to claim 1, further comprising an insulating film forming step of forming an insulating film on an inner surface of the hole between the hole forming step and the embedding step. .   3. The method for manufacturing a three-dimensional semiconductor device according to claim 2, wherein the substrate is a silicon substrate, and the insulating film is a silicon oxide film.   The hole formed in the hole forming step has a first portion extending in a thickness direction of the substrate from the surface of the substrate, and a second portion having an inner diameter larger than that of the first portion. The manufacturing method of the three-dimensional semiconductor device as described in any one of Claims 1-3.   The method of manufacturing a three-dimensional semiconductor device according to any one of claims 1 to 4, wherein the sacrificial material includes at least one of polycrystalline silicon and silicon germanium. A hole forming step of forming a bottomed hole on the surface of the substrate;
Embedding the hole with a sacrificial material;
Forming an integrated circuit having a wiring pattern in contact with the sacrificial material on the surface of the substrate; and
A thinning step of thinning the substrate from the back surface of the substrate to penetrate the hole and to expose a part of the sacrificial material from the back surface of the substrate;
And a wiring forming step of forming an interlayer wiring penetrating the substrate by removing the sacrificial material and embedding a metal material. A substrate,
An integrated circuit provided on the surface of the substrate;
An interlayer wiring penetrating the substrate,
The interlayer wiring forms a bottomed hole on the surface of the substrate, fills the hole with a sacrificial material, and after the integrated circuit having a wiring pattern in contact with the sacrificial material is formed on the surface of the substrate, The substrate is formed by thinning the substrate from the back surface of the substrate to penetrate the hole, exposing a part of the sacrificial material from the back surface of the substrate, removing the sacrificial material, and embedding a metal material. And substrate products.   The substrate product according to claim 7, wherein the sacrificial material includes at least one of polycrystalline silicon and silicon germanium.   9. The substrate product according to claim 7, wherein a diameter of the interlayer wiring on the back surface of the substrate is larger than a diameter of the interlayer wiring on the surface of the substrate.   The substrate product according to claim 7, further comprising an insulating film between the substrate and the interlayer wiring.   The substrate product according to claim 10, wherein the substrate is a silicon substrate and the insulating film is a silicon oxide film.   The substrate product according to any one of claims 7 to 11 is stacked on another substrate, and the integrated circuit and the circuit on the other substrate are electrically connected via the interlayer wiring. A three-dimensional semiconductor device characterized by that.

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