JP4696152B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of improving a manufacturing yield of a semiconductor device of a three-dimensional structure having a penetrating electrode. <P>SOLUTION: By forming a support part with a spacer 49 and a second electrode 50a laminated therein in a region without having a first bump electrode 50 formed therein between a surface protective film 48 on a principal surface of a wafer W2 and a back surface of a wafer 3, the flexure of the wafer W3 is prevented to keep the distance between the surface protective film 48 on the principal surface of the wafer W2 and the back surface of the wafer W3 uniform. Accordingly, generation of an unfilled part of an adhesive 51 between the surface protective film 48 on the principal surface of the wafer W2 and the back surface of the wafer W3 is prevented. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a three-dimensional structure and a technique effective when applied to the semiconductor device.

  A three-dimensional semiconductor device integrates semiconductor elements three-dimensionally in a structure in which semiconductor active layers are stacked in multiple layers, thereby providing various barriers that the two-dimensional semiconductor device faces, such as lithography technology in miniaturization. Increases in wiring resistance and parasitic effect due to limitations, wiring miniaturization and wiring length increase, and the accompanying tendency to saturate operating speed and high electric field effect due to miniaturization of device dimensions, etc., and maintain high integration It is attracting attention as a powerful structure.

  A semiconductor device having a three-dimensional structure is described in, for example, Japanese Patent Application Laid-Open No. 11-261000 (Patent Document 1) or Japanese Patent Application Laid-Open No. 2002-334967 (Patent Document 2), and a semiconductor substrate on which a semiconductor element is formed is attached. A method of manufacturing a semiconductor device having a three-dimensional structure by combining them is disclosed. Also, in these documents, a through electrode called a vertical interconnector or a buried connection electrode is formed in a groove penetrating between the main back surfaces of a desired semiconductor substrate so that the main back surfaces of the semiconductor substrate can be electrically connected. The structure to make is disclosed.

  Japanese Unexamined Patent Application Publication No. 2006-165025 (Patent Document 3) or Japanese Unexamined Patent Application Publication No. 2003-17558 (Patent Document 4) discloses a semiconductor device including a through electrode in a semiconductor substrate and a method of forming the through electrode. ing.

Japanese Patent Application Laid-Open No. 2007-281393 (Patent Document 5) has a protruding electrode made of a conductive material and a dummy protruding portion having a height larger than the protruding electrode on the substrate. A semiconductor device is disclosed in which a gap is determined using a portion, and a predetermined gap is accurately held by an electrical insulating material attached to the surface of an electronic component in an inner region of the protrusion.
JP 11-261000 A JP 2002-334967 A JP 2006-165025 A JP 2003-17558 A JP 2007-281393 A

  In a semiconductor device having a three-dimensional structure formed by stacking a plurality of chips, as one of means for transmitting a mutual signal between an upper chip and a lower chip facing the chip. A through electrode is used. Moreover, the space | interval of the chip | tip located on the upper side and the chip | tip located on the lower side is this, for example, about 5-30 micrometers, The resin which functions as the adhesive agent which bonds both chip | tips in between is filled. Yes.

  However, a three-dimensional semiconductor device having a through electrode has various technical problems described below in the manufacturing process.

  Since the through electrode is localized depending on the circuit configuration of the semiconductor device, there are a region where a large number of through electrodes are arranged and a region where no through electrode is arranged. In the region where the through electrode is disposed, the distance between the upper wafer and the lower wafer facing the wafer is determined by the length of the through electrode. However, in the region where the through electrode is not disposed, the thickness of the upper wafer is as thin as about 30 μm, for example, so that the upper wafer bends to oppose the upper wafer. The distance between the wafer positioned below and the wafer positioned above the area where the through electrode is disposed is approximately 20% smaller than the distance between the wafer positioned below the wafer. For this reason, the gap between the upper wafer and the lower wafer facing the wafer is varied.

  Resin is less likely to be injected where the distance between the upper wafer and the lower wafer is small, and the resin is less likely to be injected between the upper wafer and the lower wafer. Locations that are not filled with resin are formed. After laminating and laminating a plurality of wafers, the laminated wafers are separated into individual laminated chips by dicing, for example, to form a semiconductor device. In the unfilled portion, there is a problem that the chip located above and the chip located below opposite thereto are separated, and the semiconductor device is destroyed.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a three-dimensional semiconductor device having a through electrode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  In this embodiment, a plurality of semiconductor wafers are bonded together, and the integrated circuits formed on the semiconductor chips of each semiconductor wafer are electrically connected to each other to form a desired integrated circuit. It is. First, after forming a surface protective film covering the uppermost layer wiring on the main surface of the second wafer, the surface protective film is processed to expose a part of the uppermost layer wiring. Subsequently, after forming an insulating film on the main surface of the second wafer, the insulating film is processed to form a spacer made of an insulating film on the surface protective film in a region where the uppermost wiring is not exposed. Subsequently, in the same process, a first bump electrode is formed on the exposed uppermost layer wiring on the main surface of the second wafer, and a second bump electrode is formed on the spacer. Thereafter, a through electrode protruding from the back surface of the first wafer is brought into physical contact with the first bump electrode formed on the main surface of the second wafer, and the back surface of the first wafer and the main surface of the second wafer are further contacted. The resin is filled between the surface protective film.

  Further, this embodiment is a semiconductor device that forms a desired integrated circuit by bonding a plurality of semiconductor wafers and electrically connecting the integrated circuits formed on the semiconductor chips of each semiconductor wafer to each other. It is a manufacturing method. First, after forming a surface protective film covering the uppermost layer wiring on the main surface of the second wafer, the surface protective film is processed to determine the thickness of the surface protective film in a region where the first bump electrode is formed. The thickness of the surface protective film in the region where the electrode is not formed is made thinner, and the surface protective film is further processed to expose a part of the uppermost layer wiring in the region where the first bump electrode is formed. Subsequently, in the same process, a first bump electrode is formed on the exposed uppermost layer wiring on the main surface of the second wafer, and a second bump electrode is formed on the surface protection film where the uppermost layer wiring is not exposed. Thereafter, a through electrode protruding from the back surface of the first wafer is brought into physical contact with the first bump electrode formed on the main surface of the second wafer, and the back surface of the first wafer and the main surface of the second wafer are further contacted. The resin is filled between the surface protective film.

  Further, this embodiment is a semiconductor device including a desired integrated circuit in which a plurality of semiconductor chips are bonded together and integrated circuits formed on each semiconductor chip are electrically connected to each other. The semiconductor device includes: a first chip including a plurality of first integrated circuits formed on the main surface; a through electrode protruding from the back surface; a plurality of second integrated circuits formed on the main surface; A plurality of wirings electrically connected to one of the second integrated circuits and formed on the main surface, a surface protection film formed on the main surface by exposing a part of the uppermost wiring, A spacer including a spacer formed on the surface protective film, a first bump electrode formed in electrical connection with the uppermost wiring exposed from the surface protective film, and a second bump electrode formed on the spacer. The through electrode protruding from the back surface of the first chip is in physical contact with the first bump electrode on the main surface of the second chip, and the back surface of the first chip and the main surface of the second chip are A resin is filled between the surface protective film on the surface.

  Further, this embodiment is a semiconductor device including a desired integrated circuit in which a plurality of semiconductor chips are bonded together and integrated circuits formed on each semiconductor chip are electrically connected to each other. The semiconductor device includes: a first chip including a plurality of first integrated circuits formed on the main surface; a through electrode protruding from the back surface; a plurality of second integrated circuits formed on the main surface; A plurality of wirings electrically connected to one of the second integrated circuits and formed on the main surface, a surface protection film formed on the main surface by exposing a part of the uppermost wiring, A first chip having a first bump electrode formed in electrical connection with the uppermost wiring exposed from the surface protective film and a second bump electrode formed on the surface protective film; The thickness of the surface protective film in the region where the bump electrode is formed is thinner than the thickness of the surface protective film in the region where the second bump electrode is formed, and the through electrode protruding from the back surface of the first chip is the second chip. It is in physical contact with the first bump electrode on the main surface, and the back surface of the first chip and the second chip In which resin is filled between the surface protective film on the surface.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  Since the distance between the upper wafer (first wafer) and the lower wafer (second wafer) opposed to the upper wafer can be kept uniform within the wafer surface, the upper wafer and the wafer It is possible to fill the resin as an adhesive without leaving a space between the wafer and the wafer positioned oppositely. As a result, even if a plurality of stacked wafers are separated into a plurality of stacked chips to form a semiconductor device, separation of the stacked chips can be prevented. The manufacturing yield of the semiconductor device can be improved.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The semiconductor device according to the first embodiment has a three-dimensional structure in which three semiconductor chips (hereinafter simply referred to as chips) C1, C2, and C3 on which different integrated circuits are formed are laminated and bonded together. . FIG. 1 is a cross-sectional view showing an example of a package in which this semiconductor device is mounted on a wiring board 1 and sealed with a mold resin 2.

  Of the three chips C1, C2, and C3 mounted on the wiring board 1, the lowermost chip C1 is bonded to the wiring board 1 via the adhesive 3. The intermediate layer chip C2 is bonded to the chip C1 via the adhesive 3, and the uppermost layer chip C3 is bonded to the chip C2 via the adhesive 3. As will be described in detail later, the integrated circuit formed on the lowermost chip C1 and the integrated circuit formed on the middle chip C2 are electrically connected via a plurality of through electrodes 4 formed on the chip C2. The integrated circuit formed on the intermediate layer chip C2 and the integrated circuit formed on the uppermost layer chip C3 are electrically connected via a plurality of through electrodes 4 formed on the chip C3. That is, the semiconductor device according to the first embodiment realizes a desired system by connecting the integrated circuits formed on the chips C1, C2, and C3 to each other through the through electrode 4.

  The chips C1, C2, C3 and the wiring board 1 are bonded to each other between a plurality of bonding pads 5 formed on the uppermost chip C3 and a plurality of electrodes 6 formed on the wiring board 1. They are electrically connected via gold (Au) wires 7. The electrodes 6 are electrically connected to solder bumps 9 on the back surface of the wiring board 1 through copper (Cu) wirings 8 in the wiring board 1. The solder bumps 9 constitute external connection terminals when the package shown in FIG. 1 is mounted on a mother board or the like.

  FIG. 2 is a flowchart showing manufacturing steps of the semiconductor device according to the first embodiment. In this semiconductor device manufacturing process, different integrated circuits are formed on semiconductor wafers (hereinafter simply referred to as wafers) W1, W2, and W3, conductive portions are formed on wafers W2 and W3, and bumps are formed on wafers W1 and W2. A step of forming an electrode, a step of forming the through electrode 4 by polishing the back surface of the wafer W3 to expose the conductive portion, and bonding the wafers W2 and W3 to the through electrode 4 and the wafer W2 provided on the wafer W3. A step of electrically connecting the integrated circuits through the bump electrodes provided; a step of injecting an adhesive between the wafers W2 and W3; and a through electrode by polishing the back surface of the wafer W2 to expose the conductive portion. 4 and the wafer W1, (W2 + W3) are bonded together, and the integrated circuit is formed through the through electrode 4 provided on the wafer W2 and the bump electrode provided on the wafer W1. Forming a three-dimensional structure chip C1, C2, C3 by electrically connecting the wafers, injecting an adhesive between the wafers W1, (W2 + W3), and dicing the wafers W1, W2, W3. And a process of packaging the chips C1, C2, and C3 (board mounting, wire bonding, and resin sealing).

  A method for manufacturing a semiconductor device using the three wafers W1, W2, and W3 will be described below in the order of steps.

  First, a process for forming an integrated circuit and a conductive portion on a wafer and a process for forming a bump electrode on the wafer will be described with reference to FIGS. In this description, the wafer W2 located in the middle when bonded is used.

  As shown in FIG. 3, a wafer W2 made of single crystal silicon and having a thickness of about 780 μm is prepared. Then, the wafer W2 is heat-treated to form a thin silicon oxide film 20 having a thickness of about 10 nm on its main surface (surface on which an integrated circuit is formed), and then a CVD (Chemical Vapor Deposition) method is performed on the silicon oxide film 20. After the silicon nitride film 21 is deposited, the silicon nitride film 21 and the silicon oxide film 20 in the element isolation trench formation region are removed by dry etching using a photoresist film (not shown) as a mask. The silicon oxide film 20 formed between the wafer W2 and the silicon nitride film 21 relieves stress generated at the interface between the wafer W2 and the silicon nitride film 21, and causes dislocation or the like on the surface of the wafer W2 due to this stress. This is a buffer layer for preventing the occurrence of defects.

  Next, as shown in FIG. 4, the element isolation trench 22 having a depth of about 350 nm is formed in the wafer W2 in the element isolation trench formation region by dry etching using the silicon nitride film 21 as a mask, and the through electrode 4 is formed later. A groove 23 having a depth of about 350 nm is formed in the wafer W2 in the vicinity of the region to be processed. The planar shape of the groove 23 is, for example, a square frame shape as shown in FIG.

  Next, as shown in FIG. 6, the wafer W2 is heat-treated to form a silicon oxide film 24a on the inner walls of the element isolation trench 22 and the trench 23, and then a silicon oxide film is formed on the main surface of the wafer W2 by a CVD method. 24, and then the silicon oxide film 24 outside the element isolation trench 22 and the trench 23 is polished and removed by a CMP (Chemical Mechanical Polishing) method, whereby the inside of the element isolation trench 22 and the inside of the trench 23 are removed. The silicon oxide film 24 is left.

  Next, after removing the silicon nitride film 21 by etching, as shown in FIG. 7, a silicon nitride film 25 is deposited on the main surface of the wafer W2 by the CVD method. Subsequently, the silicon nitride film 25 above the groove 23, the silicon oxide film 24 inside the groove 23, and the wafer W2 below the groove 23 are sequentially etched by dry etching using a photoresist film (not shown) as a mask. Thus, an insulating groove 26A having a depth of, for example, about 40 μm is formed inside the groove 23. As shown in FIG. 8, the insulating groove 26 </ b> A is formed along the groove 23, and the width thereof is narrower than the width of the groove 23. The width of the insulating groove 26A is, for example, about 2 μm.

  Next, as shown in FIG. 9, the silicon oxide film 27 is formed on the inner wall of the insulating groove 26A by heat-treating the wafer W2 at about 1000.degree. Subsequently, as shown in FIG. 10, after the polycrystalline silicon film 28 is deposited on the main surface of the wafer W2 by the CVD method, the polycrystalline silicon film 28 outside the insulating trench 26A is removed by etch back, The polycrystalline silicon film 28 is left inside the insulating groove 26A. At this time, the surface of the polycrystalline silicon film 28 inside the insulating groove 26A is made lower than the surface of the wafer W2.

  Next, after a silicon oxide film is deposited on the main surface of the wafer W2 by the CVD method, the silicon oxide film outside the insulating groove 26A is polished and removed by the CMP method, so that the insulating groove is formed as shown in FIG. A cap insulating film 29 made of a silicon oxide film is formed on the polycrystalline silicon film 28 inside 26A. Through the steps so far, the insulating portion 26C in which the periphery of the polycrystalline silicon film 28 is surrounded by the silicon oxide film 27 and the cap insulating film 29 is completed. The insulating part 26C is formed in order to electrically isolate the integrated circuit element and the conductive part (through electrode 4) to be formed on the main surface of the wafer W2 in a later step. Further, when the silicon oxide film 27 is formed on the inner wall of the insulating groove 26A, the wafer W2 is heat-treated at about 1000 ° C. Therefore, it is desirable that the insulating portion 26C be formed before the integrated circuit element.

  Next, after the silicon nitride film 25 is removed by etching, n-type impurities and p-type impurities are ion-implanted into the element formation region of the wafer W2, as shown in FIG. A mold well 31 is formed.

  Next, the surface of the wafer W2 is wet-etched to remove the silicon oxide film 20, and then the wafer W2 is heat-treated to form a gate insulating film 32 on the surface. Then, as shown in FIG. (Metal Insulator Semiconductor) An n-channel MIS transistor Qn is formed in the p-type well 31 and a p-channel MIS transistor Qp is formed in the n-type well 30 in accordance with a transistor formation process.

  The n-channel type MIS transistor Qn mainly includes a gate insulating film 32, a gate electrode 33, and an n-type semiconductor region (source, drain) 34, and the p-channel type MIS transistor Qp mainly includes a gate insulating film 32, a gate electrode 33, and A p-type semiconductor region (source / drain) 35 is formed. The gate electrode 33 of the n-channel type MIS transistor Qn is formed by, for example, depositing an n-type polycrystalline silicon film on the gate insulating film 32 by a CVD method and then performing n-type dry etching using a photoresist film (not shown) as a mask. The polycrystalline silicon film is formed by patterning. Similarly, the gate electrode 33 of the p-channel type MIS transistor Qp is formed by, for example, depositing a p-type polycrystalline silicon film on the gate insulating film 32 by the CVD method and then dry etching using a photoresist film (not shown) as a mask. The p-type polycrystalline silicon film is formed by patterning. The n-type semiconductor region (source / drain) 34 is formed by ion-implanting an n-type impurity (for example, phosphorus (P)) into the p-type well 31, and the p-type semiconductor region (source / drain) 35 is formed by an n-type well. 30 is formed by ion implantation of a p-type impurity (for example, boron (B)).

  Next, as shown in FIG. 14, a silicon oxide film 36 is deposited on the main surface of the wafer W2 by the CVD method, and then the silicon oxide film 36 is polished by the CMP method to flatten the surface, Using the resist film (not shown) as a mask, the silicon oxide film 36 and the wafer W2 below the silicon oxide film 36 are dry-etched so that the conductive groove is separated from the insulating portion 26C and surrounded by the insulating portion 26C. 4A is formed. The through electrode 4 is formed in the conductive groove 4A in a later step. The depth from the main surface of wafer W2 to the bottom of conductive groove 4A is substantially the same as that of insulating groove 26A (about 40 μm).

  As shown in FIG. 15, the planar shape of the conductive groove 4 </ b> A is a rectangle, and its long side is about 5.6 μm, for example, and its short side is about 1.7 μm, for example. In this case, the aspect ratio in the short side direction of the conductive groove 4A is 20 or more. Thousands of conductive grooves 4A are formed for each chip (C2) obtained from wafer W2. Further, although not particularly limited, in Embodiment 1, two such rectangular conductive grooves 4A are arranged side by side inside one insulating portion 26C, and these two conductive grooves 4A are arranged in the same manner. A configuration for connecting to an integrated circuit is employed.

  Next, as shown in FIG. 16, a titanium nitride (TiN) film 40 having a thickness of about 100 nm is deposited on the main surface of the wafer W2 by sputtering. The titanium nitride film 40 has a function of improving the adhesion between the silicon oxide film 36 and the conductive film. Subsequently, a titanium nitride film 42 having a thickness of about 20 to 30 nm is deposited by CVD on the main surface of the wafer W2 including the inside of the conductive groove 4A. The titanium nitride film 42 functions as a barrier layer that prevents the reaction between the tungsten (W) film deposited in the next step and the wafer W2 (silicon (Si)). Next, a tungsten film 43 is deposited on the titanium nitride film 42 by a CVD method, and the tungsten film 43 is embedded in the conductive groove 4A. After that, the tungsten film 43 and the titanium nitride film 42 outside the conductive groove 4A are removed by an etch back method or a CMP method, and as shown in FIG. A conductive portion 4C filled with the titanium nitride film 42 and the tungsten film 43) is formed.

  Next, as shown in FIG. 18, after a silicon oxide film 37 is formed on the silicon oxide film 36 by a CVD method, an n-channel MIS transistor Qn and a p-channel MIS transistor Qp are connected to the silicon oxide film 37. First layer aluminum (Al) wiring 38 is formed. At the same time, a first layer aluminum wiring 39 that connects the tungsten film 43 in the conductive groove 4A and a part of the MIS transistor (for example, the p-channel type MIS transistor Qp) is formed. In order to form the first layer aluminum wirings 38 and 39, an aluminum alloy film is deposited on the silicon oxide film 37 by a sputtering method, and then an aluminum alloy film is formed by a dry etching method using a photoresist film (not shown) as a mask. Is patterned.

  Next, as shown in FIG. 19, a first interlayer insulating film 44 made of a silicon oxide film, a second layer aluminum wiring 45, and a second interlayer insulating film made of a silicon oxide film are formed on the first layer aluminum wirings 38 and 39. 46, a third-layer aluminum wiring 47, and a surface protective film 48 made of a laminated film of a silicon oxide film and a silicon nitride film are formed in sequence. Subsequently, the surface protective film 48 is patterned by a dry etching method using a photoresist film (not shown) as a mask to expose a part of the third layer aluminum wiring 47.

  Next, as shown in FIG. 20, after applying an organic insulating film such as a polyimide resin film on the main surface of the wafer W2, the organic insulating film is patterned to expose the third layer aluminum wiring 47. A spacer 49 made of an organic insulating film is formed on the protective film 48. The spacer 49 is arranged so that the distance between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3 stacked on the main surface of the wafer W2 in a subsequent manufacturing process is uniform within the wafer surface. Provided to adjust the spacing. That is, the thickness of the spacer 49 is determined from the distance between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3 stacked on the main surface of the wafer W2 in a later manufacturing process, from the back surface of the wafer 3. It can be determined by the length of the protruding through electrode 4 and the thickness of the first bump electrode formed by connecting to the third layer aluminum wiring 47 in a later manufacturing process.

  Next, as shown in FIG. 21, a first bump electrode 50 connected to the exposed third layer aluminum wiring 47 is formed. The first bump electrode 50 is formed by, for example, a mask vapor deposition method, and is mainly composed of a low-hardness material such as indium solder, or a metal or alloy film that can be low-hardness depending on conditions such as temperature. It is connected to the. At the same time, the second bump electrode 50 a is also formed on the spacer 49. The second bump electrode 50a is not electrically connected to the element formed on the wafer W2, and does not contribute to the operation of the element.

  Next, using FIG. 22 to FIG. 26, the step of polishing the back surface of the wafer W3, the step of bonding the wafers W2, W3, the step of injecting an adhesive between the wafers W2, W3, and the back surface of the wafer W2 are polished. The process will be described.

  A wafer W3 on which the integrated circuit, the conductive portion 4C and the like are formed is prepared by the same method as described above. However, since the wafer W3 is located in the uppermost layer, the first bump electrode 50 is not formed.

  Next, as shown in FIG. 22, the back surface of the wafer W3 is polished to a predetermined thickness by polishing, for example, by a CMP method. At this stage of polishing, the conductive grooves 4A and the insulating grooves 26A are not exposed on the back surface of the wafer W3. This is to prevent the conductive film (titanium nitride film 42 and tungsten film 43) filled in the conductive groove 4A from being destroyed by polishing and to prevent a physical damage layer from remaining on the wafer W3. This is to leave a margin for thinly processing the wafer W3 by a non-physical method in the manufacturing process.

  Next, as shown in FIG. 23, the back surface of the wafer W3 is etched by a wet etching method using, for example, a mixed solution of hydrofluoric acid and nitric acid or a similar silicon etching solution. Instead of the wet etching method, the back surface of the wafer W3 may be selectively etched by a dry etching method. Thereby, the thickness of the wafer W3 is set to, for example, about 30 μm, the conductive portion 4C is projected from the back surface of the wafer W3 to form the through electrode 4, and the insulating portion 26C is projected to form the through separation portion 26.

  Next, as shown in FIG. 24, the wafer W2 and the wafer W3 are brought close to each other, and the through electrode 4 formed on the wafer W3 and the first bump electrode 50 formed on the wafer W2 are brought into physical contact. At this time, the through electrode 4 is inserted into the first bump electrode 50 to ensure electrical connection between the element formed on the wafer W2 and the element formed on the wafer W3. Further, in the region where the through electrode 4 is not formed between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3, a support portion in which the second bump electrode 50a is laminated on the spacer 49. Is formed. The thickness of the spacer 49 is set so that the thickness of the lamination of the spacer 49 and the second bump electrode 50a is substantially the same as the distance between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3. Therefore, even in the region where the through electrode 4 is not formed, the wafer W3 does not bend, and the distance between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3 is uniform within the wafer surface. Can be kept in.

  Next, as shown in FIG. 25, an adhesive 51 that also functions as a filler is filled between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3, and the wafer W2 and the wafer W3 are filled. And fix. Since the distance between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3 is uniform within the wafer surface, the space between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3 is between. Since the adhesive 51 can easily enter and formation of an unfilled portion of the adhesive 51 can be prevented, physical strength can be ensured. As the adhesive 51, an insulating resin, for example, a thermosetting resin such as an epoxy resin, can be used, but any material may be used as long as it has a similar adhesiveness, strength, and insulating property.

  Next, as shown in FIG. 26, the back surface of the wafer W2 is polished in the same manner as the wafer W3 described above, so that the thickness of the wafer W2 is about 30 μm, for example, and the conductive portion 4C protrudes from the back surface of the wafer W2. Thus, the through electrode 4 is formed, and the insulating portion 26C is protruded to form the through separation portion 26.

  Next, with reference to FIG. 27, a process of bonding the wafer W1 and the wafers W2 and W3 and a process of injecting an adhesive between the wafers W1 and W2 will be described.

  A wafer W1 on which the integrated circuit and the first bump electrode 50 are formed is prepared by the same method as described above. Since the wafer W1 is located in the lowermost layer, the conductive portion 4C is not formed.

  Further, as shown in FIG. 27, the wafers W2 and W3 already stacked and bonded together are brought close to the main surface of the wafer W1 by the same method as described above, and the through electrodes 4 formed on the wafer W2 The first bump electrode 50 formed on the wafer W1 is physically brought into contact. Subsequently, an adhesive 51 having a function as a filler is filled between the surface protective film 48 on the main surface of the wafer 1 and the back surface of the wafer W2, and the wafer W1 and the wafers W2 and W3 are fixed. Thereafter, these wafers W1, W2, and W3 are diced into individual chips C1, C2, and C3 having a three-dimensional structure, which are mounted on the wiring board 1 and sealed with the mold resin 2. The package shown in 1 is completed.

  In the first embodiment, one second bump electrode 50a is formed on one spacer 49. However, the present invention is not limited to this. For example, a plurality of second bump electrodes 50a are formed on one spacer 49. May be formed, or one second bump electrode 50 a may be formed across two or more spacers 49.

  Thus, in the region where the first bump electrode 50 connected to the third layer aluminum wiring 47 of the wafer W1 is not formed between the surface protective film 48 on the main surface of the wafer W1 and the back surface of the wafer W2. By forming a support portion in which the spacer 49 and the second bump electrode 50a are stacked, the wafer W2 is prevented from being bent, and the distance between the surface protective film 48 on the main surface of the wafer W1 and the back surface of the wafer W2 is set to the wafer surface. Can be kept uniform within. Similarly, the distance between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3 can be kept uniform within the wafer surface. Thereby, the adhesive 51 is not left between the surface protective film 48 on the main surface of the wafer W1 and the back surface of the wafer W2 or between the surface protective film 48 on the main surface of the wafer W2 and the back surface of the wafer W3. Even if the wafers W1, W2, and W3 are stacked and bonded together, the stacked wafers W1, W2, and W3 are separated into individual chips C1, C2, and C3 to form a semiconductor device. Separation of the chips C1, C2, and C3 can be prevented.

(Embodiment 2)
FIG. 28 is a cross-sectional view of the main part of a semiconductor wafer showing the semiconductor device according to the second embodiment of the present invention.

  In the first embodiment described above, for example, when the wafer W1 (wafer located below) and the wafer W2 (wafer located above) are laminated and bonded together, the surface protective film 48 on the main surface of the wafer W1 A support portion in which the spacer 49 and the second bump electrode 50a are stacked is formed in a region where the first bump electrode 50 connected to the third layer aluminum wiring 47 of the wafer W1 is not formed between the back surface of the wafer W2. Thus, the distance between the surface protective film 48 on the main surface of the wafer W1 and the back surface of the wafer W2 is kept uniform within the wafer surface.

  However, in the second embodiment, when the wafer W1 and the wafer W2 are laminated and bonded together, the wafer is formed in a region where the first bump electrode 50 connected to the third layer aluminum wiring 47 of the wafer W1 is not formed. A surface protective film 48 thicker than the region where the first bump electrode 50 connected to the third layer aluminum wiring 47 of W1 is formed is formed on the wafer W1, and further connected to the third layer aluminum wiring 47 of the wafer W1. A second bump electrode 50a is formed on the surface protection film 48 in a region where the first bump electrode 50 is not formed. As a result, a support portion in which the relatively thick surface protection film 48 and the second bump electrode 50a are laminated can be formed in a region where the through electrode 4 does not protrude from the back surface of the wafer W2. The distance between the surface protective film 48 on the surface and the back surface of the wafer W2 can be kept uniform within the wafer surface. In the second embodiment, since it is not necessary to form the spacer 49 used in the first embodiment, the manufacturing cost can be reduced as compared with the first embodiment.

  The surface protective film 48 having a thick film region and a thin film film region is formed, for example, by forming the surface protective film 48 on the main surface of the wafer W1 on which the third layer aluminum wiring 47 is formed by the CVD method, After the surface protection film 48 in the region where the first bump electrode 50 is formed is thinly processed, the surface protection film 48 is processed so that the third layer aluminum wiring 47 in the region where the first bump electrode 50 is formed is exposed. Can be formed. Alternatively, after the surface protective film 48 is processed so that the third layer aluminum wiring 47 in the region where the first bump electrode 50 is formed is exposed, the surface protective film 48 in the region where the first bump electrode 50 is formed is formed. It may be processed thinly.

(Embodiment 3)
FIG. 29 is a cross-sectional view of the principal part of the semiconductor wafer showing the semiconductor device according to the third embodiment of the present invention. Here, description will be made using the wafer W1 and the wafer W2 which are laminated and bonded together.

  In the first embodiment described above, the through separation portion 26 is formed so as to surround the through electrode 4 at a position separated from the through electrode 4.

  However, in the third embodiment, the through electrode 4 made of a conductive film containing tungsten as a main component is formed inside the through isolation portion 26 so as to penetrate the polycrystalline silicon film 28. The through isolation part 26 includes a silicon oxide film 27 formed so as to cover the side surface of the through hole 26a, a polycrystalline silicon film 28 formed so as to cover the side surface of the silicon oxide film 27, and the polycrystalline silicon film. And a cap insulating film 29 formed so as to cover the upper surface of 28. The through electrode 4 has a titanium nitride film 42 and a tungsten film 43 formed inside the conductive groove 4A. By forming the penetration electrode 4 inside the penetration separation part 26, the wafer W 2 and the penetration electrode 4 can be electrically insulated using the penetration separation part 26, and the conductive material constituting the penetration electrode 4 can be obtained. It is possible to prevent the deterioration of the electrical characteristics of the device by suppressing the diffusion of contamination from the film.

  Thus, even in the structure in which the through electrode 4 is formed inside the through separation portion 26, the surface protective film 48 on the main surface of the wafer W1, the back surface of the wafer W2, and the like, as in the first embodiment described above. In the region where the through electrode 4 is not formed, a support portion in which the spacer 49 and the second bump electrode 50a are stacked is formed, thereby preventing the wafer W2 from being bent and on the main surface of the wafer W1. The distance between the surface protective film 48 and the back surface of the wafer W2 can be kept uniform within the wafer surface.

  The through electrode 4 formed inside the through separation part 26 can be formed by, for example, a manufacturing method described below.

  First, as shown in FIG. 30, element isolation grooves 22 and grooves 23 are formed in the main surface of the wafer W <b> 2, and then a silicon oxide film 24 is embedded in the element isolation grooves 22 and the grooves 23.

  Next, as shown in FIG. 31, after depositing an insulating film such as a silicon nitride film 25 on the main surface of the wafer W2 by the CVD method, the silicon nitride exposed from the resist pattern (not shown) is used as a mask. The film 25, the silicon oxide film 24, and the wafer W2 are removed by etching in order to form an insulating groove 26A on the main surface of the wafer W2. The insulating groove 26A is a groove that forms the above-described through hole 26a, and extends from the main surface of the wafer W2 to a position midway in the thickness direction of the wafer W2 and deeper than the depth of the groove 23. It is formed as follows.

  Subsequently, a thermal oxidation process is performed on the wafer W2, thereby forming an insulating film such as a silicon oxide film 27 on the exposed surface of the wafer W2 on the inner wall (side surface and bottom surface) of the insulating groove 26A. This insulating film is not limited to the silicon oxide film 27 formed by the thermal oxidation process, and for example, silicon oxide, silicon nitride, silicon oxynitride or the like formed by a CVD method can be used as the insulating film.

  Subsequently, an embedded film, for example, a polycrystalline silicon film 28 is deposited on the main surface of the wafer W2 by a CVD method so as to fill the insulating groove 26A. Subsequently, the polycrystalline silicon film 28 is etched back by an anisotropic dry etching method to remove the extra polycrystalline silicon film 28 outside the insulating groove 26A, and the polycrystalline silicon film only in the insulating groove 26A. Leave 28.

  Subsequently, a cap insulating film 29 made of, for example, silicon oxide is deposited on the main surface of the wafer W2 by a CVD method so that the depression above the polycrystalline silicon film 28 is buried. Subsequently, the cap insulating film 29 is polished by the CMP method to remove the extra cap insulating film 29 outside the depression above the polycrystalline silicon film 28, and only in the depression above the polycrystalline silicon film 28. The cap insulating film 29 is left. In this way, the upper surface of the polycrystalline silicon film 28 is covered with the cap insulating film 29. Thereafter, the silicon nitride film 25 is removed by wet etching.

  Next, as shown in FIG. 32, integrated circuit elements are formed in the element formation region of the main surface of the wafer W2. Examples of integrated circuit elements that constitute the integrated circuit include active elements such as MIS transistors, bipolar transistors, and diodes. Other examples of the integrated circuit element include passive elements such as resistors, capacitors and inductors. Here, an n-channel MIS transistor is illustrated as an element, and can be formed by the same manufacturing method as the n-channel MIS transistor Qn illustrated in the first embodiment.

  Next, as shown in FIG. 33, after the silicon oxide film 36 is deposited on the main surface of the wafer W2 by the CVD method, the resist pattern (not shown) is used as a mask to expose the silicon oxide film 36 and the cap. The insulating film 29 and the polycrystalline silicon film 28 are removed by etching in order. Thereby, the conductive grooves 4A are formed on the main surface of the wafer W2. The conductive groove 4A is formed to extend from the upper surface of the silicon oxide film 36 on the main surface of the wafer W2 to the silicon oxide film 27 on the bottom surface in the insulating groove 26A in the thickness direction of the wafer W2.

  Subsequently, after a titanium nitride film 42 is deposited on the main surface of the wafer W <b> 2 by a sputtering method, a tungsten film 43 is deposited by a CVD method, and the conductive groove 4 </ b> A is filled with the titanium nitride film 42 and the tungsten film 43. Subsequently, the tungsten film 43 and the titanium nitride film 42 are polished by the CMP method to remove the extra tungsten film 43 and the titanium nitride film 42 outside the conductive groove 4A, and the tungsten film 43 and the titanium nitride film 42 only in the conductive groove 4A. The titanium nitride film 42 is left. In this manner, the tungsten film 43 and the titanium nitride film 42 are buried in the conductive groove 4A to form the conductive portion 4C. The conductive portion 4C is a portion that forms the through electrode 4, and the configuration of the conductive portion 4C is the same as the through electrode 4 except that it does not penetrate between the main back surfaces of the wafer W2.

  Next, as shown in FIG. 34, a wiring layer is formed. Here, a wiring layer having a three-layer wiring configuration is illustrated as the wiring layer, and can be formed by the same manufacturing method as the wiring layer illustrated in the first embodiment. Further, in the same manner as in the first embodiment described above, a spacer 49 is formed on the surface protective film 48, and then a first bump electrode 50 connected to the exposed third layer aluminum wiring 47 is formed. Then, the second bump electrode 50a is formed.

  Next, as shown in FIG. 35, the back surface of the wafer W2 is polished by, for example, a CMP method and thinned to a predetermined thickness, and then the back surface of the wafer W2 is mixed with, for example, a mixed solution of hydrofluoric acid and nitric acid, or Etching is performed by a wet etching method using a similar silicon etching solution. Instead of the wet etching method, the back surface of the wafer W2 may be selectively etched by a dry etching method. At this stage of etching, the silicon oxide film 27 is exposed, but the conductive portion 4C is covered with the silicon oxide film 27. Subsequently, the exposed silicon oxide film 27 is removed by an etching method. As a result, a through-separation portion 26 made of the silicon oxide film 27, the polycrystalline silicon film 28, and the cap insulating film 29 covering the side surface of the through-hole 26a is formed, and the through-electrode 4 that is formed inside and protrudes from the back surface is formed. Form.

  In the third embodiment, the case where the present invention is applied to the semiconductor device having the support portion in which the spacer 49 and the second bump electrode 50a described in the first embodiment are stacked has been described. Needless to say, the present invention can also be applied to a semiconductor device having a support portion in which the second bump electrode 50a is laminated on the surface protection film 48 formed relatively thick as described in 2.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and bonded together.

It is sectional drawing which shows an example of the package which mounted the semiconductor device by Embodiment 1 of this invention on the wiring board, and was resin-sealed. It is a flowchart which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor wafer which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. FIG. 4 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 3; It is a principal part top view of the semiconductor wafer which shows the planar shape of a groove | channel. FIG. 5 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 4; FIG. 7 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 6; It is a principal part top view of the semiconductor wafer which shows the planar shape of an insulation groove | channel. FIG. 8 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 10 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 13; It is a principal part top view of the semiconductor wafer which shows the planar shape of a conductive groove. FIG. 15 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 17 is a main part cross-sectional view of the semiconductor wafer showing the manufacturing process of the semiconductor device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing step of the semiconductor device following that of FIG. 18; FIG. 20 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 19; FIG. 21 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing process of the semiconductor device following FIG. 22; FIG. 24 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing step of the semiconductor device following that of FIG. 23; FIG. 25 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 24; FIG. 26 is a fragmentary cross-sectional view of the semiconductor wafer showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a fragmentary cross-sectional view of the semiconductor wafer showing the manufacturing process of the semiconductor device following FIG. 26; It is principal part sectional drawing of the semiconductor wafer which shows the semiconductor device by Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor wafer which shows the semiconductor device by Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor wafer which shows the manufacturing process of the semiconductor device by Embodiment 3 of this invention. FIG. 31 is a main part cross-sectional view of the semiconductor wafer, showing the manufacturing process of the semiconductor device following FIG. 30; FIG. 32 is a main part cross-sectional view of the semiconductor wafer showing the manufacturing process of the semiconductor device following FIG. 31; FIG. 33 is a main part cross-sectional view of the semiconductor wafer showing the manufacturing process of the semiconductor device following FIG. 32; FIG. 34 is a main part cross-sectional view of the semiconductor wafer, showing the manufacturing process of the semiconductor device following FIG. 33; FIG. 35 is an essential part cross-sectional view of the semiconductor wafer showing the manufacturing process of the semiconductor device following FIG. 34;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Mold resin 3 Adhesive 4 Through electrode 4A Conductive groove 4C Conductive part 5 Bonding pad 6 Electrode 7 Wire 8 Wiring 9 Solder bump 20 Silicon oxide film 21 Silicon nitride film 22 Element isolation groove 23 Groove 24, 24a Silicon oxide film 25 Silicon nitride film 26 Through separation part 26A Insulating groove 26C Insulating part 26a Through hole 27 Silicon oxide film 28 Polycrystalline silicon film 29 Cap insulating film 30 n-type well 31 p-type well 32 gate insulating film 33 gate electrode 34 n-type semiconductor region (Source, drain)
35 p-type semiconductor region (source, drain)
36, 37 Silicon oxide films 38, 39 First layer aluminum wiring 40 Titanium nitride film 42 Titanium nitride film 43 Tungsten film 44 First interlayer insulating film 45 Second layer aluminum wiring 46 Second interlayer insulating film 47 Third layer aluminum wiring 48 Surface protective film 49 Spacer 50 First bump electrode 50a Second bump electrode 51 Adhesive C1, C2, C3 Semiconductor chip Qn n-channel type MIS transistor Qp p-channel type MIS transistors W1, W2, W3 Semiconductor wafer

Claims (10)

An integrated circuit is formed on the first surface, a first wafer on which a through electrode protruding from the second surface opposite to the first surface is formed, an integrated circuit is formed on the first surface, and an uppermost layer wiring A method of manufacturing a semiconductor device comprising a step of laminating and bonding a second wafer having a first bump electrode formed thereon and electrically connected to
(A) forming a surface protective film covering the uppermost layer wiring on the first surface of the second wafer;
(B) processing the surface protective film to expose a part of the uppermost layer wiring;
(C) after the step (b), forming an insulating film on the first surface of the second wafer;
(D) physically bringing the through electrode protruding from the second surface of the first wafer into contact with the first bump electrode formed on the first surface of the second wafer;
(E) In a process comprising a step of filling a resin between the second surface of the first wafer and the surface protective film on the first surface of the second wafer,
(F) processing the insulating film in the step (c) to form a spacer made of the insulating film on the surface protective film in a region where the uppermost layer wiring is not exposed;
(G) After the step (f), the first bump electrode is formed on the exposed uppermost layer wiring on the first surface of the second wafer in the same step, and the second bump electrode is formed on the spacer. Forming a semiconductor device. A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a polyimide resin film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein one or more second bump electrodes are formed on one spacer.   2. The method for manufacturing a semiconductor device according to claim 1, wherein one second bump electrode is formed on two or more of the spacers.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the spacer and the second bump electrode laminated is set to the second surface of the first wafer and the first surface of the second wafer. A method for manufacturing a semiconductor device, characterized by being substantially the same as a distance from a surface protective film. An integrated circuit is formed on the first surface, a first wafer on which a through electrode protruding from the second surface opposite to the first surface is formed, an integrated circuit is formed on the first surface, and an uppermost layer wiring A method of manufacturing a semiconductor device comprising a step of laminating and bonding a second wafer having a first bump electrode formed thereon and electrically connected to
(A) forming a surface protective film covering the uppermost layer wiring on the first surface of the second wafer;
(B) processing the surface protective film to expose a part of the uppermost layer wiring in a region where the first bump electrode is formed;
(C) physically bringing the through electrode protruding from the second surface of the first wafer into contact with the first bump electrode formed on the first surface of the second wafer;
(D) in a process comprising a step of filling a resin between the second surface of the first wafer and the surface protective film on the first surface of the second wafer;
(E) The surface protective film in the region where the first bump electrode is not formed by processing the surface protective film in the step (a) to determine the thickness of the surface protective film in the region where the first bump electrode is formed. The process of making it thinner than the thickness of
(F) forming the first bump electrode on the exposed uppermost layer wiring on the first surface of the second wafer in the same step, and on the surface protection film in a region where the uppermost layer wiring is not exposed; Forming a second bump electrode. The method for manufacturing a semiconductor device, comprising:   7. The method of manufacturing a semiconductor device according to claim 1, wherein a distance between the second surface of the first wafer and the surface protective film on the first surface of the second wafer is 5 to 30 [mu] m. A method of manufacturing a semiconductor device.   7. The semiconductor device manufacturing method according to claim 1, wherein the surface protection film is formed of a silicon oxide film, a silicon nitride film, or a laminated film in which a silicon nitride film is formed on the silicon oxide film. Device manufacturing method. A first chip including a plurality of first integrated circuits formed on the first surface and a through electrode protruding from the second surface opposite to the first surface;
A plurality of second integrated circuits formed on the first surface, a plurality of wirings formed on the first surface by being electrically connected to any of the plurality of second integrated circuits, and an uppermost layer A surface protection film formed on the first surface by exposing a part of the wiring; a spacer formed on the surface protection film , made of an insulating film; and the uppermost layer wiring exposed from the surface protection film; A second chip including a first bump electrode formed by electrical connection and a second bump electrode formed on the spacer;
The tip portion of the through electrode protruding from the second surface of the first chip is in physical contact so as to pierce from the surface of the first bump electrode on the first surface of the second chip. And a resin is filled between the second surface of the first chip and the surface protective film on the first surface of the second chip. A first chip including a plurality of first integrated circuits formed on the first surface and a through electrode protruding from the second surface opposite to the first surface;
A plurality of second integrated circuits formed on the first surface, a plurality of wirings formed on the first surface by being electrically connected to any of the plurality of second integrated circuits, and an uppermost layer A surface protection film formed on the first surface by exposing a part of the wiring; a first bump electrode formed by being electrically connected to the uppermost layer wiring exposed from the surface protection film; A second chip including a second bump electrode formed on the surface protective film,
The thickness of the surface protective film in the region where the first bump electrode is formed is thinner than the thickness of the surface protective film in the region where the second bump electrode is formed,
The through electrode protruding from the second surface of the first chip is in physical contact with the first bump electrode of the second chip, and the second surface of the first chip and the second chip A semiconductor device, wherein a resin is filled between the first surface and the surface protective film.

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