TW201010049A - Package-on-package assembly and method for manufacturing substrate thereof - Google Patents

Package-on-package assembly and method for manufacturing substrate thereof Download PDF

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Publication number
TW201010049A
TW201010049A TW97132740A TW97132740A TW201010049A TW 201010049 A TW201010049 A TW 201010049A TW 97132740 A TW97132740 A TW 97132740A TW 97132740 A TW97132740 A TW 97132740A TW 201010049 A TW201010049 A TW 201010049A
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substrate
spacer layer
package structure
package
stacked package
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TW97132740A
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Chinese (zh)
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TWI431755B (en
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Jung-Hua Liang
Yu-Ching Sun
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Advanced Semiconductor Eng
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Publication of TWI431755B publication Critical patent/TWI431755B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

A package-on-package assembly is disclosed and includes a first package and a second package. The first package is optionally stacked above or below the second package, and the first package is provided with a substrate having a surface facing the second package. The surface of the substrate is formed with an interposer layer having a plurality of through holes therein. Each of the through holes has a electro-conductive post which is used to electrically connected to the two stacked packages. Furthermore, a method for manufacturing a substrate of the package-on-package assembly is also disclosed.

Description

201010049 九、發明說明： • f發明所屬之技術領域】 本發明係關於-齡#式雖構造及其基板製造方法，特 別是關於-種藉由料柱相互連接之堆疊式封裝構造及其基 板製造方法。 【先前技術】 ❹ 現今，半導體封裝產業為了；^足各種絲度封裝之需求， 逐漸發展出各種不同型式之系統封裝構造(system in package，SIP) ’其巾纽職構造又可區分μ晶μ模組封裝 構造(multi-chip module，MCM)及三維封裝構造(3 dimensi〇nal package)。該多晶片模組封裝構造係指在同一基板上具備至少 二晶片，該晶片可選擇以鄰接(side_by_side)或堆氧如如_ 方式排列於該。該三轉裝構關&含雖體堆叠封裝 ❹ 體構造咖汰卿on Package ’ POP)及封裝體内藏封裝體構造 (package inpackage’Pip)’其中該封裝體堆疊封裝體構造(p〇p) 係指將-預先製備之封裝體堆4在另—預先製備之封裝體的 上方’並相互電性連接；而該封裝體内藏封裝體構造斤正)係指 將-預先製備之封裝體堆φ在另—封裝體的基板上方，接著再 對整體進行封裝，使上方的封裝體包埋在下方的封裝體内部。 請參照第1Α、IB、1C及1D圖所示，其揭示—種習用封 裝體堆疊封裝體構造(POP)之製造方法，其包含下列步驟：提 5 201010049 供一第-封裝體卜其具有—基板u、數個第—錫球η、一 晶片13及數個連接錫球14;利用—峨料15包埋該基板 11上之晶片13及連接錫球14 ;研磨該連接錫球14上方之封 裝材料15，朗麵該連祕球14之—部份聽露出該連接 錫球14殘餘部份之—截面141 ;提供-第二封裝體2，其具有 一基板21、數個第二錫球22、一晶片23及一封裝材料24 ; 將該第二封裝體2堆疊於該第一封裝體 22對應接觸該連接錫球14之截面ι4ι ; (reflow)，使該第二錫球22及連接錫球 性連接通路。201010049 IX. Description of the invention: • Technical field to which the invention belongs. The present invention relates to the construction of the invention and the method of manufacturing the same, and more particularly to a stacked package structure and substrate manufacturing by interconnecting the columns. method. [Prior Art] ❹ Nowadays, the semiconductor packaging industry has gradually developed a variety of different types of system package (SIP) in order to meet the needs of various silk packages. Module package structure (MCM) and 3 dimensi〇nal package. The multi-chip module package structure means that at least two wafers are provided on the same substrate, and the wafers may be arranged in a side-by-side or a stack as oxygen. The three-transfer structure & includes a bulk package package ❹ 构造 on on package ' POP) and package in package 'package 'Pip', where the package stack package structure (p〇 p) means that the pre-prepared package stack 4 is electrically connected to the other pre-prepared package; and the package contains the package structure in the package) The bulk stack φ is placed over the substrate of the other package, and then the whole is packaged so that the upper package is embedded inside the lower package. Please refer to the first, IB, 1C and 1D drawings, which disclose a method for manufacturing a conventional package-packaged package structure (POP), which comprises the following steps: 5 201010049 for a first-package body having - a substrate u, a plurality of first-tin balls η, a wafer 13 and a plurality of connecting solder balls 14; the wafer 13 on the substrate 11 and the connecting solder balls 14 are embedded by using the material 15; and the solder balls 14 are polished. The encapsulating material 15 is partially covered by the secret ball 14 and partially exposed to the remaining portion of the solder ball 14 - a second package 2 having a substrate 21 and a plurality of second solder balls 22, a wafer 23 and a package material 24; the second package 2 is stacked on the first package 22 corresponding to the cross-section of the solder ball 14 ι4ι; (reflow), the second solder ball 22 and the connection Tin ball connection path.

Ο 1上方’使該第二錫球 以及，進行高溫迴焊 14共同結合形成一電 然而’該習用封裝體堆疊封裝體構造卿)之製造方法在實 際使用上仍具有下述問題，例如：如第2A圖所示，其揭示該 連接錫球14之截面141的顯舰相，該製造方祕藉由研磨 該封裝材料15裸露該連接錫球14之截面14卜但_法之加 工ϊ甚大’不但浪費材料、耗費時間，且必需精確控制研磨程 度’使該連接錫球14之高度及該截面141之面積符合預定值， 因此必需儘可能避免發生任何過度研磨或加工不足的情況。再 者’不論在佈設該連接錫球14於該基板u上時或是在對該連 接錫球14進行研磨加工時’皆存在可能造成該基板u翹曲變 形(warpage)的風險。另一方面，在研磨加工及清洗後，該連接 錫球14之截面141不可避免的會殘留少許該封裝材料15的研 201010049 磨碎屑，該些研磨碎屑將大幅影響該連接錫球14及第二錫球 22的迴焊結合強度，進而降低封裝後之產品可靠度。再者， 如第2B圖所示，其揭示該第二錫球22(上方錫球)與連接錫球 下方錫球)迴焊結合後的剖視顯微照相，當進行高溫迴悍 時’由於該第二錫球22與連接錫球14皆為錫基焊材，因此會 同時熔化。然而，基於錫基焊材的金屬内聚力(c〇hesi〇n)特性， 其中一錫球(例如該連接錫球14)之錫基焊材將在熔化時受到 另一錫球(例如該第二錫球22)之錫基焊材的吸引，以致於進一 步縮減兩錫球之間的結合面，從而大幅影響該連接錫球14及 第二錫球22的迴焊結合強度。另外，在該製造方法中，該封 裝材料15之模具高度及模流設計必需考量並配合該連接錫球 14之尺寸，其亦提升該第一封裝體丨在注模時之困難度。此 外，在該製造方法中，由於該連接錫球14之輪廓係呈球形， 因此會限制該連接錫球丨4之間距及設置數量，使得該連接錫 球14的佈局密度無法進一步提高。 故’有必要提供一種堆疊式封裝構造及其基板製造方法， 以解決習知技術所存在的問題。 【發明内容】 本發明之主要目的在於提供一種堆疊式封裝構造，其係在 基板之一側設置一間隔層，並在間隔層内形成導電柱，以便電 性連接相互堆疊之封裝體，進而有利於增加結合強度及提高堆 7 ❹制造 1 above the 'the second solder ball and the high-temperature reflow solder 14 are combined to form an electric one. However, the manufacturing method of the conventional package stack package structure has the following problems in practical use, for example: As shown in FIG. 2A, the disclosed ship phase of the cross section 141 of the solder ball 14 is disclosed. The manufacturing method reveals the cross section of the connecting tin ball 14 by grinding the encapsulating material 15 but the processing of the method is very large. Not only is the material wasted, it takes time, and the degree of grinding must be precisely controlled 'the height of the connecting solder ball 14 and the area of the cross-section 141 are in accordance with a predetermined value, so that any excessive grinding or under-processing must be avoided as much as possible. Further, there is a risk that the substrate u may warpage if both the connecting solder balls 14 are placed on the substrate u or when the connecting solder balls 14 are polished. On the other hand, after the grinding process and cleaning, the cross section 141 of the connecting solder ball 14 inevitably remains a little grinding of the grinding material of the encapsulating material 15 , which will greatly affect the connecting solder ball 14 and The reflow of the second solder ball 22 combines the strength, thereby reducing the reliability of the packaged product. Furthermore, as shown in FIG. 2B, it discloses a cross-sectional photomicrograph of the second solder ball 22 (upper solder ball) and the solder ball under the solder ball), when the high temperature is returned, The second solder ball 22 and the connecting solder ball 14 are both tin-based solder materials, and therefore melt simultaneously. However, based on the metal cohesive force of the tin-based solder material, the tin-based solder material of one tin ball (for example, the solder ball 14) will be subjected to another solder ball when melted (for example, the second The attraction of the tin-based solder material of the solder ball 22) is such that the bonding surface between the solder balls is further reduced, thereby greatly affecting the reflow bonding strength of the connecting solder ball 14 and the second solder ball 22. In addition, in the manufacturing method, the mold height and the mold flow design of the sealing material 15 must be considered and matched with the size of the connecting solder ball 14, which also improves the difficulty of the first package body during injection molding. Further, in the manufacturing method, since the outline of the connecting solder balls 14 is spherical, the distance between the solder balls 4 and the number of the solder balls 4 are limited, so that the layout density of the connecting solder balls 14 cannot be further improved. Therefore, it is necessary to provide a stacked package structure and a substrate manufacturing method thereof to solve the problems of the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a stacked package structure in which a spacer layer is disposed on one side of a substrate, and a conductive pillar is formed in the spacer layer to electrically connect the packages stacked on each other, thereby facilitating To increase the bonding strength and increase the stack 7 ❹

201〇l〇〇49 憂良率。 本發明之林目触域供—獅紅封额造之基板製 ^方法，其係在基板之—側設置—_，並在 導電柱，⑽财不需進行研磨加工，進而有利於簡化基板 製程及提尚加工良率。 本發明之^ —目的在於提供式縣構造及其基板 製造方法，其切隔層内之導雜係呈錄，不會佔用過多空 間’進而有利於縮減電性連接通路之離及提高電性連接通路 之佈局密度。 為達上述之目的，本發供—種堆#式封歸造，其包 s第封裝體及-第二封裝體，該第一封裝體選擇堆疊於該 第-封裝體之上方或下方，且該第—封裝體具有—基板，其面 對該第二封裝體之—表面係設有—間隔層。該間隔層内具有數 個通孔，各該通孔内分別形成一導電柱。該間隔層之導電柱用 以電性連接相互堆疊之該第一及第二封裝體。 在本發明之一實施例中，該第一封裝體堆疊於該第二封裝 體之上方，且該第一封裝體之基板係在一底表面設有該間隔 層。 在本發明之一實施例中，該第一封裝體堆疊於該第二封裝 體之下方，且該第一封裝體之基板係在一上表面設有該間隔 201010049 在本發明之一實施例中，該第二封裝體具有-基板，其面 對該第一封额之—表面係設有數個料，該第二封裝體之焊 塾與該第-封敦體之間隔層的導電柱之間係分簡由一導電 介質形成電性連接。 在本發明之一實施例中，該第二封裝體具有-基板，其面 對該第-封裝體之一表面係對應設有另一間隔層，該間隔層對 應設有數個導電柱。該第—封裝體之導電柱與該第二封裝^之 導電柱之間係分別藉由一導電介質形成電性連接。 在本發明之一實施例中，該導電介質係選自錫膏(solder paste)^ 口。卩、超音波焊接(ultfas〇nic weWing)結合部、熱壓 (th__pressure)結合部或異方性導電層㈣输叩记咖如如 film，ACF)。 另-方面，本發明提供一種堆叠式封裝構造之基板製造方 法，其包含：提供-基板’其具有一第一表面、一第二表面及 數個焊墊；在該基板之第-表面設置—間隔層，制隔膚具有 數個通孔對應於該第-表面之轉；以及，在關隔層之各通 孔内分別形成-導電柱，以紐連接該焊塾。 在本發明之-實施例t，可選擇性的在該基板之第二表面 設置至少-晶片，並利用一封裝材料包埋該晶片，以組成一封 裝體。 在本發明之-實施财，該第一表面係該基板之底表面， 9 201010049 該間隔層係設於該基板之底表面。 在本發明之一實施例中，該第一表面係該基板之上表面， 該間隔層係設於該基板之上表面。 在本發明之一實施例中，選擇藉由機械鑽孔或電射鑽孔之 方式在該間隔層形成該通孔。 在本發明之一實施例中，選擇藉由電鍍(pWing)或印刷 (printing)之方式在該間隔層之通孔内形成該導電柱。 在本發明之一實施例中，在進行電鍵或印刷之前，預先在 該間隔層及基板第一表面之裸露處塗佈一光阻層，並對該光阻 層進行曝光顯影，以裸露該通孔，再進行電鑛或印刷。 在本發明之一實施例中，該導電柱係選自熔點大於錫之金 屬或合金，例如銅、銀或金。再者，該導電柱係可選擇性的選 自具有電阻、電感或電容特性之金屬或合金。 在本發明之一實施例中，該導電柱係實質突出於該間隔層 之通孔外，並高於該間隔層之表面。或者，該導電柱係實質平 齊於該間隔層之表面。 在本發明之一實施例中，該間隔層係選自異於封裴材料之 間隔材料’例如絕緣基板材料或金屬材料，以便適用於基板製 程，並整合於基板製程中。 在本發明之一實施例中，該間隔層之絕緣基板材料可選自 陶瓷材料(ceramic material)或芯層材料(core material)。再者， 201010049 該間隔層係選擇直接形成於該基板之第—表面上，或預先製備 後再黏接於該基板之第·-表面上。 在本發明之一實施例中，該間隔層之金屬材料可選自鍍鎳 銅板(Cu plate with M plating layer)，其係預先製備後再黏接於 該基板之第一表面上。再者，該間隔層之通孔内係先塗佈一絕 緣層後，再形成該導電柱。 ® 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更明顯易 it，下文將特舉本發明較佳實施例，並配合所附圖式，作詳細 說明如下。 凊參照第3A、3B、3C、3D及3E圖所示，本發明第一實 施例之堆疊式封裝構造之基板製造方法係用以製造一基板，以 應用於堆叠至少i封裝體成為一封裝體堆叠封裝體構造 β (package on package ’ P0P)。該基板製造方法主要包含下列步 驟：提供-基板3卜其具有一第一表面3U、一第二表面312 及數個焊塾313 ;在該基板31之第一表面311設置-間隔層 32，該間隔層32具有數個通孔321對應於該第一表面3ιι之 焊塾313 ;以及，在該間隔層32之各通孔321内分卿成一 導電柱322，以電性連接該焊墊313。再者，亦可選擇性的在 該基板31之第二表面312設置至少一晶片％，並利用一封裝 材料34包埋該晶片33 ’以组成一封裝體3。本發明將於下文 201010049 針對第一至第四步驟逐一進行詳細說明。 請參照第3A圖所示’本發明第一實施例之堆疊式封裝構 造及其基板製造方法第-步驟係：提供一基板3卜其具有一 第一表面31卜一第二表面312及數個焊塾313。在本步驟中， 該基板31係可依需求選自單層電路板或多層電路板，該單層 電路板係指具單-絕緣層及二表面電路層之電路板，及該多層 t路S係指具數個、絕緣層、二表面電路層及數個内電路層之電 路板。再者’該知整313係為該基板31之第一表面311及第 二表面312所裸露之表面電路層的一部份。在本實施例中該 第-表面311係指該基板31之絲面，及該第二表面312係 指該基板31之上表^惟，在本㈣之其他實_中，該第 -表面311亦可置換為該基板31之上表面，及該第二表面312 係可置換為該基板31之下表面。 ❿ 請參縣3]3及3(：騎示，本發明第-實侧之堆疊式封 裝構造及其基板製造方法第二步驟係：在該基板31之第一表 面311认置-間隔層32，該間隔層32具有數個通孔321對應 於該第-表面311之焊墊313。在本步驟中，該間隔層％係 選自異於封裝材料之間隔材料，例如絕緣基板材料，以便適用 於基板製程’並整合於基板餘巾。例如，制隔層32之絕 緣基板材料可選自陶紐料(_nic material)或騎材料_ material)。再者’在本實施例中，該間隔層％係先形成於該基 12 201010049 板31之第一表面311上，接著再對該間隔層32進行鑽孔，以 形成該通孔321。本發明可選擇藉由機械鐵孔或電射鑽孔之方 式在該間隔層32形成該通孔32卜惟’林㈣之其他實施 例中，亦可選擇預先製備該_層32後，再黏接於該基板31 之第-表面311上。此時’該間隔層32可選擇先錯孔形成該 通孔321後，再黏接於該基板31 ;或者，該間隔層32可選擇 先黏接於該基板31後，再鑽孔形成該通孔321。再者，在本 步驟中，該間隔層32僅形成於該基板31之第一表面311之周 圍區域，至於該第-表面311之中央區域則保持裸露狀態。 請參照第3D圖所示’本發明第一實施例之堆叠式封裝構 造及其基板製造方法第三步驟係:在該間隔層32之各通孔321 内分別形成一導電柱322，以電性連接該焊墊313。在本步驟 中’本發明可選擇藉由電鍵(plating)或印刷⑦細㈣之方式在 該間隔層32之通孔321内形成該導電柱322。在進行電鑛或 印刷之前，較佳預先在該間隔層32及第一表面311之裸露處 塗佈-光阻層(未繪示）’並對該光阻層進行曝光顯影，以裸露 該通孔321 ’以便進行電鍍或印刷。再者，該導電柱322係選 自熔點大於錫之金屬或合金，例如銅、銀或金，特別是銅。在 某些使用狀態下，該導電柱322係可選擇性的選自具有電阻、 電感或電容特性之金屬或合金，如此該導電柱322可使用做為 一被動元件。再者，在本實施例中，該導電柱322係實質突出 13 201010049 於該間隔層32之通孔321外，並高於該間隔層32之表面^惟， 在本發明之其他實施例中，該導電柱322亦可選擇實質平齊於 該間隔層32之表面。 、 請參照第3E圖所示’本發明第一實施例之堆疊式封裝構造 及其基板製造方法第四步驟係：在該基板31之第二表面312 設置至少一晶片33’並利用一封裝材料34包埋該晶片％，以 組成一封裝體3。在本實施例中，第四步驟係一選擇性步驟， 本發明僅在必需製造該封裝體3射需進行該細步驟。在本 步驟中’該晶片33係可藉由金屬線(wire)或金屬凸塊(bump) 電性連接至該基板3卜且該晶片33之數量可選自丨個、2個 或2個以上，並不加以限制。當設有至少二該晶片汨時，該 二a曰片33之間可選擇以鄰接(side_by_side)或堆疊(血如^㈣ 的方式排列於該基板31之第二表面312。再者，除了該晶片 %之外，該基板31之第二表面312亦可選擇設置至少一被動 元件(未繪示）。 "月參照第4A、4B、4C及4D圖所示，本發明第二實施例 之堆疊式封裝構4：之基板製造綠的主要步驟餘似於本發 明第-實施例，故其相似之構件將沿用第—實施例之圖號並省 略其詳細制。如第4A圖所示，該第二實補與第—實施例 之差異在於：在本實施例之第二步驟中，該間隔層32係選自 異於封裝材料之其他咖材料，例如金屬材料，以便適用於基 201010049 板製程，並整合於基板製程中。該間隔層32之金屬材料較佳 可選鍍錄銅板(Cu plate with Ni plating layer)，其係預先製備後 再黏接於該基板31之第一表面mi上。再者，該間隔層32之 通孔321内係先塗佈一絕緣層32〇後，再形成該導電柱322， 以隔絕該間隔層32及導電桎322。本發明可選擇在該基板31 設置該間隔層32之前或之後，形成該絕緣層32〇。 請參照第5A及5B圖所示，本發明第三實施例之堆疊式封 裝構造係將本發明第一及第二實施例製備之封裝體應用於堆 疊結合另一封裝體’其相似之構件將沿用第一及第二實施例之 圖號並省略其詳細說明。如第5A圖所示，該第三實施例之堆 疊式封裝構造係包含：一第一封裝體3及一第二封裝體4，該 第-封裝體3選擇堆叠於該第二封裝體4之上方，且該第一封 裝體3具有-基板31面對該第二封裝體4之一第一表面 係設有-間隔層32，該第一表面311係該基板31之底表面。 再者’該間隔層32内具有數個通孔32卜各該通孔321内分 別形成-導電柱322。該間隔層32之導電柱似用以電性連 接相互堆疊之該第-封裝體3及—第二封裝體4。在本實施例 中，該第-封裝體3除了該基板31及間隔層32之外另在該 基板31之-第二表面312言史有至少一晶片％及一封裝材料 34。該第二封裝體4亦具有一基板41、該基板41具有一第一 表面411及第一表面412，該第一表面設有數個谭球 15 201010049 42，及該第二表面412設有數個焊墊413、至少一晶片43及 一封裝材料44。 4再參照第5A及5B圖所示，當本發明第三實施例堆疊該 第一封裝體3及第二封裝體4時，首先選擇在該第二封裝體4 的焊墊41上或該第一封裝體3的導電柱322上預先設置一導 電介質5。接著’將該第一封裝體3堆疊到該第二封裝體4之 上，並透過該導電介質5電性連接該焊墊41及導電柱322。 藉此，即可組成一封裝體堆疊封裝體構造⑦沉匕职〇n package，POP)。在本實施例中，該導電介質5係可選自藉由 錫膏(solder paste)、超音波焊接(ultras〇nic welding)、熱壓 (therm〇-pressure)結合或異方性導電層㈣犯加咖c〇nductive film ’ ACF)等所形成之結合部。再者，在本發明之其他實施例 中，該第一封裝體3亦可選擇堆疊於該第二封裝體4之下方， 且該間隔層32設於該第一封裝體3之基板31的第一表面 311，該第一表面33係該基板31之上表面。 請參照第6A及6B圖所示，本發明第四實施例之堆疊式封 裝構造係將本發明第一及第二實施例製備之封裝體應用於堆 疊結合另一封裝體’並相似於第三實施例。如第6a及6B圖 所示，該第四實施例與第三實施例之差異在於：該第一封裝體 3之基板31面對該第二封裝體4之一第一表面311(亦即底表 面)設有一第一間隔層32;且該第二封裝體4之基板41面對該 201010049 第-雖體3之-第二表面411(亦即上表面)聰設有一第二 間隔層45，該第-間隔層32及第二間隔層45對應設有數個 導電柱322、451。該導電柱322及451之間。當該第一封裝 體3堆叠到該第二封裝體4上時，同樣可透過數個導電介質5 電性連接該導電柱322及451。該導電介質5係可選自錫貪結 合部、超音波焊接結合部、熱壓結合部或異方性導電層。 如上所述，相較於習用封裝體堆疊封裝體構造(POP)之製造 方法存在··研磨加卫量大、加瑞確度要求高、可能發生勉曲 變形、因研磨剌或焊材内聚力影_合強度、模具設計受 限’及連觸球佈局密度無法提高等缺點，第3至6圖之本發 明藉由在該基板31之第-表面311設置該間隔層32，並在該 間隔層32内形成該導電柱322，以電性連接相互堆疊之該第 -及第二封裝體3、4，且在製財不需進行補加工，其確 级 實可以有效簡化基板製程、增加結合強度、提高堆叠良率。再 者’由於該間隔層32内之導電柱322係呈柱狀，不會佔用過 多空間’進而亦有利於縮減電性連接通路之間距及提高電性連 接通路之佈局密度。 雖然本發明已以較佳實施例揭露，然其並非用以限制本發 明，任何熟習此項技藝之人士，在不脫離本發明之精神和範圍 内，當可作各種更動與修飾，因此本發明之保護範圍當視後附 之申請專利範圍所界定者為準。 17 201010049 【圖式簡單說明】 示意圖。1B、1C及1D圖：制堆疊式聰構造之製造方法 圖·習用堆疊式封裝構造之連接踢球區域之酿 第2A及2B 照相圖。 3C 3D及3E圖：本發明第一實施例之堆疊 裝構造之Μ製造方法之示意圖。 第A 4B、4C及4D圖：本發明第二實施例之堆叠式封裳構 造之基板製造方法之示意圖。 :之示意 第5A及5B圓：本發明第三實施例之堆疊式封裝構造 圖。 之示意 第6A及6B圖：本發明第四實施例之堆疊式封裝構造 圖。 Ο 11基板 13晶片 141截面 2 第二封裝體 22第二錫球 24封裝材料 【主要元件符號說明】 1 第一封裝體 12第一錫球 14連接錫球 15封裝材料 21基板 23晶片 201010049201〇l〇〇49 sadness rate. The method for manufacturing a substrate made by the lion red seal of the invention is provided on the side of the substrate - _, and in the conductive column, (10) does not need to be polished, thereby facilitating the simplification of the substrate process And improve processing yield. The object of the present invention is to provide a structure of a county and a method for manufacturing the same, wherein the impurity system in the layer is recorded without occupying too much space, thereby facilitating the reduction of the electrical connection path and the improvement of the electrical connection. The layout density of the vias. In order to achieve the above purpose, the present invention provides a package of a package, which includes a package body and a second package body, and the first package body is selected to be stacked above or below the first package body, and The first package has a substrate facing the surface of the second package with a spacer layer. The spacer layer has a plurality of through holes, and a conductive pillar is formed in each of the through holes. The conductive pillars of the spacer layer are electrically connected to the first and second packages stacked on each other. In an embodiment of the invention, the first package is stacked above the second package, and the substrate of the first package is provided with the spacer layer on a bottom surface. In an embodiment of the present invention, the first package is stacked under the second package, and the substrate of the first package is disposed on an upper surface of the space 201010049. In an embodiment of the present invention The second package has a substrate facing the surface of the first seal, and a plurality of materials are disposed between the solder bumps of the second package and the conductive pillars of the spacer layer of the first sealing body The system is electrically connected by a conductive medium. In an embodiment of the invention, the second package has a substrate, and another surface layer is disposed on a surface of the first package, and the spacer layer is provided with a plurality of conductive columns. The conductive pillars of the first package and the conductive pillars of the second package are respectively electrically connected by a conductive medium. In one embodiment of the invention, the electrically conductive medium is selected from the group consisting of solder pastes.卩, ultrasonic welding (ultfas〇nic weWing) joint, hot pressing (th__pressure) joint or anisotropic conductive layer (4), such as film, ACF). In another aspect, the present invention provides a substrate manufacturing method of a stacked package structure, comprising: providing a substrate having a first surface, a second surface, and a plurality of pads; disposed on a first surface of the substrate - The spacer layer has a plurality of through holes corresponding to the rotation of the first surface; and a conductive pillar is formed in each of the through holes of the barrier layer to connect the soldering iron. In the embodiment t of the present invention, at least a wafer may be selectively disposed on the second surface of the substrate, and the wafer may be embedded with a packaging material to constitute a package. In the practice of the present invention, the first surface is the bottom surface of the substrate, 9 201010049. The spacer layer is disposed on the bottom surface of the substrate. In an embodiment of the invention, the first surface is an upper surface of the substrate, and the spacer layer is disposed on an upper surface of the substrate. In an embodiment of the invention, the through hole is formed in the spacer layer by mechanical drilling or electro-drilling. In one embodiment of the invention, the conductive pillars are selected to be formed in the vias of the spacer layer by means of electroplating (pWing) or printing. In an embodiment of the present invention, before performing the electric key or printing, a photoresist layer is coated on the exposed layer and the exposed surface of the first surface of the substrate, and the photoresist layer is exposed and developed to expose the pass. Hole, then electric or mine. In one embodiment of the invention, the electrically conductive pillar is selected from a metal or alloy having a melting point greater than tin, such as copper, silver or gold. Furthermore, the conductive pillars are selectively selected from metals or alloys having electrical, electrical or capacitive properties. In an embodiment of the invention, the conductive pillars protrude substantially beyond the through holes of the spacer layer and are higher than the surface of the spacer layer. Alternatively, the conductive pillars are substantially flush with the surface of the spacer layer. In one embodiment of the invention, the spacer layer is selected from a spacer material that is different from the sealing material, such as an insulating substrate material or a metal material, to be suitable for substrate processing and integrated into the substrate process. In an embodiment of the invention, the insulating substrate material of the spacer layer may be selected from a ceramic material or a core material. Furthermore, 201010049, the spacer layer is selected to be directly formed on the first surface of the substrate, or is prepared and adhered to the first surface of the substrate. In an embodiment of the invention, the metal material of the spacer layer may be selected from a Cu plate with M plating layer, which is pre-prepared and then bonded to the first surface of the substrate. Further, after the insulating layer is coated in the via hole of the spacer layer, the conductive pillar is formed. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. Referring to FIGS. 3A, 3B, 3C, 3D, and 3E, the substrate manufacturing method of the stacked package structure according to the first embodiment of the present invention is for manufacturing a substrate for stacking at least an i package into a package. Stacked package structure β (package on package ' P0P). The substrate manufacturing method mainly includes the following steps: providing a substrate 3 having a first surface 3U, a second surface 312, and a plurality of solder pads 313; and providing a spacer layer 32 on the first surface 311 of the substrate 31, The spacer layer 32 has a plurality of vias 321 corresponding to the first surface 3 ι 313; and a plurality of vias 321 are formed in the vias 321 to electrically connect the pads 313. Furthermore, at least one wafer % may be selectively disposed on the second surface 312 of the substrate 31, and the wafer 33' may be embedded by a package material 34 to form a package 3. The present invention will be described in detail below with respect to the first to fourth steps in 201010049. Referring to FIG. 3A, a stacked package structure according to a first embodiment of the present invention and a substrate manufacturing method thereof provide a substrate 3 having a first surface 31 and a second surface 312 and a plurality of Weld 313. In this step, the substrate 31 can be selected from a single-layer circuit board or a multi-layer circuit board as required, and the single-layer circuit board refers to a circuit board having a single-insulation layer and a two-surface circuit layer, and the multi-layered circuit S A circuit board having a plurality of insulating layers, two surface circuit layers, and a plurality of inner circuit layers. Further, the 313 is a part of the surface circuit layer exposed by the first surface 311 and the second surface 312 of the substrate 31. In the present embodiment, the first surface 311 refers to the surface of the substrate 31, and the second surface 312 refers to the surface of the substrate 31. In the other real (4), the first surface 311 It is also possible to replace the upper surface of the substrate 31, and the second surface 312 can be replaced with the lower surface of the substrate 31. ❿ 参 3 3 3 3 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参 参The spacer layer 32 has a plurality of vias 321 corresponding to the pads 313 of the first surface 311. In this step, the spacer layer % is selected from a spacer material different from the packaging material, such as an insulating substrate material, so as to be applicable. In the substrate process 'and integrated into the substrate waste. For example, the insulating substrate material of the barrier layer 32 may be selected from a _nic material or a material. Further, in the present embodiment, the spacer layer % is first formed on the first surface 311 of the substrate 12 201010049, and then the spacer layer 32 is drilled to form the via hole 321. The invention may select another embodiment in which the through hole 32 is formed in the spacer layer 32 by means of mechanical iron hole or electro-radiation drilling, or may be selected after the _ layer 32 is prepared in advance. Connected to the first surface 311 of the substrate 31. At this time, the spacer layer 32 can be formed by first forming the via hole 321 and then bonding to the substrate 31. Alternatively, the spacer layer 32 can be bonded to the substrate 31 first, and then drilled to form the through hole. Hole 321. Furthermore, in this step, the spacer layer 32 is formed only in the peripheral region of the first surface 311 of the substrate 31, and the central region of the first surface 311 remains in a bare state. The third step of the stacked package structure and the substrate manufacturing method of the first embodiment of the present invention is as follows: a conductive pillar 322 is formed in each of the through holes 321 of the spacer layer 32 to electrically The pad 313 is connected. In this step, the present invention can optionally form the conductive pillars 322 in the vias 321 of the spacer layer 32 by means of plating or printing. Preferably, a photoresist layer (not shown) is applied to the exposed portions of the spacer layer 32 and the first surface 311 before the electrowinning or printing is performed, and the photoresist layer is exposed and developed to expose the pass. Hole 321 'for plating or printing. Further, the conductive pillars 322 are selected from metals or alloys having a melting point greater than tin, such as copper, silver or gold, particularly copper. In some states of use, the conductive pillars 322 are selectively selected from metals or alloys having electrical, electrical, or capacitive properties such that the conductive pillars 322 can be used as a passive component. Furthermore, in this embodiment, the conductive pillar 322 is substantially protruded from the through hole 321 of the spacer layer 32 and higher than the surface of the spacer layer 32. In other embodiments of the present invention, The conductive pillars 322 can also be selected to be substantially flush with the surface of the spacer layer 32. Referring to FIG. 3E, a fourth embodiment of the stacked package structure and the substrate manufacturing method thereof according to the first embodiment of the present invention is characterized in that at least one wafer 33' is disposed on the second surface 312 of the substrate 31 and an encapsulating material is utilized. 34% of the wafer is embedded to form a package 3. In the present embodiment, the fourth step is an optional step, and the present invention only needs to perform the fine step when it is necessary to manufacture the package. In this step, the wafer 33 can be electrically connected to the substrate 3 by wires or metal bumps, and the number of the wafers 33 can be selected from one, two or more. , not limited. When at least two of the wafer cassettes are provided, the two a-side sheets 33 may be arranged adjacent to each other on the second surface 312 of the substrate 31 in a side (by_by_side) or stack (blood as ^4). In addition to the % of the wafer, the second surface 312 of the substrate 31 may optionally be provided with at least one passive component (not shown). "Monthly Referring to Figures 4A, 4B, 4C and 4D, the second embodiment of the present invention The main steps of manufacturing the green of the stacked package 4: the same as the first embodiment of the present invention, the similar components will follow the drawings of the first embodiment and the detailed system will be omitted. As shown in FIG. 4A, The second complement is different from the first embodiment in that, in the second step of the embodiment, the spacer layer 32 is selected from other coffee materials different from the packaging material, such as a metal material, so as to be suitable for the base 201010049 board. The process is integrated into the substrate process. The metal material of the spacer layer 32 is preferably a Cu plate with a Ni plating layer, which is pre-prepared and then bonded to the first surface mi of the substrate 31. Furthermore, the through hole 321 of the spacer layer 32 is coated first. After the insulating layer 32 is formed, the conductive pillar 322 is further formed to isolate the spacer layer 32 and the conductive germanium 322. The present invention may optionally form the insulating layer 32 before or after the spacer 31 is disposed on the substrate 31. 5A and 5B, the stacked package structure of the third embodiment of the present invention applies the package prepared by the first and second embodiments of the present invention to a stack and another package body. The first embodiment of the stacked package structure includes a first package 3 and a second package 4, as shown in FIG. 5A. The first package body 3 is disposed above the second package body 4, and the first package body 3 has a substrate layer 31 facing the first surface of the second package body 4 and is provided with a spacer layer 32. The first surface 311 is a bottom surface of the substrate 31. Further, the spacer layer 32 has a plurality of through holes 32. Each of the through holes 321 defines a conductive pillar 322. The conductive pillar of the spacer layer 32 is similar to Electrically connecting the first package 3 and the second package 4 stacked on each other. In the example, the first package body 3 has at least one wafer % and one encapsulation material 34 on the second surface 312 of the substrate 31 in addition to the substrate 31 and the spacer layer 32. The second package body 4 is also The substrate 41 has a first surface 411 and a first surface 412. The first surface is provided with a plurality of Tan balls 15 201010049 42 , and the second surface 412 is provided with a plurality of pads 413 and at least one wafer 43 . And a package material 44. Referring to FIGS. 5A and 5B, when the first package 3 and the second package 4 are stacked in the third embodiment of the present invention, the soldering of the second package 4 is first selected. A conductive medium 5 is preliminarily disposed on the pad 41 or on the conductive post 322 of the first package 3. Then, the first package 3 is stacked on the second package 4, and the pad 41 and the conductive pillars 322 are electrically connected through the conductive medium 5. Thereby, a package stack structure 7 can be formed into a package, POP). In this embodiment, the conductive medium 5 can be selected from the group consisting of solder paste, ultrasonic welding, thermther-pressure bonding or the anisotropic conductive layer (4). A joint formed by a coffee, c〇nductive film 'ACF) or the like. Furthermore, in other embodiments of the present invention, the first package 3 may be stacked under the second package 4, and the spacer layer 32 is disposed on the substrate 31 of the first package 3. A surface 311 is the upper surface of the substrate 31. Referring to FIGS. 6A and 6B, the stacked package structure according to the fourth embodiment of the present invention applies the package prepared by the first and second embodiments of the present invention to a stack and another package' and is similar to the third. Example. As shown in FIGS. 6a and 6B, the difference between the fourth embodiment and the third embodiment is that the substrate 31 of the first package 3 faces the first surface 311 of the second package 4 (ie, the bottom). a first spacer layer 32 is disposed on the surface of the first package body 4; and the second surface layer 45 is disposed on the second surface 411 (ie, the upper surface) of the second substrate 411 (ie, the upper surface) of the second package body 4; The first spacer layer 32 and the second spacer layer 45 are provided with a plurality of conductive pillars 322 and 451. Between the conductive pillars 322 and 451. When the first package 3 is stacked on the second package 4, the conductive pillars 322 and 451 are also electrically connected through a plurality of conductive media 5. The conductive medium 5 may be selected from the group consisting of a solder joint, an ultrasonic solder joint, a thermocompression joint, or an anisotropic conductive layer. As described above, the manufacturing method of the conventional package stacked package structure (POP) exists. · The grinding amount is large, the accuracy of the Gard is high, the distortion may occur, and the grinding force or the welding material cohesion force _ The present invention of FIGS. 3 to 6 is provided with the spacer layer 32 on the first surface 311 of the substrate 31, and the spacer layer 32 is disposed on the first surface 311 of the substrate 31, which is limited in strength, mold design limitation, and the density of the contact ball layout. The conductive pillar 322 is formed to electrically connect the first and second package bodies 3 and 4 stacked on each other, and does not need to be processed in the manufacturing process, and the level of the substrate can effectively simplify the substrate process and increase the bonding strength. Improve stacking yield. Moreover, since the conductive pillars 322 in the spacer layer 32 are columnar, they do not occupy excessive space, which is also advantageous for reducing the distance between the electrical connection vias and increasing the layout density of the electrical connection vias. The present invention has been disclosed in its preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 17 201010049 [Simple description of the diagram] Schematic. 1B, 1C, and 1D diagrams: Manufacturing method of stacking and sturdy structure Fig. 2 of the stacked-package structure to connect the kicking area. 2A and 2B. 3C 3D and 3E drawings: A schematic view of a crucible manufacturing method of the stacked structure of the first embodiment of the present invention. Figs. 4A, 4C and 4D are schematic views showing a method of manufacturing a substrate of a stacked package structure according to a second embodiment of the present invention. Fig. 5A and 5B are circles: a stacked package structure diagram of a third embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 6A and 6B are views showing a stacked package structure of a fourth embodiment of the present invention. Ο 11 substrate 13 wafer 141 section 2 second package 22 second solder ball 24 package material [Main component symbol description] 1 first package 12 first solder ball 14 solder ball 15 package material 21 substrate 23 wafer 201010049

3 第一封裝體 311第一表面 313焊墊 320絕緣層 322導電柱 34封裝材料 41基板 412第二表面 43晶片 45第二間隔層 5 導電介質 31基板 312第二表面 32間隔層 321通孔 33晶片 4 第二封裝體 411第一表面 42焊球 44封裝材料 451導電柱3 first package 311 first surface 313 pad 320 insulating layer 322 conductive column 34 encapsulation material 41 substrate 412 second surface 43 wafer 45 second spacer layer 5 conductive medium 31 substrate 312 second surface 32 spacer layer 321 through hole 33 Wafer 4 second package 411 first surface 42 solder ball 44 encapsulation material 451 conductive column

Claims (1)

201010049 十、申請專利範圍： 1. 一種堆疊式封裝構造，其包含： 一第一封裴體，其具有一基板； 一第二封缝，其選擇堆該第—封裝體之上方或 及 ， =間隔層’其設在該第-封紐之基板_鄕二封裝體之 ❺ =表®上’該__具魏贿孔，各騎制分卿成 —導電柱，料電㈣錢接相互堆疊之該帛—及第二封 BA 體0 2·如申請專概M1項所述之堆疊式封裝構造，其中該第一 封装體堆疊於該第二封裝體之上方，且該第一封裝體之基板 係在一底表面設有該間隔層。 3·如申請專利範圍第i項所述之堆疊式封裝構造，其中該第一 备 _體堆砂該第三封裝體之下方，且該第—封裝體之基板 係在一上表面設有該間隔層。 4. 如申請專利範圍第1項所述之堆叠式封裝構造，其中該第二 封装體具有一基板’其面對該第一封裝體之一表面係設有數 個焊墊，該第二封裝體之焊整與該第一封裝體之間隔層的導 電柱之間係分別藉由一導電介質形成電性連接。 5. 如申請專利範圍第4項所述之堆疊式封裝構造，其中該導電 介質係選自錫膏結合部、超音波焊接結合部、熱壓結合部或 異方性導電層。 20 201010049 封申清專利範圍第1項所述之堆叠式封裝構造，其中該第二 有=體具有—基板，其面對該第—封裝體之—表面係對應設 間隔層，該間隔層對應設有數個導電柱。 申明專她㈣6項所述之堆叠式封裝構造，其中該第一 一裝體之導電柱與該第二封紐之導電柱之間係分別藉由 一導電介f形錢性連接。 ❹ ^申w專利範圍第7項所述之堆4式難構造，其中該導電 ;1質係選自錫膏結合部、超音波焊接結合部、熱壓結合部或 異方性導電層。 飞 9,如申請專利範圍第1項所述之堆疊式封裝構造，其中該導電 柱係選自熔點大於錫之金屬或合金。 如申明專利範圍第9項所述之堆疊式封裝構造，其中該導電 柱係選自銅、銀或金。 ❹ U.如申料利細第1或9項所述之堆叠式封裝構造，其中該 導電柱係選自具有電阻、電感或電容特性之金屬或合金。 I2·如申δ|專利細第丨項所狀堆φ式封裝構造，其中該導電 柱係實質突出於該間隔層之通孔外，並高於該間隔層之表 面。 I3.如申請專利範圍第i項所述之堆疊式封裝構造，其中該導電 柱係實質平齊於該間隔層之表面。 14·如申請專利範圍第！項所述之堆4朗裝構造，其中該間隔 21 201010049 • 層係選自異於封襄材料之間隔材料，其包含絕緣基板材料或 金屬材料。 15.如申請專利範㈣14項所述之堆叠式封裝構造，其中該間 隔層之絕緣基板材料選自陶瓷材料或芯層材料。 16·如申請專利範圍第14項所述之堆疊式封裝構造，其中該間 隔層之金屬材料選自鑛錄銅板。 ❹ 17.如申明專利範圍第卜Μ或Ιό項所述之堆疊式封裝構造， 其中該間隔層之通孔内塗佈一絕緣層，以隔絕該間隔層及導 電柱。 18. —種堆疊式封裝構造之基板製造方法，其包含： 提供一基板，其具有一第一表面、一第二表面及數個焊墊； 在該基板之第一表面設置一間隔層，該間隔層具有數個通孔 對應於該第一表面之焊塾；及 鲁 在該間隔層之各通孔内分別形成一導電柱，以電性連接該焊 塾。 19. 如申請專利範圍第18項所述之堆叠式封裝構造之基板製造 方法，其中在形成該導電柱後，另在該基板之第二表面設置 至少一晶片，並利用一封裝材料包埋該晶片，以組成一封裝 體。 20. 如申請專利範圍第18項所述之堆疊式封裝構造之基板製造 方法，其中在設置該間隔層時，該間隔層係選擇直接形成於 22 201010049 該基板之第一表面上’接著才在該間隔層上形成該通孔β 21. 如申請專利範圍第18項所述之堆疊式封裝構造之基板製造 方法’其中在設置該間隔層時，該間隔層係預先製備後再黏 接於§亥基板之第一表面上。 22. 如申請專利範圍第21項所述之堆疊式封裝構造之基板製造 方法’其中在將該間隔層黏接於該基板之前，先在該間隔層 上形成該通孔β 23. 如申請專利範圍第21項所述之堆疊式封裝構造之基板製造 方法’其中在將該間隔層黏接於該基板之後，才在該間隔層 上形成該通孔。 24·如申請專利細第18項所述之堆疊式封裝構造之基板製造 方法’其中該第一表面係該基板之底表面，該間隔層係設於 該基板之底表面。 25·如申請專概圍第18項所述之堆疊式封裝構造之基板製造 方法，其中該第一表面係該基板之上表面，該間隔層係設於 該基板之上表面。 26·如申請專·_ 18項所狀堆Φ式封裝構造之基板製造 方法’其中在形成該通孔時，選擇藉由機械鑽孔或電射鑽孔 之方式在該間隔層形成該通孔。 27.如申料魏_ 18撕叙堆4式封㈣造之基板製造 方法，其中在形成該導電柱時，選擇藉由電鍵或印刷之方式 23 201010049 在該間隔層之通孔内形成該導電柱。 28. 如申請專利範圍第27項所述之堆疊式封裝構造之基板製造 方法’其中在進行電鍍或印刷之前，預先在該間隔層及基板 第一表面之裸露處塗佈一光阻層，並對該光阻層進行曝光顯 影’以裸露該通孔’再進行電鍵或印刷。 29. 如申請專利範圍第18項所述之堆疊式封裝構造之基板製造 方法，其中該導電柱係選自熔點大於錫之金屬或合金。 30. 如申請專利範圍第25項所述之堆疊式封裝構造之基板製造 方法’其中該導電柱係選自銅、銀或金。 31·如申請專利範圍第18或29項所述之堆疊式封裝構造之基板 製造方法’其中該導電柱係選自具有電阻、電感或電容特性 之金屬或合金。 32. 如申請專利範圍第18項所述之堆疊式封裝構造之基板製造 方法’其中該導電柱係實質突出於該間隔層之通孔外，並高 於該間隔層之表面。 33. 如申請專利範圍第18項所述之堆疊式封裝構造之基板製造 方法，其中該導電柱係實質平齊於該間隔層之表面。 34·如申請專麵®第丨8摘述之堆叠式封裝構造之基板製造 方法，其中該間隔層係選自異於封裝材料之間隔材料，其包 含絕緣基板材料或金屬材料。 35.如申請專圍第％項所叙科式封裝觀之基板製造 24 201010049 方法，其中該間隔層之絕緣基板材料選自陶瓷材料或芯層材 * 料。 36. 如申請專利範圍第34項所述之堆疊式封裝構造之基板製造 方法，其中該間隔層之金屬材料選自鑛鎳銅板。 37. 如申請專利範圍第18、34或36項所述之堆疊式封裝構造之 基板製造方法，其中該間隔層之通孔内塗佈一絕緣層，以隔 絕該間隔層及導電柱。201010049 X. Patent Application Range: 1. A stacked package structure comprising: a first sealing body having a substrate; a second sealing seam selected to stack above the first package or The spacer layer 'is located on the substrate of the first-season _ 鄕 two package ❺ = table о on the __ has a bribe hole, each riding system into a - conductive column, electricity (four) money stack stacked The stacked package structure described in the above-mentioned application, wherein the first package is stacked above the second package, and the first package is The substrate is provided with the spacer layer on a bottom surface. 3. The stacked package structure of claim i, wherein the first body is sanded below the third package, and the substrate of the first package is provided on an upper surface Spacer layer. 4. The stacked package structure of claim 1, wherein the second package has a substrate having a plurality of pads facing a surface of the first package, the second package The soldering is electrically connected to the conductive pillars of the spacer layer of the first package by a conductive medium. 5. The stacked package structure of claim 4, wherein the conductive medium is selected from the group consisting of a solder paste bond, an ultrasonic solder joint, a thermocompression bond, or an anisotropic conductive layer. The present invention provides a stacked package structure according to the first aspect of the invention, wherein the second body has a substrate, and a surface layer corresponding to the surface of the first package is provided with a spacer layer corresponding to the spacer layer. There are several conductive columns. The invention discloses a stacking package structure according to the item (4), wherein the conductive pillars of the first package and the conductive pillars of the second capacitor are respectively connected by a conductive type.堆 申 申 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 。 。 。 。 。 。 。 。 。 。 。 。 。 The stacked package structure of claim 1, wherein the conductive pillar is selected from the group consisting of a metal or an alloy having a melting point greater than that of tin. The stacked package structure of claim 9, wherein the conductive pillar is selected from the group consisting of copper, silver or gold. The stacked package structure of claim 1 or 9, wherein the conductive pillar is selected from the group consisting of a metal or an alloy having electrical, electrical, or capacitive properties. I2. The φ-type package structure of the stencil of the patent δ, wherein the conductive pillar substantially protrudes beyond the through hole of the spacer layer and is higher than the surface of the spacer layer. I3. The stacked package structure of claim i, wherein the conductive pillars are substantially flush with the surface of the spacer layer. 14·If you apply for a patent scope! The stack 4 truss construction described in the section, wherein the interval 21 201010049 • The layer is selected from a spacer material different from the sealing material, which comprises an insulating substrate material or a metal material. 15. The stacked package structure of claim 4, wherein the insulating substrate material of the spacer layer is selected from a ceramic material or a core material. The stacked package structure of claim 14, wherein the metal material of the spacer layer is selected from the group consisting of a copper plate. The stacked package structure of claim 2, wherein an insulating layer is coated in the via hole of the spacer layer to isolate the spacer layer and the conductive post. 18. A substrate manufacturing method of a stacked package structure, comprising: providing a substrate having a first surface, a second surface, and a plurality of pads; and providing a spacer layer on the first surface of the substrate, The spacer layer has a plurality of via holes corresponding to the solder pads of the first surface; and a conductive pillar is formed in each of the via holes of the spacer layer to electrically connect the solder bumps. The substrate manufacturing method of the stacked package structure according to claim 18, wherein after the conductive pillar is formed, at least one wafer is further disposed on the second surface of the substrate, and the package material is used to embed the package. Wafers to form a package. 20. The substrate manufacturing method of the stacked package structure according to claim 18, wherein, when the spacer layer is disposed, the spacer layer is selected to be directly formed on the first surface of the substrate of 2010201049. The through hole β is formed on the spacer layer. The substrate manufacturing method of the stacked package structure according to claim 18, wherein when the spacer layer is provided, the spacer layer is prepared in advance and then bonded to § On the first surface of the substrate. The substrate manufacturing method of the stacked package structure according to claim 21, wherein the through hole β is formed on the spacer layer before the spacer layer is adhered to the substrate. The substrate manufacturing method of the stacked package structure of claim 21, wherein the via hole is formed on the spacer layer after the spacer layer is bonded to the substrate. The method of manufacturing a substrate of a stacked package structure as described in claim 18, wherein the first surface is a bottom surface of the substrate, and the spacer layer is provided on a bottom surface of the substrate. The substrate manufacturing method of the stacked package structure according to Item 18, wherein the first surface is an upper surface of the substrate, and the spacer layer is disposed on an upper surface of the substrate. 26. The method for manufacturing a substrate according to the application of the Φ-type package structure of the invention, wherein in forming the through hole, the through hole is formed in the spacer layer by mechanical drilling or electric drilling. . 27. The substrate manufacturing method of claim 4, wherein in forming the conductive pillar, selecting the conductive layer or the printing method 23 201010049 to form the conductive in the via hole of the spacer layer column. 28. The substrate manufacturing method of the stacked package structure according to claim 27, wherein before the plating or printing, a photoresist layer is applied in advance to the spacer layer and the exposed surface of the first surface of the substrate, and The photoresist layer is subjected to exposure development "to expose the via hole" and then to perform electrical keying or printing. 29. The substrate manufacturing method of the stacked package structure according to claim 18, wherein the conductive pillar is selected from a metal or an alloy having a melting point greater than that of tin. 30. The substrate manufacturing method of the stacked package structure according to claim 25, wherein the conductive pillar is selected from the group consisting of copper, silver or gold. The substrate manufacturing method of the stacked package structure as described in claim 18 or 29 wherein the conductive pillar is selected from a metal or alloy having electrical resistance, inductance or capacitance characteristics. The substrate manufacturing method of the stacked package structure according to claim 18, wherein the conductive pillar substantially protrudes beyond the through hole of the spacer layer and is higher than the surface of the spacer layer. The substrate manufacturing method of the stacked package structure according to claim 18, wherein the conductive pillar is substantially flush with a surface of the spacer layer. 34. A substrate manufacturing method of a stacked package structure as claimed in the application of the first aspect, wherein the spacer layer is selected from a spacer material different from the encapsulating material, and comprises an insulating substrate material or a metal material. 35. The method of claim 1, wherein the insulating substrate material of the spacer layer is selected from the group consisting of ceramic materials or core materials. The substrate manufacturing method of the stacked package structure according to claim 34, wherein the metal material of the spacer layer is selected from the group consisting of a nickel-nickel copper plate. The substrate manufacturing method of the stacked package structure according to claim 18, 34 or 36, wherein an insulating layer is coated in the via hole of the spacer layer to block the spacer layer and the conductive pillar. 2525
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CN103515362A (en) * 2012-06-25 2014-01-15 台湾积体电路制造股份有限公司 Package on package device and method of packaging semiconductor die
TWI458026B (en) * 2012-01-13 2014-10-21 Dawning Leading Technology Inc Package module with package embedded therein and method for manufacturing the same
TWI501365B (en) * 2010-10-13 2015-09-21 Ind Tech Res Inst Package unit, stacking structure thereof and manufacturing method thereof
US9775246B2 (en) 2015-08-07 2017-09-26 Unimicron Technology Corp. Circuit board and manufacturing method thereof
CN107910321A (en) * 2016-10-26 2018-04-13 日月光半导体制造股份有限公司 Semiconductor device and semiconductor fabrication process

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI501365B (en) * 2010-10-13 2015-09-21 Ind Tech Res Inst Package unit, stacking structure thereof and manufacturing method thereof
TWI458026B (en) * 2012-01-13 2014-10-21 Dawning Leading Technology Inc Package module with package embedded therein and method for manufacturing the same
CN103515362A (en) * 2012-06-25 2014-01-15 台湾积体电路制造股份有限公司 Package on package device and method of packaging semiconductor die
US9397080B2 (en) 2012-06-25 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
CN103515362B (en) * 2012-06-25 2016-12-21 台湾积体电路制造股份有限公司 Stacked package device and the method for encapsulation semiconductor element
US9775246B2 (en) 2015-08-07 2017-09-26 Unimicron Technology Corp. Circuit board and manufacturing method thereof
CN107910321A (en) * 2016-10-26 2018-04-13 日月光半导体制造股份有限公司 Semiconductor device and semiconductor fabrication process
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