JP4033968B2 - Multiple chip mixed semiconductor device - Google Patents

Multiple chip mixed semiconductor device Download PDF

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Publication number
JP4033968B2
JP4033968B2 JP10413298A JP10413298A JP4033968B2 JP 4033968 B2 JP4033968 B2 JP 4033968B2 JP 10413298 A JP10413298 A JP 10413298A JP 10413298 A JP10413298 A JP 10413298A JP 4033968 B2 JP4033968 B2 JP 4033968B2
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Japan
Prior art keywords
alloy
connection electrode
semiconductor chip
metal bump
aluminum
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JP10413298A
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JPH11288977A (en
Inventor
宏平 巽
雄一郎 藤原
健二 下川
洋司 川上
ダグラス バトラー
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Nippon Steel Chemical and Materials Co Ltd
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Nippon Steel Materials Co Ltd
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体チップが混載されてパッケージングされてなる複数チップ混載型半導体装置に関する。
【０００２】
【従来の技術】
近年、大規模集積回路（ＬＳＩ）の応用範囲が急速に拡大化し、且つ各応用製品に搭載されるＬＳＩの数量も急速に拡大化している。通常、ＬＳＩは、各応用製品の内部に組み込まれている基板（或いはボード）に搭載されており、同一基板上に複数個のＬＳＩが使用され、且つ当該基板上の配線によって電気的に接続されている。
【０００３】
ところが、ＬＳＩの高集積化が進み、基板上に搭載されるＬＳＩの数量が多くなるにつれて、ＬＳＩ自体の小型化を促進しても、結局基板全体としての面積は増大化し、また配線長も増大化することになる。
【０００４】
そこで、多数のＬＳＩを搭載した基板の総面積を縮小し、且つ複数のＬＳＩ間の配線長を短縮する技術として注目されているものに、いわゆるエンベッデド化技術がある。このエンベッデド化技術とは、異なる機能を有する複数のＬＳＩを同一チップ内に作り込む技術である。例えば、ダイナミック・ランダム・アクセス・メモリ（ＤＲＡＭ）とロジックＬＳＩ等のＤＲＡＭ以外のＬＳＩとを同一プロセスで同一基板上に作り込み、１チップ化したものはエンベッデドＤＲＡＭと称されており、また、マイクロコンピュータ、ＤＲＡＭ、リード・オンリー・メモリ（ＲＯＭ）等を組み込み、１チップでシステムとして機能するように作り込まれたＬＳＩはシステムＬＳＩと称される。
【０００５】
しかしながら、エンベッデド化技術を実現するには、通常は異なるウェハプロセスで製造される異種機能部分を同一のプロセスで製造する必要があり、そのためのプロセスを合わせ混み、或いは新たなエンベッデド化専用のプロセス開発が必要となる。新規にプロセスを開発する場合には、更に、当該新規プロセスを基礎としたライブラリーの構築など、設計関連の環境整備も必要となる。従って、エンベッデド化技術を新規に立ち上げる場合、新規プロセス開発や設計環境整備のための費用と時間が必要となり、製造コストの増加や市場投入の遅れといった問題が生じる。
【０００６】
複数ＬＳＩを搭載した基板の総面積を縮小し、且つ複数ＬＳＩ間の配線長を短縮する技術として、エンベッデド化技術が案出される以前から、マルチ・チップ・モジュール（ＭＣＭ）技術が広く実用化されてきた。このＭＣＭ技術は、複数個のベアチップが一つの基板上に搭載され、その基板毎に１パッケージ化されたものである。
【０００７】
ＭＣＭ技術においては、用いられるＬＳＩはそれぞれ別々に製造することが可能であるため、エンベッデド化技術とは異なり、プロセスの合わせ混みや新たなプロセス開発を行う必要がなく、従って、それに伴うコストの増加や市場投入の遅れといった問題は生じない。
【０００８】
しかしながら、このＭＣＭ技術では、複数個のベアチップが平面的に配置されているため、総面積の増加要因となる。この場合、各チップ毎にパッケージングするよりは有利である反面、エンベッデド化技術に比して小型化効果は減少することになる。
【０００９】
なお、リードフレームに搭載された複数の半導体チップについて、インダクタンスを低減させることを目的とした発明の一例が、特開平６−１２０４１５号公報に開示されている。
【００１０】
【発明が解決しようとする課題】
上述のように、エンベッデド化技術及びＭＣＭ技術には、それぞれ一長一短があり、両者の利点のみを有する半導体装置、即ち複数ＬＳＩの総面積の縮小化や複数ＬＳＩの配線長の短縮化を実現するとともに、プロセスの合わせ混み、プロセス開発に伴うコストの増加や市場投入の遅れ等の問題を生ぜしめることのない半導体装置の開発が待たれている現状にある。
【００１１】
そこで本発明は、このような問題を解決するために成されたものであり、複数の異なる機能を有するＬＳＩを、プロセス開発や設計環境整備等の費用や時間を費やすことなく、しかも平面的に配置する場合よりも小型化及び配線長の短縮化が実現するように１パッケージ化することを可能とする複数チップ混載型半導体装置を提供することを目的とする。
【００１２】
【課題を解決するための手段】
本発明の複数チップ混載型半導体装置は、第１の集積回路及び第１の接続電極を備えた第１の半導体チップと、第２の集積回路及び第２の接続電極を備えた１つ又は複数の第２の半導体チップであって、前記第１の半導体チップと前記第２の半導体チップとは、前記第１の接続電極と前記第２の接続電極とが１個の金属バンプを介して対向し、当該金属バンプにより接続されており、前記第１又は第２の接続電極が、アルミニウム又はその合金からなるとともに、前記金属バンプが金、銅、パラジウム、白金、アルミニウム又はそれらの何れか１種の金属の合金からなるか、前記第１又は第２の接続電極が、銅又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、前記第１又は第２の接続電極が、金又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、前記第１又は第２の接続電極が、パラジウム又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、前記第１又は第２の接続電極が、ニッケル又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、又は、前記第１又は第２の接続電極が、錫合金、鉛合金又はインジウム合金の何れかの半田からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなり、前記第１の半導体チップは、外部の端子と接続するための外部接続電極を有しており、前記第１の半導体チップの前記外部接続電極上に他の金属バンプが設けられており、前記第１の半導体チップの一部及び前記第２の半導体チップの一部がモールド絶縁樹脂で覆われており、前記第１の半導体チップの裏面及び前記第２の半導体チップの裏面は前記モールド絶縁樹脂から露出しており、前記第１の半導体チップの前記外部接続電極上で、前記第１の接続電極と同じ面に設けられた前記他の金属バンプの一部が、前記モールド絶縁樹脂の表面から露出している。
本発明の複数チップ混載型半導体装置は、第１の集積回路及び第１の接続電極を備えた第１の半導体チップと、第２の集積回路及び第２の接続電極を備えた１つ又は複数の第２の半導体チップであって、前記第１の半導体チップと前記第２の半導体チップとは、前記第１の接続電極と前記第２の接続電極とが１個の金属バンプを介して対向し、当該金属バンプにより接続されており、前記第１又は第２の接続電極が、アルミニウム又はその合金からなるとともに、前記金属バンプが金、銅、パラジウム、白金、アルミニウム又はそれらの何れか１種の金属の合金からなるか、前記第１又は第２の接続電極が、銅又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、前記第１又は第２の接続電極が、金又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、前記第１又は第２の接続電極が、パラジウム又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、前記第１又は第２の接続電極が、ニッケル又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、又は、前記第１又は第２の接続電極が、錫合金、鉛合金又はインジウム合金の何れかの半田からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなり、前記第１の半導体チップは、当該第１の半導体チップに形成されたヴィア孔を介して当該第１の半導体チップの裏面に形成された、外部の端子と接続するための外部接続電極を有しており、前記第１の半導体チップの一部及び前記第２の半導体チップの一部がモールド絶縁樹脂で覆われているとともに、前記第１の半導体チップの裏面及び前記第２の半導体チップの裏面は前記モールド絶縁樹脂から露出しており、前記第１の半導体チップの裏面において、前記外部接続電極上に他の金属バンプが設けられており、前記他の金属バンプが前記第１の半導体チップの裏面で外部に露出している。
本発明の一態様では、前記金属バンプが金属ボールバンプである。
本発明の一態様では、前記他の金属バンプは、直径０．８ｍｍ以下の金属ボールを前記外部接続電極に接合することで形成されるものである。
本発明の一態様では、前記金属バンプは、直径２０μｍ〜２５０μｍの金属ボールである。
本発明の一態様では、前記第１の半導体チップがロジックチップであり、前記第２の半導体チップがメモリチップである。
本発明の一態様では、前記第１及び第２の半導体チップが各々異なる機能のメモリチップである。
本発明の複数チップ混載型半導体装置は、第１の集積回路及びアルミニウム又はアルミニウム合金からなる第１の接続電極を備えた第１の半導体チップと、１つ又は複数の第２の集積回路及びアルミニウム又はアルミニウム合金からなる第２の接続電極を備えた第２の半導体チップとを備え、前記第１の半導体チップの第１の接続電極と前記第２の半導体チップの第２の接続電極間に１個の金属バンプを配置して前記第１の半導体チップと前記第２の半導体チップとを接続するとともに、前記第１の接続電極と前記金属バンプ間又は前記第２の接続電極と前記金属バンプ間の少なくとも一方が、前記第１又は第２の接続電極と前記金属バンプの表面材料の間に物理的蒸着法により形成された層を介して接続されており、前記金属バンプが半田であり、前記物理的蒸着法により形成された層がパラジウム合金からなる単層構造、又はチタン合金・パラジウムのこの順の積層構造であるか、前記金属バンプが金合金であり、前記物理的蒸着法により形成された層がクロム・銅・金のこの順の積層構造である。
【００３１】
【作用】
本発明の複数チップ混載型半導体装置は、それぞれ独立の集積回路が形成されてなる第１及び少なくとも１つの第２の半導体チップを備えており（ここで、各第２の半導体チップの集積回路は同一の場合もあれば異なる場合もある。）、第１の半導体チップ上に少なくとも１つの第２の半導体チップが積層されて構成されている。従って、複数のチップを例えば基板上に平面的に配置する場合に比べて、占有する平面積が格段に縮小される。ここで、第１及び第２の半導体チップは、各々の表面の所定位置に設けられた接続電極同士を対向させるように位置付けされて金属バンプによって接続される。このとき、第１の接続電極と金属バンプ間又は第２の接続電極と金属バンプ間の少なくとも一方が、接続電極と金属バンプの表面材料との親和性を改善する材料で形成された層を介して接続される。
【００３２】
この層は、例えば、接続電極の表面に金属バンプの表面材料と親和性の高い金属を蒸着等することにより皮膜を形成する等の手法で実現できる。また、金属バンプに接続電極の表面材料と親和性の高い金属を選択することや、金属バンプの表面に接続電極の表面材料と親和性の高い金属を蒸着等することにより皮膜を形成することによっても同様の効果を得ることができる。
【００３３】
このように、接続電極と金属バンプの材料選択が行われるので、第１及び第２の半導体チップを金属バンプで接続する場合に接続が簡易且つ確実に行われ、諸々の機能を持つ各半導体チップの１チップ化が可能となるとともに、更なる小型化が容易に実現する。
【００３４】
【発明の実施の形態】
以下、本発明を適用したいくつかの好適な実施形態を図面を用いて詳細に説明する。
【００３５】
（第１の実施形態）
先ず、第１の実施形態について説明する。図１は、第１の実施形態の半導体装置の主要部分を示す断面図である。この半導体装置は、図１（ａ）に示すように、半導体チップ１と半導体チップ２とが互いに表面を対向させ積層チップ１１とされてなるものである。
【００３６】
半導体チップ１は、サイズが９ｍｍ×９ｍｍであり、その表面にロジック回路３が形成されてなるロジックＬＳＩであり、半導体チップ２と接続するための接続電極４を備えている。当該接続電極４は、半導体チップ１の対向する２辺に沿って各々所定間隔をもって並列している。更に、半導体チップ１の表面には、接続電極４の外方に外部と接続するための外部接続電極５が形成されている。これら接続電極４及び外部接続電極５は、共にアルミニウム合金を材料として形成されている。
【００３７】
半導体チップ２は、サイズが９ｍｍ×９ｍｍであり、その表面にメモリ回路８が形成されてなるメモリＬＳＩ、例えばＤＲＡＭであり、半導体チップ１と接続するための接続電極６を半導体チップ１の接続電極４に対応する位置に備えている。接続電極６も、接続電極４と同様に、アルミニウム合金を材料として形成されている。複数の接続電極６が形成されている様子を図１（ｂ）に示す。なお、半導体チップ１，２の表面の電極４，５，６を除く部位には、絶縁性のパッシベーション膜（不図示）が形成されている。
【００３８】
そして、半導体チップ１と半導体チップ２とが、接続電極４と接続電極６が対向するように金属バンプ、ここでは金属ボール７を介して当該金属ボール７により接続されて積層チップ１１が構成されている。この金属ボール７は、直径約８０μｍで材料が純度９５％の金合金からなるものである。金（合金）は、アルミニウム（合金）との親和性に優れていることが知られており、良好な接合が得られる。
【００３９】
ここで、接続電極４，６と金属ボール７との接合は熱圧着により行われる。この場合、先ず金属ボール７を半導体チップ１の接続電極４に接合させた後、半導体チップ１，２の位置合わせをして金属ボール７を接続電極６と接合する。半導体チップ１への接合時には、予め接続電極４の位置に対応した部位に穴を開けた吸着配列板の裏側を真空減圧して、金属ボール７をその穴に吸着保持し、半導体チップ１に位置合わせをした後に一括接合する。このとき、接合温度を３００℃とし、半導体チップ１の接続電極４に金属ボール７を接合するときの圧力を金属ボール７の１個あたり１０ｇとし、半導体チップ２の接続電極６に接合する際には１個あたり４０ｇとする。ここで、金属ボール７を最初に接続電極４に接合するとしたが、逆に最初に半導体チップ２の接続電極６に接合するようにしてもよい。
【００４０】
半導体チップ１，２を接合した際に、両者の間には例えば４０μｍ程度の隙間が生じる。この隙間を、絶縁樹脂、絶縁テープ、絶縁性粒子が混入された樹脂及び絶縁性粒子が混入されたテープから選ばれた１種により埋め込むようにしてもよい。
【００４１】
ここで、製造された積層チップ１１について、半導体チップ１の外部接続電極５に所定のプローブを接続して、接続電極６の隣接する１組毎の接続の優良性を電気的に検査したところ、いずれの電極についても接続不良は観察されず、極めて良好な接続状態であることが分かった。
【００４２】
なお、アルミニウム合金を接続電極の材料として用い、それと親和性に優れた金合金を金属ボールの材料に用いたが、この組み合わせに限定されることはない。例えば、接続電極の材料がアルミニウム（合金）である場合には、金属ボールの材料は金（合金）の他に銅（合金）やパラジウム（合金）、白金（合金）、アルミニウム（合金）が好適である。また、接続電極の材料を銅（合金）としても良く、この場合には金属ボールの材料は金（合金）や銅（合金）、アルミニウム（合金）、パラジウム（合金）、白金（合金）、半田（錫合金、鉛合金、インジウム合金等）が好適である。更に、接続電極の材料を金（合金）としても良く、この場合には金属ボールの材料は金（合金）や銅（合金）、アルミニウム（合金）、白金（合金）、半田（錫合金、鉛合金、インジウム合金等）が好適である。更に、接続電極の材料をパラジウム（合金）としても良く、この場合には金属ボールの材料は金（合金）や銅（合金）、アルミニウム（合金）、パラジウム（合金）、白金（合金）、半田（錫合金、鉛合金、インジウム合金等）が好適である。更に、接続電極の材料をニッケル（合金）としても良く、この場合には金属ボールの材料は金（合金）や銅（合金）、アルミニウム（合金）、パラジウム（合金）、白金（合金）、半田（錫合金、鉛合金、インジウム合金等）が好適である。更に、接続電極の材料を半田（錫合金、鉛合金、インジウム合金等）としても良く、この場合には金属ボールの材料は金（合金）や銅（合金）、アルミニウム（合金）、パラジウム（合金）、白金（合金）、半田（錫合金、鉛合金、インジウム合金等）、ニッケル（合金）が好適である。
【００４３】
上記のような組み合わせを選択することで、接続電極間の信頼性の高い接合が可能となる。それぞれの半導体チップは、集積回路、接続電極の材料が同一でも、異なっていても良く、金属バンプ（ボール）の材料と接続電極の材料との組み合わせが、上記のうちのいずれかであれば良い。また、例えばアルミニウム（合金）と半田とは濡れ性に劣るので、半田と濡れ性の良いパラジウム合金を物理的蒸着法等により接続電極の表面に被着させて、濡れ性向上のための下地膜を形成すればよい。
【００４４】
更に、接続電極と金属ボールとの接合が困難であったり、或いは更に接合性を向上させたい場合には、異方性導電膜や導電ペースト等を介して両者を接続することも可能である。
【００４５】
更に、金属ボールの表面のみに接続電極との組み合わせで最適な金属を被着させることで、接続電極との接合性を更に向上させることも可能である。
【００４６】
また、半導体チップ１，２に搭載する集積回路の組み合わせとしては、上記の場合に限定されることなく、例えば相異なるメモリＬＳＩとしてもよい。メモリＬＳＩとしては、ＤＲＡＭの他、ＳＲＡＭやフラッシュメモリ等がある。ＳＲＡＭとＤＲＡＭを組み合わせた場合、例えばメモリを必要とするデータ処理用ＬＳＩと併用することが考えられる。この場合、使用頻度が高く、頻繁に記憶内容を変更しながら高速で処理するデータについてはＳＲＡＭを使用し、高速性よりは大容量の記憶保持が必要なデータについてはＤＲＡＭに記憶しておくことが可能となる。
【００４７】
また、ＳＲＡＭとフラッシュメモリを組み合わせた場合、例えばあるプログラムに従って信号を高速処理する信号処理用ＬＳＩと併用することが考えられる。この場合、プログラムをフラッシュメモリに格納しておくと、電源を切ってもプログラムは消去されないため、同じプログラム処理が可能となる。そして、その間の処理中の信号の一時的な記憶にはＳＲＡＭを使用すればよい。
【００４８】
更に、図１では、半導体チップ１，２に設ける集積回路、ここではロジック回路３やメモリ回路８を接続電極４，５の直下を除く部位に形成した例を示したが、これは金合金からなる金属ボール７を用いるためであって、例えば半田からなる金属ボールを用いれば、熱圧着が不要となるため、接続電極４，５の直下にも集積回路を形成することが可能となる。
【００４９】
また、本実施形態で半導体チップ１に搭載する半導体チップ２は１つに限定されるものではなく、図１（ｃ）に示すように、サイズの大きな半導体チップ１上に２つの半導体チップ２（相異なる集積回路が形成されたものでもよい。）を併設してもよい。
【００５０】
そして、図２に示すように、積層チップ１１を基板１２に搭載する。基板１２の表面にはボンディングパッド１３が設けられている。この基板１２としては、セラミクス基板、絶縁テープ基板、リードフレーム等が考えられる。この場合、半導体チップ１の裏面を基板１２の表面に接着剤等により固定し、半導体チップ１の外部接続電極５とボンディングパッド１３とを金ワイヤ１４を用いてワイヤボンディング法により接続する。そして、図３に示すように、エポキシ系の絶縁樹脂１５により複合チップ１１の全面及び基板１２の一部を残した全面をモールドすることにより、本実施形態の半導体装置となる。ここで、モールド用の絶縁樹脂１５中のＳｉＯ2 粒子であるフィラーは、径の小さい２０μｍ以下のものを使用して、半導体チップ１間の隙間（上記の如く４０μｍ程度となる。なお、この場合には当該隙間に絶縁テープ等を埋め込む必要はない。）に十分に充填されることが確認された。
【００５１】
以上説明したように、第１の実施形態の半導体装置は、それぞれ独立の集積回路が形成されてなる半導体チップ１，２を備えており、半導体チップ１上に半導体チップ２が積層されて構成されている。従って、複数のチップを例えば基板上に平面的に配置する場合に比べて、占有する平面積が格段に縮小される。ここで、半導体チップ１，２は、各々の表面の所定位置に設けられた接続電極４，６同士を対向させるように、当該接続電極材料と親和性のある金属バンプ、例えば金属ボール７を介してこれにより両者が接続されている。従って、各半導体チップ１，２間の配線長は殆ど無視し得るほど短く、諸々の機能を持つ各半導体チップの１チップ化が可能となるとともに、更なる小型化が容易に実現する。
【００５２】
従って、第１の実施形態の半導体装置によれば、複数の異なる機能を有するＬＳＩを、プロセス開発や設計環境整備等の費用や時間を費やすことなく、しかも平面的に配置する場合よりも小型化及び配線長の短縮化が実現するように１パッケージ化することが可能となる。
【００５３】
以下、第１の実施形態の半導体装置のいくつかの変形例について説明する。なお、第１の実施形態の半導体装置に対応する構成部材等については同符号を記して説明を省略する。
【００５４】
−変形例１−
先ず、変形例１の半導体装置について説明する。この半導体装置は、第１の実施形態と同様に複合チップ１１が構成されるが、複合チップ１１の樹脂封止法等が異なる。この半導体装置においては、図４（ａ）に示すように、複合チップ１１の半導体チップ１，２の寸法が第１の実施形態のそれと若干異なり、半導体チップ１が１２ｍｍ×１２ｍｍ、半導体チップ２が５ｍｍ×５ｍｍのサイズとされている。
【００５５】
半導体チップ１に形成された接続電極４及び外部接続電極５は、第１の実施形態のそれと同様にそれぞれアルミニウム合金からなるが、各々の接続電極４，５はチップ表面から外側に向かって順にクロム（Ｃｒ）、Ｃｕ（銅）、Ａｕ（金）の順に濡れ性向上のための下地膜（不図示）が形成されている。そして、接続電極４のＡｕ面と金合金からなる金属ボール７が接合されるとともに、他方で半導体チップ２のアルミニウム合金からなる接続電極６と当該金属ボール７が接合されている。
【００５６】
更に、外部接続電極５には、金属ボール７より大きな直径の半田からなる金属ボール１６が接合されている。ここで、金属ボール７が直径６０μｍであり、金属ボール１６が直径５００μｍとされている。金属ボール７については上述のように熱圧着により接続電極４，６と接合し、金属ボール１６については先ずフラックスの粘着力を利用して外部接続電極５上に固定した後、半導体チップ１を半田の融点である１８３℃以上に加熱し、金属ボール１６を外部接続電極５にリフローにより接合する。
【００５７】
そして、半導体チップ１，２間を充填するとともに、図４（ａ）のように、金属ボール１６の先端部位が露出するようにエポキシ系の絶縁樹脂１５で覆う。ここで、絶縁樹脂１５の表面から露出する金属ボール１６が外部接続用のバンプとして機能することになる。また、半導体チップ２の裏面を露出させることにより、放熱性を向上させることができる。
【００５８】
なお、この変形例１では、半導体チップ１の代わりに集積回路の形成されていない基板を用いる場合にも適用可能である。また、各金属ボールの材料についても、第１の実施形態で述べたような諸々の材料を用いてもよい。
【００５９】
この変形例１の半導体装置によれば、既述した第１の実施形態の半導体装置の奏する作用・効果に加えて、絶縁樹脂１５で封止された複合チップ１１を例えば外部の基板と接続する場合に、露出した金属ボール１６で接続できるため、更なる配線長の短縮化、ひいては装置全体の小型化に大幅に寄与することが可能となる。
【００６０】
また、図４（ｂ）に示すように、外部接続電極５を半導体チップ１に形成されたヴィア孔を介して当該半導体チップ１の裏面に形成し、この外部接続電極５に金属ボール１６を接合するようにしてもよい。
【００６１】
−変形例２−
次に、変形例２の半導体装置について説明する。この半導体装置は、第１の実施形態と同様に複合チップ１１が構成されるが、複合チップ１１を搭載する基板が異なる。この半導体装置は、図５に示すように、リード・オン・チップ（ＬＯＣ）方式又はＴＡＢテープで形成されるものであり、半導体チップ１の外部接続電極５とリードフレーム又はＴＡＢテープのインナーリード１８が例えば半田を材料とするスタッドバンプ１９により接合されている。ここで、インナーリード１８はポリイミド等からなる絶縁テープ１７により固定されて位置規制がなされている。
【００６２】
なお、図６に示すように、スタッドバンプ１９の代わりに、金属ボール２０を用いて接合を行うようにしても好適である。
【００６３】
この変形例２の半導体装置によれば、既述した第１の実施形態の半導体装置の奏する作用・効果に加えて、ＬＯＣ構造とすることにより、比較的小さなパッケージに大型化した半導体チップを収納して高密度の実装を図ることが可能となる。
【００６４】
−変形例３−
次に、変形例３の半導体装置について説明する。この半導体装置は、第１の実施形態と同様に複合チップ１１が構成されるが、更に異なる半導体チップが搭載される点で異なる。この半導体装置は、図７に示すように、半導体チップ１，２が接合されてなる複合チップ１１において、半導体チップ２上に互いに裏面同士で固定されるように半導体チップ３１が設けられている。
【００６５】
半導体チップ３１は、半導体チップ１，２と同様に、その表面にロジック回路又はメモリ回路である集積回路２１が形成されてなるＬＳＩであり、外部と接続するためのアルミニウム合金を材料としたボンディングパッド２２が形成されている。また、半導体チップ１の表面には、半導体チップ３１の外部接続電極２２と接続するためのボンディングパッド２３が設けられている。
【００６６】
そして、半導体チップ３１と半導体チップ２とが裏面同士で所定のダイペーストにより接着固定されており、半導体チップ３１のボンディングパッド２２と半導体チップ１のボンディングパッド２３とが金ワイヤ１４を用いたワイヤボンディング法により接続されている。
【００６７】
なお、半導体チップ１の代わりに集積回路の形成されていない基板を用いる場合にも適用可能である。また、金属ボールの材料についても、第１の実施形態で述べたような諸々の材料を用いてもよい。
【００６８】
この変形例３の半導体装置によれば、既述した第１の実施形態の半導体装置の奏する作用・効果に加えて、複合チップ１１上に半導体チップ３１を更に積層しても、小型化を損なうことなく高集積化を図ることが可能となる。
【００６９】
（第２の実施形態）
次に、本発明の第２の実施形態について説明する。この第２の実施形態の半導体装置は、第１の実施形態のそれとほぼ同様の複合チップ１１を有するが、半導体チップ１，２の接合が若干異なる。なお、第１の実施形態と同一の構成部材等については同符号を記して説明を省略する。図８は、第２の実施形態の半導体装置の主要部分を示す断面図である。なお、半導体チップ１のサイズは第１の実施形態と同様で１０ｍｍ×１０ｍｍであり、半導体チップ２のサイズは７ｍｍ×７ｍｍである。
【００７０】
半導体チップ２のアルミニウム合金からなる接続電極６上には、直径約６０μｍの金合金からなる金属ボール７が接合されている。半導体チップ１のアルミニウム合金からなる接続電極４の表面には、チタン（Ｔｉ）合金、パラジウム（Ｐｄ）の順に表面処理が施されており、最表層のパラジウム上に直径約６０μｍの半田からなる金属ボール３２が溶融接合されている。そして、金属ボール７と金属ボール３２とが位置合わせされ、２５０℃以上の温度で加熱しながら金属ボール７，３２が接合される。
【００７１】
なお、接合する２種の金属ボールの材料については、金合金と半田に限定されるものではなく、親和性に優れた組み合わせであれば、例えば第１の実施形態で例示したような他の金属（合金）でもよい。
【００７２】
そして、図９に示すように、積層チップ１１を例えばＬＯＣ構造のリードフレーム又はＴＡＢテープに搭載する。この場合、リードフレーム又はＴＡＢテープのインナーリード１８と半導体チップ１の外部接続電極５とが、金合金からなる金属ボール３３により接合されている。なお、金属ボール３３の材料としては、金合金の他に銅（合金）や半田等を用いてもよく、更には金属ボールの代わりにスタッドバンプ又はメッキバンプを用いてもよい。
【００７３】
第２の実施形態の半導体装置によれば、既述した第１の実施形態の半導体装置の奏する作用・効果に加えて、半導体チップ１，２に設ける接続電極の材料に対する規制が緩和され、選択幅を拡大させることが可能となる。また、２種の金属ボールを接合に用いることで、半導体チップ１，２間の離間距離（隙間）が配線長には影響しない限度内で若干大きくなり、例えば半導体チップ１，２に熱膨張が生じても短絡等の発生が回避される。従って、製品の信頼性の向上により一層寄与することになる。
【００７４】
−変形例−
ここで、第２の実施形態の半導体装置の変形例について説明する。この半導体装置は、第１の実施形態と同様に複合チップ１１が構成されるが、リードフレーム又はＴＡＢテープへの搭載の仕方が異なる。なお、第２の実施形態の半導体装置に対応する構成部材等については同符号を記して説明を省略する。
【００７５】
この変形例の半導体装置においては、製造した複合チップ１１をリードフレームに搭載するのではなく、複合チップ１１の形成時に同時にインナーリード１８との接続が行われる。即ち、この半導体装置においては、図１０に示すように、半導体チップ１の接続電極４上の金属ボール４１と、半導体チップ２の接続電極６上の金属ボール４２とが、インナーリード１８を介して当該インナーリード１８を狭持するように溶融接合されている。なお、金属ボール４１，４２の材料としては、金合金や半田、又は第１の実施形態で述べた各種金属（合金）を用いることが可能である。
【００７６】
この変形例の半導体装置によれば、既述した第１及び第２の実施形態の半導体装置の奏する作用・効果に加えて、半導体チップ１に外部接続電極を設ける必要がないため、半導体チップ１の占有面積を縮小することが可能であり、例えば半導体チップ２と同等のサイズとすることができる。従って、半導体装置の更なる小型化に貢献することが可能となる。
【００７７】
【発明の効果】
本発明によれば、複数の異なる機能を有するＬＳＩを、プロセス開発や設計環境整備等の費用や時間を費やすことなく、しかも平面的に配置する場合よりも小型化及び配線長の短縮化が実現するように１パッケージ化することが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態による半導体装置の主要構成を示す模式図である。
【図２】本発明の第１の実施形態による半導体装置において、複合チップが基板に搭載された様子を示す概略断面図である。
【図３】本発明の第１の実施形態による半導体装置において、基板に搭載された複合チップがモールド樹脂によりパッケージングされた様子を示す概略断面図である。
【図４】本発明の第１の実施形態による変形例１の半導体装置の主要構成を示す概略断面図である。
【図５】本発明の第１の実施形態による変形例２の半導体装置の主要構成を示す概略断面図である。
【図６】本発明の第１の実施形態による変形例２の半導体装置の他の例の主要構成を示す概略断面図である。
【図７】本発明の第１の実施形態による変形例３の半導体装置の主要構成を示す概略断面図である。
【図８】本発明の第１の実施形態による半導体装置の主要構成を示す概略断面図である。
【図９】本発明の第２の実施形態による半導体装置において、複合チップが基板に搭載された様子を示す概略断面図である。
【図１０】本発明の第２の実施形態による変形例の半導体装置の主要構成を示す概略断面図である。
【符号の説明】
１，２，３１ 半導体チップ
３ ロジック回路
４，６ 接続端子
５ 外部接続端子
７，１６，２０，３２，３３，４１，４２ 金属ボール
８ メモリ回路
１１ 積層チップ
１２，１７ 基板
１３，２２，２３ ボンディングパッド
１４ 金ワイヤ
１５ 絶縁樹脂
１７ 絶縁テープ
１８ インナーリード
１９ スタッドバンプ
２１ 集積回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-chip mixed semiconductor device in which a plurality of semiconductor chips are mixed and packaged.
[0002]
[Prior art]
In recent years, the application range of large-scale integrated circuits (LSIs) is rapidly expanding, and the number of LSIs mounted on each application product is also rapidly expanding. Normally, LSIs are mounted on a board (or board) built into each application product, and a plurality of LSIs are used on the same board and are electrically connected by wiring on the board. ing.
[0003]
However, as LSI integration increases and the number of LSIs mounted on a substrate increases, the overall area of the substrate increases and the wiring length increases even if the LSI itself is reduced in size. It will become.
[0004]
Therefore, a so-called embedded technology is attracting attention as a technique for reducing the total area of a substrate on which a large number of LSIs are mounted and reducing the wiring length between a plurality of LSIs. This embedded technology is a technology for creating a plurality of LSIs having different functions in the same chip. For example, a dynamic random access memory (DRAM) and an LSI other than a DRAM such as a logic LSI are formed on the same substrate by the same process and integrated into one chip is called an embedded DRAM. An LSI that incorporates a computer, DRAM, read-only memory (ROM), etc. and is built to function as a system on a single chip is called a system LSI.
[0005]
However, in order to realize the embedded technology, it is necessary to manufacture different functional parts, which are usually manufactured in different wafer processes, in the same process. Therefore, the processes are mixed together or a new process dedicated to embedded processing is developed. Is required. When developing a new process, it is also necessary to improve the design-related environment such as building a library based on the new process. Therefore, when a new embedded technology is launched, costs and time for new process development and design environment maintenance are required, which causes problems such as an increase in manufacturing cost and a delay in market launch.
[0006]
Multi-chip module (MCM) technology has been widely put into practical use before embedding technology was devised as a technology for reducing the total area of a substrate on which multiple LSIs are mounted and reducing the wiring length between multiple LSIs. I came. In this MCM technology, a plurality of bare chips are mounted on one substrate, and one package is formed for each substrate.
[0007]
In the MCM technology, the LSIs used can be manufactured separately, so unlike the embedded technology, there is no need to mix processes and develop new processes. And there are no problems such as delays to market.
[0008]
However, in this MCM technology, a plurality of bare chips are arranged in a plane, which causes an increase in the total area. In this case, although it is more advantageous than packaging for each chip, the miniaturization effect is reduced as compared with the embedded technology.
[0009]
An example of an invention for reducing the inductance of a plurality of semiconductor chips mounted on a lead frame is disclosed in JP-A-6-120415.
[0010]
[Problems to be solved by the invention]
As described above, the embedded technology and the MCM technology have advantages and disadvantages, respectively, and a semiconductor device having only the advantages of both, that is, the reduction of the total area of the plurality of LSIs and the reduction of the wiring length of the plurality of LSIs is realized. However, the development of a semiconductor device that does not cause problems such as crowding of processes, an increase in costs associated with process development, and a delay in market entry is awaited.
[0011]
Therefore, the present invention has been made to solve such a problem. An LSI having a plurality of different functions can be planarly processed without spending costs and time for process development and design environment maintenance. It is an object of the present invention to provide a multi-chip mixed semiconductor device that can be made into one package so as to realize a reduction in size and a reduction in wiring length as compared with the case of arrangement.
[0012]
[Means for Solving the Problems]
The multi-chip mixed semiconductor device according to the present invention includes a first semiconductor chip having a first integrated circuit and a first connection electrode, and one or a plurality having a second integrated circuit and a second connection electrode. The first semiconductor chip and the second semiconductor chip are such that the first connection electrode and the second connection electrode are opposed to each other through one metal bump. And the first or second connection electrode is made of aluminum or an alloy thereof, and the metal bump is gold, copper, palladium, platinum, aluminum, or any one of them. The first or second connection electrode is made of copper or an alloy thereof, and the metal bump is made of gold, copper, aluminum, palladium, platinum, or any one of these metals. It is made of gold, or a solder of any one of a tin alloy, a lead alloy, and an indium alloy, or the first or second connection electrode is made of gold or an alloy thereof, and the metal bump is made of gold, copper, aluminum, or platinum. Or an alloy of any one of these metals, or a solder of any one of a tin alloy, a lead alloy, and an indium alloy, or the first or second connection electrode is made of palladium or an alloy thereof, and The metal bumps are made of gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a solder of any one of a tin alloy, a lead alloy and an indium alloy, or the first or second connection. The electrode is made of nickel or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum, or any one metal thereof An alloy, or a tin alloy, a lead alloy or an indium alloy, or the first or second connection electrode is a tin alloy, a lead alloy or an indium alloy, and The metal bump is made of gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a solder of a tin alloy, a lead alloy or an indium alloy, and the first semiconductor chip is: An external connection electrode for connecting to an external terminal; another metal bump is provided on the external connection electrode of the first semiconductor chip; and a part of the first semiconductor chip and A part of the second semiconductor chip is covered with a mold insulating resin, and the back surface of the first semiconductor chip and the back surface of the second semiconductor chip are exposed from the mold insulating resin. A part of the other metal bump provided on the same surface as the first connection electrode on the external connection electrode of the first semiconductor chip is exposed from the surface of the mold insulating resin. ing.
The multi-chip mixed semiconductor device according to the present invention includes a first semiconductor chip having a first integrated circuit and a first connection electrode, and one or a plurality having a second integrated circuit and a second connection electrode. The first semiconductor chip and the second semiconductor chip are such that the first connection electrode and the second connection electrode are opposed to each other through one metal bump. And the first or second connection electrode is made of aluminum or an alloy thereof, and the metal bump is gold, copper, palladium, platinum, aluminum, or any one of them. The first or second connection electrode is made of copper or an alloy thereof, and the metal bump is made of gold, copper, aluminum, palladium, platinum, or any one of these metals. It is made of gold, or a solder of any one of a tin alloy, a lead alloy, and an indium alloy, or the first or second connection electrode is made of gold or an alloy thereof, and the metal bump is made of gold, copper, aluminum, or platinum. Or an alloy of any one of these metals, or a solder of any one of a tin alloy, a lead alloy, and an indium alloy, or the first or second connection electrode is made of palladium or an alloy thereof, and The metal bumps are made of gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a solder of any one of a tin alloy, a lead alloy and an indium alloy, or the first or second connection. The electrode is made of nickel or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum, or any one metal thereof An alloy, or a tin alloy, a lead alloy or an indium alloy, or the first or second connection electrode is a tin alloy, a lead alloy or an indium alloy, and The metal bump is made of gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a solder of a tin alloy, a lead alloy or an indium alloy, and the first semiconductor chip is: An external connection electrode formed on the back surface of the first semiconductor chip through a via hole formed in the first semiconductor chip and connected to an external terminal; A part of the chip and a part of the second semiconductor chip are covered with a mold insulating resin, and the back surface of the first semiconductor chip and the back surface of the second semiconductor chip are the front side. It is exposed from the mold insulating resin, and another metal bump is provided on the external connection electrode on the back surface of the first semiconductor chip, and the other metal bump is provided on the back surface of the first semiconductor chip. It is exposed to the outside.
In one aspect of the present invention, the metal bump is a metal ball bump.
In one aspect of the present invention, the other metal bump is formed by bonding a metal ball having a diameter of 0.8 mm or less to the external connection electrode.
In one aspect of the present invention, the metal bump is a metal ball having a diameter of 20 μm to 250 μm.
In one embodiment of the present invention, the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.
In one embodiment of the present invention, the first and second semiconductor chips are memory chips having different functions.
A multi-chip mixed semiconductor device according to the present invention includes a first semiconductor chip including a first integrated circuit and a first connection electrode made of aluminum or an aluminum alloy, and one or more second integrated circuits and aluminum. Or a second semiconductor chip provided with a second connection electrode made of an aluminum alloy, and 1 between the first connection electrode of the first semiconductor chip and the second connection electrode of the second semiconductor chip. A plurality of metal bumps are arranged to connect the first semiconductor chip and the second semiconductor chip, and between the first connection electrode and the metal bump or between the second connection electrode and the metal bump. Are connected via a layer formed by a physical vapor deposition method between the first or second connection electrode and the surface material of the metal bump, and the metal bump is soldered. There, the layer formed by the physical vapor deposition is a palladium alloy Or a layered structure of titanium alloy / palladium in this order, or the metal bump is a gold alloy, and the layer formed by the physical vapor deposition method is chromium / copper / gold in this order. It is a laminated structure.
[0031]
[Action]
The multi-chip mixed semiconductor device of the present invention includes first and at least one second semiconductor chip in which independent integrated circuits are formed (here, the integrated circuit of each second semiconductor chip is an integrated circuit). The case may be the same or different, and at least one second semiconductor chip is stacked on the first semiconductor chip. Therefore, the occupied planar area is significantly reduced as compared with the case where a plurality of chips are arranged on a substrate in a planar manner. Here, the first and second semiconductor chips are positioned so that the connection electrodes provided at predetermined positions on the respective surfaces face each other and are connected by metal bumps. At this time, at least one between the first connection electrode and the metal bump or between the second connection electrode and the metal bump is interposed through a layer formed of a material that improves the affinity between the connection electrode and the surface material of the metal bump. Connected.
[0032]
This layer can be realized by, for example, a method of forming a film on the surface of the connection electrode by vapor-depositing a metal having a high affinity with the surface material of the metal bump. In addition, by selecting a metal that has a high affinity for the surface material of the connection electrode for the metal bump, or by forming a film on the surface of the metal bump by depositing a metal that has a high affinity for the surface material of the connection electrode. The same effect can be obtained.
[0033]
Since the connection electrodes and the metal bumps are thus selected, each semiconductor chip having various functions can be easily and reliably connected when the first and second semiconductor chips are connected by the metal bumps. This makes it possible to reduce the size of the chip to one chip and to easily achieve further miniaturization.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some preferred embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0035]
(First embodiment)
First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing the main part of the semiconductor device of the first embodiment. As shown in FIG. 1 (a), the semiconductor device is formed of a laminated chip 11 in which a semiconductor chip 1 and a semiconductor chip 2 face each other.
[0036]
The semiconductor chip 1 is a logic LSI having a size of 9 mm × 9 mm and having a logic circuit 3 formed on the surface thereof, and includes a connection electrode 4 for connection to the semiconductor chip 2. The connection electrodes 4 are arranged in parallel at predetermined intervals along two opposing sides of the semiconductor chip 1. Furthermore, external connection electrodes 5 for connecting to the outside are formed on the surface of the semiconductor chip 1 outside the connection electrodes 4. Both the connection electrode 4 and the external connection electrode 5 are made of aluminum alloy.
[0037]
The semiconductor chip 2 is a memory LSI, for example a DRAM, having a size of 9 mm × 9 mm and having a memory circuit 8 formed on the surface thereof. The connection electrode 6 for connecting to the semiconductor chip 1 is connected to the connection electrode of the semiconductor chip 1. 4 is provided at a position corresponding to 4. Similarly to the connection electrode 4, the connection electrode 6 is also formed using an aluminum alloy as a material. A state in which a plurality of connection electrodes 6 are formed is shown in FIG. An insulating passivation film (not shown) is formed on the surface of the semiconductor chips 1 and 2 excluding the electrodes 4, 5 and 6.
[0038]
Then, the semiconductor chip 1 and the semiconductor chip 2 are connected by the metal ball 7 via the metal bump, here the metal ball 7 so that the connection electrode 4 and the connection electrode 6 face each other, thereby forming the laminated chip 11. Yes. The metal ball 7 is made of a gold alloy having a diameter of about 80 μm and a material of 95% purity. Gold (alloy) is known to have excellent affinity with aluminum (alloy), and good bonding can be obtained.
[0039]
Here, the connection electrodes 4, 6 and the metal ball 7 are joined by thermocompression bonding. In this case, the metal ball 7 is first bonded to the connection electrode 4 of the semiconductor chip 1, and then the semiconductor chips 1 and 2 are aligned to bond the metal ball 7 to the connection electrode 6. At the time of bonding to the semiconductor chip 1, the back side of the adsorption array plate in which holes are made in advance at positions corresponding to the positions of the connection electrodes 4 is vacuum-reduced, and the metal balls 7 are adsorbed and held in the holes to be positioned on the semiconductor chip 1. Join together after matching. At this time, the bonding temperature is set to 300 ° C., the pressure when bonding the metal balls 7 to the connection electrodes 4 of the semiconductor chip 1 is set to 10 g per metal ball 7, and the bonding is performed to the connection electrodes 6 of the semiconductor chip 2. Is 40 g per piece. Here, the metal ball 7 is first bonded to the connection electrode 4, but conversely, the metal ball 7 may be bonded to the connection electrode 6 of the semiconductor chip 2 first.
[0040]
When the semiconductor chips 1 and 2 are joined, a gap of, for example, about 40 μm is generated between them. The gap may be filled with one type selected from an insulating resin, an insulating tape, a resin mixed with insulating particles, and a tape mixed with insulating particles.
[0041]
Here, with respect to the manufactured laminated chip 11, when a predetermined probe was connected to the external connection electrode 5 of the semiconductor chip 1 and the connection superiority of each adjacent set of the connection electrodes 6 was electrically inspected, No connection failure was observed for any of the electrodes, and it was found that the connection was extremely good.
[0042]
In addition, although aluminum alloy was used as the material of the connection electrode and gold alloy having excellent affinity with it was used as the material of the metal ball, it is not limited to this combination. For example, when the connection electrode material is aluminum (alloy), the metal ball material is preferably gold (alloy), copper (alloy), palladium (alloy), platinum (alloy), or aluminum (alloy). It is. The connection electrode material may be copper (alloy). In this case, the metal ball material is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy), solder. (Tin alloys, lead alloys, indium alloys, etc.) are preferred. Furthermore, the material of the connection electrode may be gold (alloy). In this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), platinum (alloy), solder (tin alloy, lead). Alloys, indium alloys, etc.) are preferred. Furthermore, the material of the connection electrode may be palladium (alloy). In this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy), solder (Tin alloys, lead alloys, indium alloys, etc.) are preferred. Furthermore, the material of the connection electrode may be nickel (alloy). In this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy), solder (Tin alloys, lead alloys, indium alloys, etc.) are preferred. Furthermore, the connection electrode material may be solder (tin alloy, lead alloy, indium alloy, etc.). In this case, the metal ball material is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy). ), Platinum (alloy), solder (tin alloy, lead alloy, indium alloy, etc.), nickel (alloy) are suitable.
[0043]
By selecting the combination as described above, highly reliable bonding between the connection electrodes is possible. Each semiconductor chip may have the same or different materials for the integrated circuit and the connection electrode, and the combination of the metal bump (ball) material and the connection electrode material may be any of the above. . Also, for example, aluminum (alloy) and solder are inferior in wettability, so a base film for improving wettability is obtained by depositing a solder and good wettability palladium alloy on the surface of the connection electrode by physical vapor deposition or the like. May be formed.
[0044]
Furthermore, when it is difficult to bond the connection electrode and the metal ball, or when it is desired to further improve the bondability, it is possible to connect the two via an anisotropic conductive film or a conductive paste.
[0045]
Furthermore, it is also possible to further improve the bondability with the connection electrode by depositing an optimum metal only in combination with the connection electrode on the surface of the metal ball.
[0046]
Further, the combination of the integrated circuits mounted on the semiconductor chips 1 and 2 is not limited to the above case, and for example, different memory LSIs may be used. As the memory LSI, there are SRAM, flash memory, and the like in addition to DRAM. When SRAM and DRAM are combined, for example, it may be used together with a data processing LSI that requires memory. In this case, SRAM is used for data that is frequently used and processed at high speed while frequently changing the storage contents, and data that needs to be stored in large capacity rather than high speed is stored in DRAM. Is possible.
[0047]
In addition, when an SRAM and a flash memory are combined, for example, it may be used together with a signal processing LSI that processes signals at high speed according to a certain program. In this case, if the program is stored in the flash memory, since the program is not erased even when the power is turned off, the same program processing can be performed. An SRAM may be used for temporary storage of signals being processed during that time.
[0048]
Further, FIG. 1 shows an example in which the integrated circuits provided on the semiconductor chips 1 and 2, in this case, the logic circuit 3 and the memory circuit 8 are formed in portions other than directly below the connection electrodes 4 and 5. For example, if a metal ball made of solder is used, no thermocompression bonding is required, so that an integrated circuit can be formed immediately below the connection electrodes 4 and 5.
[0049]
In the present embodiment, the number of semiconductor chips 2 mounted on the semiconductor chip 1 is not limited to one. As shown in FIG. 1C, two semiconductor chips 2 ( Different integrated circuits may be formed).
[0050]
Then, as shown in FIG. 2, the laminated chip 11 is mounted on the substrate 12. Bonding pads 13 are provided on the surface of the substrate 12. The substrate 12 may be a ceramic substrate, an insulating tape substrate, a lead frame, or the like. In this case, the back surface of the semiconductor chip 1 is fixed to the front surface of the substrate 12 with an adhesive or the like, and the external connection electrode 5 of the semiconductor chip 1 and the bonding pad 13 are connected using a gold wire 14 by a wire bonding method. Then, as shown in FIG. 3, the entire surface of the composite chip 11 and the entire surface of the substrate 12 with a part of the substrate 12 are molded with an epoxy insulating resin 15, whereby the semiconductor device of this embodiment is obtained. Here, SiO in the insulating resin 15 for molding 2 The filler, which is particles, has a small diameter of 20 μm or less, and the gap between the semiconductor chips 1 (about 40 μm as described above. In this case, it is not necessary to embed an insulating tape or the like in the gap. .) Was confirmed to be sufficiently filled.
[0051]
As described above, the semiconductor device according to the first embodiment includes the semiconductor chips 1 and 2 in which independent integrated circuits are formed, and the semiconductor chip 2 is stacked on the semiconductor chip 1. ing. Therefore, the occupied planar area is significantly reduced as compared with the case where a plurality of chips are arranged on a substrate in a planar manner. Here, the semiconductor chips 1 and 2 are connected via metal bumps having affinity with the connection electrode material, for example, metal balls 7 so that the connection electrodes 4 and 6 provided at predetermined positions on the respective surfaces face each other. Thus, both are connected. Therefore, the wiring length between the semiconductor chips 1 and 2 is so short that it can be ignored, and each semiconductor chip having various functions can be made into one chip, and further miniaturization can be easily realized.
[0052]
Therefore, according to the semiconductor device of the first embodiment, LSIs having a plurality of different functions can be reduced in size compared with the case where they are arranged in a plane without spending costs and time for process development and design environment maintenance. In addition, it is possible to make one package so that the wiring length can be shortened.
[0053]
Hereinafter, some modified examples of the semiconductor device of the first embodiment will be described. In addition, about the structural member etc. corresponding to the semiconductor device of 1st Embodiment, the same code | symbol is described and description is abbreviate | omitted.
[0054]
-Modification 1-
First, the semiconductor device of Modification 1 will be described. This semiconductor device includes the composite chip 11 as in the first embodiment, but the resin sealing method of the composite chip 11 is different. In this semiconductor device, as shown in FIG. 4A, the dimensions of the semiconductor chips 1 and 2 of the composite chip 11 are slightly different from those of the first embodiment, the semiconductor chip 1 is 12 mm × 12 mm, and the semiconductor chip 2 is The size is 5 mm × 5 mm.
[0055]
The connection electrodes 4 and the external connection electrodes 5 formed on the semiconductor chip 1 are each made of an aluminum alloy as in the first embodiment, but the connection electrodes 4 and 5 are made of chromium in order from the chip surface toward the outside. A base film (not shown) for improving wettability is formed in the order of (Cr), Cu (copper), and Au (gold). The Au surface of the connection electrode 4 and the metal ball 7 made of a gold alloy are joined, and on the other hand, the connection electrode 6 made of an aluminum alloy of the semiconductor chip 2 and the metal ball 7 are joined.
[0056]
Further, a metal ball 16 made of solder having a diameter larger than that of the metal ball 7 is joined to the external connection electrode 5. Here, the metal ball 7 has a diameter of 60 μm, and the metal ball 16 has a diameter of 500 μm. As described above, the metal ball 7 is bonded to the connection electrodes 4 and 6 by thermocompression bonding, and the metal ball 16 is first fixed on the external connection electrode 5 using the adhesive force of the flux, and then the semiconductor chip 1 is soldered. The metal ball 16 is joined to the external connection electrode 5 by reflowing.
[0057]
Then, the space between the semiconductor chips 1 and 2 is filled, and as shown in FIG. 4A, the tip portion of the metal ball 16 is covered with an epoxy insulating resin 15 so as to be exposed. Here, the metal balls 16 exposed from the surface of the insulating resin 15 function as bumps for external connection. Further, by exposing the back surface of the semiconductor chip 2, the heat dissipation can be improved.
[0058]
The first modification can also be applied to a case where a substrate on which an integrated circuit is not formed is used instead of the semiconductor chip 1. Also, various materials as described in the first embodiment may be used for the material of each metal ball.
[0059]
According to the semiconductor device of the first modification, in addition to the functions and effects exhibited by the semiconductor device of the first embodiment described above, the composite chip 11 sealed with the insulating resin 15 is connected to, for example, an external substrate. In this case, since it can be connected by the exposed metal ball 16, it is possible to further contribute to further shortening of the wiring length, and consequently to downsizing of the entire apparatus.
[0060]
4B, the external connection electrode 5 is formed on the back surface of the semiconductor chip 1 through a via hole formed in the semiconductor chip 1, and a metal ball 16 is bonded to the external connection electrode 5. You may make it do.
[0061]
-Modification 2-
Next, a semiconductor device of Modification 2 will be described. This semiconductor device includes the composite chip 11 as in the first embodiment, but the substrate on which the composite chip 11 is mounted is different. As shown in FIG. 5, this semiconductor device is formed by a lead-on-chip (LOC) system or a TAB tape. The external connection electrode 5 of the semiconductor chip 1 and the inner lead 18 of the lead frame or TAB tape. Are joined by stud bumps 19 made of, for example, solder. Here, the inner lead 18 is fixed by an insulating tape 17 made of polyimide or the like, and its position is regulated.
[0062]
In addition, as shown in FIG. 6, it is also preferable to perform bonding using a metal ball 20 instead of the stud bump 19.
[0063]
According to the semiconductor device of the second modification, in addition to the functions and effects achieved by the semiconductor device according to the first embodiment described above, the LOC structure allows a large semiconductor chip to be accommodated in a relatively small package. Thus, high-density mounting can be achieved.
[0064]
-Modification 3-
Next, a semiconductor device of Modification 3 will be described. This semiconductor device includes the composite chip 11 as in the first embodiment, but is different in that a different semiconductor chip is mounted. In this semiconductor device, as shown in FIG. 7, in a composite chip 11 in which semiconductor chips 1 and 2 are joined, a semiconductor chip 31 is provided on the semiconductor chip 2 so that the back surfaces are fixed to each other.
[0065]
Similar to the semiconductor chips 1 and 2, the semiconductor chip 31 is an LSI in which an integrated circuit 21 that is a logic circuit or a memory circuit is formed on the surface thereof, and is a bonding pad made of an aluminum alloy for connection to the outside. 22 is formed. A bonding pad 23 for connecting to the external connection electrode 22 of the semiconductor chip 31 is provided on the surface of the semiconductor chip 1.
[0066]
The semiconductor chip 31 and the semiconductor chip 2 are bonded and fixed to each other by a predetermined die paste on the back surfaces, and the bonding pad 22 of the semiconductor chip 31 and the bonding pad 23 of the semiconductor chip 1 are wire bonded using a gold wire 14. Connected by law.
[0067]
Note that the present invention can also be applied to the case where a substrate on which an integrated circuit is not formed is used instead of the semiconductor chip 1. Also, various materials as described in the first embodiment may be used as the material for the metal balls.
[0068]
According to the semiconductor device of the third modification, in addition to the functions and effects exhibited by the semiconductor device of the first embodiment described above, even if the semiconductor chip 31 is further stacked on the composite chip 11, the miniaturization is impaired. High integration can be achieved without any problem.
[0069]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. The semiconductor device of the second embodiment has a composite chip 11 that is substantially the same as that of the first embodiment, but the junction of the semiconductor chips 1 and 2 is slightly different. In addition, about the same component as 1st Embodiment, the same code | symbol is described and description is abbreviate | omitted. FIG. 8 is a cross-sectional view showing the main part of the semiconductor device of the second embodiment. Note that the size of the semiconductor chip 1 is 10 mm × 10 mm as in the first embodiment, and the size of the semiconductor chip 2 is 7 mm × 7 mm.
[0070]
On the connection electrode 6 made of an aluminum alloy of the semiconductor chip 2, a metal ball 7 made of a gold alloy having a diameter of about 60 μm is bonded. The surface of the connection electrode 4 made of an aluminum alloy of the semiconductor chip 1 is subjected to surface treatment in the order of titanium (Ti) alloy and palladium (Pd), and a metal made of solder having a diameter of about 60 μm on the outermost palladium layer. Ball 32 is melt bonded. Then, the metal ball 7 and the metal ball 32 are aligned, and the metal balls 7 and 32 are joined while being heated at a temperature of 250 ° C. or higher.
[0071]
Note that the materials of the two types of metal balls to be joined are not limited to gold alloy and solder, and other metals such as those exemplified in the first embodiment can be used as long as the combinations have excellent affinity. (Alloy) may also be used.
[0072]
Then, as shown in FIG. 9, the laminated chip 11 is mounted on a lead frame or TAB tape having a LOC structure, for example. In this case, the inner lead 18 of the lead frame or TAB tape and the external connection electrode 5 of the semiconductor chip 1 are joined by a metal ball 33 made of a gold alloy. As a material for the metal ball 33, copper (alloy), solder, or the like may be used in addition to the gold alloy, and a stud bump or a plated bump may be used instead of the metal ball.
[0073]
According to the semiconductor device of the second embodiment, in addition to the functions and effects exhibited by the semiconductor device of the first embodiment described above, the restrictions on the material of the connection electrodes provided on the semiconductor chips 1 and 2 are relaxed and selected. The width can be increased. Further, by using two kinds of metal balls for bonding, the distance (gap) between the semiconductor chips 1 and 2 is slightly increased within the limit that does not affect the wiring length. Even if it occurs, the occurrence of a short circuit or the like is avoided. Therefore, it contributes more by improving the reliability of the product.
[0074]
-Modification-
Here, a modification of the semiconductor device of the second embodiment will be described. In this semiconductor device, the composite chip 11 is configured as in the first embodiment, but the mounting method to the lead frame or TAB tape is different. In addition, about the structural member etc. corresponding to the semiconductor device of 2nd Embodiment, the same code | symbol is described and description is abbreviate | omitted.
[0075]
In the semiconductor device of this modification, the manufactured composite chip 11 is not mounted on the lead frame, but is connected to the inner lead 18 at the same time as the composite chip 11 is formed. That is, in this semiconductor device, as shown in FIG. 10, the metal ball 41 on the connection electrode 4 of the semiconductor chip 1 and the metal ball 42 on the connection electrode 6 of the semiconductor chip 2 are connected via the inner lead 18. The inner leads 18 are melt-bonded so as to sandwich them. In addition, as a material of the metal balls 41 and 42, it is possible to use a gold alloy, solder, or various metals (alloys) described in the first embodiment.
[0076]
According to the semiconductor device of this modification, in addition to the operations and effects achieved by the semiconductor devices of the first and second embodiments described above, it is not necessary to provide external connection electrodes on the semiconductor chip 1. The area occupied by the semiconductor chip 2 can be reduced. For example, it can be made the same size as the semiconductor chip 2. Therefore, it is possible to contribute to further downsizing of the semiconductor device.
[0077]
【The invention's effect】
According to the present invention, it is possible to reduce the size and the wiring length of a LSI having a plurality of different functions without spending costs and time for process development, design environment maintenance, etc., and more than in the case of planar arrangement. Thus, it is possible to make one package.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a main configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a state where a composite chip is mounted on a substrate in the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a state in which a composite chip mounted on a substrate is packaged with a mold resin in the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing the main configuration of a semiconductor device of Modification 1 according to the first embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view showing the main configuration of a semiconductor device of Modification 2 according to the first embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view showing the main configuration of another example of the semiconductor device of Modification 2 according to the first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing the main configuration of a semiconductor device of Modification 3 according to the first embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view showing the main configuration of the semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing a state where a composite chip is mounted on a substrate in a semiconductor device according to a second embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view showing the main configuration of a modified semiconductor device according to a second embodiment of the present invention.
[Explanation of symbols]
1,2,31 Semiconductor chip
3 Logic circuit
4,6 connection terminal
5 External connection terminals
7, 16, 20, 32, 33, 41, 42 Metal balls
8 Memory circuit
11 Multilayer chip
12, 17 substrate
13, 22, 23 Bonding pad
14 Gold wire
15 Insulating resin
17 Insulation tape
18 Inner lead
19 Stud bump
21 Integrated circuits

Claims (8)

第１の集積回路及び第１の接続電極を備えた第１の半導体チップと、第２の集積回路及び第２の接続電極を備えた１つ又は複数の第２の半導体チップであって、
前記第１の半導体チップと前記第２の半導体チップとは、前記第１の接続電極と前記第２の接続電極とが１個の金属バンプを介して対向し、当該金属バンプにより接続されており、
前記第１又は第２の接続電極が、アルミニウム又はその合金からなるとともに、前記金属バンプが金、銅、パラジウム、白金、アルミニウム又はそれらの何れか１種の金属の合金からなるか、
前記第１又は第２の接続電極が、銅又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
前記第１又は第２の接続電極が、金又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
前記第１又は第２の接続電極が、パラジウム又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
前記第１又は第２の接続電極が、ニッケル又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
又は、
前記第１又は第２の接続電極が、錫合金、鉛合金又はインジウム合金の何れかの半田からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなり、
前記第１の半導体チップは、外部の端子と接続するための外部接続電極を有しており、
前記第１の半導体チップの前記外部接続電極上に他の金属バンプが設けられており、
前記第１の半導体チップの一部及び前記第２の半導体チップの一部がモールド絶縁樹脂で覆われており、前記第１の半導体チップの裏面及び前記第２の半導体チップの裏面は前記モールド絶縁樹脂から露出しており、前記第１の半導体チップの前記外部接続電極上で、前記第１の接続電極と同じ面に設けられた前記他の金属バンプの一部が、前記モールド絶縁樹脂の表面から露出していることを特徴とする複数チップ混載型半導体装置。A first semiconductor chip comprising a first integrated circuit and a first connection electrode, and one or more second semiconductor chips comprising a second integrated circuit and a second connection electrode,
In the first semiconductor chip and the second semiconductor chip, the first connection electrode and the second connection electrode face each other through one metal bump and are connected by the metal bump. ,
The first or second connection electrode is made of aluminum or an alloy thereof, and the metal bump is made of gold, copper, palladium, platinum, aluminum, or an alloy of any one of these metals,
The first or second connection electrode is made of copper or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a tin alloy or a lead alloy Or made of any indium alloy solder,
The first or second connection electrode is made of gold or an alloy thereof, and the metal bump is gold, copper, aluminum, platinum or an alloy of any one of these metals, a tin alloy, a lead alloy, or indium. Whether it is made of any alloy solder,
The first or second connection electrode is made of palladium or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a tin alloy or a lead alloy Or made of any indium alloy solder,
The first or second connection electrode is made of nickel or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum, or an alloy of any one of these metals, or a tin alloy or a lead alloy Or made of any indium alloy solder,
Or
The first or second connection electrode is made of a solder of either a tin alloy, a lead alloy, or an indium alloy, and the metal bump is gold, copper, aluminum, palladium, platinum, or any one of these metals Alloy, or a solder of either tin alloy, lead alloy or indium alloy,
The first semiconductor chip has an external connection electrode for connecting to an external terminal;
Other metal bumps are provided on the external connection electrodes of the first semiconductor chip,
A part of the first semiconductor chip and a part of the second semiconductor chip are covered with a mold insulating resin, and the back surface of the first semiconductor chip and the back surface of the second semiconductor chip are formed by the mold insulation. A part of the other metal bump that is exposed from the resin and is provided on the same surface as the first connection electrode on the external connection electrode of the first semiconductor chip is a surface of the mold insulating resin. A multiple-chip mixed semiconductor device, wherein the semiconductor device is exposed from the semiconductor chip. 第１の集積回路及び第１の接続電極を備えた第１の半導体チップと、第２の集積回路及び第２の接続電極を備えた１つ又は複数の第２の半導体チップであって、
前記第１の半導体チップと前記第２の半導体チップとは、前記第１の接続電極と前記第２の接続電極とが１個の金属バンプを介して対向し、当該金属バンプにより接続されており、
前記第１又は第２の接続電極が、アルミニウム又はその合金からなるとともに、前記金属バンプが金、銅、パラジウム、白金、アルミニウム又はそれらの何れか１種の金属の合金からなるか、
前記第１又は第２の接続電極が、銅又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
前記第１又は第２の接続電極が、金又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
前記第１又は第２の接続電極が、パラジウム又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
前記第１又は第２の接続電極が、ニッケル又はその合金からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなるか、
又は、
前記第１又は第２の接続電極が、錫合金、鉛合金又はインジウム合金の何れかの半田からなるとともに、前記金属バンプが金、銅、アルミニウム、パラジウム、白金若しくはそれらの何れか１種の金属の合金、又は錫合金、鉛合金若しくはインジウム合金の何れかの半田からなり、
前記第１の半導体チップは、当該第１の半導体チップに形成されたヴィア孔を介して当該第１の半導体チップの裏面に形成された、外部の端子と接続するための外部接続電極を有しており、
前記第１の半導体チップの一部及び前記第２の半導体チップの一部がモールド絶縁樹脂で覆われているとともに、前記第１の半導体チップの裏面及び前記第２の半導体チップの裏面は前記モールド絶縁樹脂から露出しており、前記第１の半導体チップの裏面において、前記外部接続電極上に他の金属バンプが設けられており、前記他の金属バンプが前記第１の半導体チップの裏面で外部に露出していることを特徴とする複数チップ混載型半導体装置。A first semiconductor chip comprising a first integrated circuit and a first connection electrode, and one or more second semiconductor chips comprising a second integrated circuit and a second connection electrode,
In the first semiconductor chip and the second semiconductor chip, the first connection electrode and the second connection electrode face each other through one metal bump and are connected by the metal bump. ,
The first or second connection electrode is made of aluminum or an alloy thereof, and the metal bump is made of gold, copper, palladium, platinum, aluminum, or an alloy of any one of these metals,
The first or second connection electrode is made of copper or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a tin alloy or a lead alloy Or made of any indium alloy solder,
The first or second connection electrode is made of gold or an alloy thereof, and the metal bump is gold, copper, aluminum, platinum or an alloy of any one of these metals, a tin alloy, a lead alloy, or indium. Whether it is made of any alloy solder,
The first or second connection electrode is made of palladium or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum or an alloy of any one of these metals, or a tin alloy or a lead alloy Or made of any indium alloy solder,
The first or second connection electrode is made of nickel or an alloy thereof, and the metal bump is gold, copper, aluminum, palladium, platinum, or an alloy of any one of these metals, or a tin alloy or a lead alloy Or made of any indium alloy solder,
Or
The first or second connection electrode is made of a solder of either a tin alloy, a lead alloy, or an indium alloy, and the metal bump is gold, copper, aluminum, palladium, platinum, or any one of these metals Alloy, or a solder of either tin alloy, lead alloy or indium alloy,
The first semiconductor chip has an external connection electrode formed on the back surface of the first semiconductor chip through a via hole formed in the first semiconductor chip and connected to an external terminal. And
A part of the first semiconductor chip and a part of the second semiconductor chip are covered with a mold insulating resin, and the back surface of the first semiconductor chip and the back surface of the second semiconductor chip are the mold. Exposed from the insulating resin, another metal bump is provided on the external connection electrode on the back surface of the first semiconductor chip, and the other metal bump is externally provided on the back surface of the first semiconductor chip. A multiple-chip mixed type semiconductor device characterized by being exposed to 前記金属バンプが金属ボールバンプであることを特徴とする請求項１又は２に記載の複数チップ混載型半導体装置。  The multi-chip mixed semiconductor device according to claim 1, wherein the metal bump is a metal ball bump. 前記他の金属バンプは、直径０．８ｍｍ以下の金属ボールを前記外部接続電極に接合することで形成されるものであることを特徴とする請求項１〜３のいずれか１項に記載の複数チップ混載型半導体装置。  The plurality of other metal bumps according to any one of claims 1 to 3, wherein the other metal bump is formed by bonding a metal ball having a diameter of 0.8 mm or less to the external connection electrode. Chip-embedded semiconductor device. 前記金属バンプは、直径２０μｍ〜２５０μｍの金属ボールであることを特徴とする請求項１〜４のいずれか１項に記載の複数チップ混載型半導体装置。  5. The multi-chip mixed semiconductor device according to claim 1, wherein the metal bump is a metal ball having a diameter of 20 μm to 250 μm. 前記第１の半導体チップがロジックチップであり、前記第２の半導体チップがメモリチップであることを特徴とする請求項１〜５のいずれか１項に記載の複数チップ混載型半導体装置。  6. The multi-chip mixed semiconductor device according to claim 1, wherein the first semiconductor chip is a logic chip and the second semiconductor chip is a memory chip. 7. 前記第１及び第２の半導体チップが各々異なる機能のメモリチップであることを特徴とする請求項１〜５のいずれか１項に記載の複数チップ混載型半導体装置。  6. The multi-chip mixed semiconductor device according to claim 1, wherein the first and second semiconductor chips are memory chips having different functions. 第１の集積回路及びアルミニウム又はアルミニウム合金からなる第１の接続電極を備えた第１の半導体チップと、１つ又は複数の第２の集積回路及びアルミニウム又はアルミニウム合金からなる第２の接続電極を備えた第２の半導体チップとを備え、
前記第１の半導体チップの第１の接続電極と前記第２の半導体チップの第２の接続電極間に１個の金属バンプを配置して前記第１の半導体チップと前記第２の半導体チップとを接続するとともに、前記第１の接続電極と前記金属バンプ間又は前記第２の接続電極と前記金属バンプ間の少なくとも一方が、前記第１又は第２の接続電極と前記金属バンプの表面材料の間に物理的蒸着法により形成された層を介して接続されており、
前記金属バンプが半田であり、前記物理的蒸着法により形成された層がパラジウム合金からなる単層構造、又はチタン合金・パラジウムのこの順の積層構造であるか、
前記金属バンプが金合金であり、前記物理的蒸着法により形成された層がクロム・銅・金のこの順の積層構造であることを特徴とする複数チップ混載型半導体装置。A first semiconductor chip having a first integrated circuit and a first connection electrode made of aluminum or an aluminum alloy, and one or a plurality of second integrated circuits and a second connection electrode made of aluminum or an aluminum alloy A second semiconductor chip comprising,
A metal bump is disposed between the first connection electrode of the first semiconductor chip and the second connection electrode of the second semiconductor chip, and the first semiconductor chip, the second semiconductor chip, And at least one of the first connection electrode and the metal bump or between the second connection electrode and the metal bump is made of the surface material of the first or second connection electrode and the metal bump. Connected through a layer formed by physical vapor deposition,
The metal bump is a solder, and the layer formed by the physical vapor deposition method has a single layer structure made of a palladium alloy , or a laminated structure in this order of titanium alloy / palladium,
The multi-chip mixed semiconductor device, wherein the metal bumps are a gold alloy, and the layer formed by the physical vapor deposition has a laminated structure of chromium, copper, and gold in this order.
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