TW201025532A - Chip stacked package having single-sided pads on chips - Google Patents

Chip stacked package having single-sided pads on chips Download PDF

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Publication number
TW201025532A
TW201025532A TW097149041A TW97149041A TW201025532A TW 201025532 A TW201025532 A TW 201025532A TW 097149041 A TW097149041 A TW 097149041A TW 97149041 A TW97149041 A TW 97149041A TW 201025532 A TW201025532 A TW 201025532A
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Taiwan
Prior art keywords
wafer
substrate
package structure
stacked package
pads
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TW097149041A
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Chinese (zh)
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TWI378545B (en
Inventor
Pao-Hsiung Wang
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Powertech Technology Inc
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Priority to TW097149041A priority Critical patent/TWI378545B/en
Publication of TW201025532A publication Critical patent/TW201025532A/en
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Publication of TWI378545B publication Critical patent/TWI378545B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

Disclosed is a chip stacked package having single-sided pads on chips, primarily comprising a substrate, a first chip and a second chip. The substrate has an upper surface and a first step thereon. The first chip is flip-chip bonded to the upper surface of the substrate. The second chip is flip-chip bonded to the first step of the substrate and partially overlapped with the first chip. By this way, it can let a plurality of chips having single-sided pads flip-chip bonded to the substrate to achieve high-density stacking and without affecting the packaging quality. Therefore, it can effectively reduce the package thickness and omit the wire-bonding process. Besides, it doesn't need to consider the risk of wire sweeping.

Description

201025532 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種單侧 銲墊晶片之堆疊封裝構造。 【先前技術】 由於電子產品朝向輕薄短小化與高密度積體電路發 展已成為現今趨勢，當產品尺寸縮小，基板可供黏晶面 積亦被縮小，所有需要的晶片無法再以並排方式 ^ (side-by_side)全部黏貼到基板上，晶片與晶片之間必須 作堆疊處理。已知一種晶片之銲墊配置為單側邊，其堆 疊方式係以主動面朝上的方式進行階梯式斜向堆疊以 使單側銲墊露出，以便於使用銲線作為電性連接至基板 之媒介。階梯式斜向堆疊的方式雖不需設置間隔件並 且可降低多晶片堆疊高度，但基板對晶片的結合力甚 差。此外，在堆疊過程’晶片上銲墊與基板上接墊之間 • 的距離會隨著堆疊的高度増加而增加，進而使得連接之 銲線的長度增加，並且銲線都集中在一特定區域，這種 堆疊型態會有銲線過長與銲線密集的現象，容易發生沖 線問題。此外，所形成的銲線會有超過晶片之弧高。為 避免鲜線外露’封裝厚度必須增加。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 -種單側銲墊晶片之堆叠封裝構造，所開創之架構能使 多顆單侧料晶片冑覆晶式堆疊成能省略打線形成之鲜 201025532 線，故解決了習知堆疊單侧銲墊晶片時容易引發沖線問 題並能有效降低封裝厚度。 本發明之次一目的係在於提供一種單侧銲墊晶片之 堆疊封裝構造’能使多顆單側銲墊晶片在階梯式覆晶堆 疊時得到基板與被堆疊晶片之良好支持。 本發明之再一目的係在於提供一種單側銲墊晶片之 堆疊封裝構造’能改善多顆單侧銲塾晶片在階梯式覆晶 堆疊時的封膠品質。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種單側銲墊晶片之堆疊封裝 構造’主要包含一基板、一第一晶片以及一第二晶片。 該基板係具有一上表面以及一設於該上表面之一側邊上 之第一階梯，該基板係包含複數個第一揍墊與複數個第 二接墊’該些第一接墊係位於該上表面且鄰近於該第一 階梯，該些第二接墊係位於該第一階梯上。該第一晶片 係覆晶接合該基板之該上表面，該第一晶片係具有複數 個第一單侧銲墊’在該些第一單侧輝墊上設有複數個第 一凸塊’該些第一凸塊係接合至該些第一接塾。該第二 晶片係覆晶接合該基板之該第一階梯並與該第一晶片部 分重昼，該第二晶片係具有複數個第二單侧銲墊，在該 些第二單侧鲜塾上設有複數個第二凸塊，該些第二凸塊 係接合至該些第二接墊。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 201025532 第一黏著 可為包含 係可為球 在前述的堆疊封裝構造中，可另包含有— 層，係形成於該第—晶片與該第二晶片之間。 在前述的堆疊封裝構造中，該第一黏著層係 複數個間隙維持件（stand off)與一黏著材料。、 在前述的堆疊封裝構造中，該些間隙維持件 狀物。 在前述的堆疊封裝構造中 數個膠帶。 該些間隙維持件係可為複201025532 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a stacked package structure of a single-sided pad wafer. [Prior Art] Since the development of electronic products towards thin and light and high-density integrated circuits has become a trend nowadays, when the product size is reduced, the area of the substrate for the bonded crystals is also reduced, and all the required wafers can no longer be side by side ^ (side -by_side) All adhered to the substrate, and the wafer and the wafer must be stacked. It is known that a pad of a wafer is configured as a single side, and the stacking manner is performed by stepwise oblique stacking in an active face-up manner to expose a single-sided pad to facilitate electrical connection to the substrate using a bonding wire. medium. The stepwise oblique stacking method does not require spacers and can reduce the multi-wafer stack height, but the substrate has poor adhesion to the wafer. In addition, during the stacking process, the distance between the pad on the wafer and the pad on the substrate increases with the height of the stack, which increases the length of the bonded wire, and the wire is concentrated in a specific area. This type of stacking has a phenomenon that the wire is too long and the wire is dense, which is prone to the problem of punching. In addition, the resulting bond wire will have an arc height that exceeds the wafer. In order to avoid the exposure of fresh lines, the package thickness must be increased. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a stacked package structure of a single-sided pad wafer, which is constructed to enable multiple single-sided wafers to be stacked on top of each other to be omitted. The line is formed by the fresh 201025532 line, so it is easy to cause the problem of the punching line when the conventional one-side pad wafer is stacked and can effectively reduce the package thickness. A second object of the present invention is to provide a stacked package structure for a single-sided pad wafer which enables a plurality of single-sided pad wafers to be well supported for substrate and stacked wafers in a stepped flip chip stack. It is still another object of the present invention to provide a stacked package structure of a single-sided pad wafer which can improve the quality of sealing of a plurality of single-sided pad wafers in a stepped flip chip stack. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a stacked package structure of a single-sided pad wafer 'mainly including a substrate, a first wafer, and a second wafer. The substrate has an upper surface and a first step disposed on a side of the upper surface, the substrate includes a plurality of first mats and a plurality of second pads 'the first pads are located The upper surface is adjacent to the first step, and the second pads are located on the first step. The first wafer is die-bonded to the upper surface of the substrate, and the first wafer has a plurality of first one-side pads, and a plurality of first bumps are disposed on the first one-side glow pads. The first bump is coupled to the first joints. The second wafer is flip-chip bonded to the first step of the substrate and overlaps with the first wafer portion. The second wafer has a plurality of second single-sided pads on the second one-side fresh-spotted A plurality of second bumps are disposed, and the second bumps are coupled to the second pads. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. 201025532 The first adhesive may be an inclusion or a ball. In the foregoing stacked package structure, a layer may be further included between the first wafer and the second wafer. In the foregoing stacked package construction, the first adhesive layer is a plurality of gaps and an adhesive material. In the aforementioned stacked package configuration, the gaps maintain the member. Several tapes were used in the aforementioned stacked package construction. The gap maintaining members can be complex

在前述的堆疊封裝構造中，在該些膠帶之間可留有被 該黏著材料填滿的間隙。 在前述的堆疊封裝構造中，該黏著材料係可選自μ 部填充膠與模封膠體之其中之一。 一 在前述的堆叠封裝構造中，該第-階梯係可為條狀而 僅形成於該基板之該上表面之單—側邊，以使該基板不 具有中央凹穴。 在前述的堆叠封裝_中，帛第-階梯突出㈣上表 面之高度係可不小於該第一晶片之厚度與該第一凸塊之 高度之總合。 在前述的堆疊封裝構造中，可另包含有一模封膠體， 係形成於該基板之該上表面並覆蓋該第一晶片該第二 晶片與該第一階梯。 在則述的堆疊封裝構造中，該第一晶片與該第二晶片 係可為實質相同之記憶體晶片。 在·前述的堆疊封裝構造中，該基板係可更具有一設於 201025532 該第一階梯上之第二階梯’該堆疊封裝構造另包含有一 第三晶片’係覆晶接合該基板之該第二階梯並與該第二 晶片部分重疊。 在前述的堆疊封裝構造中，該基板係可為一印刷電路 板’並包含複數個設置於該第一階梯中之鍍通孔以及複 數個在該基板之一下表面之外接墊。 在前述的堆疊封裝構造中，可另包含複數個銲球，係 接合於該些外接塾。 參在前述的堆疊封裝構造中，該基板係可為一金屬導線 架，該第一階梯係由該導線架之複數個引腳彎折形成， 該些引腳更延伸到該模封膠體之外。 在前述的堆疊封裝構造中，該基板可另具有一延伸板 部，連接至該第一階梯，並且該第一階梯係為斜向延伸， 以使該延伸板部與該基板之該上表面不重叠，另在該延 伸板部與第一階梯之下方各設有複數個延伸接墊，以供 Φ 複數個階梯狀堆疊晶片之覆晶接合。 由以上技術方案可以看出，本發明之單側銲墊晶片之 堆疊封裝構造，具有以下優點與功效： 一、可藉由基板的階梯設計與單側銲墊晶片的特定組合 型態作為其中一技術手段，開創一種架構，能使多 顆單侧銲墊晶片為覆晶式堆疊並能省略打線形成之 銲線，故解決了習知堆疊單側銲墊晶片時容易引發 沖線問題並能有效降低封裝厚度。 一、可藉由基板的階梯設計與單側銲墊晶片的特定組合 201025532 型態作為其中一技術手段，包含晶片之凸塊接合至 基板之階梯以及晶片與晶片之間部分重疊之黏合， 能使多顆單侧銲墊晶片在階梯式覆晶堆疊時得到基 板與被堆疊晶片之良好支持。 二、可藉由基板的階梯設計與單側銲墊晶片的特定組合 型態作為其中-技術手段，更配合了基板的階梯形 狀與厚度，能改善多顆單側銲墊晶片在階梯式覆晶 堆疊時的封膠品質。 四、 可藉由單側銲墊晶片的凸塊與堆Μ晶片上的黏著 層所包含之多個間隙維持件的匹配作為其中一技術 手段，能維持多個單側銲墊晶片在斜向覆晶堆疊時 的水平度。 五、 可藉由基板之階梯之特定形狀變化作為其中一技術 手段，能使基板不具有中央凹穴，故有利於各種封 膠材料填滿覆晶間隙。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 201025532 依據本發明之第一具體實施例，一種單侧銲墊晶片之 堆叠封裝構造舉例說明於第1圖之截面示意圖與第4圖 之基板下表面示意圖。該堆疊封裝構造1〇〇主要包含一 基板110、一第一晶片12〇以及一第二晶片130。其中， 該基板110舉例說明於第2圖之立體圖，該第一晶片12〇 舉例說明於第3圖之立體圖，並且該第二晶片13〇係與 與該第一晶片120為實質相同》該基板11〇係具有一上 表面110A以及一設於該上表面1 i〇A之一側邊11 〇c上 之第一階梯111。該上表面110A係作為晶片設置表面， 以供設置該第一晶片120。具體而言，該第一階梯lu 之表面係高於該上表面110A，且與該上表面u〇A為平 行。該第一階梯111係可以機械、儀刻或雷射方式形成， 為該基板110 —體連接之一突出部位。較佳地，該第一 階梯111係可為條狀而僅形成於該基板110之該上表面 110A之單一側邊，以使該基板11〇不具有中央凹穴有 利於各種封膠材料填滿覆晶間隙。該基板11〇係更具有 電性傳輸功能’其係包含複數個第一接墊112A與複數 個第二接墊112B。該些第一接墊112A與該些第二接墊 U2B係形成於不同平面，以供該第一晶片12〇以及該第 二晶片130之電性連接。其中，該些第一接墊112A係 位於該上表面11 〇A且鄰近於該第一階梯m，該些第二 接塾112B係位於該第一階梯in上。該些第一接墊U2A 與該些第二接墊112B之材質係可為銅，其形狀係可為長 條指狀。請參閲第1圖所示，在本實施例中，該基板！ J 〇 201025532 係可為一印刷電路板❶該基板110並可包含複數個設置 於該第-階梯⑴中之鍍通孔113以及複數個在該基板 110之一下表面110B之外接墊114。該些鍍通孔113係 可分別連接該些第一接墊112A與該些第二接墊U2B至 該些外接墊114。該些外接墊114係可為圓形球墊。在 本實施例中，該堆疊封裝構造100可另包含複數個銲球 170，係接合於該些外接墊114，以供對外接合。請參閲 粵 第4圖所示，該些銲球170係可為多排交錯排列。 請參閱第1圖所示，該第一晶片120係覆晶接合該基 板110之該上表面110A。而上述覆晶接合技術係可為熱 超音波加熱鍵合。請參閱第丨及3圖所示，該第一晶片 120係具有複數個第一單側銲墊丨2丨，在該些第一單側銲 塾121上設有複數個第一凸塊j22，該些第一凸塊122 係接合至該些第一接墊112A。在本實施例中，該些第一 凸塊122係可為金凸塊，其形狀係為矩形塊或立方塊。 ❿ 該些第一凸塊122之材質係可包含金、銅、或鋁或其合 金金屬。請參閱第1圖所示’可利用一黏晶層14〇，例 如環氧化合物或是B階黏膠，黏接該第一晶片12〇之表 面與該基板110之該上表面11 0A，以支撐該第一晶片ι2〇 未設置有該些第一凸塊122之區域，故能避免在覆晶時 該第一晶片120產生傾斜的情況，更可在疊設該第二晶 片130提供水平之晶片設置表面。 請參閱第1圖所示，該第二晶片13〇係覆晶接合該基 板110之該第一階梯H1並與該第一晶月丨2〇部分重 201025532 疊。該第二晶片130係具有複數個第二單側銲墊131， 在該些第二單側銲墊131上設有複數個第二凸塊132, 該些第二凸塊132係接合至該些第二接墊112B。較佳 地’該第一晶片120與該第二晶片130係可為實質相同 之記憶體晶片’例如晶片尺寸、電性功能與銲塾配置位 置皆為松同’以減少晶片種類進而降低晶片之製造成本 與管理成本。 請參閱第1圖所示，在本實施例中，該堆疊封裝構造 ❹ 100可另包含有一第一黏著層15卜係形成於該第-晶片 120與該第二晶片13〇之間。該第二晶片13〇在該第一 晶片120上之部分重疊部位為非電性連接之機械性黏 著，該第二晶片130超出該第一晶片12〇之其餘部位係 為電性連接之凸塊接合。因此，該第二晶片13〇與該第 一晶片120的組合能構成一種階梯狀堆疊之良好覆晶接 合0 ❹ 較佳地’該第一黏著層15丨係可為包含複數個間隙绅 持件l5lA(standoff)與一黏著材料151B，藉以維持該第 二晶片130在覆晶接合時水平度。在本實施例中，該些 β隙維持件151A係可為複數個膠帶。在該些膠帶之度 了留有被該黏著材料151B填滿的間隙。在本實施例中 =霉著材料151B係為底部填充膠在未固化前具有戾 二動眭’可利用點膠技術藉由點膠針頭將尚為液態文 =材料點塗在該第二晶片13〇之一側邊㈣ 、現象使該黏著材料151B可完全填滿該第一晶片12 201025532 與該第二晶片130之間之間隙並包覆該些第二凸塊i32 與該些間隙維持件151A，在固化後可黏著該第二晶片 130與該第—晶片120。尤佳地，請參閱第1圖之放大圖 所不’該第一階梯111突出於該上表面110A之高度H1 係可不小於該第一晶片120之厚度T與該第一凸塊122 之南度H2之總合，以避免該第一晶片120之背面超出 該第一階梯111而有擋膠之現象，造成填膠之困難。除 此之外，該黏著材料151B亦可選自於模封膠體（molding 鲁 C〇mP〇Und)。或者，該第一黏著層151之材質係可與該黏 晶層140為相同並為一體形成。 請參閱第1圖所示，在本實施例中，該堆疊封裝構造 100可另包含有一模封膠體160。該模封膠體160係可為 壓模（或稱轉移成形，transfer m〇lding)的技術加以形 成。該模封膠體160係形成於該基板u〇之該上表面 ιιοΑ並覆蓋該第一晶片120、該第二晶片與該第一 • 階梯U1，以提供適當的封裝保護以防止塵埃污染。由 於該第一晶片120與該第二晶片13〇已堅固地結合於該 基板U0,故該模封膠體16〇在形成過程產生之模流壓 力不會對晶片及其凸塊造成任何不利的影響。 因此，利用該第一階梯U1之形成位置使該基板ιι〇 具有呈單侧階梯狀之型態，^吏單侧㈣形態之該第一 晶片120與該第二晶片13〇的部分重疊達到斜向晶片堆 叠之覆晶接合’故開創了—種全新架構，能使多顆單側 銲墊晶片為覆晶式堆疊並能省略打線形成之銲線，故解 201025532 決了習知堆疊單側銲墊晶片時容易引發沖線問題並能有 效降低封裝厚度。換言之，能在堆疊晶片之後可省略打 線製程，無須預留打線弧高之容置空間，也無須考慮鲜 線偏移的風險。此外，該第二晶片130係以該些第二凸 塊132接合至該第一階梯m，作為第一種接合，又利 用該第一黏著層151黏合該第一晶片12〇與該第二晶片 1 30之間部分重疊區域，能使多顆單侧銲墊晶片在階梯 ❿ 式覆晶堆疊時得到基板與被堆疊晶片之良好支持。較佳 地’更利用該第一黏著層1 5 1所包含之該些間隙維持件 151A，能維持該第二晶片13〇或更多個單側銲墊晶片在 斜向覆晶堆疊時的水平度，並使電性連接關係更為確實 有效。 依據本發明之第二具體實施例，另一種單側銲墊晶片 之堆疊封裝構造舉例說明於第5圖之截面示意圖。該堆 疊封裝構造200所包含之主要元件係與第一具體實施例 • 的基板110、第一晶片120以及第二晶片130大致為相 同’故以第一具體實施例之相同元件符號標示之並部分 省略說明。該基板1 1 〇係具有一上表面1 i 0 A以及一設於 該上表面110A之一側邊11 〇c上之第一階梯111。該上 表面110A與該第一階梯ill上係分別形成有複數個第一 接墊112A與複數個第二接墊π2B，其中該第一接墊 112A係鄰近於該第一階梯in。該第一晶片12〇係覆晶 接合該基板110之該上表面110A，並具有複數個第一單 側銲墊121以及設置於其上之複數個第一凸塊122。在 12 201025532 本實施例中，該些第一凸塊122係可為焊料凸塊，並回 焊接合於該些第一接墊112Αβ該些第一凸塊122之形成 方式可為電鍍或印刷，而該些第—凸塊122使用的材料 係一般為錫鉛或無鉛銲料，或可包含銅、銀鎳、金、 鉑或鈀等材質。&外’利用一黏晶層24〇形成於該第一 晶片120與該基板11〇之間，能避免該第一晶片12〇傾 該第二晶片130 斜，以便於該第二晶片13〇之水平疊置In the aforementioned stacked package construction, a gap filled by the adhesive material may remain between the tapes. In the foregoing stacked package configuration, the adhesive material may be selected from one of a μ-filler and a mold-filler. In the foregoing stacked package configuration, the first step can be strip-shaped and formed only on the single side of the upper surface of the substrate such that the substrate does not have a central recess. In the foregoing stacked package, the height of the upper surface of the first step protrusion (four) may be not less than the sum of the thickness of the first wafer and the height of the first bump. In the foregoing stacked package structure, a molding compound may be further disposed on the upper surface of the substrate and cover the second wafer and the first step of the first wafer. In the stacked package structure described above, the first wafer and the second wafer may be substantially identical memory chips. In the foregoing stacked package structure, the substrate may further have a second step disposed on the first step of 201025532. The stacked package structure further includes a third wafer 'which is flip-chip bonded to the second of the substrate. The step is partially overlapped with the second wafer. In the foregoing stacked package configuration, the substrate may be a printed circuit board' and includes a plurality of plated through holes disposed in the first step and a plurality of pads on a lower surface of the substrate. In the foregoing stacked package configuration, a plurality of solder balls may be further included to be bonded to the external turns. In the foregoing stacked package structure, the substrate can be a metal lead frame, and the first step is formed by bending a plurality of pins of the lead frame, and the pins extend beyond the mold sealing body. . In the foregoing stacked package structure, the substrate may further have an extension plate portion connected to the first step, and the first step is obliquely extended so that the extension plate portion and the upper surface of the substrate are not The plurality of extension pads are respectively disposed under the extension plate portion and the first step for the flip chip bonding of the plurality of stepped stacked wafers. It can be seen from the above technical solutions that the stacked package structure of the single-sided pad wafer of the present invention has the following advantages and effects: 1. A specific combination of the step design of the substrate and the single-sided pad wafer can be taken as one of The technical means, creating a structure, can make a plurality of single-sided pad wafers to be flip-chip stacked and can omit the bonding wires formed by the wire bonding, so that the conventional problem of stacking single-sided pad wafers is easy to cause the problem of punching lines and can be effective. Reduce the package thickness. 1. A special combination of the step design of the substrate and the single-sided pad wafer 201025532 can be used as one of the technical means, including the step of bonding the bump of the wafer to the substrate and the partial overlap between the wafer and the wafer, A plurality of single-sided pad wafers are well supported by the substrate and the stacked wafers in a stepped flip-chip stack. Second, the stepwise design of the substrate and the specific combination of the single-sided pad wafer can be used as a technical means, and the step shape and thickness of the substrate can be further matched, and the single-sided pad wafer can be improved in stepped flip chip. The quality of the seal when stacked. 4. The matching of the bumps of the single-sided pad wafer and the plurality of gap maintaining members included in the adhesive layer on the stacked wafer can be used as one of the technical means to maintain the plurality of single-sided pad wafers in an oblique direction. The level of crystal stacking. 5. The specific shape change of the step of the substrate can be used as one of the technical means, so that the substrate can have no central recess, so that various sealing materials are filled to fill the gap. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. 201025532 According to a first embodiment of the present invention, a stacked package structure of a single-sided pad wafer is illustrated in a cross-sectional view of FIG. 1 and a schematic view of a lower surface of the substrate of FIG. The stacked package structure 1 〇〇 mainly includes a substrate 110, a first wafer 12A, and a second wafer 130. The substrate 110 is illustrated in a perspective view of FIG. 2, the first wafer 12A is illustrated in a perspective view of FIG. 3, and the second wafer 13 is substantially the same as the first wafer 120. The rafter has an upper surface 110A and a first step 111 disposed on one of the side edges 11 〇c of the upper surface 1 i〇A. The upper surface 110A serves as a wafer placement surface for providing the first wafer 120. Specifically, the surface of the first step lu is higher than the upper surface 110A and is parallel to the upper surface u 〇 A. The first step 111 can be formed mechanically, in an inscribed manner or in a laser manner, and is a protruding portion of the substrate 110. Preferably, the first step 111 can be strip-shaped and formed only on a single side of the upper surface 110A of the substrate 110, so that the substrate 11 does not have a central recess to facilitate filling of various sealing materials. Cladding gap. The substrate 11 further has an electrical transmission function. The system includes a plurality of first pads 112A and a plurality of second pads 112B. The first pads 112A and the second pads U2B are formed on different planes for electrically connecting the first wafer 12A and the second wafer 130. The first pads 112A are located on the upper surface 11A and adjacent to the first step m, and the second interfaces 112B are located on the first step in. The material of the first pads U2A and the second pads 112B may be copper, and the shape may be a long finger shape. Please refer to Fig. 1, in this embodiment, the substrate! J 〇 201025532 can be a printed circuit board 基板 the substrate 110 and can include a plurality of plated through holes 113 disposed in the first step (1) and a plurality of pads 114 outside the lower surface 110B of the substrate 110. The plated through holes 113 can respectively connect the first pads 112A and the second pads U2B to the external pads 114. The outer pads 114 can be round ball pads. In this embodiment, the stacked package structure 100 can further include a plurality of solder balls 170 bonded to the external pads 114 for external bonding. Please refer to Figure 4, which shows that the solder balls 170 can be staggered in multiple rows. Referring to FIG. 1, the first wafer 120 is flip-chip bonded to the upper surface 110A of the substrate 110. The above flip chip bonding technique can be a thermal ultrasonic bonding. Referring to FIGS. 3 and 3, the first wafer 120 has a plurality of first one-side pads 2, and a plurality of first bumps j22 are disposed on the first one-side pads 121. The first bumps 122 are bonded to the first pads 112A. In this embodiment, the first bumps 122 may be gold bumps, and the shape thereof is a rectangular block or a cubic block. The material of the first bumps 122 may comprise gold, copper, or aluminum or an alloy metal thereof. Referring to FIG. 1 , a surface of the first wafer 12 与 and the upper surface 11 0A of the substrate 110 may be adhered by using a bonding layer 14 , such as an epoxy compound or a B-stage adhesive. Supporting the first wafer ι2 is not provided with the regions of the first bumps 122, so that the tilting of the first wafer 120 during flip chiping can be avoided, and the second wafer 130 can be stacked to provide a level. The wafer sets the surface. Referring to FIG. 1, the second wafer 13 is flip-chip bonded to the first step H1 of the substrate 110 and overlapped with the first crystal moon 2〇 portion 201025532. The second wafer 130 has a plurality of second single-sided pads 131. The second single-sided pads 131 are provided with a plurality of second bumps 132. The second bumps 132 are bonded to the second bumps 132. The second pad 112B. Preferably, the first wafer 120 and the second wafer 130 can be substantially the same memory chip, for example, the wafer size, the electrical function, and the soldering arrangement position are all the same to reduce the type of the wafer and thereby reduce the wafer. Manufacturing costs and management costs. Referring to FIG. 1, in the embodiment, the stacked package structure 100 further includes a first adhesive layer 15 formed between the first wafer 120 and the second wafer 13A. The portion of the second wafer 13 is partially electrically overlapped on the first wafer 120. The second wafer 130 is electrically connected to the rest of the first wafer 12 Engage. Therefore, the combination of the second wafer 13A and the first wafer 120 can form a good flip-chip bond of a stepped stack. Preferably, the first adhesive layer 15 can comprise a plurality of gap holders. l5lA (standoff) and an adhesive material 151B, thereby maintaining the levelness of the second wafer 130 during flip chip bonding. In this embodiment, the β-gap maintainers 151A may be a plurality of tapes. The gap of the tape is filled with the adhesive material 151B. In the present embodiment, the mold material 151B is an underfill having a second action before it is uncured. The dispensing process can be applied to the second wafer 13 by dispensing a needle through a dispensing needle. One side of the crucible (four), the phenomenon that the adhesive material 151B can completely fill the gap between the first wafer 12 201025532 and the second wafer 130 and cover the second bumps i32 and the gap maintaining members 151A The second wafer 130 and the first wafer 120 may be adhered after curing. More preferably, please refer to the enlarged view of FIG. 1 . The height H1 of the first step 111 protruding from the upper surface 110A may be not less than the thickness T of the first wafer 120 and the south of the first bump 122. The sum of H2 prevents the back side of the first wafer 120 from exceeding the first step 111 and has a phenomenon of blocking glue, which makes the filling difficult. In addition to this, the adhesive material 151B may also be selected from a molding gel (molding C〇mP〇Und). Alternatively, the material of the first adhesive layer 151 may be the same as that of the adhesive layer 140 and formed integrally. Referring to FIG. 1 , in the embodiment, the stacked package structure 100 may further include a molding compound 160 . The molding compound 160 can be formed by a technique of press molding (or transfer molding). The molding compound 160 is formed on the upper surface of the substrate 〇 Α Α and covers the first wafer 120, the second wafer and the first step U1 to provide proper package protection to prevent dust pollution. Since the first wafer 120 and the second wafer 13 are firmly bonded to the substrate U0, the molding pressure generated by the molding compound 16 during the forming process does not adversely affect the wafer and its bumps. . Therefore, the formation position of the first step U1 is such that the substrate ιι has a single-sided stepped shape, and the first wafer 120 and the second wafer 13 形态 are partially overlapped in a single-sided (four) form. The flip-chip bonding to the wafer stack has created a new architecture that enables multiple single-sided pad wafers to be flip-chip stacked and can be omitted from wire bonding. Therefore, 201025532 eliminates the conventional stacking of single-sided soldering. When the wafer is padded, it is easy to cause a problem of punching and can effectively reduce the thickness of the package. In other words, the wiring process can be omitted after stacking the wafers, without having to reserve the space for the arcing height of the wire, and the risk of fresh line offset is not considered. In addition, the second wafer 130 is bonded to the first step m by the second bumps 132. As the first bonding, the first bonding layer 151 is used to bond the first wafer 12 and the second wafer. The partially overlapped area between 1 and 30 enables a good support of the substrate and the stacked wafers when the single-sided pad wafers are stacked in a step-by-step flip chip. Preferably, the gap holders 151A included in the first adhesive layer 151 are used to maintain the level of the second wafer 13 or more single-sided pad wafers in oblique flip-chip stacking. Degree, and make the electrical connection relationship more effective. According to a second embodiment of the present invention, another stacked package structure of a single-sided pad wafer is illustrated in a cross-sectional view of FIG. The main components included in the stacked package structure 200 are substantially the same as the substrate 110, the first wafer 120, and the second wafer 130 of the first embodiment, and are labeled with the same component symbols of the first embodiment. The description is omitted. The substrate 1 1 has an upper surface 1 i 0 A and a first step 111 disposed on one side 11 〇c of the upper surface 110A. The upper surface 110A and the first step ill are respectively formed with a plurality of first pads 112A and a plurality of second pads π2B, wherein the first pads 112A are adjacent to the first steps in. The first wafer 12 is flip-chip bonded to the upper surface 110A of the substrate 110, and has a plurality of first single-sided pads 121 and a plurality of first bumps 122 disposed thereon. In the embodiment of the present invention, the first bumps 122 may be solder bumps, and may be soldered to the first pads 112A. The first bumps 122 may be formed by electroplating or printing. The materials used for the first bumps are generally tin-lead or lead-free solder, or may include materials such as copper, silver nickel, gold, platinum or palladium. & externally using a bonding layer 24〇 between the first wafer 120 and the substrate 11〇, the first wafer 12 can be prevented from tilting the second wafer 130 to facilitate the second wafer 13〇 Horizontal stacking

係覆晶接合該基板110之該第一階梯1U並與該第一晶 片120部分重疊》同樣地，該第二晶片13〇係具有複數 個第一單侧銲墊131以及複數個第二凸塊Η〗，該些第 二凸塊132係接合至該些第二接墊U2B。請參閱第5圖 所示該堆疊封裝構造200可另包含有一第一黏著層 25卜係形成於該第一晶片12〇與該第二晶片13〇之間。 該第一黏著層251係可為包含複數個間隙維持件25i a 與一黏著材料251B。在本實施例中，該些間隙維持件 251A係可為球狀物。具體而言，該些間隙維持件251A 之直徑係可相同或略小於該些第二凸塊132突出於該第 二晶片uo之高度^較佳地，該黏著材料25ib與該黏 晶層240係由一底部填充膠所構成。 依據本發明之第三具體實施例，另一種單側銲墊晶片 之堆疊封裝構造舉例說明於第6圖之截面示意圖。該堆 整封裝構造300所包含之主要元件係與第—具體實施例 的基板no、第一晶片120以及第二晶片13〇大致為相 同，故以第一具體實施例之相同元件符號標示之並部分 13 201025532 省略說明。該基板110係具有一上表面11 0A以及一設於 該上表面11 0A上之第一階梯111。該第一晶片120係覆 晶接合該基板110之該上表面11 〇A。該第一晶片120與 該基板110之間係形成有一黏晶層340。在本實施例中， 該黏晶層3 40係可為黏晶膠帶。該第二晶片丨3 〇係覆晶 接合該基板110之該第一階梯111並與該第一晶片12〇 部分重疊。請參閱第6圖所示，該堆疊封裝構造300可 另包含有一第一黏著層351’係形成於該第一晶片120 與該第二晶片130之間。在本實施例中，該第一黏著層 351係可為晶片貼附物質（Dam，Die Attach Material)，即 在晶圓等級時形成於該第一晶片丨2〇之背面，通常是全 面覆蓋該背面，並在作晶片堆疊時呈現B階段或半固化 狀態。而該第一黏著層351之厚度可大致等於或稍小於 該4·第一凸塊132之尚度。在本實施例中，該堆疊封裝 構造300可另包含有一第二黏著層352，係形成於該第 二晶片130之背面。該堆疊封裝構造3〇〇可另包含有一 模封膠體160,係形成於該基板11〇之該上表面11〇八並 覆蓋該第晶片120、該第二晶片130與該第一階梯 111。由於該第一黏著層351係為晶片貼附物質故已填 滿該第一晶片120與該第二晶片13〇之間部分重疊之間 隙’故可取代底部填充膠料黏著材料並省略間隔維持 件。利用該基板110的非環狀階梯形狀以不構成中央凹 穴的設計以及該第一黏著層351的厚度限制故在本實 施例中，該模封膠體160更可行地填滿該第二晶片13〇 201025532 未與該第一晶片1 20重疊之間隙以及該第一晶片120之 周邊缝隙，並密封該些凸塊122、132，不會形成氣孔， 以改善多顆單側銲墊晶片在階梯式覆晶堆疊時的封膠品 質。 依據本發明之第四具體實施例，另一種單侧銲墊晶片 之堆疊封裝構造舉例說明於第7圖之截面示意圖。該堆 疊封裝構造400所包含之主要元件係與第一具體實施例 的基板110、第一晶片120以及第二晶片130大致為相 ® 同’故以第一具體實施例之相同元件符號加以標示之並 省略部分說明。此外，第四具體實施例之基本架構主要 與第三具體實施例’並可增加更多晶片數量進行階梯式 覆晶堆疊。該基板110係具有一上表面HOA以及一設於 該上表面110A上之第一階梯m，並在該上表面11〇A 與該第一階梯111上形成複數個第一接墊U2A與複數個 第二接墊112B。該第一晶片120係覆晶接合該基板u〇 φ 之該上表面11 0A。具髏而言，一黏晶層440係形成於該 第一晶片120與該基板11()之間，用以黏接與支撐該第 一晶片12 0。該第二晶片i 3 〇係覆晶接合該基板j j 〇之 該第一階梯111並與該第一晶片120部分重疊。一第一 黏著層451係形成於該第一晶片12〇與該第二晶片13〇 之間’用以黏接與支撐該第二晶片1 3 0。 請參閱第7圖所示，在本實施例中，該基板11()係可 更具有一設於該第一階梯ηι上之第二階梯415。該第 二階梯415之表面係高於該第一階梯U1之表面，該第 15 201025532 1¾梯415上係形成有複數個第三接墊412C。在本實施 例中該堆疊封裝構造4〇〇另包含有一第三晶片48〇， 係覆晶接合該基板110之該第二階梯415並與該第二晶 片130部分重疊。該第三晶片480係具有複數個第三單 侧銲墊481以及複數個第三凸塊482,該些第三凸塊482 係設置於該些第三單側銲墊481上。在覆晶接合時該 些第二凸塊482係接合至該基板110之該些第三接墊 412C。在本實施例中，該第二晶片13〇與該第三晶片48〇 ® 之間係形成有一第二黏著層452，其係用以黏接與支撐 該第三晶片480。 請再參閱第7圖所示’在本實施例中，該基板11()係 可更具有一設於該第二階梯415上之第三階梯416。該 第三階梯416之表面係形成有複數個第四接墊41 2D。在 本實施例中，該堆疊封裝構造400另包含有一第四晶片 490’係覆晶接合該基板11()之該第三階梯416並與該第 φ 三晶片480部分重疊。同樣地，該第四晶片490係具有 複數個第四單側銲墊491以及複數個第四凸塊492，該 些第四凸塊492係設置於該些第四單侧銲墊491上。在 覆晶接合時，該些第四凸塊492係接合至該基板11〇之 該些第四接墊412D »在本實施例中，該第三晶片480與 該第四晶片490之間係形成有一第三黏著層453。具體 而言，該些晶片120、130、480與490係可為實質相同。 該黏晶層440與該些黏著層45卜452與453係可為黏晶 膠帶。請再參閱第7圖所示，在本實施例中，一模封膠 16 201025532 體160係形成於該基板no之該上表面π 〇A並覆蓋該些 晶片 120、130、48 0、490 與該些階梯 111、415、416。 由上述可知，該堆疊封裝構造400可堆疊更多的晶片 以增加電訊功能或擴大記憶體容量，並且無論堆疊數量 之多寡’多顆單側銲墊晶片在階梯式覆晶堆疊時皆可得 到基板與被堆疊晶片之良好固著與支持，並易於控制其 覆晶堆疊之水平度。 依據本發明之第五具體實施例，另一種單側銲墊晶片 之堆疊封裝構造500舉例說明於第8圖之截面示意圖。 該堆疊封裝構造500所包含之主要元件係與第一具體實 施例的基板110、第一晶片120以及第二晶片130大致 為相同’故以第一具體實施例之元件符號標示或可省略 說明。該基板110係具有一上表面110A以及一設於該上 表面110A上之第一階梯U1。該第一晶片ι2〇係覆晶接 合該基板110之該上表面110A。該第二晶片13〇係覆晶 接合該基板110之該第一階梯m並與該第一晶片12〇 部分重疊。在本實施例中，該堆疊封裝構造500係可更 堆疊一第三晶片581與一第四晶片582。該第三晶片581 與該第四晶片582係分別覆晶接合至該基板丨1〇之第二 階梯518與第三階梯519。 請參閲第8圖所示’在本實施例中，該基板11〇可另 具有一延伸板部517。該延伸板部517係連接至該第一 階梯111，並且該第一階梯U1係為斜向延伸，以使該 延伸板部517與該基板11〇之該上表面u〇A不重疊。在 17 201025532 本實施例中，該延伸板部517與第一階梯1U之下方各 設有複數個延伸接墊512E，以供複數個階梯狀堆疊晶片 590之覆晶接合。每一階梯狀堆疊晶片59〇係具有複數 個單侧銲墊59i，並於該些單側銲墊591上設置複數個 凸塊592，以供接合至該些延伸接墊512E。該些階梯狀 堆疊晶片590係可實質相同於該第一晶片12〇與該第二 晶片130,且該些階梯狀堆疊晶片59〇之疊設方式係可 與該第二晶片130之設置方式相同❶在一具體結構該 ❿ 些階梯狀堆疊晶片590之數量係為四個晶片，可與另一 側階禅狀覆晶堆疊之晶片數量相同。 請參閱第8圖所示，一模封膠體16〇係形成於該基板 110之該上表面11 0A並覆蓋該些階梯1U、518與519, 但局部顯露該延伸板部517，其中該模封夥體160更密 封該些晶片120、130、581與582。在本實施例中，該 堆疊封裝構造500可另包含一模封膠體561，係形成於 φ 該第一階梯111下方並覆蓋該延伸板部517，以密封該 些階梯狀堆疊晶片590，該模封膠體561係顯露該基板 110之該下表面110B。此外，該模封膠體561與該模封 膠體160係可為同時形成’故不會增加該堆疊封裝構造 500之製程步驟。請參閲第8圖所示，複數個録球170 係設置於該基板110之下表面110B。在本實施例中，該 堆疊封裝構造500可另包含有複數個銲球571，係設置 於該延伸板部517之上表面，以供堆疊接合另一堆疊封 裝構造500(如第9圖所示）。請參閱第9圖所示，利用回 18 201025532 焊技術焊接上方堆疊封裝構造500之該些銲球17〇與另 一下方堆疊封裝構造5 00之該些銲球571。 透過上述該基板110之設計，能夠充分利用該基板 11 0下方之空間，以增加封裝晶片的數量，並可進行八 個或更多晶片堆疊的結構。另可藉由該些銲球17〇與571 堆疊至另一堆疊封裝構造500，以形成覆晶堆疊式封裝 構造（POP，Package On Package) 〇 依據本發明之第六具體實施例，另一種單側銲墊晶片 之堆疊封裝構造舉例說明於第10圖之截面示意圖。該堆 疊封裝構造600所包含之主要元件係與第一具體實施例 的基板110、第一晶片120以及第二晶片130大致為相 同’故以第一具體實施例之相同元件符號標示之並部分 省略說明。該基板110係具有一上表面n〇A以及一第一 階梯111。在本實施例中’該基板11()係可為一金屬導 線架’該第一階梯111係由該導線架之複數個引腳彎折 形成。該第一晶片120與該第二晶片13〇係分別覆晶接 合該基板110之該上表面11 〇A與該第一階梯111，其中 該第二晶片130並與該第一晶片120部分重疊。該第二 晶片130上係可疊設一第三晶片681與一第四晶片 682’並使該第三晶片681與該第四晶片682呈階梯狀堆 疊。 請參閲第10圖所示’該基板110之該第一階梯m 係可為斜向延伸並形成一延伸板部617，其中該延伸板 部617與該基板110之該上表面u〇A不重疊。在本實施 19 201025532 例中’該基板110之該延伸板部617係可設置有複數個 階梯狀堆疊晶片690。該堆疊封裝構造600係包含—密 封該些晶片120、130、681與682之模封膠體ι6〇，以 及另一密封該些階梯狀堆疊晶片69〇之模封膠體661。 具體而言’該模封膠體661與該模封膠體16〇係可為一 體成形。較佳地，該些引腳更延伸到該模封膠體16〇與 661之外，以形成複數個延伸引腳61〇D，以供對外接合The second wafer 13 has a plurality of first single-sided pads 131 and a plurality of second bumps. Similarly, the first wafer 1U of the substrate 110 is overlapped and partially overlapped with the first wafer 120. The second bumps 132 are bonded to the second pads U2B. Referring to FIG. 5, the stacked package structure 200 may further include a first adhesive layer 25 formed between the first wafer 12A and the second wafer 13A. The first adhesive layer 251 can include a plurality of gap maintaining members 25i a and an adhesive material 251B. In this embodiment, the gap maintaining members 251A may be balls. Specifically, the diameters of the gap maintaining members 251A may be the same or slightly smaller than the height of the second bumps 132 protruding from the second wafer uo. Preferably, the adhesive material 25ib and the adhesive layer 240 are It consists of an underfill. According to a third embodiment of the present invention, another stacked package structure of a single-sided pad wafer is illustrated in a cross-sectional view of Fig. 6. The main components included in the stacking structure 300 are substantially the same as those of the substrate no, the first wafer 120, and the second wafer 13 of the first embodiment, and are labeled with the same component symbols in the first embodiment. Section 13 201025532 Omit the description. The substrate 110 has an upper surface 110A and a first step 111 disposed on the upper surface 110A. The first wafer 120 is die-bonded to the upper surface 11A of the substrate 110. A die bond layer 340 is formed between the first wafer 120 and the substrate 110. In this embodiment, the adhesive layer 340 may be a die-bonding tape. The second wafer 丨3 is flip-chip bonded to the first step 111 of the substrate 110 and partially overlaps the first wafer 12 。. Referring to FIG. 6, the stacked package structure 300 may further include a first adhesive layer 351' formed between the first wafer 120 and the second wafer 130. In this embodiment, the first adhesive layer 351 can be a die attach material (Dam, Die Attach Material), that is, formed on the back surface of the first wafer 〇 2 在 at the wafer level, usually covering the entire surface. The back side, and in the case of wafer stacking, presents a B-stage or semi-cured state. The thickness of the first adhesive layer 351 may be substantially equal to or slightly smaller than the thickness of the first bump 132. In this embodiment, the stacked package structure 300 further includes a second adhesive layer 352 formed on the back surface of the second wafer 130. The stacked package structure 3 can further include a molding compound 160 formed on the upper surface 11 of the substrate 11 and covering the first wafer 120, the second wafer 130 and the first step 111. Since the first adhesive layer 351 is a wafer attaching material, the gap between the first wafer 120 and the second wafer 13 is partially filled, so that the underfill adhesive material can be replaced and the spacer is omitted. . By using the non-annular stepped shape of the substrate 110 to not constitute the central recess and the thickness limitation of the first adhesive layer 351, in the present embodiment, the molding compound 160 is more feasible to fill the second wafer 13 〇201025532 does not overlap the gap between the first wafer 1 20 and the periphery of the first wafer 120, and seals the bumps 122, 132 without forming air holes to improve the multi-sided pad wafer in a stepped manner Sealing quality when flip chip stacking. According to a fourth embodiment of the present invention, another stacked package structure of a single-sided pad wafer is illustrated in a cross-sectional view of Fig. 7. The main components included in the stacked package structure 400 are substantially the same as those of the substrate 110, the first wafer 120, and the second wafer 130 of the first embodiment, and thus are labeled with the same component symbols of the first embodiment. Some explanations are omitted. Further, the basic architecture of the fourth embodiment is mainly related to the third embodiment' and the number of wafers can be increased to perform stepped flip-chip stacking. The substrate 110 has an upper surface HOA and a first step m disposed on the upper surface 110A, and a plurality of first pads U2A and a plurality of the upper surface 11A and the first step 111 are formed on the upper surface 11A. The second pad 112B. The first wafer 120 is die-bonded to the upper surface 110A of the substrate u〇 φ. In one embodiment, a bonding layer 440 is formed between the first wafer 120 and the substrate 11 to bond and support the first wafer 120. The second wafer i 3 is flip-chip bonded to the first step 111 of the substrate j j 并 and partially overlaps the first wafer 120. A first adhesive layer 451 is formed between the first wafer 12 and the second wafer 13' to bond and support the second wafer 130. Referring to FIG. 7, in the embodiment, the substrate 11() may further have a second step 415 disposed on the first step η. The surface of the second step 415 is higher than the surface of the first step U1. The 15th 201025532 13⁄4 ladder 415 is formed with a plurality of third pads 412C. In this embodiment, the stacked package structure 4 further includes a third wafer 48, which is bonded to the second step 415 of the substrate 110 and partially overlaps the second wafer 130. The third wafer 480 has a plurality of third single-sided pads 481 and a plurality of third bumps 482. The third bumps 482 are disposed on the third single-sided pads 481. The second bumps 482 are bonded to the third pads 412C of the substrate 110 during flip chip bonding. In this embodiment, a second adhesive layer 452 is formed between the second wafer 13A and the third wafer 48A for bonding and supporting the third wafer 480. Referring to FIG. 7 again, in the embodiment, the substrate 11() may further have a third step 416 disposed on the second step 415. The surface of the third step 416 is formed with a plurality of fourth pads 41 2D. In this embodiment, the stacked package structure 400 further includes a fourth wafer 490' that is bonded to the third step 416 of the substrate 11 and partially overlaps the third φ wafer 480. Similarly, the fourth wafer 490 has a plurality of fourth single-sided pads 491 and a plurality of fourth bumps 492 disposed on the fourth one-side pads 491. During the flip chip bonding, the fourth bumps 492 are bonded to the fourth pads 412D of the substrate 11 . In the embodiment, the third wafer 480 and the fourth wafer 490 are formed. There is a third adhesive layer 453. In particular, the wafers 120, 130, 480 and 490 can be substantially identical. The adhesive layer 440 and the adhesive layers 45 and 452 and 453 may be a die-bonding tape. Referring to FIG. 7 again, in the embodiment, a molding compound 16 201025532 body 160 is formed on the upper surface π 〇 A of the substrate no and covers the wafers 120, 130, 48 0, 490 and The steps 111, 415, 416. As can be seen from the above, the stacked package structure 400 can stack more wafers to increase the telecommunication function or expand the memory capacity, and the substrate can be obtained in the step-type flip-chip stack regardless of the number of stacks. Good adhesion and support with the stacked wafers, and easy control of the level of its flip chip stack. In accordance with a fifth embodiment of the present invention, another stacked package structure 500 of a single-sided pad wafer is illustrated in a cross-sectional view of FIG. The main components included in the stacked package structure 500 are substantially the same as those of the substrate 110, the first wafer 120, and the second wafer 130 of the first embodiment. Therefore, the components of the first embodiment are labeled or may be omitted. The substrate 110 has an upper surface 110A and a first step U1 disposed on the upper surface 110A. The first wafer ι2 is flip-chip bonded to the upper surface 110A of the substrate 110. The second wafer 13 is flip-chip bonded to the first step m of the substrate 110 and partially overlaps the first wafer 12A. In this embodiment, the stacked package structure 500 can further stack a third wafer 581 and a fourth wafer 582. The third wafer 581 and the fourth wafer 582 are respectively flip-chip bonded to the second step 518 and the third step 519 of the substrate 丨1. Referring to Fig. 8, in the embodiment, the substrate 11A may further have an extension plate portion 517. The extension plate portion 517 is connected to the first step 111, and the first step U1 is obliquely extended so that the extension plate portion 517 does not overlap the upper surface u〇A of the substrate 11A. In the embodiment of the present invention, the extension plate portion 517 and the first step 1U are respectively provided with a plurality of extension pads 512E for the flip chip bonding of the plurality of stepped stacked wafers 590. Each of the stepped stacked wafers 59 has a plurality of single-sided pads 59i, and a plurality of bumps 592 are disposed on the single-sided pads 591 for bonding to the extension pads 512E. The stepped stacked wafers 590 can be substantially the same as the first wafers 12 and the second wafers 130, and the stacked stacked wafers 59 can be stacked in the same manner as the second wafers 130. The number of the stepped stacked wafers 590 is four wafers in a specific structure, which is the same as the number of wafers stacked on the other side zen-shaped flip chip. Referring to FIG. 8, a molding compound 16 is formed on the upper surface 110A of the substrate 110 and covers the steps 1U, 518 and 519, but the extension plate portion 517 is partially exposed, wherein the molding is performed. The body 160 seals the wafers 120, 130, 581 and 582. In this embodiment, the stacked package structure 500 may further include a molding compound 561 formed under the first step 111 and covering the extension plate portion 517 to seal the stepped stacked wafer 590. The encapsulant 561 exposes the lower surface 110B of the substrate 110. In addition, the molding compound 561 and the molding compound 160 may be formed simultaneously so that the process of the stacked package structure 500 is not increased. Referring to FIG. 8, a plurality of recording balls 170 are disposed on the lower surface 110B of the substrate 110. In this embodiment, the stacked package structure 500 may further include a plurality of solder balls 571 disposed on the upper surface of the extension plate portion 517 for stacking and bonding another stacked package structure 500 (as shown in FIG. 9). ). Referring to FIG. 9, the solder balls 17 of the upper stacked package structure 500 are soldered to the other solder balls 571 of the lower package structure 500 by the soldering technique of 18 201025532. Through the design of the substrate 110 described above, the space under the substrate 110 can be fully utilized to increase the number of packaged wafers, and a structure in which eight or more wafers are stacked can be performed. Alternatively, the solder balls 17 〇 and 571 can be stacked to another stacked package structure 500 to form a packaged on package (POP) package. According to the sixth embodiment of the present invention, another single The stacked package structure of the side pad wafer is illustrated in a cross-sectional view in FIG. The main components included in the stacked package structure 600 are substantially the same as those of the substrate 110, the first wafer 120, and the second wafer 130 of the first embodiment, and are therefore partially designated by the same component symbols in the first embodiment. Description. The substrate 110 has an upper surface n〇A and a first step 111. In the present embodiment, the substrate 11 () may be a metal wire guide. The first step 111 is formed by bending a plurality of pins of the lead frame. The first wafer 120 and the second wafer 13 are respectively flip-chip bonded to the upper surface 11A of the substrate 110 and the first step 111, wherein the second wafer 130 partially overlaps the first wafer 120. A third wafer 681 and a fourth wafer 682' are stacked on the second wafer 130, and the third wafer 681 and the fourth wafer 682 are stacked in a stepped manner. Referring to FIG. 10, the first step m of the substrate 110 may be obliquely extended and form an extension plate portion 617, wherein the extension plate portion 617 and the upper surface of the substrate 110 are not overlapping. In the embodiment 19 201025532, the extension plate portion 617 of the substrate 110 may be provided with a plurality of stepped stacked wafers 690. The stacked package structure 600 includes a molding compound 661 that seals the wafers 120, 130, 681, and 682, and another molding compound 661 that seals the stepped stacked wafers 69. Specifically, the molding compound 661 and the molding compound 16 can be integrally formed. Preferably, the pins extend beyond the molding pastes 16A and 661 to form a plurality of extension pins 61〇D for external bonding.

至一外部印刷電路板（圖中未繪出）或堆疊至另一堆疊封 裝構造600(如第11圖所示）。請參閱第u圖所示，利用 焊料671接合上方堆疊封裝構造6〇〇之該些延伸引腳 61〇D之端部至另一下方堆曼封裝構造600之延伸引腳 61〇D之肩部，以形成堆叠式封裝構造。由上述可知，該 堆養封裝構造600係可應用㈣小外形封裝(Ts〇p，Thin Small 〇utline Package)的立體堆疊。 所述僅疋本發明的較佳實施例而已，並非對本 發明作任何形式上的限制 ^ 制’雖然本發明已以較佳實施例 揭露如上，然而並非用 _ . U限定本發明，任何熟悉本項技 術者，在不脫離本發明之妊…# ^ <技術範圍内，所作的任何簡單 修改、等效性變化與佟 同干 内〇 >鄉’均仍屬於本發明的技術範圍 【圖式簡單說明】 之第一具體實施例的一種單側銲 封裝構造之截面示意圖與局部放 第1圖·為依據本發明 塾晶片之堆叠 大圖。 20 201025532 第2圖.為依據本發明之第一具體實施例的單侧銲塾晶 .片之堆疊封裝構造中一基板之立體示意圖。 第3圖^依據本發明之第一具體實施例的單侧 片之堆疊封裝構造中一晶片之立體示意圖。 第4圖：為依據本發明之第-具體實施例的單侧銲墊晶 片之堆疊封裝構造之基板下表面示意圖。 第5圖.為依據本發明之第二具體實施例的另一種單側 鲜塾曰曰片之堆疊封裝構造之截面示意圖。 第6圖據本發明之第三具體實施例的另一種單側 知塾晶片之 疊封裝構ie之截面示意圖。 第7圖：為依據本發明夕馇_曰成威 鍟… 第具體實施例的另-種單侧 曰曰片之堆疊封裝構造之截面示意圖。 第8圖.為依據本發明之篦 帛五具體實施例的另-種單側 •晶片之堆疊封裝構造之截面示意圖。 第9圖.為依據本發明之第五具體實施例的單側銲墊晶 之堆疊封裝構造堆疊呈另 堆疊封裝構造之截面示意圖。 晶片之 第1〇圖=本發明之第六具艘實施例的另-種單侧 銲墊曰曰片之堆疊封裝構造之截面示意圖。 第11圖，依據本發明之第六具體實施例的單側銲墊晶 之堆疊封裝構造堆疊I另-單側銲墊晶片之 ㈣封裝構造之截面示意圖。 片之 【主要元件符號說明】 1〇〇堆疊封裝構造 21 201025532To an external printed circuit board (not shown) or stacked to another stacked package construction 600 (as shown in Figure 11). Referring to FIG. u, the ends of the extension pins 61〇D of the upper stacked package structure 6 are bonded by solder 671 to the shoulders of the extension pins 61〇D of the other lower stack package structure 600. To form a stacked package configuration. As can be seen from the above, the stacking and packaging structure 600 is applicable to a three-dimensional stack of (T) 外形 小 line 。 。 。 。 。 。 。 。. The present invention has been described with respect to the preferred embodiments of the present invention. The present invention has been described in terms of the preferred embodiments. The technical person, without departing from the invention of the present invention, #^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ BRIEF DESCRIPTION OF THE DRAWINGS A cross-sectional view and a partial plan view of a single-sided solder package structure of a first embodiment are a larger view of a stack of germanium wafers in accordance with the present invention. 20 201025532 FIG. 2 is a perspective view of a substrate in a stacked package structure according to a first embodiment of the present invention. Fig. 3 is a perspective view showing a wafer in a stacked package structure of a one-sided sheet according to a first embodiment of the present invention. Fig. 4 is a view showing the lower surface of the substrate in a stacked package structure of a single-sided pad wafer according to the first embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing another stacked package structure of a single-sided fresh enamel according to a second embodiment of the present invention. Figure 6 is a cross-sectional view showing another stack of one-sided semiconductor wafers according to a third embodiment of the present invention. Fig. 7 is a cross-sectional view showing the stacked package structure of another single-sided cymbal according to the present invention in accordance with the present invention. Fig. 8 is a schematic cross-sectional view showing a stacked package structure of another one-side wafer according to a fifth embodiment of the present invention. Fig. 9 is a schematic cross-sectional view showing a stacked package structure of a single-sided pad crystal according to a fifth embodiment of the present invention in a stacked package structure. Fig. 1 is a cross-sectional view showing a stacked package structure of another one-side pad pad of the sixth embodiment of the present invention. 11 is a cross-sectional view showing a package structure of a stack of a single-sided pad wafer according to a sixth embodiment of the present invention. [The main component symbol description] 1〇〇 stacked package structure 21 201025532

110 基板 110A 上表面 110Β 下表面 111 第一 階梯 112A 第- -接塾 112Β 第二接墊 113 鑛通 孔 114 外接墊 120 第一 晶片 121 第一單侧輝塾 130 第二 晶片 131 第二單側銲墊 140 黏晶 層 151 第一 黏著層 151Α 間隙維持件 160 模封 膠體 170 銲球 200 堆疊 封裝構造 240 黏晶 層 251 第一 黏著層 251Α 間隙維持件 300 堆疊 封裝構造 340 黏晶 層 351 第一 黏著層 352 第二黏著層 400 堆疊 封裝構造 412C :第. 二接塾 412D 1第四接墊 415 第二 階梯 416 第三階梯 440 黏晶 層 451 第一 黏著層 452 第二黏著層 480 第三 总 μ 曰曰片 481 第三單側鮮墊 490 第四 晶片 491 第四單側銲墊 500 堆疊 封裝構造 110C 侧邊 122第一凸塊 132第二凸塊 151B黏著材料 251B黏著材料 453第三黏著層 482第三凸塊 492第四凸塊 22 201025532 512E延伸接墊 517延伸板部 518第二階梯 519第三階梯 561模封膠體 571銲球 581第三晶片 582第四晶片 590階梯狀堆疊晶片 591 單側銲墊 591凸塊 600堆疊封裝構造 610D延伸引腳 617延伸板部 ® 661模封膠體 671焊料 681第三晶片 682第四晶片 690階梯狀堆疊晶片 H1 第一階梯突出於上表面之高度 H2 第一凸塊之高度 T 第一晶片之厚度 ❿ 23110 substrate 110A upper surface 110 Β lower surface 111 first step 112A first - interface 112 Β second pad 113 mine through hole 114 external pad 120 first wafer 121 first single side 塾 130 second wafer 131 second unilateral Pad 140 Bonded Layer 151 First Adhesive Layer 151 间隙 Gap Holder 160 Mold Seal 170 Solder Ball 200 Stack Package Structure 240 Bond Layer 251 First Adhesion Layer 251 间隙 Gap Holder 300 Stack Package Structure 340 Mold Layer 351 First Adhesive layer 352 second adhesive layer 400 stacked package structure 412C: second interface 412D 1 fourth pad 415 second step 416 third step 440 adhesive layer 451 first adhesive layer 452 second adhesive layer 480 third total μ 曰曰 481 third single side fresh pad 490 fourth wafer 491 fourth single side pad 500 stacked package structure 110C side 122 first bump 132 second bump 151B adhesive material 251B adhesive material 453 third adhesive layer 482 third bump 492 fourth bump 22 201025532 512E extension pad 517 extension plate portion 518 second step 519 third step 561 mold seal 57 1 solder ball 581 third wafer 582 fourth wafer 590 stepped stacked wafer 591 single side pad 591 bump 600 stacked package structure 610D extension pin 617 extension plate portion 661 molding compound 671 solder 681 third wafer 682 fourth The wafer 690 is stepped and stacked on the wafer H1. The first step protrudes from the height H2 of the upper surface. The height of the first bump T. The thickness of the first wafer ❿ 23

Claims (1)

201025532 七、申請專利範圍： 1、 一種單側銲墊晶片之堆疊封裝構造，包含： 一基板，係具有一上表面以及一設於該上表面之一 侧邊上之第一階梯，該基板係包含複數個第一接 墊與複數個第二接墊，該些第一接墊係位於該上 表面且鄰近於該第一階梯，該些第二接墊係位於 該第一階梯上； 一第一晶片，係覆晶接合該基板之該上表面，該第 一晶片係具有複數個第一單側輝塾，在該些第一 單側銲墊上設有複數個第一凸塊，該些第一凸塊 係接合至該些第一接墊；以及 一第二晶片，係覆晶接合該基板之該第一階梯並與 該第一晶片部分重疊，該第二晶片係具有複數個 第二單側銲墊，在該些第二單側銲墊上設有複數 個第二凸塊，該些第二凸塊係接合至該些第二接 ❿ 塾。 2、 根據申請專利範圍第1項之單側銲墊晶片之堆養封 裝構造，另包含有一第-黏著層，係形成於該第一 晶片與該第二晶片之間。 3、 根據申請專利範圍第2項之單側銲墊晶片之堆叠封 裝構造’其中該第-黏著層係為包含複數個間隙維 持件（stand off)與一黏著材料。 4、 根據申請專利範圍第3項之單侧銲墊晶片之堆疊封 裝構造’其中該些間隙維持件係為球狀物。 24 201025532 5、 根據申請專利範圍第3項之單側銲墊晶片之堆疊封 裝構造’其中該些間隙維持件係為複數個膠帶。 6、 根據申請專利範圍第5項之單側銲墊晶片之堆疊封 裝構造’其中在該些膠帶之間留有被該黏著材料填 滿的間隙。 7、 根據申請專利範圍第3項之單側銲墊晶片之堆疊封 裝構造’其中該黏著材料係選自於底部填充膠與模 封膠體之其中之一。 A 8、 根據申請專利範圍第1項之單側銲墊晶片之堆疊封 裝構造，其中該第一階梯係為條狀而僅形成於該基 板之該上表面之單一側邊，以使該基板不具有中央 凹穴。 9、 根據申請專利範圍第1項之單側銲墊晶片之堆疊封 裳構造，其中該第一階梯突出於該上表面之高度係 不小於該第一晶片之厚度與該第一凸塊之高度之 φ 總合》 1 〇、根據申請專利範圍第1項之單側銲墊晶片之堆疊 封裝構造’另包含有一模封膠體’係形成於該基板 之該上表面並覆蓋該第一晶片、該第二晶片與該第 一階梯。 11、 根據申請專利範圍第1項之單侧銲墊晶片之堆叠封 裝構造’其中該第一晶片與該第二晶片係為實質相 同之記憶體晶片。 12、 根據申請專利範圍第1項之單侧銲墊晶片之堆疊 25 201025532 封裝構造，其中該基板係更具有一設於該第一階梯 上之第二階梯，該堆疊封裝構造另包含有一第三晶 片，係覆晶接合該基板之該第二階梯並與該第二晶 片部分重疊。 13、 根據申請專利範圍第丨項之單側銲墊晶片之堆叠 封裝構造，其中該基板係為一印刷電路板並包含 複數個設置於該第一階梯中之鍍通孔以及複數個 在該基板之一下表面之外接墊。 14、 根據申請專利範圍第13項之單侧銲墊晶片之堆疊 封裝構造，另包含複數個銲球’係接合於該些外接 墊。 15、 根據申請專利範圍第10項之單侧銲墊晶片之堆疊 封裝構造，其中該基板係為一金屬導線架，該第一 階梯係由該導線架之複數個引腳彎折形成，該些引 腳更延伸到該模封膠體之外。 16、 根據申請專利範圍第！項之單側銲墊晶片之堆疊 封裝構造，其中該基板另具有一延伸板部，連接至 該第一階梯，並且該第一階梯係為斜向延伸，以使 該延伸板部與該基板之該上表面不重疊，另在該延 伸板部與第一階梯之下方各設有複數個延^接 墊’以供複數個階梯狀堆疊晶片之覆晶接合。 26201025532 VII. Patent application scope: 1. A stacked package structure of a single-sided pad wafer, comprising: a substrate having an upper surface and a first step disposed on a side of the upper surface, the substrate system a plurality of first pads and a plurality of second pads, the first pads are located on the upper surface and adjacent to the first step, and the second pads are located on the first step; a first wafer system having a plurality of first one-side ridges, and a plurality of first bumps on the first one-side pads, a bump is bonded to the first pads; and a second wafer is bonded to the first step of the substrate and partially overlaps the first wafer, the second wafer has a plurality of second orders The side pads are provided with a plurality of second bumps on the second one-side pads, and the second bumps are bonded to the second ports. 2. The stacking structure of a single-sided pad wafer according to claim 1 of the patent application, further comprising a first-adhesive layer formed between the first wafer and the second wafer. 3. The stacked package structure of a single-sided pad wafer according to claim 2, wherein the first-adhesive layer comprises a plurality of gap-off and an adhesive material. 4. A stacked package structure of a single-sided pad wafer according to item 3 of the scope of the patent application, wherein the gap maintaining members are balls. 24 201025532 5. The stacked package structure of a single-sided pad wafer according to item 3 of the patent application scope, wherein the gap maintaining members are a plurality of tapes. 6. A stacked package structure of a single-sided pad wafer according to item 5 of the patent application scope, wherein a gap filled by the adhesive material is left between the tapes. 7. The stacked package structure of a single-sided pad wafer according to item 3 of the patent application, wherein the adhesive material is selected from one of an underfill and a molding gel. A. The stacked package structure of the single-sided pad wafer according to claim 1, wherein the first step is strip-shaped and formed only on a single side of the upper surface of the substrate, so that the substrate is not Has a central pocket. 9. The stacked package structure of a single-sided pad wafer according to claim 1, wherein the height of the first step protruding from the upper surface is not less than a thickness of the first wafer and a height of the first bump. φ 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 根据 根据 根据 根据 根据 根据 根据 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The second wafer and the first step. 11. The stacked package structure of a single-sided pad wafer according to the first aspect of the patent application, wherein the first wafer and the second wafer are substantially the same memory wafer. 12. The stacking structure of a single-sided pad wafer according to claim 1, wherein the substrate has a second step disposed on the first step, the stacked package structure further comprising a third The wafer is flip-chip bonded to the second step of the substrate and partially overlaps the second wafer. 13. The stacked package structure of a single-sided pad wafer according to claim </ RTI> wherein the substrate is a printed circuit board and includes a plurality of plated through holes disposed in the first step and a plurality of substrates One of the outer surfaces of the lower surface. 14. The stacked package structure of a single-sided pad wafer according to claim 13 of the patent application, further comprising a plurality of solder balls attached to the external pads. 15. The stacked package structure of a single-sided pad wafer according to claim 10, wherein the substrate is a metal lead frame, and the first step is formed by bending a plurality of pins of the lead frame. The pins extend beyond the molding compound. 16, according to the scope of the patent application! The stacked package structure of the single-sided pad wafer, wherein the substrate further has an extension plate portion connected to the first step, and the first step is obliquely extended to make the extension plate portion and the substrate The upper surface does not overlap, and a plurality of extension pads are disposed under the extension plate portion and the first step for flip chip bonding of the plurality of stepped stacked wafers. 26
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TWI641103B (en) * 2016-12-15 2018-11-11 力成科技股份有限公司 Semiconductor device with stacking chips and manufacture method thereof
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