TW484221B - A dual chip package and the wafer level packaging method - Google Patents

Abstract

A dual chip package and the wafer level packaging method for the same are disclosed. The dual chip package includes a first chip, a second chip and the least an electrically connecting device. The first chip has an active surface orienting toward the active surface of the second chip. The electrically connecting device connects the first bonding pad on the active surface of the first chip and the corresponding second bonding pad on the active surface of the second chip and has an exposing surface end vertical with the active surface of the first chip or/and the second chip. So the dual chip package possesses the benefits of lateral surface mounting, chip size package, and wafer level packaging.

Description

484221 V. Description of the invention d) [Field of the invention] The present invention relates to a dual-chip structure and a wafer-level packaging method thereof. In particular, the present invention relates to a dual-chip structure that can be laterally bonded and has a chip size package. body. [Previous technology] The so-called "chip size package structure" [Chip Size Package, CSP] refers to the size of a chip in a package structure with a package size equal to or slightly smaller or larger than 1.2 times, so that the chip size package structure has Design and application of small surface bonding area and miniaturization. In addition, the current general packaging structure has an upper surface, a lower surface, and smaller four sides. When the lower surface is used as the surface bonding [sur face mount i ng] Only the upper surface is used as a heat dissipation surface, making it difficult to dissipate heat. US Patent No. 5,493, 151 "Semiconductor Device, Lead Frame and Manufacturing Method" discloses a packaging structure that can be laterally bonded. As shown in Figure ^, the packaging structure 60 is made by half The etched lead frame carries and electrically connects the wafer 61. The lead frame has a crystal sticking box which is used to fix the wafer 2 'and a plurality of inner and outer fingers 63 and 64. The inner finger 63 should be the outer lead. Finger 64 is formed in a body and is formed by etching to form a height difference, so that the inner finger 63 and the finger 64 are bonded. When the wafer 61 is fixed to the die attach portion 66,

62 Internally electrically connects the chip 61 to the inner lead, and then seals the chip 61 with-seal = a U [encapsulant] and ^ the exposed surface of the face 6 5 You yan from the naked heart out of the bow 丨 the heart 64 on the side surface Tian 65 As an external termination point, this package has a high density and is laterally bonded to a printed circuit board 50 (as shown in Figure 2), which can be sliced to a plurality of packaging structures with a density of 60 °. heart. To a printed circuit board 50

λζΗ First page 3 of 484221 V. Description of the invention (2) Two large-area scattered wafers are completed with a lead frame as a low-cost, low-cost package. [The purpose of the invention and the two wafers of the present invention are face-to-face connections The device is provided with a wafer structure. According to the present invention, the film has a first first pad and a first back, and the first wafer is in the first direction; the hot surface, but the circuit is parallel to the carrier, and the letter cannot be summarized. The wafer has a side table and this chip packaging structure 60 must be cut into a plurality of individual wafers before it can be individually packaged without the wafer. The package only contains-wafers, and it is not available for wafer level. Packaging method manufacturing. The purpose is to provide a dual-chip structure that is connected by a pen-type connection device and the electrical front surface is a vertical surface contact, so that the double-chip structure with double-sided bonding, chip size packaging and wafer-level sealing, It mainly includes: a first surface, which has a plurality of two wafers on the front surface of the first wafer; a second wafer, which has a front surface and a plurality of second solder pads on the front surface, and which faces the electrical connection device to electrically connect the first solder Pads, surface contacts with bare paths, where the watch face is on the front side of the second wafer. The surface and the back surface B are facing the second chip and at least one of the contacts is perpendicular to the [Detailed Description of the Invention] As shown in Figs. 3 and 4, one of the two-chip structure rectangular blocks is listed, which includes The layer 14 and a plurality of electrically connected surfaces exposed on the sides are said to be in the shape of a square plate according to the first embodiment of the present invention, preferably a square plate—a chip 11— Two wafers 12, — if ;, 3 'Among which are 13 electrical connection devices 131, in which the surface contacts 131 are fish 484221 V. Description of the invention (3) One wafer 11 is perpendicular to the front sides ill, 121 of the second wafer 12 And formed on one side of the dual-chip structure body 10 for side surface bonding [1 atera 1 surface mounting], the details of its components are as follows: As shown in FIG. 4, the first wafer 1 1 series has a The front side 111 and a back side 1 1 2 'The front side 1 11 faces the second wafer 12 and is formed with an integrated circuit element [integrated circuit element] and a plurality of first bonding pads 113 [bonding pad], the first bonding pad 113 Generally made of copper or aluminum M, in this embodiment, the first Chip 11 is a memory chip or other chip, such as DRAM, SDRM, SRAM, flasll, ROM, EPROM, Rambus DRAM, or DDR memory. The DR AM memory chip 0 with the number of external termination points in the range of 2 8 to 8 0 is preferred. As shown in FIG. 4, the second chip 12 also has one... Only by i Z i And January = 122, the front surface 121 faces the first wafer u and is formed with a plurality of second bonding pads, 123 [bonding pads]. In this embodiment, the second wafer 12 may be the same as the first wafer 11 and may be one. Memory chip, but the electrical function of the second pad 123 of the second chip i 2 is not necessarily the same as that of the first chip n. The electrical connection device 13 is used to electrically connect the first of the first chip 丨 丨塾 113 and the second solder pad 123 corresponding to the second wafer 12 have an exposed surface contact 131, wherein the surface contact 131 is perpendicular to the front faces m, 121 of the first wafer u and the third wafer 12, For lateral surface bonding, preferably, the surface contacts of the plurality of electrical connection devices 3 are formed on the side of one of the pairs: In this embodiment +, the plurality of electrical jumpsuits 13 are bumps or are taken from a lead frame 484221 V. Description of the invention (4) The plurality of lead fingers [lead] are To increase the bonding strength and strengthen the protection, an insulating sealant layer 14 'such as an epoxy compound, etc.' is formed between the first wafer 11 and the second wafer 2 but the above-mentioned electrical connection device 13 must still be exposed. Surface contacts 1 3 1. Therefore, as shown in FIG. 5, the above-mentioned dual-chip structure 10 can be densely bonded to a plurality of lateral surfaces on a printed circuit board 50, and the printed circuit board 50 has solder 31 [solder paste] on it, so that Electrically connect the surface contacts 131 of the dual-chip structure 10 to the printed circuit board 50 and securely couple the dual-chip structure 10 with a bottom pad 32 [underfill]. The dual-chip structure 10 has The two surfaces of a larger area [that is, the back surface of the first wafer n and the back surface 12 of the first wafer 12 are two-sided heat dissipation walls, so the heat dissipation is good. At the same time, one of the surface areas of the dual-chip structure 10 is It is close to the maximum surface area of the first wafer worker or the second wafer 12, and becomes a dual-chip wafer ruler packaging structure, so it has the effect of small-size packaging. , Gu = Figure 6 does not show, it is the dual wafer structure 10 of the present invention, the first one hundred "provide a wafer" [wafer] 41, the wafer is integrated into one: several first wafer U 'then "provide another circle" 42. The circle is integrally formed with a plurality of second wafers 12, and the 43 is so that the front side of the first wafer U faces backward. ",; ® ", and set 13 on the front side of the 11th plate of the third day of the 19th day of the wafer / 12 of the first day of the 12th day, and electrically connect the 3rd = to make the above electrical connection. 44 ϊ⑴ and the corresponding second welding 塾 m, the most 10, so that the electrical connection device 13 has at least one exposed body 131, so the surface contact of the Μ Μ μ μ ^ in the present invention is more and more The chip structure 1 is also available for wafer level packaging

Page 8 484221 V. Description of the invention (5) [wafer level package] The effect of reducing costs. In addition, as shown in FIGS. 7 and 8, it is another dual-wafer structure 20 according to the second embodiment of the present invention, and is intended to explain that the dual-wafer structure of the present invention is not limited to the two-wafer structure. The shape, the distribution of the first or second pads of the component, and the type of the electrical connection device, as shown in FIG. 7, the dual-chip structure 20 is triangular plate-shaped and has a plurality of The surface contact 2 3 1 on the side, as shown in FIG. 8, the dual-wafer structure 20 mainly includes a first wafer 21, a second wafer 22, and a circuit substrate 23, which is based on the circuit substrate 23. As the electrical connection device of the present invention, the front surface 211 of the first chip 21 and the front surface 221 of the second chip 22 are fixed by the adhesive 24, and the circuit board 23 can be a multi-layer circuit board with proper conduction. A hole 232 [via hole], a circuit line 2 33 and a surface contact 231, the first welding pad 213 of the front surface 211 of the first wafer 21 and the corresponding one are soldered 234], and the second welding pad 2 of the front surface 221 of the wafer 22 2 3 leads and transfers to point 231 of the opposite face for lateral surface bonding, said surface connection ^ f / / Ί

It also has a wafer size and a wafer structure that can be used for wafer-level sealing. Therefore, the scope of protection of the present invention shall be subject to the attached patent application. 'Anyone who is familiar with this technology I, Any changes and modifications made within the scope belong to the present invention and

484221 Brief Description of Drawings [Illustration of Drawings] Figure 1: Sectional view of the packaging structure of US Patent No. 5,4 9 3, 1 51 "Semiconductor Device, Lead Frame and Manufacturing Method"; Figure 2: US Patent No. 5, 4 9 3, 1 5 1 "Semiconductor device, lead frame and manufacturing method thereof" a schematic diagram of the side structure of the packaging structure is bonded to the printed circuit board; Figure 3: According to the first embodiment of the present invention, dual-chip A perspective view of the structure; FIG. 4: A cross-sectional view of a dual-wafer structure according to the first embodiment of the present invention, and FIG. 5: A plurality of dual-wafer structures are combined according to the first embodiment of the present invention Figure 6 is a schematic diagram of a printed circuit board; Figure 6: A flowchart of manufacturing the dual-chip structure in a wafer-level package according to the first embodiment of the present invention; Figure 7: A second embodiment according to the present invention Example, a perspective view of a dual-wafer structure; and FIG. 8: a sectional view of a dual-wafer structure according to a second embodiment of the present invention. [Illustration of the drawing number] 10 Double wafer structure 11 First wafer 111 Front face 112 Back face 113 First-pad 12 Second wafer 121 Front face 122 Back face 123 Second pad

484221 Brief description of the drawings 13 Electrical connection device 131 Surface contacts 14 Sealing body 20 Double-chip structure 21 First wafer 211 Front face 212 Back face 213 First pad 22 Second wafer 221 Front face 222 Back face 223 Second welding pad 23 Circuit board 231 Surface contact 232 Via hole 233 Circuit wire 234 Solder 24 Adhesive 31 Solder 32 Underlay 41 Provide one wafer 42 Provide another wafer 43 Combine two crystals 44 Cut dual wafer structure 50 Printed circuit board 60 Package structure 61 Wafer 62 Welding wire 63 Inner finger 64 Outer finger 65 Exposed surface 66 Sticky crystal part 67 Sealant

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Claims (1)

484221 VI. Scope of patent application [Patent for patent application 1, a double crystal enclosure] A sheet structure including: a first wafer having a front surface and a back surface, and a front surface of the first wafer having a first to a plurality of two The wafer has a plurality of first solder pads and the front side faces the second wafer; and has a front surface and a back surface, the second solder pads on the front side of the second wafer and the front side faces the first wafer; and one electrical connection device for electrical connection The first pad and the corresponding second pad have an exposed surface contact, wherein the surface contact is the front side of the second wafer. The dual wafer structure described in item 1 further includes the dual wafer structure described in item 1 in which the surface contacts of the multiplexing device are formed on the dual wafer structure perpendicular to the first wafer structure. A chip and a profit range, such as containing one, such as one of several, such as one crystal, such as the best of twin crystals, such as electrical, such as electrical, such as applying for a special sealant colloid, applying for exclusive electrical connection to the side. Apply for the special film and the first application for the construction of the large surface. Apply for the connection device. Apply for the connection connection. Apply for the dual-chip structure described in item 3 of the patent scope. The second chip is a memory chip. The dual-wafer structure according to the first item of the invention, wherein the surface area of one of the bodies is close to the area of the first wafer or the second wafer. The profit range is set as a bump. The two-chip structure according to the first item, wherein the two-chip structure according to the first item, wherein the lead frame has a plurality of lead fingers. The dual wafer structure according to item 1, wherein the Page 12 Scope of the patent application for electrical appliances 5 、 If the patent application scope = circuit board. The wafer structure system is a dual-wafer structure as described in item 1, wherein the double 10, as in the application for patent two ;: square plate. The wafer structure system is a dual-wafer structure as described in item h, in which the double 11 and one 雔 a are triangular plate-shaped. A wafer-level encapsulation method for a wafer structure, wherein the front surface of the twin-crystal wafer has J :: It has a front surface and a back surface. On the first and second wafers, several first pads are destroyed and The front side faces the second crystal. There is a front side and a back side, there are a plurality of second pinches on the positive side of the second wafer, > V — W π ~ electrical connection device, the front side of the Γ f pad faces the first wafer; The first and second pads are connected to each other, and the first pad and the corresponding second pad are connected, and the steps are as follows: providing another wafer body; a plurality of first wafers; Combining two wafers, forming a plurality of second wafers on the limb of the Γ ^^;%: 'and forming at least-electrical connection between the first wafer and the second wafer by electrically connecting the first wafer to the first wafer. Cut the dual wafer, the miscellaneous pad and the corresponding second solder pad; < The electrical connection is mounted as a plurality of dual wafer structures, and there are at least one exposed surface contact, such as from 4 to 4 animals. Upgrade package side \ Special two = or circuit board. The electrical connection device is selected from the lead frame, and is convex 1 piece