TW200522284A - A carrier for stacked chips and a method for fabricating the same and a semiconductor package with the chip carrier - Google Patents
A carrier for stacked chips and a method for fabricating the same and a semiconductor package with the chip carrier Download PDFInfo
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- TW200522284A TW200522284A TW092137574A TW92137574A TW200522284A TW 200522284 A TW200522284 A TW 200522284A TW 092137574 A TW092137574 A TW 092137574A TW 92137574 A TW92137574 A TW 92137574A TW 200522284 A TW200522284 A TW 200522284A
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- substrate
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- wafer carrier
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 158
- 229910000679 solder Inorganic materials 0.000 claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 230000003292 diminished effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 70
- 235000012431 wafers Nutrition 0.000 description 57
- 238000010586 diagram Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000008393 encapsulating agent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical group [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012050 conventional carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- QUQFTIVBFKLPCL-UHFFFAOYSA-L copper;2-amino-3-[(2-amino-2-carboxylatoethyl)disulfanyl]propanoate Chemical compound [Cu+2].[O-]C(=O)C(N)CSSCC(N)C([O-])=O QUQFTIVBFKLPCL-UHFFFAOYSA-L 0.000 description 1
- 239000002274 desiccant Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011120 plywood Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
200522284 _五、，發明說明（l) :【發明所屬之技術領域】 ’ 一種晶片承載件（Chip Carr ie〇 ，尤指一種在壓合 式基板至少一側上疊接一增層基板，以縮減銲球墊間距 (Finger Pitch)而於相同基板單位面積下設置更多數量 的輸入/輸出連接端之晶片承載件，及具有該晶片承載件 之半導體封裝件。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 —能、高性能的研發方向，為滿足半導體封裝件高積集度 (^ntegration)以及微型化（Miniaturization)的封裝需 1求，提供多數主被動元件及線路載接之基板（b〇ard)亦逐 漸由雙層板演變成多層板，以在有限的空間下藉由層間連 接技術（I n t e r 1 a y e r C〇η n e c t i〇η )擴大基板上可利用的電 路面積’俾以配合向電子密度之積體電路（integrated C i rcu i t)的需求。 傳統的多層電路板種類，以目前來說計有壓合式電路 板（Laminated，board)及增層式電路板（Build-up board) 兩種’其中以壓合法製成之多層板如第8A圖及第8B圖所 示’係於絕緣基材兩面的銅结上各形成一内層線路層 1響11 ’俾以構成一核心基板1 〇 〇 ”，之後，在不同核心基板 1 0 0 "，1 0 0 a n，1 〇 〇 b "之間分別夾置一黏著層5 ’’，經過疊層 (Laminated)及熱壓（Heat Press)等步驟，將不同核心基 板1 0 0 n， 1 0 0 a "，1 0 0 b ’’上下壓合即形成一多層基板結構。 惟以壓合法製造多層基板時，在層數及孔數的製造上200522284 _V. Description of the invention (l): [Technical field to which the invention belongs] 'A chip carrier (Chip Carr ie, in particular, a laminated substrate is laminated on at least one side of a press-type substrate to reduce soldering. Ball pad pitch (Finger Pitch) and a chip carrier with a larger number of input / output terminals and a semiconductor package having the chip carrier under the same substrate unit area. [Previous Technology] With the prosperity of the electronics industry Development, electronic products have gradually entered the multi-functional, high-performance R & D direction. In order to meet the requirements of high-integration and miniaturization of semiconductor packages, most active and passive components and The circuit-mounted substrate (board) has gradually evolved from a double-layer board to a multi-layer board to expand the available space on the substrate by using the inter-layer connection technology (I nter 1 ayer C〇η necti〇η) in a limited space. The circuit area 'meets the needs of integrated circuit (integrated circuit) for electron density. Traditional multi-layer circuit board types are currently press-fit Laminated (board) and build-up board (multilayer boards made by pressing as shown in Figures 8A and 8B) are copper on both sides of the insulating substrate An inner circuit layer 1 and a ring 11 'are formed on the knots to form a core substrate 100, and then, between different core substrates 10 0 ", 10 0 an, 1 〇〇b " An adhesive layer 5 ″ is placed, and after laminating (Heat Press) and other steps, different core substrates 1 0 n, 1 0 0 a ", 1 0 0 b '' are laminated up and down. Form a multilayer substrate structure. However, when manufacturing a multilayer substrate by pressing, the number of layers and holes are manufactured.
17508碎品.ptd 第8頁 200522284 五、發明說明（2) 有明顯限制，同時，由於其圖案化製程中係以壓合銅箔經 曝光、微影、姓刻等減層方式（S u b s t r a c t i v e )所形成，使 其銲球塾寬度及相鄰銲球墊間距（F i n g e r P i t c h)因受製 程限制最小均只能縮小到5 0" m，既難以適用高密度電性 連接端（I / 0 C ο η n e c t i ◦ n s )之封裝產品，也無法作為多晶 片模組（Multiple Chip Module， MCM)或晶片規格封裝 (Chip Scale Package， CSP)等半導體封裝件之基板來 源。 再者，受到傳統蝕刻製程之限制，基板上每一個銲球 墊最小寬度約為5 0 v in，加上相鄰銲球墊間最短距離約為 5 0 // m，此表示每多設一個銲球墊至基板上即須佔據約1 〇 〇 V m寬的距離，若進一步將該等銲球墊圓形環列在晶片周 圍外，並以半導體晶片之幾何中心作為圓心時，如第9圖 所示，各銲球墊6 π距離圓心的半徑R為1 〇 〇 η / 2 7Γ // m (其中 η為鮮球塾數量），因此基板1π上如佈有2 0 0個焊球塾時， 党到相鄰鋅球墊間距5 0 // m及銲球塾寬5 0 " m共1 0 0 // m寬度 的限制，銲球墊6，，排列的圓周長約為1 0 0 ( // m) X ( 2 0 0 - 1 )’換算其圓周直徑相當於6mm ;顯示基板輸入/輸出連接 端（未圖示）矩量增加而導致銲球墊佈設量提高時，相對 地銲球墊形成的圓周區域也會擴大而增加基板及封裝件的 成品面積。 又增層電路板必須由内至外逐層堆疊方能完成，而其 黾錄製程極為精密與緩慢，因此在量產（M a s s Product ion)上極為耗時、複雜而且成本極高，售價約為17508 碎 品 .ptd Page 8 200522284 V. Description of the invention (2) There are obvious limitations. At the same time, the patterning process uses a laminated copper foil through exposure, lithography, surname engraving, etc. (Substractive) It is formed so that the width of the solder ball and the pitch of adjacent solder pads (Finger Pitch) can only be reduced to 5 0 " m due to the minimum process restrictions, which is difficult to apply to high-density electrical connection terminals (I / 0 C ο η necti ◦ ns) package products can not be used as the substrate source for semiconductor packages such as Multiple Chip Module (MCM) or Chip Scale Package (CSP). Furthermore, due to the limitation of the traditional etching process, the minimum width of each solder ball pad on the substrate is about 50 v in, plus the shortest distance between adjacent solder ball pads is about 50 0 // m, which means that each additional The solder ball pad must occupy a distance of about 1000V m to the substrate. If the circular ring of these solder ball pads is further arranged around the wafer, and the geometric center of the semiconductor wafer is used as the center, as in Section 9 As shown in the figure, the radius R of each solder ball pad 6 π from the center of the circle is 1 〇η / 2 7Γ // m (where η is the number of fresh balls), so there are 2 0 solder balls on the substrate 1π. When the distance between the party and the adjacent zinc ball pad is 5 0 // m and the width of the solder ball is 5 0 " m total 1 0 0 // m width limit, the solder ball pad 6, the circumferential length of the arrangement is about 1 0 0 (// m) X (2 0 0-1) 'equivalent to a circumference diameter of 6mm; when the input / output connection end (not shown) of the display substrate increases in torque and the amount of solder ball pads is increased, relatively The circumferential area formed by the solder ball pads will also expand and increase the finished product area of the substrate and package. The additional circuit board must be stacked layer by layer from the inside to the outside, and its recording process is extremely precise and slow, so it is extremely time-consuming, complicated, and costly in mass production. About
17508矽品.ptd 第9頁 200522284 4五 '發明說明（3) 此不利於大量生產與普及使 因 :一般壓合板的三至五倍 用’。 為這溥小封I及降低成本之 第5，8 7 0，2 8 9號，其係揭露一 、 果國專矛 一單面電路板9。的底面設有 以^ σσ 1將積體電路晶片9 2黏結於單面兩 板90的頂面’且該I面電路板9Q及黏膠片91上 电 穿孔9 0 2、911:於該穿孔他、9"内穿設有導電杈T3 該導電柱93底私電性連接在單面電路板9〇的電路％ ^亥導電93的頂端則電性連接積體電路晶片92底’ 墊9 2 1，即成為一單層之單元結構9。 、1 請芩閱第1 〇 B圖，刖述之單元結構9上的單面電路板9 得擴展成一大面積的基板9 0 a，且在該基板9 〇 a上得電性連 接複數個積體電路晶片9 2，而在積體電路晶片9 2上再套裝 一内殼94,並以膠體95進行封裝，且在基板9〇3之一側設~ 有一作為輸入/輸出的連接為96’即可完成一單層多個的 封裝結構。 請參閱第1 Μ圖，若要夕層封裝，則將單元結構9與絕 緣層97上下交錯疊裝在一多層電路板90匕上，再以長導電 -才#98穿過各個單元結構9的。單面電路板90及多層電路板 _ 9 0 b，使各個單元結構9的單面電路板9 〇電性連接在多層電 路板9 0 b的上方’接著在堃裝的單元結構9外面包覆一外殼 9 9，且該外殼9 9的底面結合在多層電路板9 〇 b的上方，以 將疊裝的單元結構9封裝在多層電路板9〇b上，然後再於多17508 silicon product.ptd page 9 200522284 4F 'Invention description (3) This is not conducive to mass production and popularization because: three to five times the use of general plywood'. For this small seal I and No. 5, 8 0, 2 8 9 to reduce costs, it is to expose a single-sided circuit board 9 and the country. The bottom surface is provided with ^ σσ 1 to bond the integrated circuit chip 9 2 to the top surface of the single-sided two boards 90 ′, and the I-side circuit board 9Q and the adhesive sheet 91 are electroporated 9 0 2, 911: In the perforated other , 9 " Inside is provided with a conductive branch T3. The bottom of the conductive pillar 93 is electrically connected to the circuit of the single-sided circuit board 90. ^ The top of the conductive 93 is electrically connected to the bottom of the integrated circuit chip 92. Pad 9 2 1 , Becomes a single-layer unit structure 9. 1. Please read the 10B diagram. The single-sided circuit board 9 on the unit structure 9 described above can be expanded into a large-area substrate 90a, and a plurality of electrical connections are electrically connected to the substrate 90a. The body circuit chip 92, and an inner shell 94 is set on the body circuit chip 92, and is encapsulated with a gel 95, and is provided on one side of the substrate 903 ~ there is an input / output connection of 96 ' You can complete a single-layer multiple packaging structure. Please refer to FIG. 1M. For layer encapsulation, the unit structure 9 and the insulating layer 97 are alternately stacked on a multi-layer circuit board 90, and then a long conductive-only # 98 passes through each unit structure 9 of. Single-sided circuit board 90 and multi-layer circuit board _ 9 0 b, so that the single-sided circuit board 9 of each unit structure 9 is electrically connected above the multi-layer circuit board 9 0 b ', and then is coated on the outside of the mounted unit structure 9 A casing 9 9, and the bottom surface of the casing 9 9 is combined above the multilayer circuit board 90 b to package the stacked unit structure 9 on the multilayer circuit board 90 b.
17508石夕品.ptd 第10頁 200522284 五、發明說明（4) 層電路板9 0 b底面連接作為輸出/輸入的銲球9 0 c，即成為 一多層封裝的結構。 而由於積體電路晶片9 2係藉由長導電柱9 8直接連接在 多層電路板9 0 b上，雖可降低封裝面積，但若要增加輸出/ 輸入接點的使用數目，則因單元結構9之單面電路板9 0所 能提供的接點有限，因此無法直接在單面電路板9 0上增加 接點，僅能藉由向外擴張電路基板的面積藉以增加接點的 數量，如此一來即無法減少面積以達薄小封裝之目的。 若僅能維持電路基板之面積，則無法增加輸出/輸入 接點的使用數目，如此一來即無法達到縮小體積、高密度 與多I / 0接點之封裝目的。 再者，該積體電路晶片9 2連接在多層電路板9 0 b後， 必須先經過一次封裝，之後的單層或多層封裝，則必須再 進行外形的第二次封裝，因而增加製造程序的複雜性，故 增加製造成本。 為此，如何改善封裝方式，使基板在容納大量銲球墊17508 Shi Xipin.ptd Page 10 200522284 V. Description of the invention (4) The bottom surface of the multilayer circuit board 90b is connected with the solder ball 90c as an output / input, which becomes a multilayer package structure. Since the integrated circuit chip 9 2 is directly connected to the multilayer circuit board 9 0 b through a long conductive post 9 8, although the packaging area can be reduced, if the number of output / input contacts is to be increased, the unit structure is The single-sided circuit board 9 of 9 can provide limited contacts, so it is not possible to directly add contacts on the single-sided circuit board 90. The number of contacts can only be increased by expanding the area of the circuit substrate outward. It is impossible to reduce the area to achieve the purpose of thin and small package. If only the area of the circuit board can be maintained, the number of output / input contacts cannot be increased, so that the packaging purpose of reducing the size, high density, and multiple I / 0 contacts cannot be achieved. Furthermore, after the integrated circuit chip 92 is connected to the multi-layer circuit board 90b, it must be packaged once, and then the single-layer or multi-layer package must be packaged for the second time, thus increasing the manufacturing process. Complexity, increasing manufacturing costs. For this reason, how to improve the packaging method so that the substrate can accommodate a large number of solder ball pads
17508石夕品.ptd 第11頁 200522284 '五、4發明說明（5) 湘鄰銲球墊間距至5 0/i m以下之堆疊式晶片承載件及其製 法，以及具有該堆疊式晶月承載件之半導體封裝件。 本發明之再一目的，係在提供一種僅須進行一次封裝 以降低製造成本之堆疊式晶片承載件之半導體封裝件。 為達成上述及其他目的，本發明係提供一種將增層式 基板（Build-up Substrate)及壓合式基板（Laminated Substrate)合而為一，並能進一步形成晶片朝上型或晶 片朝下型封裝結構，以減少封裝成品之整體尺寸之組合式 晶片承載件及其製法，以及具有該組合式晶片承載件之半 封裝件。 '其中，本發明之組合式晶片承載件係包括：一壓合式 基板（Laminated Substrate)，其包含至少一電路層及 一敷設於該電路層外之第一絕緣層，該第一絕緣層上係形 成複數個供該電路層外露之第一開口；至少一接置於該壓 合式基板上之增層式基板，該增層式基板具有複數層增層 線路層及一覆蓋在該增層線路層表面而與該壓合式基板第 一絕緣層相對之第二絕緣層，該第二絕緣層係形成有複數 個提供該增層線路層曝露之第二開口；以及複數個導電元 件，係形成於該第一開口及第二開口之間，俾接合該壓合 板電路層及該增層線路層而使該壓合式基板與該增層 _式基板之間電性連接。 而上述組合式晶片承載件之製法，則包括以下步驟： 預備一壓合式基板（Laminated Substrate)，該壓合式 基板包括有至少一電路層及一敷設於該電路層外之第一絕17508 Shi Xipin. Ptd Page 11 200522284 'Fifth, 4 Invention Description (5) Stacked wafer carrier with adjacent solder ball pad spacing below 50 / im and its manufacturing method, and the stacked wafer carrier with the same Semiconductor package. Yet another object of the present invention is to provide a semiconductor package of a stacked wafer carrier which only needs to be packaged once to reduce the manufacturing cost. To achieve the above and other objectives, the present invention provides a combination of a build-up substrate and a laminated substrate into one, and can further form a chip-up or chip-down package. Structure, combined wafer carrier for reducing the overall size of packaged finished product and manufacturing method thereof, and semi-packaged part having the combined wafer carrier. 'Wherein, the combined wafer carrier of the present invention includes: a laminated substrate (Laminated Substrate), which includes at least a circuit layer and a first insulation layer laid on the circuit layer, the first insulation layer is Forming a plurality of first openings for exposing the circuit layer; at least one build-up substrate connected to the press-type substrate, the build-up substrate having a plurality of build-up circuit layers and a cover-up circuit layer A second insulating layer on the surface opposite to the first insulating layer of the compression-molded substrate, the second insulating layer is formed with a plurality of second openings that provide exposure of the layered circuit layer; and a plurality of conductive elements are formed on the Between the first opening and the second opening, the pressure-bonded circuit layer and the build-up circuit layer are bonded to electrically connect the pressure-bonded substrate and the build-up substrate. The method for manufacturing the combined wafer carrier includes the following steps: preparing a laminated substrate (Laminated Substrate), the laminated substrate includes at least one circuit layer and a first insulation layer disposed outside the circuit layer
]7508石夕品.ptd 第12頁 200522284 五、發明說明（6) 緣層，該第一絕緣層上係形成複數個供該電路層外露之第 一開口；製備至少一與該壓合式基板接置之增層式基板， 該增層式基板具有複數層增層線路層及一覆蓋在該增層線 路層表面而與該壓合式基板第一絕緣層相對之第二絕緣 層，且該第二絕緣層係形成有複數個提供該增層線路層曝 露之第二開口；以及，設置複數個導電元件至該第一開口 及第二開口之間，俾接合該壓合式基板電路層及該增層線 路層而使該壓合式基板與該增層式基板之間電性連接。 另外，本發明亦包含以上述堆疊式晶片承載件載接晶 片之球柵陣列式半導體封裝件。該半導體封裝件係包括： 一組合式晶片承載件，其包含一壓合式基板，至少一增層 式基板及提供該壓合式基板與增層式基板接合並且電性連 接之複數個導電元件，其中，該增層式基板中央部係設有 一晶承載區；至少一半導體晶片，係接置於該組合式晶 片承載件之晶片承載區上，並與該堆疊式晶片承載件電性 導接；一封裝膠體，用以包覆該半導體晶片；以及複數個 銲球，係植接於該組合式晶片承載件上。 由於增層式基板之相鄰銲球墊間距及銲球墊寬在現有 製程上可以控制到2 0/z m，相較於壓合式基板5 0〆m的製程 極限，當基板上佈設相同數量之銲球墊並以圓形環繞於晶 片周圍時，若按照圓周等於（相鄰銲球墊間距（// m)+銲 球墊寬（V m))乘以（銲球墊數量-1)計算，排列銲球墊 所佔據的圓周直徑將可從原本的6mm縮減至2. 5mm而明顯降 低基板使用面積，以橫向縮減該基板及半導體封裝件的尺] 7508 石 夕 品 .ptd Page 12 200522284 V. Description of the invention (6) An edge layer, the first insulating layer is formed with a plurality of first openings for the circuit layer to be exposed; and at least one is connected to the press-type substrate The build-up substrate has a plurality of build-up circuit layers and a second insulation layer covering the surface of the build-up circuit layer and opposed to the first insulation layer of the laminated substrate, and the second insulation layer. The insulating layer is formed with a plurality of second openings that provide exposure of the layer-increased circuit layer; and a plurality of conductive elements are provided between the first opening and the second opening, and the compression-molded substrate circuit layer and the layer are joined together The circuit layer electrically connects the press-bonded substrate and the build-up substrate. In addition, the present invention also includes a ball grid array type semiconductor package in which a wafer is mounted on the stacked wafer carrier. The semiconductor package includes: a combined wafer carrier, which includes a laminated substrate, at least one build-up substrate, and a plurality of conductive elements for providing the laminated substrate and the build-up substrate to be electrically connected. A central substrate is provided with a crystal bearing region; at least one semiconductor wafer is connected to the wafer bearing region of the combined wafer carrier and is electrically connected to the stacked wafer carrier; The encapsulating gel is used for covering the semiconductor wafer; and a plurality of solder balls are implanted on the combined wafer carrier. Because the distance between the adjacent solder ball pads and the width of the solder ball pads of the build-up substrate can be controlled to 20 / zm in the existing process, compared with the process limit of 50 μm for the laminated substrate, when the same number of When the solder ball pad is circled around the wafer, if the circumference is equal to (the distance between adjacent solder ball pads (// m) + solder ball pad width (V m)) multiplied by (the number of solder ball pads -1) , The diameter of the circle occupied by the array of solder ball pads can be reduced from the original 6mm to 2.5mm, which significantly reduces the area of the substrate to laterally reduce the size of the substrate and the semiconductor package.
17508石夕品.ptd 第13頁 200522284 五、，發明說明（7) -·寸 〇 另一方面，本發明之組合式晶片承載件整合增層式基 板與壓合式基板’利用增層式基板在線路精密度上南出壓 合式基板，在有限的基板面積下佈設更多數量之銲球墊， 而壓合式基板在結構強度與製作成本上優於增層式基板之 特點，使壓合式基板可以提供良好的結構強度，以及相對 於增層式基板來說可降低整體封裝件之製作成本。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 #，熟習此技藝之人士可由本說明書所揭示之内容輕易地 '瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 以下之實施例係進一步詳細說明本發明之觀點，但並 非以任何觀點限制本發明之範疇。 本發明係提供一種將增層式基板（Bui ld-up Substrate)及壓合式基板（Laminated Substrate)合而 為一，並且進一步形成晶片朝下型之覆晶方式 (鲁1 lp-chip)，如第1 A圖及第1B圖所示之封裝結構，或晶 _片朝上型之焊線式（wire bond)，如第2 A圖及第2 B圖所示 之封裝結構，以減少封裝成品尺寸之組合式晶片承載件及 其製法，以及具有該組合式晶片承載件之半導體封裝件， 而藉由下述實施例分別予以詳細說明。17508 Shi Xipin. Ptd Page 13 200522284 V. Description of the invention (7)-· Inch 〇 On the other hand, the combined wafer carrier of the present invention integrates the build-up substrate and the press-type substrate. The precision of the circuit is based on the pressure-bonded substrate, and a larger number of solder ball pads are arranged under a limited substrate area. The pressure-bonded substrate is superior to the build-up substrate in terms of structural strength and manufacturing cost, so that the pressure-bonded substrate can be used. Provide good structural strength, and reduce the manufacturing cost of the overall package compared to the build-up substrate. [Embodiment] The following is a description of the embodiment # of the present invention through specific embodiments. Those skilled in the art can easily 'understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way. The present invention provides a flip-chip method (Lu 1 lp-chip) that combines a build-up substrate (Bui ld-up Substrate) and a laminated substrate (Laminated Substrate) into one, and further forms a wafer-down type, such as The package structure shown in Figure 1A and Figure 1B, or a wire bond with a wafer-up type, such as the package structure shown in Figure 2A and Figure 2B, in order to reduce the package finished product The combined wafer carrier with a size and a manufacturing method thereof, and a semiconductor package having the combined wafer carrier are described in detail in the following embodiments.
17508碎品.ptd 第14頁 200522284 五、發明說明（8) 本發明具有組合式晶片承載件之半導體封裝件係包 括·一堆$式晶片承載件1 ;至少一半導體晶片2係以覆晶 式if Chlp)電性連接組合在該堆疊式晶片承載件1頂 面’如第1 A圖及第丨B圖所示，或該半導體晶片2以銲線式 (Wire fond)電性連接組合在該堆疊式晶片承載件1頂 面’如第2A圖及第2B圖所示；一封裝膠體3係用以包覆該 半導體晶片2 ;以及複數個植接於該堆疊式晶片承載件1底 部之銲球4。 而上述堆疊式晶片承載件1及其製法進一步包括··預 備一壓合式基板1〇( Laminated Substrate)，該壓合式 基板1 0之一側係提供該等銲球4植接’以供半導體晶片2與 外部裝置（未圖示）電性連結；製備至少一增層式基板丄工 (Bui Id-up Substrate)，係接置於該壓合式基板丨味植 球之一側，該增層式基板Π上設有至少一供半導體晶片2 女置之aa片承載區1 1 〇，以及，提供至少一導電元件1 2， 係用以接合並提供該壓合式基板1 〇與該增層式基板1丨兩 連接。 兒 如第3 A圖及篇3 B圖所示，該壓合式基板1〇 (L a m i n a t e d S u b s t r a t e)係包含多數如銅箔與例如b 丁樹 脂、聚亞Si胺C Ρ ο 1 y 1 m i d e) 、F R - 5樹脂或環氧樹脂等絕 緣材料所製成之核心基板1 〇 〇，以及形成於該核心基板工⑽ 表面之一或多層内層線路層101，其中，該壓合式基板1〇 之一側係形成有多數銲球墊1 〇 3提供銲球（未圖示）植17508fragment.ptd Page 14 200522284 V. Description of the invention (8) The semiconductor package with a combined wafer carrier of the present invention includes a stack of $ -type wafer carriers 1; at least one semiconductor wafer 2 is a flip-chip type if Chlp) electrical connection combination on the top surface of the stacked wafer carrier 1 'as shown in Figure 1A and Figure 丨 B, or the semiconductor wafer 2 is combined with a wire fond electrical connection The top surface of the stacked wafer carrier 1 is as shown in FIG. 2A and FIG. 2B; an encapsulant 3 is used to cover the semiconductor wafer 2; and a plurality of solders implanted on the bottom of the stacked wafer carrier 1 Ball 4. The above-mentioned stacked wafer carrier 1 and the manufacturing method thereof further include preparing a laminated substrate 10 (Laminated Substrate). One side of the laminated substrate 10 is provided with the solder balls 4 implanted for semiconductor wafers. 2 Electrically connected with an external device (not shown); preparing at least one build-up substrate substrate (Bui Id-up Substrate), which is connected to one side of the press-fit substrate 丨 taste planting ball, and the build-up substrate The substrate Π is provided with at least one aa chip bearing area 1 1 0 for the semiconductor wafer 2 and the female, and at least one conductive element 12 is provided for bonding and providing the compression-type substrate 10 and the build-up substrate 1 丨 Two connections. As shown in Fig. 3A and Fig. 3B, the laminated substrate 10 (L aminated Substrate) contains a large number of copper foil and, for example, butyl resin, poly-Si amine C ρ 1 y 1 mide) Core substrate 100 made of insulating materials such as FR-5 resin or epoxy resin, and one or more inner layer circuit layers 101 formed on the surface of the core substrate, among which one of the press-type substrates 10 A large number of solder ball pads are formed on the side system 103 to provide solder ball (not shown) planting.
17508石夕品.ptd 第15頁 200522284 五、，發明說明（9) •線路層1 0 1經過圖案化後’於該内層線路層1 〇 1上外覆一層 具·有多數第—開口 1 〇 2 a之第一拒銲劑層1 0 2 ( S〇1 d e r M a s k )，以使該内廣線路層1 〇 1透過各第一開口 102 a而外露。 如第4A圖戶斤示’該增層式基板11( Build-up Subs t rat e)係利用增層技術交互堆疊多層絕緣層及導電 層，並於該絕緣層中開設多數導電貫孔1 1 3 ( C〇n d u c t i v e V l a)，經過電鍍以及圖案化等製程後形成複數層上下電 性導通之增層線路層1 1 4。惟如第4 B圖所示，本發明之堆 -疊式晶片承載件’係在增層式基板i 中央形成一晶片承載 ¥1 1 0，該晶片承載區1 1 〇藉以電性連接半導體晶片2。 而為阻隔外界電性干擾，增層式基板1 1外側的增層線 路層1 1 4經過圖案化後，亦會和壓合式基板1 〇一樣於基板 最外側覆蓋一層具複數個第二開口丨丨“之第二拒銲劑層 1 1 2，該第二開口 1 1 2a之位置係與該壓合式基板丨〇之第一 開口 1 0 2a位置彼此對應，以形成如第4β圖底視圖所示之基 板結構。 本發明之堆疊式。曰y 7 Μ Λ曰曰片承載件1不同於習知承載件之 處，係利用至少導·兩； ^ v &兀件1 2將該壓合式基板1 〇及增層式 基板11合而為一，該篆秦— 應。， ^ ♦电兀件1 2如導電性膠黏劑、銲錫膏 _S〇lder Paste)或辟力p n 乂4干錫凸塊（Solder Bump)等，俾藉 由膠黏或迴銲等技術八#阿、人 ^ ^ ^ — 了 7该堡合式基板1 0與增層式基板1 1間 電性連接。以本貫施伽主 ^ . , . . , n ^ 例為例，如第5A圖及第5B圖所示，該 壓合式基板1 0之第一拓π Λ ^ 娜# 祖在干劑層1 0 2的第一開口 1 〇 2 a處利用 網印或點膠寺方式塗彳右 佈一鲜錫膏1 2後，將該增層式基板1 117508 Shi Xipin.ptd Page 15 200522284 V. Description of the invention (9) • After the circuit layer 1 0 1 is patterned, a layer is overlaid on the inner circuit layer 1 〇1. There are many first openings 1 〇 2 a first solder resist layer 102 (S〇1 der M ask), so that the inner wide circuit layer 101 is exposed through each first opening 102a. As shown in FIG. 4A, the build-up substrate 11 (build-up substrate) is a method of using a build-up technology to alternately stack a plurality of insulating layers and conductive layers, and open a plurality of conductive through holes in the insulating layer 1 1 3 (Conductive Vla). After the processes of plating and patterning, a plurality of layers of layered circuit layers 1 1 4 which are electrically conductive up and down are formed. However, as shown in FIG. 4B, the stack-stack wafer carrier according to the present invention is formed with a wafer carrier ¥ 1 1 0 in the center of the build-up substrate i, and the wafer carrier region 1 1 10 is used to electrically connect the semiconductor wafer. 2. In order to block external electrical interference, the build-up circuit layer 1 1 4 on the outside of the build-up substrate 11 will be covered with a plurality of second openings on the outermost side of the substrate after the patterning as in the case of the laminated substrate 1 0.丨 丨 "the second solder resist layer 1 1 2, the position of the second opening 1 1 2a corresponds to the position of the first opening 1 0 2a of the compression-type substrate 丨 〇 to form as shown in the bottom view of Figure 4β The substrate structure shown in the present invention. The stacking type of the present invention. The y 7 Μ Λ said film carrier 1 is different from the conventional carrier, using at least two guides; ^ v & The substrate 10 and the build-up substrate 11 are combined into one. The electrical components 12 should be electrically conductive components such as conductive adhesives, solder pastes, or pn. Solder Bump, etc., are electrically connected by a technique such as gluing or re-welding. The electrical connection is made between the base substrate 10 and the build-up substrate 11. For example, as shown in FIG. 5A and FIG. 5B, the first extension π Λ ^ 娜 # of the pressed substrate 1 0 is in the desiccant layer 1 0 2 of The first opening 1 〇 2 a is coated with a fresh solder paste 1 2 by screen printing or dispensing temple method, and then the build-up substrate 1 1
第16頁 200522284 五、發明說明（10) 覆K i: t ί基板10上’以使該第一開口102a與該第二開 口 1 1 2a對應接觸而讓該銲錫膏1 2溢流入該第二開口 1 1 ， I2iHreflow)等程序，使得該内層線路層1〇1及增層 ί導：元:之二能透過該銲錫膏12接合並且電性連接。惟 式基板 :板，合前預先佈設於該壓合 二拒銲劑層112异\ 2&外，亦可反過來預先形成於該第 s 、之第一開口 112a ’然本實施例之導電 1 1盥厣1式：：：電膠或銲錫膏外，凡不影響增層式基板 t ^ ^ ; ί板10電性接合之接合技術或元件，均包含於 本發明之可實施範疇。 右制：Τ增層式基板1 1之相鄰銲球墊間距及銲球墊寬在現 =二可以控制到2 〇 V m，相較於傳統壓合式基板5 0/CZ m 读 田I板上佈设相同數量之銲球墊並以圓形環 周圍時，若按照圓周等於（相鄰銲球墊間距q ™ '干球墊見（以m))乘以（銲球墊數量）計算，排列銲 :: Ϊ據的圓周直徑將可從原本的6m_減至V 5mm而明 用面積，棱向細減該基板及半導體封裝件的 了 f面，本發明之堆疊式晶片承載件丨整合增層式 二 舁壓合式基板10，利用該增層式基板丨丨在線路精密 =旦=於壓合式基板10，以在有限的基板面積下佈設更多 銲球墊，而該壓合式基板10在結構強度上佳於增層 ' 1之特點，使壓合式基板1〇可提供良好的結構強 又，以及相對於增層式基板丨丨來說可降低整體封裝件之製Page 16 200522284 V. Description of the invention (10) Cover K i: t ί on the substrate 10 so that the first opening 102a and the second opening 1 1 2a are in corresponding contact so that the solder paste 12 overflows into the second Opening 1 1, I2iHreflow) and other procedures make the inner circuit layer 10 and the additional layer 导: yuan: the second can be joined and electrically connected through the solder paste 12. The only type substrate: board, which is arranged in advance on the pressure-sensitive solder resist layer 112 before closing, and can also be formed in advance in the first opening 112a of the s, and then the conductive 1 1 of this embodiment. Type 1 of toilet: ::: In addition to electric glue or solder paste, any bonding technique or component that does not affect the buildup substrate t ^ ^; ί board 10 is included in the scope of the present invention. Right system: The distance between adjacent solder ball pads and the width of the solder ball pads of the T build-up substrate 1 1 can be controlled to 20V m, compared to the traditional pressed substrate 5 0 / CZ m Yurada I board When the same number of solder ball pads are arranged on a circular ring, if the circumference is equal to (the distance between adjacent solder ball pads q ™ 'see for dry ball pads (in m)) multiplied by (the number of solder ball pads), Arrangement welding: The circumferential diameter of the data can be reduced from the original 6m_ to V 5mm and the area used is clear, and the f-side of the substrate and the semiconductor package is finely reduced. The stacked wafer carrier of the present invention is integrated Multi-layer laminated substrate 10 using the multi-layer substrate 丨 丨 Precise line = denier = on the laminated substrate 10 to arrange more solder ball pads under a limited substrate area, and the laminated substrate 10 The structural strength is better than that of the build-up '1, so that the laminated substrate 10 can provide good structural strength, and can reduce the overall package manufacturing compared to the build-up substrate.
200522284 五、發明說明（11) '作成本。 ‘ 請參閱第6圖，該封裝膠體3係為一散熱片3 a，而該散 熱片3 a係為一罩體，其四周邊固定在堆疊式晶片承載件1 之壓合式基板 避免半導體晶 果，此為本發 請參閱第 個相同或不同 基板1 1上方分 著再以封裝 封裝複數個半 目的，且僅須 省製造成本。 上述實施 而非用於限制 背本發明之精 化。因此，本 範圍所列。 1 0上面，俾可藉由該散熱片3 a進行散熱，以 片2過熱而損壞，因而可以更佳的使用效 明封裝之另一實施。 7圖，該壓合式基板1 0上方得排開疊裝複數 尺寸規格的增層式基板1 1，且在各個增層式 別疊裝同功能或不同功能的半導體晶片2， 膠體3封裝，使其可在壓合式基板1 0上多重 導體晶片2，因而得以達到縮小封裝面積之 一次進行封裝，而得簡化封裝製程，俾以節 例僅為例示性說明本發明之原理及其功效， 本發明。任何熟習此技藝之人士均可在不違 神及範疇下，對上述實施例進行修飾與變 發明之權利保護範圍，應如後述之申請專利200522284 V. Description of Invention (11) 'Working costs. '' Please refer to FIG. 6, the encapsulant 3 is a heat sink 3 a, and the heat sink 3 a is a cover, and the four periphery is fixed to the laminated substrate of the stacked wafer carrier 1 to avoid semiconductor crystal fruit. This is for the purpose of this article. Please refer to the same or different substrates 1 and 1 above, and then use a package to pack multiple halves, and only save manufacturing costs. The above implementations are not intended to limit the refinement of the present invention. Therefore, the scope is listed. Above 10, 俾 can dissipate heat through the heat sink 3a, and the chip 2 is overheated and damaged, so it can better use another implementation of the effective package. Fig. 7 shows that the laminated substrates 10 of multiple layers are stacked on top of the laminated substrates 10, and semiconductor wafers 2 of the same function or different functions are stacked on each of the layers, and the colloid 3 is packaged so that The multi-conductor wafer 2 can be formed on the press-type substrate 10, so that the packaging area can be reduced at a time, and the packaging process can be simplified. The example is only used to illustrate the principle and effect of the present invention. . Anyone who is familiar with this technique can modify and change the above embodiments without departing from the spirit and scope of the invention. The scope of protection of the rights of the invention should be applied for as described below.
]7508石夕品.ptd 第18頁 200522284 圖式簡單說明 【圖式簡單說明】 第1 A圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝下型的分解組合示意圖； 第1 B圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝下型的組合示意圖； 第2 A圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝上型的分解組合7F意圖， 第2 B圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝上型的組合示意圖； 第3 A圖係本發明堆疊式晶片承載件之壓合式基板之局 部剖視圖； 第3 B圖係本發明堆疊式晶片承載件之壓合式基板之底 視圖， 第4 A圖係本發明堆疊式晶片承載件之增層式基板之局 部剖視圖； 第4B圖係本發明堆疊式晶片承載件之增層式基板之上 視圖； 第5 A圖係本_發明之堆疊式晶片承載件中，該增層式基 板與壓合式基板接合前之示意圖； 第5 B圖係本發明之堆疊式晶片承載件中，該增層式基 板與壓合式基板接合後之示意圖； 第6圖係本發明具有堆疊式晶片承載件之半導體封裝 件另一封裝實施之剖面示意圖； 第7圖係本發明具有堆疊式晶片承載件之半導體封裝] 7508 Shi Xipin.ptd Page 18 200522284 Brief Description of Drawings [Simplified Description of Drawings] Figure 1A is an exploded and assembled schematic diagram of a wafer-down type semiconductor package with the stacked wafer carrier of the present invention; FIG. 1B is a schematic diagram of a wafer-down assembly of a semiconductor package with the stacked wafer carrier according to the present invention; FIG. 2A is a wafer-oriented view of a semiconductor package with the stacked wafer carrier according to the present invention; The disassembled combination 7F of the upper type is intended, and FIG. 2B is a schematic diagram of the combination of the wafer-up type of the semiconductor package with the stacked wafer carrier of the present invention; FIG. 3A is the pressure of the stacked wafer carrier of the present invention Partial cross-sectional view of a composite substrate; Figure 3B is a bottom view of a laminated substrate of the stacked wafer carrier of the present invention, and Figure 4A is a partial sectional view of a build-up substrate of the stacked wafer carrier of the present invention; Figure 4B FIG. 5A is a top view of a build-up substrate of a stacked wafer carrier of the present invention; FIG. 5A is a view of the present invention_stacked wafer carrier of the present invention, the build-up substrate is bonded to a press-bonded substrate Figure 5B is a schematic diagram of the stacked wafer carrier of the present invention after the build-up substrate is bonded to the pressure-bonded substrate; Figure 6 is another semiconductor package of the present invention with a stacked wafer carrier. A schematic cross-sectional view of a package implementation; FIG. 7 is a semiconductor package with a stacked wafer carrier according to the present invention
1 7508石夕品· ptd 第19頁 200522284 圖式簡單說明 。件又一封裝實施之剖面示意圖； * 第8 A圖及第8 B圖係習知以壓合法製作多層基板之剖視 圖； 第9圖係習知銲球墊環設於晶片周圍之基板區域之假 想示意圖；以及 第1 0 A圖、第1 0 B圖及第1 0 C圖係為美國專利第 5，8 7 0，2 8 9號半導體封裝之剖視示意圖。 1 堆 疊 式 晶 片 承 載 件 1 0 0π 核 心 基 板 _0a 丨丨核 心 基 板 10 0b" 核 心 基 板 90a 基 板 101 > 10： 1，’ 内 層 線 102a 第 一 開 D 102 拒 銲 劑 層 103 銲 球 墊 10 壓 合 式 基 板 110 晶 片 承 載 1 12a 第 二 開 α 112 第 二 拒 銲 劑 層 113 導 電 貫 孔 1 14 增 層 線 路 層 11 增 層 式 基 板 12 銲 錫 膏 、 導 電 元 件 2 半 導 體 晶 片 3a 散 執 片 - 3 封 裝 膠 體 4 銲 球 5Π 黏 著 層 • 銲 球 墊 9 單 元 結 構 90 單 面 電 路 板 90b 多 層 電 路 板 90c 銲 球 901 電 路 9 0 2〜 91 1 .穿孔 91 黏 膠 片 92 積 體 電 路 晶 片 921 銲 墊1 7508 Shi Xipin · ptd Page 19 200522284 Simple illustration of the diagram. A schematic cross-sectional view of the implementation of another package; * Figures 8A and 8B are cross-sectional views of a conventional method for making a multilayer substrate by pressing; Figure 9 is a conventional imaginary region of a substrate where a solder ball pad ring is arranged around a wafer. Schematic diagrams; and FIG. 10A, FIG. 10B, and FIG. 10C are cross-sectional schematic diagrams of a semiconductor package of US Pat. No. 5,878,829. 1 stacked wafer carrier 1 0 0π core substrate_0a 丨 丨 core substrate 10 0b " core substrate 90a substrate 101 > 10: 1, 'inner layer line 102a first open D 102 solder resist layer 103 solder ball pad 10 compression type Substrate 110 Wafer carrier 1 12a Second opening α 112 Second solder resist layer 113 Conductive through hole 1 14 Layer-increasing circuit layer 11 Layer-increasing substrate 12 Solder paste, conductive element 2 Semiconductor wafer 3a Discrete film-3 Encapsulant 4 Soldering Ball 5Π Adhesive layer • Solder ball pad 9 Unit structure 90 Single-sided circuit board 90b Multi-layer circuit board 90c Solder ball 901 Circuit 9 0 2 to 91 1. Perforation 91 Adhesive sheet 92 Integrated circuit chip 921 Solder pad
1 7508石夕品· ptd 第20頁 200522284 圖式簡單說明 93 導電柱 94 内殼 9 5 膠體 96 連接器 9 7 絕緣層 98 長導電柱 9 9 外殼 iiil 第21頁 17508石夕品.ptd1 7508 Shi Xipin · ptd Page 20 200522284 Brief description of the diagram 93 Conductive post 94 Inner shell 9 5 Gel 96 Connector 9 7 Insulation layer 98 Long conductive post 9 9 Shell iiil Page 21 17508 Shi Xipin.ptd
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| TW092137574A TWI246750B (en) | 2003-12-31 | 2003-12-31 | A carrier for stacked chips and a method for fabricating the same and a semiconductor package with the chip carrier |
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| TW092137574A TWI246750B (en) | 2003-12-31 | 2003-12-31 | A carrier for stacked chips and a method for fabricating the same and a semiconductor package with the chip carrier |
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| TWI246750B TWI246750B (en) | 2006-01-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI508239B (en) * | 2009-08-20 | 2015-11-11 | Xintec Inc | Chip package and manufacturing method thereof |
| TWI768552B (en) * | 2020-11-20 | 2022-06-21 | 力成科技股份有限公司 | Stacked semiconductor package and packaging method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI320594B (en) | 2006-05-04 | 2010-02-11 | Cyntec Co Ltd | Package structure |
| TWI426588B (en) * | 2010-10-12 | 2014-02-11 | Advanced Semiconductor Eng | Package structure and package process |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI508239B (en) * | 2009-08-20 | 2015-11-11 | Xintec Inc | Chip package and manufacturing method thereof |
| TWI768552B (en) * | 2020-11-20 | 2022-06-21 | 力成科技股份有限公司 | Stacked semiconductor package and packaging method thereof |
| US11670622B2 (en) | 2020-11-20 | 2023-06-06 | Powertech Technology Inc. | Stacked semiconductor package and packaging method thereof |
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| TWI246750B (en) | 2006-01-01 |
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