TWI508239B - Chip package and manufacturing method thereof - Google Patents

Description

Chip package and method of forming same

This invention relates to wafer packages, and more particularly to chip packages having a plurality of wafers.

As electronic products are moving toward light, thin, short, and small trends, the packaging structure of semiconductor wafers is also moving toward multi-chip package (MCP) structures to meet versatility and high performance requirements. Multi-chip package structures integrate different types of semiconductor wafers, such as logic wafers, analog wafers, control wafers or memory chips, onto a single package substrate.

However, as the number of wafers to be integrated increases, the two-dimensional integration of the multi-wafer on the package substrate (such as a germanium substrate) causes the package volume to be effectively reduced, and also takes up too much area, resulting in an increase in manufacturing cost. In addition, the conventional packaging method also has a problem of poor signal transmission speed.

In addition, due to the need to integrate multiple wafers in a limited area, the accuracy of the placement of the wafer and the material reliability of the chip package are also in need of improvement.

An embodiment of the present invention provides a chip package including a semiconductor substrate having an upper surface and an opposite lower surface; a through hole penetrating the upper surface and the lower surface of the semiconductor substrate; and a first wafer disposed on the upper surface of the semiconductor substrate; conductive a layer on the sidewall of the via and electrically connected to the first wafer; a first insulating layer on the upper surface of the semiconductor substrate; and a second insulating layer on the lower surface of the semiconductor substrate, wherein the material of the second insulating layer Different from the first insulating layer; and the bonding structure is disposed on a lower surface of the semiconductor substrate.

An embodiment of the present invention provides a method of forming a chip package, comprising: providing a semiconductor substrate having an upper surface and an opposite lower surface; forming a through hole in the semiconductor substrate, the through hole penetrating the upper surface and the lower surface of the semiconductor substrate; and the sidewall of the through hole Forming a conductive layer thereon; disposing a first wafer on the upper surface of the semiconductor substrate, the first wafer is electrically connected to the conductive layer; forming a first insulating layer on the upper surface of the semiconductor substrate; forming a second surface on the lower surface of the semiconductor substrate An insulating layer, wherein a material of the second insulating layer is different from the first insulating layer; and a bonding structure is disposed on a lower surface of the semiconductor substrate.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

1A-1K is a cross-sectional view showing a series of processes of a chip package in accordance with an embodiment of the present invention. As shown in FIG. 1A, a semiconductor substrate 100 is provided having an upper surface 100a and an opposite lower surface 100b. The semiconductor substrate 100 can include a germanium substrate, a germanium wafer, or a substrate of other semiconductor materials. Alternatively, the semiconductor substrate can also be a semiconductor wafer, such as a logic processing chip, a microelectromechanical system wafer, a microfluidic system wafer, or a physical sensor wafer, a radio frequency component wafer, measured by physical variations such as heat, light, and pressure. Accelerometer chips, gyroscope wafers, micro-brake wafers, surface acoustic wave element wafers, pressure sensor wafers, inkjet head wafers, light-emitting element wafers, or solar cell wafers, and the like.

Next, a through hole penetrating the upper surface and the lower surface is formed in the semiconductor substrate. In one embodiment, the perforations through the upper surface and the lower surface may be formed directly, for example by lithographic etching. Alternatively, as shown in FIGS. 1A and 1B, the hole 102a extending toward the lower surface 100b may be formed from the upper surface 100a of the semiconductor substrate 100. Next, the semiconductor substrate 100 is thinned from the lower surface 100b of the semiconductor substrate 100 to expose the holes 102a from the lower surface 100b, thereby forming the through holes 102. That is, the two-stage process of etching and thinning is performed to form the through holes 102 penetrating the upper surface 100a and the lower surface 100b of the semiconductor substrate 100. Although the sidewalls of the perforations 102 shown in FIG. 1B are substantially perpendicular to the upper surface 100a and the lower surface 100b, in other embodiments, adjustments to process conditions (eg, etchant and/or etching methods) may be selected as desired. The side walls of the perforations 102 are inclined to the upper surface 100a and/or the lower surface 100b.

Referring to FIG. 1C, since a conductive layer is formed on the sidewall of the via 102 in the subsequent process, in order to avoid short-circuit or contamination between the subsequently formed conductive layer and the semiconductor substrate 100, the sidewall of the via 102 may be advanced. A dielectric layer 104 is formed thereon. It should be noted that the formation of the dielectric layer 104 is not required and is only a selective process. The dielectric layer 104 is formed by, for example, chemical vapor deposition, thermal oxidation, or coating of an insulating film. In the embodiment shown in FIG. 1C, a dielectric layer 104 is formed on the exposed surface of the semiconductor substrate 100 by thermal oxidation, and the material thereof may be, for example, yttrium oxide or other semiconductor oxide. In other embodiments, the material of the dielectric layer 104 may include, for example, an oxide, a nitride, an oxynitride, a polymer material, or a combination thereof.

Next, a conductive layer 106 is formed on the sidewalls of the vias 102. As shown in FIG. 1D, in this embodiment, the conductive layer 106 is formed on the sidewalls of the vias 102 and further extends onto the upper surface 100a and the lower surface 100b of the semiconductor substrate 100. The manner in which the conductive layer 106 is formed may include physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating, and the like. The material of the conductive layer 106 may be a metal material such as copper, aluminum, gold, or a combination thereof. The material of the conductive layer 106 may further include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof. In one embodiment, a conductive layer is formed conformally over the entire semiconductor substrate 100, and then the conductive layer is patterned into, for example, the distribution shown in FIG.

Next, a self-aligned barrier wall 107 is formed on the surface of the semiconductor substrate 100 where the wafer is to be placed (for example, on the upper surface 100a). The self-aligned barrier wall 107 will facilitate the automatic and accurate placement of the wafers subsequently disposed on the semiconductor substrate 100 at a set location. As shown in FIG. 1D, in this embodiment, the self-aligned barrier wall 107 is preferably patterned from the same conductive layer forming the conductive layer 106. Therefore, in this embodiment, the self-aligned barrier wall 107 is formed simultaneously with the conductive layer 106, and the material of the conductive layer 106 includes a conductive material. In other embodiments, the self-aligned barrier wall 107 can be formed independently of the conductive layer 106 in the same process, in which case the material of the self-aligned barrier wall 107 can be different from the conductive layer 106. The material of the self-aligned barrier wall 107 may include a metal material, a ceramic material, a polymer material, a semiconductor material, or a combination thereof.

Next, a wafer 108 is placed on the upper surface 100a of the semiconductor substrate 100. As shown in FIG. 1E, the wafer 108 can be attached to the upper surface 100a of the semiconductor substrate 100 through the adhesive layer 110 between the wafer 108 and the semiconductor substrate 100. Wafer 108 may, for example, comprise a logic operational wafer, a microelectromechanical system wafer, a microfluidic system wafer, or a physical sensor wafer, radio frequency component wafer, accelerometer wafer, gyroscope wafer measured using physical variations such as heat, light, and pressure. , micro-brake wafer, surface acoustic wave element wafer, pressure sensor wafer, inkjet head wafer, light-emitting element wafer, or solar cell wafer, and the like. The wafer 108 can include at least one pad 108a for electrically connecting to other lines or components.

Since the adhesive layer 110 may be fluid due to the possibility of experiencing higher temperatures during the process of the chip package, the wafer 108 may be moved away from the original preset position, which may cause wafer package failure. In the embodiment shown in FIG. 1E, since the self-aligned barrier wall 107 has been formed in advance, the self-aligned barrier wall 107 can limit the movement of the wafer 108 to the extent defined by the self-aligned barrier wall 107. Therefore, the packaging process of the wafer can be smoothly carried out.

The relative position and configuration between the self-aligning barrier wall 107 and the wafer 108 can be varied, such that the wafer 108 can be over-biased by its preset position due to the fluidity of the adhesive layer 110 at higher temperatures. The manner in which the quasi-blocking wall 107 is disposed is within the scope of the embodiments of the present invention. For example, FIG. 2A-2C shows a top view of the arrangement of the self-aligned barrier wall 107 and the wafer 108 in the embodiment of the present invention.

As shown in FIG. 2A, the self-aligned barrier wall 107 is adjacent to or may be in slight contact with the wafer 108. In one embodiment, the self-aligned barrier wall 107 is a continuous structure, such as an annular structure that surrounds the wafer 108 to prevent it from excessively deviating from its predetermined position. As shown in FIG. 2B, in another embodiment, the self-aligning retaining wall 107 is a discontinuous structure including at least a first portion 107a and a second portion 107b that is not coupled to the first portion 107a. In this embodiment, the first portion 107a and the second portion 107b are disposed opposite to each other on the wafer 108 to prevent the wafer 108 from being excessively offset from its predetermined position. Moreover, in another embodiment, the self-aligned retaining wall 107 can include a third portion 107c and a fourth portion 107d that can be disposed at a corner of the wafer 108 and that resists the wafer, for example, by an L-shaped structure against the wafer. Excessive displacement. As shown in FIG. 2C, in still another embodiment, the self-aligning retaining wall 107 is a discontinuous structure and includes a plurality of portions, in this embodiment, the first, second, third, and fourth portions, respectively. 107a, 107b, 107c, and 107d, and the shapes of the portions may be different from each other, for example, may have a square, a rectangle, or an arc or the like.

Next, referring to FIG. 1F, a first insulating layer 110a is formed on the upper surface 100a of the semiconductor substrate 100, and a second insulating layer 110b is formed on the lower surface 100b, wherein the material of the first insulating layer 110a is different from the second insulating layer. Layer 110b. In a subsequent process, an opening exposing the conductive layer 106 is formed on the second insulating layer 110b, and a bonding structure (for example, forming a solder ball) is formed in the opening, and the applicant has found in the research that the second insulating layer 110b Compared with the first insulating layer 110a, it is often required to be in contact with the external environment. Therefore, the environmental resistance of the second insulating layer 110b is preferably selected to be superior to the first insulating layer 110a. For example, the second insulating layer 110b may be made higher in acid resistance than the first insulating layer 110a, or the second insulating layer 110b may be more waterproof than the first insulating layer 110a. For example, the material of the first insulating layer 110a may include a liquid type material such as a liquid epoxy resin, a polyimide, a benzocyclobutene (BCB), or the like, or the foregoing. The combination of the second insulating layer 110b may be selected from a solder mask, a tantalum oxide layer or a tantalum nitride layer, or a combination thereof.

In addition, in another embodiment, since a plurality of small-sized openings are formed in the first insulating layer 110a and the opening size of the second insulating layer is large, a photosensitive insulating material having a better exposure resolution may be selected. As the first insulating layer 110a, a photosensitive insulating material having a general exposure resolution can be selected as the second insulating layer, and the above process can reduce the cost since it is not necessary to separately form a photoresist pattern. For example, the material of the first insulating layer 110a may include a photosensitive insulating material with better resolution, such as a liquid epoxy resin, a polyimid, a benzocyclobutene (BCB), or the like, or a combination thereof. The material of the second insulating layer 110b may be selected from a general resolution photosensitive insulating material, such as a solder mask.

In the embodiment shown in FIG. 1F, the first insulating layer 110a and the second insulating layer 110b further extend over the conductive layer 106 on the sidewall of the via 102. In an embodiment, the first insulating layer 110a and the second insulating layer 110b fill the through holes 102. In an embodiment, the depth of the first insulating layer 110a extending into the through hole 102 is greater than the extending depth of the second insulating layer 110b. In this case, the hole filling ability of the material selected for the first insulating layer 110a may be superior to the hole filling ability of the second insulating layer 110b. For example, in an embodiment, the material of the first insulating layer 110a includes a dry film having a better hole filling ability, such as a dry film type epoxy resin, a silicone or a combination thereof. The material of the second insulating layer 110b may be selected from an insulating material generally filled with a hole, such as a solder mask, a tantalum oxide layer or a tantalum nitride layer, or a combination thereof.

The manner in which the first insulating layer 110a and the second insulating layer 110b are formed may include, for example, spin coating, spray coating, or curtain coating, or other suitable deposition methods, for example, Liquid deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric chemical vapor deposition.

In one embodiment, the first insulating layer 110a and the second insulating layer 110b are formed by attaching a dry film to the upper surface 110a and the lower surface 110b of the semiconductor substrate 100, respectively, and softening the dry film to fill it. The perforation is finally cured by heat treatment to soften the dry film. The formation of the above preferred embodiment is shown in Figures 3A-3B.

As shown in FIG. 3A, the first insulating film 111a and the second insulating film 111b are attached to the upper surface 100a and the lower surface 100b of the semiconductor substrate 100, respectively. In this embodiment, the first insulating film 111a is in direct contact with the dielectric layer 104 and the conductive layer 106 on the upper surface 100a, and the second insulating film 111b is connected to the dielectric layer 104 and the conductive layer 106 on the lower surface 100b. direct contact.

Next, as shown in FIG. 3B, the first insulating film 111a and the second insulating film 111b are heated, and at this time, the temperature can be raised to exceed the softening point of the first insulating film 111a and the second insulating film 111b, and the first insulating layer is made. The film 111a and the second insulating film 111b are softened, and the softened first insulating film 111a' and the softened second insulating film 111b' extend into the perforations 102 on the side walls of the perforations 102 because of a certain degree of fluidity. Above the conductive layer 106. In an embodiment, the softening point of the first insulating film 111a' may be lower than that of the second insulating film 111b'; or the fluidity of the first insulating film 111a' may be higher than that of the second insulating film 111b'.

In the embodiment shown in Fig. 3B, the depth of the softened first insulating film 111a' extending into the through hole 102 is thus greater than the depth of extension of the softened second insulating film 111b'. However, in other embodiments, the depth of extension of the individual softened insulating film can be adjusted by control of process conditions (eg, controlling the heating temperature). Alternatively, for example, the first insulating film and the second insulating film having a large difference in softening point may be selected, and only the temperature is heated to be higher than the softening point of only one of the insulating films, so that the perforation 102 is only largely filled with a softening of a single material. The rear insulating film is returned to a solid state later, and then a hardening step is performed to form the first insulating layer 110a and the second insulating layer 110b shown in FIG. In one embodiment, when the first insulating layer 110a and the second insulating layer 110b are polymer materials, the polymer material may be cross-linked by a heat treatment to be hardened, for example, at a temperature of 150 ° C to 300 ° C. More than 0.5 hours.

Referring to FIG. 1F, after the first insulating layer 110a and the second insulating layer 110b are formed, the first insulating layer 110a and the second insulating layer 110b are respectively patterned to form a plurality of openings therein. In the first insulating layer 110a, since a large number of openings having a small size are required, the first insulating layer 110a may be selected from a photosensitive insulating material having a high exposure resolution. The second insulating layer 110b needs to have better environmental resistance because it needs to withstand the subsequent process of forming the bonding structure. The opening of the patterned first insulating layer 110a exposes the conductive layer 106 extending on the upper surface 100a and the pads 108a of the wafer 108. The opening of the patterned second insulating layer 110b exposes the conductive layer 106 extending on the lower surface 100a.

Next, as shown in FIG. 1G, a line redistribution layer 112 is formed on the bottom and side walls of the opening in the first insulating layer 110a. In this embodiment, the circuit redistribution layer 112 is in direct contact with the conductive layer 106 and the pads 108a of the wafer 108 through the openings, thereby electrically connecting the wafer 108 and the conductive layer 106. The formation of the line redistribution layer 112 may include physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating. The material of the line redistribution layer 112 may be a metal material such as copper, aluminum, gold, or a combination thereof. The material of the line redistribution layer 112 may further include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof.

As shown in FIG. 1H, a third insulating layer 114 is then formed on the semiconductor substrate 100. The third insulating layer 114 can be, for example, a solder resist material, or other suitable insulating material. The third insulating layer 114 may also be formed in a manner similar to the attached dry film shown in Figs. 3A-3B.

Next, as shown in FIG. 1I, at least one wafer 116 is disposed on the third insulating layer 114. Wafer 116 can be electrically coupled to wafer 108 via, for example, solder balls 116a, a line redistribution layer (not shown) formed in third insulating layer 114, and a line redistribution layer 112. Therefore, the wafer 116 can be operated in conjunction with the wafer 108 to transmit signals to each other.

The function of the wafer 116 may be different from that of the wafer 108, and may include a logic operational wafer, a microelectromechanical system wafer, a microfluidic system wafer, or a physical sensor wafer, a radio frequency component wafer, measured using physical variations such as heat, light, and pressure. Accelerometer chips, gyroscope wafers, micro-brake wafers, surface acoustic wave element wafers, pressure sensor wafers, inkjet head wafers, light-emitting element wafers, or solar cell wafers, and the like. In addition, more wafers with other functions can be further provided. Through the stacking method as shown in FIG. 1I, various functional wafers can be integrated in a limited area to obtain desired products. In addition to reducing the cost of wafer area, the electrical connection in the vertical direction can shorten the signal transmission distance and further increase the speed of signal transmission to improve product performance.

As shown in FIG. 1J, an underfill 118 is then formed under the wafer 116 to secure and protect the wafer 116. Next, as shown in FIG. 1K, the bonding structure 120 is formed in the opening in the second insulating layer 110b. In this embodiment, the bonding structure 120 is a conductive bonding structure, such as a solder ball. The bonding structure 120 can be electrically connected to the conductive layer 106 through an opening in the second insulating layer 110b. Therefore, when the bonding structure 120 is a conductive bonding structure, it can be electrically and electrically connected to the wafer 108 and the wafer 106 respectively through the conductive layer 106 and the line redistribution layer 112. In addition, the chip package of the embodiment of the present invention can be further disposed on other electronic components through the bonding structure 120, for example, can be flip-chip mounted on the circuit board.

Further, in other embodiments, a cover plate may be disposed on a lower surface of the semiconductor substrate through the bonding structure. For example, in the chip package of an embodiment shown in FIG. 4, the cap plate 406 is disposed on the lower surface 100b of the semiconductor substrate 100 through the bonding structure 120a (for example, a metal bump). A metal pad 404 may be pre-formed on the cover plate 406 for engaging the engagement structure 120a. For example, when the material of the bonding structure 120a is metal, eutectic bonding or diffusion bonding may occur between the bonding structure and the metal pad 404 through a heating process. However, when it is not necessary to form a conductive path between the cover 406 and the chip package, other non-metal materials may be used to complete the bonding.

In one embodiment, the cover 406 can be, for example, a transparent cover, such as glass, quartz, opal, plastic or any other transparent substrate that allows light to enter and exit. At this time, the semiconductor substrate 100 may be, for example, (or include) a photosensitive wafer or a light emitting wafer, such as an image capturing wafer, a light emitting diode wafer, or a solar cell wafer.

The formation process of the chip package of the embodiment of the present invention is described above in conjunction with the drawings. It should be noted that the order of the above various processes is for illustrative purposes only, and the order of partial processes may be reversed without departing from the spirit of the present invention. Alternatively, other required processes may be interspersed between the various processes as appropriate.

The chip package of the embodiment of the invention forms a vertical conductive path through the through hole, so that a plurality of types of wafers can be integrated in the vertical direction, which can save manufacturing cost, reduce product size, and improve product performance. By forming two insulating layers different in material from above and below the semiconductor substrate, the process requirements and package reliability can be achieved. Through the setting of the self-aligning retaining wall, the position of the wafer can be controlled to improve the yield of the package.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

100. . . Semiconductor substrate

100a, 100b. . . surface

102. . . perforation

102a. . . Hole

104. . . Dielectric layer

106. . . Conductive layer

107. . . Self-aligning barrier wall

107a, 107b, 107c, 107d. . . section

108, 116. . . Wafer

108a. . . Pad

110a, 110b, 114. . . Insulation

111a, 111a', 111b, 111b'. . . Insulating film

112. . . Line redistribution

116a. . . Solder ball

118. . . Primer

120, 120a. . . Joint structure

404. . . Metal pad

406. . . Cover

1A-1K is a cross-sectional view showing a series of processes of a chip package in accordance with an embodiment of the present invention.

2A-2C is a top plan view showing the arrangement of the self-aligned barrier wall and the wafer in the embodiment of the present invention.

3A-3B is a cross-sectional view showing a process for forming an insulating layer in a chip package in an embodiment of the present invention.

Fig. 4 is a cross-sectional view showing a chip package according to an embodiment of the present invention.

100. . . Semiconductor substrate

100a, 100b. . . surface

104. . . Dielectric layer

106. . . Conductive layer

107. . . Self-aligning barrier wall

108, 116. . . Wafer

108a. . . Pad

110a, 110b, 114. . . Insulation

112. . . Line redistribution

118. . . Primer

120. . . Joint structure

Claims (34)

A chip package comprising: a semiconductor substrate having an upper surface and an opposite lower surface; a through hole penetrating the upper surface and the lower surface of the semiconductor substrate; a first wafer disposed on the semiconductor substrate a conductive layer on the sidewall of the via and electrically connected to the first wafer; a first insulating layer on the upper surface of the semiconductor substrate; and a second insulating layer on the semiconductor substrate The lower surface of the second insulating layer is different from the first insulating layer; and a bonding structure is disposed on the lower surface of the semiconductor substrate. The chip package of claim 1, wherein the second insulating layer is superior to the first insulating layer in environmental resistance. The chip package of claim 2, wherein the first insulating layer and the second insulating layer extend into the through holes, respectively. The chip package of claim 2, wherein the first insulating layer extends into the through hole to a depth greater than the second insulating layer. The chip package of claim 4, wherein a softening point of the first insulating layer is lower than a mobility of the second insulating layer or the first insulating layer is higher than the second insulating layer. The chip package of claim 1, wherein the first insulating layer has a higher exposure resolution than the second insulating layer. The chip package of claim 1, wherein The second insulating layer is more resistant to acid or water repellency than the first insulating layer. The chip package of claim 1, further comprising a self-aligning barrier on the upper surface of the semiconductor substrate adjacent to or in contact with the first wafer. The chip package of claim 8, wherein the self-aligning retaining wall is a continuous annular structure surrounding the first wafer. The chip package of claim 8, wherein the self-aligning retaining wall is a discontinuous structure comprising at least a first portion and a second portion, the first portion being disposed opposite to the second portion Both sides of the first wafer. The chip package of claim 8, wherein the material of the self-aligning retaining wall comprises a conductive material. The chip package of claim 1, further comprising a second wafer disposed on the first insulating layer and the first wafer, wherein the second wafer is electrically connected to the first wafer. The chip package of claim 12, further comprising a third insulating layer formed between the second wafer and the first wafer. The chip package of claim 1, further comprising: an opening formed in the first insulating layer; and a line redistribution layer formed on the bottom and the sidewall of the opening, and the line The redistribution layer electrically connects the first wafer and the conductive layer. The chip package of claim 8, wherein the self-aligned retaining wall and the conductive layer are simultaneously formed metal materials. The chip package of claim 1, wherein the semiconductor substrate is a wafer. The chip package of claim 16, further comprising a cover plate disposed on the lower surface of the semiconductor substrate through the bonding structure. A method for forming a chip package, comprising: providing a semiconductor substrate having an upper surface and an opposite lower surface; forming a through hole in the semiconductor substrate, the through hole penetrating the upper surface and the lower surface of the semiconductor substrate; a conductive layer is formed on the sidewall of the via and extends to the semiconductor substrate; a first wafer is disposed on the upper surface of the semiconductor substrate, the first wafer is electrically connected to the conductive layer; and the semiconductor substrate is Forming a first insulating layer on the upper surface; forming a second insulating layer on the lower surface of the semiconductor substrate, wherein a material and environmental resistance of the second insulating layer are different from the first insulating layer; An engagement structure is disposed on the lower surface of the semiconductor substrate. The method for forming a chip package according to claim 18, wherein the forming of the first insulating layer and the second insulating layer comprises: attaching respectively to the upper surface and the lower surface of the semiconductor substrate a first insulating film and a second insulating film; heating the first insulating film and the second insulating film to soften and extend the first insulating film and the second insulating film to the sidewall of the through hole Above the electrical layer; and curing the softened first insulating film and the second insulating film into the first insulating layer and the second insulating layer, respectively. The method of forming a chip package according to claim 18, wherein the second insulating layer is superior in environmental resistance to the first insulating layer. The method for forming a chip package according to claim 18, wherein the first insulating layer and the second insulating layer respectively extend into the through hole, and the depth of the first insulating layer extending into the through hole is greater than the Second insulating layer. The method of forming a chip package according to claim 18, wherein a softening point of the first insulating layer is lower than a mobility of the second insulating layer or the first insulating layer is higher than the second insulating layer. The method of forming a chip package according to claim 18, wherein the first insulating layer has a higher exposure resolution than the second insulating layer. The method for forming a chip package according to claim 18, wherein the second insulating layer is higher in acid resistance or water repellency than the first insulating layer. The method for forming a chip package according to claim 18, further comprising forming a self-aligning retaining wall on the upper surface of the semiconductor substrate, the self-aligning retaining wall being adjacent to or slightly contacting the first Wafer. The method of forming a chip package according to claim 25, wherein the self-aligning barrier is a continuous annular structure surrounding the first wafer. The method for forming a chip package according to claim 25, wherein the self-aligning retaining wall is a discontinuous structure comprising at least a first portion and a second portion, the first portion being opposite to the second portion Provided on both sides of the first wafer. The method for forming a chip package according to claim 25, wherein the material of the self-aligning barrier comprises a conductive material. The method of forming a chip package according to claim 25, wherein the self-aligning barrier is formed simultaneously with the conductive layer. The method for forming a chip package according to claim 18, further comprising: providing a second wafer on the first insulating layer and the first wafer, and electrically connecting the second wafer to the first wafer . The method for forming a chip package according to claim 30, further comprising forming a third insulating layer between the second wafer and the first wafer. The method for forming a chip package according to claim 18, further comprising: forming an opening in the first insulating layer; and forming a line redistribution layer on the bottom and the sidewall of the opening, the line is heavy The layer is electrically connected to the first wafer and the conductive layer. The method of forming a chip package according to claim 18, wherein the semiconductor substrate is a wafer. The method of forming a chip package according to claim 33, further comprising a cover plate disposed on the lower surface of the semiconductor substrate through the bonding structure.