1254462 16495twf.doc/006 九、發明說明: 【發明所屬之技術領域】 ,發明S有’—麵裝結構,且制是有關於一種 具有向封裝積集度之堆叠型晶片封裝結構◦ 【先前技術】 在現今的貧訊社會中,使用者均是追求高速度、高品 二:多工能性的電子產品。就產品外觀而言,電子產品的 • ^十也朝向輕、薄、短、小的趨勢邁進。為了達到上述目 的/ =夕Λ司在進行電路設計時,均融入系統化的概念, • 使知單顆晶片可以具備有多種功能,以節省配置在電子產 、 品中的晶片數目。另外,就電子封裝技術而言,為了配合 輕、薄、短、小的設計趨勢,亦發展出多晶片模組(娜 卿她,MCM)的封裝設計概念、晶片尺寸構裝(chip scale package,CSP)的封裝設計概念及堆疊型乡晶4封裝設計 的概念等。以下就分別針對幾種習知堆疊型晶片封裝結構 進行說明。 • ▲目1緣示習知堆疊型晶片封裝結構的剖面示意圖。請 芩考圖1,習知的堆疊型晶片封裝結構丨⑻包括一封裝基 板(package substrate) 110、晶片 12〇a、12%、一間隔物 (spacer) 130、多條導線 14〇 與一封裝膠體(encapsulant) 150。其中,晶片12〇3與12〇b配置於封裝基板上,且 間隔物130配置於晶片120a與12%之間。部分導線14〇 刀別電性連接於晶片12〇a與封裝基板u〇之間,而其他部 分導線140則分別電性連接於晶# 12%與封裝基板11〇 5 1254462 16495twf.doc/〇〇6 ' ^間。此外,封裝膠體150配置於封裝基板no上,並包 覆這些導線140、晶片120a、120b與間隔物130。 由於晶片120a與120b之間必須相距一定的距離,以 便於進行打線製程(wire bonding process),因此習知堆 豐型晶片封裝結構100的整體厚度會因為間隔物130的厚 度而然法進一步縮減。此外,習知堆疊型晶片封裝結構1〇〇 也會產生散熱方面的問題。因此,為了解決上述問題,習 鲁 知發展出另一種堆疊型晶片封裝結構。 圖2繪示另一習知堆疊型晶片封裝結構的剖面示意 - ,。请芩考圖2,習知的堆疊型晶片封裝結構10包括一封 、 叙基板12與多個晶片封裝體200a、200b,其中這些晶片 封裝體20〇a、200b堆疊於封裝基板12上,並與封裝基板 12電性連接。每一晶片封裝體2〇〇a、2〇此包括一封裝基 板210、一晶片220、多個凸塊230、一底膠240與多個銲 球250。晶片220與這些凸塊230配置於封裝基板210上, 而這些凸塊23〇配置於晶片220與封裝基板21〇之間,且 晶片220經由這些凸塊電性連接至封裝基板21〇。底膠24〇 配置於晶片220與封裝基板210之間,以包覆這些凸塊 230 〇 封裝基板210具有多個導電柱212與多個銲球墊 214,其中這些導電柱212分別貫穿封裝基板21〇,且這些 銲球墊214分別配置於這些導電柱212上。此外,這些銲 球250配置於這些鋅球墊214上。值得注意的是,晶片封 裝體200a與200b經由銲球250彼此電性連接,而晶片封 1254462 16495twf.doc/006 裝體200b經由銲球250電性連接至封裝基板12。 相較於習知的堆疊型晶片封裝結構100,此種習知的 堆疊型晶片封裝結構10雖然製程複雜度較低,但此種習知 的堆疊型晶片封裝結構10的厚度卻是大於習知的堆疊型 晶片封裝結構100的厚度。 【發明内容】 有鑒於此,本發明的目的就是在提供一種晶片封裝 體,其整體的厚度較薄。 此外,本發明的再一目的就是提供一種堆疊型晶片封 裝結構,其具有較高的封裝積集度。 另外,本發明的又一目的就是提供一種晶片封裝體的 製造方法,以提高封裝積集度。 基於上述目的或其他目的,本發明提出一種晶片封裝 體,其包括一可撓性電路板、一第一晶片與一第二晶片, 其中可撓性電路板係折彎以形成一容置空間。第一晶片與 第二晶片分別配置於可撓性電路板上,並分別與可撓性電 路板電性連接。此外,第一晶片與第二晶片位於容置空間 内,且第一晶片位於第二晶片上方。 依照本發明實施例,晶片封裝體更可以包括一黏著 層,其配置於第一晶片與第二晶片之間,以固定第一晶片 與第二晶片之間的相對位置。 依照本發明實施例,可撓性電路板可以包括一可撓性 基材與一圖案化線路層,其中圖案化線路層配置於可撓性 基材上。第一晶片與第二晶片分別配置於圖案化線路層 1254462 16495twfdoc/〇〇6 亚與圖案化線路層電性連接 工 L <上〇 其暴撓縣材^具有乡個貫孔, 括多個外部連接端子 ^此外,晶片封裝體更可以包 外部連接端子分別經。置於這些貫孔内,且每一 及/或第二晶片。另外,,b、树層電性連接至第-晶片 料,且鮮料填入這些·^些外部連接端子的材質可以是銲 可以是多個銲球。、内或者,這些外部連接端子也 依照本發明實施例,θ 晶 晶 凸塊,其配置於第—曰y日日片封衣脰更可以包括多個第一 片經由這些第—凸^與可撓性電路板之間,且第 片封裝體更可以包括接至可撓性電路板。此外 徺性電路板之間 =、丄底膝’其配置於第-晶片與可 體更可以包括多個第些第—凸塊。另外,晶片封裝 電路板之間,且第二:塊,其配置於第二晶片與可撓性 嬈性電路板。再者曰片、、由這些第一凸塊電性連接至可 其配置於第封裝體更可以包括—第二底膠, 凸塊。 ,、可撓性電路板之間,並包覆這些第二 依照本發明實 導線,且第-晶以、晶片封裝體更可以包括多條第-略板。此外,晶片些第一導線電性連接至可撓性電 配置於可撓性電路_衣歧更可以包括一第一封裝膠體,其 片。另外,晶片封穿邱兩,亚包覆這些第一導線與第一晶 經由這些第二導可以多條第二導線,且第二晶片 兒性連接至可撓性電路板。再者,晶片 1254462 16495twf.doc/〇〇6 封衮體更可以包括 板上,並包覆這些第1254462 16495twf.doc/006 IX. Description of the invention: [Technical field to which the invention pertains], the invention S has a 'face-mounted structure, and the system is related to a stacked chip package structure having a degree of integration into the package. In today's poor society, users are pursuing high-speed, high-quality two: multi-functional electronic products. As far as the appearance of the product is concerned, the electronic product is also moving towards a light, thin, short and small trend. In order to achieve the above objectives, the system concept is integrated into the circuit design. • It is known that a single chip can have multiple functions to save the number of chips disposed in electronic products. In addition, in terms of electronic packaging technology, in order to cope with the light, thin, short, and small design trends, the package design concept and chip scale package of multi-chip modules (Naqing, MCM) have also been developed. CSP) package design concept and the concept of stacked-type 4 crystal package design. The following describes several conventional stacked chip package structures. • ▲ Head 1 shows a schematic cross-sectional view of a stacked chip package structure. Referring to FIG. 1, a conventional stacked chip package structure (8) includes a package substrate 110, a wafer 12A, a 12%, a spacer 130, a plurality of wires 14 and a package. Encapsulant 150. The wafers 12〇3 and 12〇b are disposed on the package substrate, and the spacers 130 are disposed between the wafers 120a and 12%. The portion of the wire 14 is electrically connected between the wafer 12A and the package substrate u, and the other portions of the wire 140 are electrically connected to the crystal 12% and the package substrate 11〇5 1254462 16495twf.doc/〇〇 6 ' ^ between. Further, the encapsulant 150 is disposed on the package substrate no and covers the wires 140, the wafers 120a and 120b, and the spacers 130. Since the wafers 120a and 120b must be separated by a certain distance to facilitate the wire bonding process, the overall thickness of the conventional stacked wafer package structure 100 is further reduced by the thickness of the spacers 130. In addition, conventional stacked chip package structures 1 also cause heat dissipation problems. Therefore, in order to solve the above problems, it is known that another stacked type chip package structure has been developed. FIG. 2 is a cross-sectional view showing another conventional stacked chip package structure. Referring to FIG. 2, a conventional stacked chip package structure 10 includes a substrate 12 and a plurality of chip packages 200a, 200b, wherein the chip packages 20A, 200b are stacked on the package substrate 12, and It is electrically connected to the package substrate 12 . Each of the chip packages 2A, 2 includes a package substrate 210, a wafer 220, a plurality of bumps 230, a primer 240, and a plurality of solder balls 250. The bumps 230 and the bumps 230 are disposed on the package substrate 210, and the bumps 23 are disposed between the wafer 220 and the package substrate 21A, and the wafers 220 are electrically connected to the package substrate 21A via the bumps. The primer 24 is disposed between the wafer 220 and the package substrate 210 to cover the bumps 230. The package substrate 210 has a plurality of conductive pillars 212 and a plurality of solder ball pads 214, wherein the conductive pillars 212 respectively penetrate the package substrate 21 The solder ball pads 214 are respectively disposed on the conductive pillars 212. Further, these solder balls 250 are disposed on these zinc ball pads 214. It is to be noted that the wafer packages 200a and 200b are electrically connected to each other via the solder balls 250, and the wafer package 1254462 16495 twf.doc/006 package 200b is electrically connected to the package substrate 12 via the solder balls 250. Compared with the conventional stacked chip package structure 100, the conventional stacked chip package structure 10 has a lower process complexity, but the thickness of the conventional stacked chip package structure 10 is larger than that of the conventional one. The thickness of the stacked wafer package structure 100. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a chip package having a thin overall thickness. Further, it is still another object of the present invention to provide a stacked type wafer package structure which has a high degree of package integration. Further, it is still another object of the present invention to provide a method of manufacturing a chip package to improve package integration. Based on the above or other objects, the present invention provides a chip package including a flexible circuit board, a first wafer, and a second wafer, wherein the flexible circuit board is bent to form an accommodation space. The first wafer and the second wafer are respectively disposed on the flexible circuit board and electrically connected to the flexible circuit board. Further, the first wafer and the second wafer are located in the accommodating space, and the first wafer is located above the second wafer. According to an embodiment of the invention, the chip package may further include an adhesive layer disposed between the first wafer and the second wafer to fix a relative position between the first wafer and the second wafer. In accordance with an embodiment of the invention, a flexible circuit board can include a flexible substrate and a patterned wiring layer, wherein the patterned wiring layer is disposed on the flexible substrate. The first wafer and the second wafer are respectively disposed on the patterned circuit layer 1254462 16495twfdoc/〇〇6 and the patterned circuit layer electrical connection L < the upper 〇 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县External connection terminals ^ In addition, the chip package can be separately packaged with external connection terminals. Placed in these through holes, and each and/or second wafer. In addition, b, the tree layer is electrically connected to the first wafer, and the material of the external connection terminals filled with the fresh material may be a solder which may be a plurality of solder balls. In addition, these external connection terminals are also in accordance with the embodiment of the present invention, the θ crystal bumps, which are disposed on the first 日 日 日 封 封 可以 可以 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由Between the flexible circuit boards, and the first package may further comprise a flexible circuit board. In addition, between the flexible circuit boards, the bottom knees, which are disposed on the first wafer and the body, may include a plurality of the first first bumps. In addition, between the chip package boards, and a second: block, which is disposed on the second wafer and the flexible flexible circuit board. Further, the cymbals are electrically connected to the first bumps to be disposed on the first package, and may further include a second primer, a bump. Between the flexible circuit boards, and covering the second solid wires according to the present invention, and the first, the chip package may further include a plurality of first-slice plates. In addition, the first conductive wires of the wafer are electrically connected to the flexible electrical circuit, and the flexible circuit may further comprise a first encapsulant, the film. In addition, the wafer is sealed by two, and the first wires and the first crystals are covered by the second wires, and the second wires are connected to the flexible circuit board. Furthermore, the wafer 1254462 16495twf.doc/〇〇6 can also include the board and wrap these
其配置於可撓性電路 基於上述目的或並他目;7 片封裝結構,其包括多明提一 j ^體包括—可撓性電路板、-第—Γ連接。母— 片與多個外部連接端子, =曰曰片、-第二晶 容置空間。此外,可撓性^电路板折彎以形成- 於可挽性基材上之—圖案“路ί 基材與配置 多個貫孔,其暴露出部分圖案化魏;中^糾基材具有 ;片分別配置於圖案化線路層上,並;別:::片與第二 。此外’第-晶片與第二晶片線路層 置於這些貫孔内::=這些外部連接端子分別配 電性連接至筮曰 邛連接端子經由圖案化嗖路岛 由對應之外部連接端子電性連接至另封裝體經 依照本發明實施例,堆日、衣肢。 —共同承載器,而這些晶片構更可以包括 並與共同承載器電性連接。此外,共承載器上, 板或導線架。 /、 7载杰可以是電路 依,本發明實施例,每—晶片封裝體更可以 者層’其配置於第一晶片與第二晶片,、黏 片與第二晶片之間的相對位置。 以固疋第一晶 端子ίίΐ發明實施例’每—晶片封裝體之這此外部連拉 而子之材質可以是銲料,且銲料填人這些貫_。=接 货田 $ 型 晶 1254462 】6495twf.doc/006 母—晶片封裝體之這些外部連接 依照本發明實施例,每— =二個=: 弟一凸塊,其配置於第一晶片愈可样=更可以包括多個 -晶片經由這些第一凸塊電:間,且第 1每—晶片封裝體更可以包括—第4;; Ϊ路板 曰曰月與可撓性電路板之間,並 第^配置於弟 母-晶片封裝體更可以包括多個第凸塊。另外, 晶片與可撓性電路板之間,且 :’其配置於第二 電性連接至可触電路板。再者—、:由<些第二凸塊 包括-第二底膠,其配置於第,=封裝體更可以 間,並包覆這些第二凸塊。 一可換性電路板之 依照本發明實施例,每—晶 弟—導線,且第一晶片經由 導包括多條 ::r:。此外,每,封裝=至= 瓜肢,其配置於可撓性電路板上,承、弟一封I 第一晶片。另外,每一曰片 “已後14些第一導線與 再者’每-晶片封裝體更可撓性電路板 置於可撓性電路板上,並包:;弟二:裳膠體’其f 基於上述目的或其他目的與:二晶片 體:製r法’其包括下列步驟。首先,種第晶片封 弟—日日片與一可撓性電路板,並 晶片 ,性基材與配置於可撓性^ 板包括 在可撓性基材内已形成多 ^化線路層, 貝孔其恭路出部分圖案化 且第二晶片經由這:第: •-晶片封連ί至可撓性電路板 10 1254462 16495twf.doc/006 路層。然後,將第一晶片與第二晶片配置於可撓性電路板 上,以使第一晶片與第二晶片分別電性連接至圖案化線路 層。接著,將可撓性電路板彎折,以形成一容置空間,其 中第一晶片與第二晶片位於容置空間内,且第一晶片位於 第二晶片上方。 依照本發明實施例,晶片封裝體的製造方法更可以在 第一晶片與第二晶片之間形成一黏著層,以固定第一晶片 與第二晶片之間的相對位置。 依照本發明實施例,晶片封裝體的製造方法更可以在 這些貫孔内形成多個外部連接端子,且每一外部連接端子 分別經由圖案化線路層電性連接至第一晶片及/或第二晶 片。此外,形成這些外部連接端子的方法可以是將銲料填 入這些貫孔内。或者,形成這些外部連接端子的方法可以 是形成多個録球。 依照本發明實施例,晶片封裝體的製造方法更可以在 第一晶片與可撓性電路板之間形成多個第一凸塊,且第一 晶片經由這些第一凸塊電性連接至可撓性電路板。然後, 在第一晶片與可撓性電路板之間形成一第一底膠,以包覆 這些第一凸塊。接著,在第二晶片與可撓性電路板之間形 成多個第二凸塊,且第二晶片經由這些第二凸塊電性連接 至可撓性電路板。隨後,在第二晶片與可撓性電路板之間 形成一第二底膠,以包覆這些第二凸塊。 依照本發明實施例,晶片封裝體的製造方法更可以形 成多條第一導線,且這些第一導線分別連接第一晶片與可 1254462 f 16495twf.d〇c/〇〇6 ίΐϊΐ:额,在可撓性電路板上形成—第一封裝膠 二導線匕些ΪΤ導線與第—晶片。接著,形成多條第 板、Q ^些第—導線分別連接第U與可撓性電路It is disposed on the flexible circuit based on the above purpose or in other aspects; a seven-piece package structure including a multi-layered body including a flexible circuit board, a - first connection. The mother-chip and a plurality of external connection terminals, = 曰曰, - second crystal accommodation space. In addition, the flexible circuit board is bent to form a pattern on the tractable substrate, and the plurality of through holes are disposed, which expose a portion of the patterned wei; The sheets are respectively disposed on the patterned circuit layer, and are: :: sheets and second. Further, the 'first wafer and the second wafer wiring layer are placed in the through holes::= These external connection terminals are respectively electrically connected to The 筮曰邛 connection terminal is electrically connected to the other package via the corresponding external connection terminal via the patterned 嗖 island, according to the embodiment of the invention, the stack, the common body, and the wafer structure may further comprise Electrically connected to the common carrier. In addition, the common carrier, the board or the lead frame. /, 7 can be the circuit, in the embodiment of the present invention, each chip package is more layerable The relative position between the wafer and the second wafer, and between the adhesive sheet and the second wafer. The first crystal terminal is fixed. In the embodiment of the invention, the external material of the wafer package may be solder. And the solder fills in these _.=货田型晶1254462 】6495twf.doc/006 These external connections of the mother-chip package are in accordance with the embodiment of the present invention, each -= two =: a bump, the configuration of the first wafer is more like = more The plurality of wafers may be electrically connected via the first bumps: and the first per-chip package may further include - 4th; the circuit board between the moon and the flexible circuit board, and The chip-chip package may further include a plurality of bumps. In addition, between the chip and the flexible circuit board, and: 'the second electrode is electrically connected to the touch circuit board. The second bump includes a second primer, which is disposed at the first, and the package is more likely to cover the second bumps. A replaceable circuit board according to an embodiment of the present invention, Each - the younger brother - the wire, and the first wafer includes a plurality of strips::r:. In addition, each package = to = melon limb, which is disposed on the flexible circuit board, and the younger brother In addition, each of the dies "has been followed by 14 first conductors and again" per-chip package more flexible circuit board placed Circuit board, and the package:; brother II: Colloidal Sang 'which f or the above object and other objects: two chip body: manufactured by methods r' which includes the following steps. First, the first wafer-season-day film and a flexible circuit board, and the wafer, the substrate and the flexible substrate are included in the flexible substrate to form a multi-layer circuit layer, The hole is partially patterned and the second wafer is passed through this: • - wafer bonded to the flexible circuit board 10 1254462 16495twf.doc / 006 road layer. Then, the first wafer and the second wafer are disposed on the flexible circuit board to electrically connect the first wafer and the second wafer to the patterned wiring layer, respectively. Next, the flexible circuit board is bent to form an accommodating space, wherein the first wafer and the second wafer are located in the accommodating space, and the first wafer is located above the second wafer. According to an embodiment of the invention, the method of fabricating the chip package further forms an adhesive layer between the first wafer and the second wafer to fix the relative position between the first wafer and the second wafer. According to an embodiment of the present invention, a method of manufacturing a chip package may further form a plurality of external connection terminals in the through holes, and each of the external connection terminals is electrically connected to the first wafer and/or the second via a patterned circuit layer, respectively. Wafer. Further, the method of forming these external connection terminals may be to fill solder into the through holes. Alternatively, the method of forming these external connection terminals may be to form a plurality of recorded balls. According to an embodiment of the present invention, a method of manufacturing a chip package may further form a plurality of first bumps between the first wafer and the flexible circuit board, and the first wafer is electrically connected to the flexible via the first bumps. Sex board. Then, a first primer is formed between the first wafer and the flexible circuit board to cover the first bumps. Next, a plurality of second bumps are formed between the second wafer and the flexible circuit board, and the second wafer is electrically connected to the flexible circuit board via the second bumps. Subsequently, a second primer is formed between the second wafer and the flexible circuit board to cover the second bumps. According to an embodiment of the present invention, a method of manufacturing a chip package may further form a plurality of first wires, and the first wires are respectively connected to the first wafer and may be 1254462 f 16495 twf.d〇c/〇〇6 ΐϊΐ: The flexible circuit board is formed with a first package of two wires, a plurality of wires, and a first wafer. Then, a plurality of first plates are formed, and the Q-th-first wires are respectively connected to the U-th and the flexible circuit
Iri,在可撓性電路板上形成—第二封裝膠體,以包 復这些弟二導線與第二晶片。 曰,本發明所形成之堆叠型晶片封裝結構或是 B曰片封1_厚度具有較高的封裝積集度。Iri, a second encapsulant is formed on the flexible circuit board to cover the two wires and the second wafer. In other words, the stacked wafer package structure formed by the present invention or the B-chip package 1_thick has a high degree of package integration.
為_發日狀上述和其他目的、特徵和優點能更明顯 下靖軸佳實施例,並配合賴目^,作詳細說 明如下。 【實施方式】 【第一實施例】 f 3A至圖3C繪示依照本發明第一實施例之堆疊型晶 片于衣、,構的製造流程剖面示意圖。請參考冑3A,本實施 =之堆宜型晶片封裝結構的製造方法包括下列步驟。首 先,提供-可撓性電路板31G,而可撓性電路板31〇包括 一可撓性基材312與配置於可撓性基材312上之-圖案化 ,路層314。本實施例中,可撓性基材312的材質可以是 德亞胺(polyimide)歧其他可撓性塑膠材料。 *然後,在可撓性基材312内形成多個貫孔312&,且這 些=孔312a暴露出部分圖案化線路層314。此外,形成這 些貫孔312a的方法可以是姓刻製程或是其他能夠形成貫 孔的製程。接著,提供晶片320a與32〇b,並將晶片32〇a 與320b配置於可撓性電路板31〇上,以使得晶片32加與 12 1254462 16495twf.doc/006 320b刀別黾性連接至圖案化線路層3μ。其中,晶片 與320b可以分別以覆晶接合技術電性連接至圖案化線路 層 314 〇 就本實施例而言,凸塊330a可以是形成於圖案化線 路層/14上或是在晶片32〇3上,然後再經過迴銲(refl〇w) 以使知曰曰片320a能夠藉由凸塊330a電性連接至圖案化線 路層314電性連接。同樣地,凸塊33%也可以是形成於圖 案路層314上或是在晶片320b上,然後再經過迴銲以 ^件晶片320b能夠藉由凸塊33〇b電性連接至圖案化線路 1 314電性連接。接著,本實施例也可以在晶片%如與可 祕電路板31G之間形成—底膠340a,以包覆這些凸塊 33〇a。同樣地’本實施例也可以在晶片3施與可挽性電路 板310之間形成一底膠3獅,以包覆這些凸塊3勘。 =考圖3B,將可撓性電路板31〇彎折以形成一容 f工間31〇a,此時,晶片320a與320b係位於容置空間31〇a _ ^晶片32〇a位於晶片32〇b上方。此外,在折彎此可 :二路板310之前,也可以在晶片施或鳩上形成 H35Q’以固定晶片32Qa與32%之間的相對位置。 外部連接端二 ^ 母杯球36〇分別經由圖案化線路 晶片遍心或晶片通。此外,這些 將三 可以疋恶鉛銲球或是錫鉛銲球。然而,也可以是 將揲鉛銲料、錫鉛銲料、苴 j以疋 填入部分貫们19力 崎枓或其他導電材質 刀貝孔312a内,以形成外部連接端 13 1254462 16495twf.doc/006 - 不)。至此,大致完成晶片封裝體300a的製作。 請參考圖3C,重複上述之步驟,以製造出晶片封袭 體300b與300c。然後,提供一共用承載器22,而共用承 載器22具有多個銲球墊22a。在本實施例中,共用承載器 22可以是電路板或是其他的類型的承載器。然後,將晶片 封裝體300a、300b與300c堆疊於共用承載器22上。接著, 對於上述結構進彳于迴銲製程(re^]〇w pr〇cess),以使得這 鲁 些晶片封裝體300a、3⑽b與300c彼此電性,並使得晶片5 封裝體3〇〇c與共用承載器22連接。值得注意的是;=沒 有使用共用承载器22的情況下,晶片封裝體3⑻a、3〇〇b /、300c也可以先結為一體而直接配置於一電路板上戋一 電子裝置上。 — 在本實施例中,各個晶片封裝體3⑻a、3〇〇b與3〇〇c 之晶片320a與320b均是採用覆晶接合技術電性連接至可 撓性電路板310。然而,各個晶片封裝體3〇〇a、3⑻b與3〇〇c 鲁巾之晶片320a與320b也可以採用打線接合技術或是其他 晶片封裝技術而電性連接至可撓性電路板3丨〇。 、然後,在共用承載器22之銲球墊22a上形成多個銲 球24 ’以完成堆疊型晶片封裝結構2〇的製作。此堆疊型 晶片曰封裝結# 20便可以藉由_ 24配置於一電路板上。 值得-提的是,本實施例並不限制堆疊型晶片封裝結構2〇 内之晶片封裝體的數量。 於每一個晶片封裝體3〇〇a、3⑻1?與3〇(^的厚度可 以、交薄,因此堆疊型晶片封裝結構2〇的整體厚度也隨著變 14 1254462 16495twf.doc/006 _ 薄。此外,本實施例之堆疊型晶片封裝結構20所使用的製 程技術較為成熟。另外,由於每一個晶片封裝體3⑻a、3〇〇b 與300c均是單難造而成,因此不良品之晶片封裝體不會 使用至堆疊型晶片封裝結構2〇内,以提高堆疊型晶片封裝 結構20的良率。 【弟二貫施例】 圖4 A至圖4 B繪示依照本發明第二實施例之堆疊型晶 • 片封裝結構的製造流程剖面示意圖。請參考圖4A,本f施 Φ例與上述實施例相似,二者主要不同之處在於 • 410a與420b分別配置於可撓性電路板31〇上,然後形成 多條導線420a與420b。晶片410a藉由導線420a電性連 接至圖案化線路層314,而晶片41〇b藉由導線42%電性 連接至圖案化線路層314。接著,在可撓性電路板31〇上 分別形成封裝膠體430a與430b,其中封裝膠體430a包覆 晶片41〇a與導線42〇a。此外,封裝膠體43〇b包覆晶片&诎 與導線420a。 _ 然後,彎折可撓性電路板31Q,以形成—容置空間 310a’其中晶片41〇a與4l〇b位於容置空間310a内,且晶 片410a位於晶片41〇b上方。此外,在折彎此可撓性電路 板310之前,也可以在封裝膠體430a或430b上形成—黏 著層440 ’以固定晶片410a與410b之間的相對位置。至 此’初步完成晶片封裝體4〇〇a的製作。 接著,將無錯焊料、錫錯焊料、其他類型的焊料或是 其他導電材料填入部分這些貫孔312a内,以形成多個外部 15 1254462 16495twf.doc/006 連接端子450。铁而,μ、+、廢:#办丨丄 …、向上述貝施例中之銲球360也可以取 代本貫施例之外部連接端子450。 明,考圖4B’重複上述步驟,以形成晶片封裝體400b t她。然後,將這些晶片封裝體_a、400b與400c堆 豐於共★同承載器22上,且這些晶片封裝體_a、與 =接端子_彼此電性連接。此外,晶片封 衣體 *由外部連接端子440電性連接至丘同承載哭 L同樣地、,此堆疊型晶片封裝結構30也可;;藉由㈣ ^solder)或預銲料(pre_s〇kier)配置於一電路板(未緣 丁)上另外,如同上述實施例,在沒有使用共用承載哭 22的情況下,晶片封裝體.、與她也可以= 為-體而直接配置於—電路板上或—電子裝置上。 值知· ^的疋,各個晶片封裝體4⑻b與4〇〇c 之曰曰片410a與410b均採用打線接合技術電性連接至可垆 性電路板310。然而,上述各實施例之各個晶片也可以^ 別以覆晶接合技術、打線接合技術或其他晶片封裝技術而 電,連接至可撓性電_ 31G。此外,本實施例並不限制 堆豐型晶片封裝結構30内之晶片封裝體的數量。 綜上所述,本發明至少具有下列優點·· 一、 本發明之堆疊型晶片封裝結構或是晶片封裝俨 厚度較薄。 1 二、 本發明之堆疊型晶片封裝結構或是晶片封裝體 應用於覆晶接合製程或是打線接合製程。 二、本發明所使用的製程技術較為成熟,因此本發明 16 1254462 16495twf.doc/006 之製造方法具有較佳的製程良率。 和範圍内,自此技#者,在不脫離本發明之精神 之申;;=二:本雜 L圖式間早說明】The above and other objects, features and advantages of the present invention can be more clearly seen in the following examples, and are explained in detail below. [Embodiment] [First Embodiment] f 3A to 3C are schematic cross-sectional views showing a manufacturing process of a stacked type wafer in accordance with a first embodiment of the present invention. Please refer to 胄3A. The manufacturing method of the stack-type chip package structure of the present embodiment includes the following steps. First, a flexible circuit board 31G is provided, and the flexible circuit board 31A includes a flexible substrate 312 and a patterned, road layer 314 disposed on the flexible substrate 312. In this embodiment, the material of the flexible substrate 312 may be polyimide or other flexible plastic material. * Then, a plurality of through holes 312 & amps are formed in the flexible substrate 312, and these = holes 312a expose a portion of the patterned wiring layer 314. In addition, the method of forming the through holes 312a may be a process of surname or other process capable of forming a through hole. Next, the wafers 320a and 32B are provided, and the wafers 32A and 320b are disposed on the flexible circuit board 31A, so that the wafer 32 is attached to the pattern with 12 1254462 16495 twf.doc/006 320b. The circuit layer is 3μ. The wafers 320b can be electrically connected to the patterned circuit layer 314 by a flip chip bonding technique. For the present embodiment, the bumps 330a can be formed on the patterned circuit layer / 14 or on the wafer 32 〇 3 Then, it is reflowed (refl〇w) so that the knowledge piece 320a can be electrically connected to the patterned circuit layer 314 by the bumps 330a. Similarly, the bumps 33% may be formed on the pattern layer 314 or on the wafer 320b, and then reflowed so that the wafer 320b can be electrically connected to the patterned line 1 by the bumps 33〇b. 314 electrical connection. Next, in this embodiment, a primer 340a may be formed between the wafer % and the secret circuit board 31G to cover the bumps 33A. Similarly, this embodiment can also form a primer 3 lion between the wafer 3 and the slidable circuit board 310 to cover the bumps. Referring to FIG. 3B, the flexible circuit board 31 is bent to form a cavity 31〇a. At this time, the wafers 320a and 320b are located in the accommodating space 31〇a_^the wafer 32〇a is located on the wafer 32. Above 〇b. Further, before the two-way board 310 is bent, H35Q' may be formed on the wafer or the crucible to fix the relative position between the wafer 32Qa and 32%. The external connection terminals 2 ^ mother cup balls 36 are respectively passed through the patterned wiring wafer or the wafer. In addition, these three can dislike lead solder balls or tin-lead solder balls. However, it is also possible to fill the lead-lead solder, the tin-lead solder, and the 苴j into the nipple hole 312a of the ferrule or other conductive material to form the external connection end 13 1254462 16495 twf.doc/006 - Do not). Thus far, the fabrication of the chip package 300a is substantially completed. Referring to Figure 3C, the above steps are repeated to fabricate wafer entrapment bodies 300b and 300c. Then, a common carrier 22 is provided, and the shared carrier 22 has a plurality of solder ball pads 22a. In this embodiment, the shared carrier 22 can be a circuit board or other type of carrier. Then, the wafer packages 300a, 300b, and 300c are stacked on the common carrier 22. Then, the above structure is applied to the reflow process (re^) 以w pr〇cess) so that the chip packages 300a, 3(10)b and 300c are electrically connected to each other, and the wafer 5 package 3〇〇c and The shared carrier 22 is connected. It is to be noted that, in the case where the shared carrier 22 is not used, the chip packages 3 (8) a, 3 〇〇 b / , 300c may be integrally formed and integrated directly on a single electronic device on a circuit board. - In the present embodiment, the wafers 320a and 320b of the respective chip packages 3 (8) a, 3 〇〇 b and 3 〇〇 c are electrically connected to the flexible circuit board 310 by flip chip bonding. However, the wafers 320a and 320b of the respective chip packages 3a, 3(8)b and 3〇〇c can also be electrically connected to the flexible circuit board 3 by wire bonding or other chip packaging technology. Then, a plurality of solder balls 24' are formed on the solder ball pads 22a of the shared carrier 22 to complete the fabrication of the stacked wafer package structure 2''. The stacked wafer package package #20 can be disposed on a circuit board by _24. It is worth mentioning that this embodiment does not limit the number of chip packages in the stacked chip package structure 2A. The thickness of each of the chip packages 3〇〇a, 3(8)1 and 3〇(^ can be thinned, so the overall thickness of the stacked chip package structure 2〇 is also thinner with the change of 14 1254462 16495 twf.doc/006 _. In addition, the process technology used in the stacked chip package structure 20 of the present embodiment is relatively mature. In addition, since each of the chip packages 3 (8) a, 3 〇〇 b, and 300 c is difficult to manufacture, the chip package of the defective product is The body is not used in the stacked chip package structure 2 to improve the yield of the stacked chip package structure 20. [2] FIG. 4A to FIG. 4B illustrate a second embodiment according to the present invention. Schematic diagram of the manufacturing process of the stacked crystal chip package structure. Referring to FIG. 4A, the Φ example is similar to the above embodiment, and the main difference is that the 410a and 420b are respectively disposed on the flexible circuit board 31〇. Then, a plurality of wires 420a and 420b are formed. The wafer 410a is electrically connected to the patterned wiring layer 314 by the wires 420a, and the wafer 41〇b is electrically connected to the patterned wiring layer 314 by the wires 42%. Then, Flexible circuit board 31 The encapsulants 430a and 430b are respectively formed, wherein the encapsulant 430a covers the wafer 41〇a and the wires 42〇a. Further, the encapsulant 43〇b covers the wafer & 诎 and the wires 420a. _ Then, the flexible circuit is bent The board 31Q is formed to accommodate the accommodating space 310a' in which the wafers 41A and 〇b are located in the accommodating space 310a, and the wafer 410a is located above the wafer 41 〇b. Further, before the flexible circuit board 310 is bent The adhesive layer 440' may also be formed on the encapsulant 430a or 430b to fix the relative position between the wafers 410a and 410b. Thus, the fabrication of the chip package 4a is completed. Next, the solder-free solder, tin A wrong solder, other types of solder or other conductive material is filled into a portion of the through holes 312a to form a plurality of external 15 1254462 16495 twf.doc/006 connection terminals 450. Iron, μ, +, waste: #丨丄The solder ball 360 in the above-described embodiment can also replace the external connection terminal 450 of the present embodiment. The above steps are repeated to form the chip package 400b. Then, the chips are packaged. Heap of body_a, 400b and 400c The chip package _a and the terminal _a are electrically connected to each other. Further, the wafer package body * is electrically connected to the same by the external connection terminal 440 The stacked chip package structure 30 can also be disposed on a circuit board by (4) ^ solder or pre- solder (pre_s), in addition to the above embodiment, without sharing In the case of carrying the cry 22, the chip package, and her can also be directly placed on the circuit board or on the electronic device. For example, the wafers 410a and 410b of the respective chip packages 4(8)b and 4〇〇c are electrically connected to the flexible circuit board 310 by wire bonding techniques. However, each of the wafers of the above embodiments may be electrically connected to the flexible _31G by flip chip bonding, wire bonding, or other chip packaging techniques. Moreover, this embodiment does not limit the number of chip packages within the stacked wafer package structure 30. In summary, the present invention has at least the following advantages: 1. The stacked chip package structure or the chip package of the present invention has a thin thickness. 1 . The stacked chip package structure or the chip package of the present invention is applied to a flip chip bonding process or a wire bonding process. 2. The process technology used in the present invention is relatively mature, and therefore the manufacturing method of the invention 16 1254462 16495 twf.doc/006 has a better process yield. And within the scope, since this technology #, without departing from the spirit of the invention;; = two: this miscellaneous L schema early description]
^ 9示^知堆豐型晶片封裝結構的剖面示意圖。 圖。會示另—習知堆疊型晶片封裝結構的剖面示意 圖3A至圖3C緣示依照本發明第—實施例之堆疊型晶 片封I結構的製造流程剖面示意圖。 圖4A至圖4B纟會示依照本發明第二實施例之堆疊型晶 片封裝結構的製造流程剖面示意圖。 【主要元件符號說明】 10、100 :習知的堆疊型晶片封裝結構 12、110、210 :封裝基板 20、30 :堆疊型晶片封裝結構 22a、214 :鋅球墊 24、250、360 :銲球 120a、120b、220、320a、320b、410a、410b :晶片 130 :間隔物 140、420a、420b :導線 150、430a、430b ··封裝膠體 200a、200b、300a、300b、300c、400a、400b、400c : 1254462 16495twf.doc/006 晶片封裝體 212 :導電柱 230、330a、330b :凸塊 240、340a、340b :底膠 310 :可撓性電路板 310a :容置空間 312 :可撓性基材 312a :貫孔 314 :圖案化線路層 350、440 :黏著層 450 :外部連接端子^9 shows a schematic cross-sectional view of the stacking structure of the wafer. Figure. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3A to FIG. 3C are schematic cross-sectional views showing a manufacturing process of a stacked type wafer package I structure according to a first embodiment of the present invention. 4A to 4B are cross-sectional views showing the manufacturing process of the stacked type wafer package structure in accordance with the second embodiment of the present invention. [Main component symbol description] 10, 100: conventional stacked chip package structure 12, 110, 210: package substrate 20, 30: stacked chip package structure 22a, 214: zinc ball pad 24, 250, 360: solder ball 120a, 120b, 220, 320a, 320b, 410a, 410b: wafer 130: spacers 140, 420a, 420b: wires 150, 430a, 430b · encapsulants 200a, 200b, 300a, 300b, 300c, 400a, 400b, 400c 1254462 16495twf.doc/006 Chip package 212: conductive pillars 230, 330a, 330b: bumps 240, 340a, 340b: primer 310: flexible circuit board 310a: housing space 312: flexible substrate 312a :through hole 314: patterned circuit layer 350, 440: adhesive layer 450: external connection terminal
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