TWI254462B - Stacked chip package structure, chip package and fabricating method thereof - Google Patents

Abstract

A chip package is provided, and the chip package includes a flexible circuit board (FPC), a first chip and a second chip. The FPC is bent to form a receive space, and the first chip and the second chip are disposed on the FPC and electrically connected to FPC, respectively. Additionally, the first chip and the second chip is disposed in the receive space, and the first chip is above the second chip. As mentioned above, the thickness of the chip package of the present invention is thinner. Moreover, a stacked chip package structure and a fabricating method for the chip package are further provided.

Description

1254462 16495twf.doc/006 IX. Description of the invention: [Technical field to which the invention pertains], the invention S has a 'face-mounted structure, and the system is related to a stacked chip package structure having a degree of integration into the package. In today's poor society, users are pursuing high-speed, high-quality two: multi-functional electronic products. As far as the appearance of the product is concerned, the electronic product is also moving towards a light, thin, short and small trend. In order to achieve the above objectives, the system concept is integrated into the circuit design. • It is known that a single chip can have multiple functions to save the number of chips disposed in electronic products. In addition, in terms of electronic packaging technology, in order to cope with the light, thin, short, and small design trends, the package design concept and chip scale package of multi-chip modules (Naqing, MCM) have also been developed. CSP) package design concept and the concept of stacked-type 4 crystal package design. The following describes several conventional stacked chip package structures. • ▲ Head 1 shows a schematic cross-sectional view of a stacked chip package structure. Referring to FIG. 1, a conventional stacked chip package structure (8) includes a package substrate 110, a wafer 12A, a 12%, a spacer 130, a plurality of wires 14 and a package. Encapsulant 150. The wafers 12〇3 and 12〇b are disposed on the package substrate, and the spacers 130 are disposed between the wafers 120a and 12%. The portion of the wire 14 is electrically connected between the wafer 12A and the package substrate u, and the other portions of the wire 140 are electrically connected to the crystal 12% and the package substrate 11〇5 1254462 16495twf.doc/〇〇 6 ' ^ between. Further, the encapsulant 150 is disposed on the package substrate no and covers the wires 140, the wafers 120a and 120b, and the spacers 130. Since the wafers 120a and 120b must be separated by a certain distance to facilitate the wire bonding process, the overall thickness of the conventional stacked wafer package structure 100 is further reduced by the thickness of the spacers 130. In addition, conventional stacked chip package structures 1 also cause heat dissipation problems. Therefore, in order to solve the above problems, it is known that another stacked type chip package structure has been developed. FIG. 2 is a cross-sectional view showing another conventional stacked chip package structure. Referring to FIG. 2, a conventional stacked chip package structure 10 includes a substrate 12 and a plurality of chip packages 200a, 200b, wherein the chip packages 20A, 200b are stacked on the package substrate 12, and It is electrically connected to the package substrate 12 . Each of the chip packages 2A, 2 includes a package substrate 210, a wafer 220, a plurality of bumps 230, a primer 240, and a plurality of solder balls 250. The bumps 230 and the bumps 230 are disposed on the package substrate 210, and the bumps 23 are disposed between the wafer 220 and the package substrate 21A, and the wafers 220 are electrically connected to the package substrate 21A via the bumps. The primer 24 is disposed between the wafer 220 and the package substrate 210 to cover the bumps 230. The package substrate 210 has a plurality of conductive pillars 212 and a plurality of solder ball pads 214, wherein the conductive pillars 212 respectively penetrate the package substrate 21 The solder ball pads 214 are respectively disposed on the conductive pillars 212. Further, these solder balls 250 are disposed on these zinc ball pads 214. It is to be noted that the wafer packages 200a and 200b are electrically connected to each other via the solder balls 250, and the wafer package 1254462 16495 twf.doc/006 package 200b is electrically connected to the package substrate 12 via the solder balls 250. Compared with the conventional stacked chip package structure 100, the conventional stacked chip package structure 10 has a lower process complexity, but the thickness of the conventional stacked chip package structure 10 is larger than that of the conventional one. The thickness of the stacked wafer package structure 100. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a chip package having a thin overall thickness. Further, it is still another object of the present invention to provide a stacked type wafer package structure which has a high degree of package integration. Further, it is still another object of the present invention to provide a method of manufacturing a chip package to improve package integration. Based on the above or other objects, the present invention provides a chip package including a flexible circuit board, a first wafer, and a second wafer, wherein the flexible circuit board is bent to form an accommodation space. The first wafer and the second wafer are respectively disposed on the flexible circuit board and electrically connected to the flexible circuit board. Further, the first wafer and the second wafer are located in the accommodating space, and the first wafer is located above the second wafer. According to an embodiment of the invention, the chip package may further include an adhesive layer disposed between the first wafer and the second wafer to fix a relative position between the first wafer and the second wafer. In accordance with an embodiment of the invention, a flexible circuit board can include a flexible substrate and a patterned wiring layer, wherein the patterned wiring layer is disposed on the flexible substrate. The first wafer and the second wafer are respectively disposed on the patterned circuit layer 1254462 16495twfdoc/〇〇6 and the patterned circuit layer electrical connection L < the upper 〇 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县External connection terminals ^ In addition, the chip package can be separately packaged with external connection terminals. Placed in these through holes, and each and/or second wafer. In addition, b, the tree layer is electrically connected to the first wafer, and the material of the external connection terminals filled with the fresh material may be a solder which may be a plurality of solder balls. In addition, these external connection terminals are also in accordance with the embodiment of the present invention, the θ crystal bumps, which are disposed on the first 日 日 日 封 封 可以 可以 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由 经由Between the flexible circuit boards, and the first package may further comprise a flexible circuit board. In addition, between the flexible circuit boards, the bottom knees, which are disposed on the first wafer and the body, may include a plurality of the first first bumps. In addition, between the chip package boards, and a second: block, which is disposed on the second wafer and the flexible flexible circuit board. Further, the cymbals are electrically connected to the first bumps to be disposed on the first package, and may further include a second primer, a bump. Between the flexible circuit boards, and covering the second solid wires according to the present invention, and the first, the chip package may further include a plurality of first-slice plates. In addition, the first conductive wires of the wafer are electrically connected to the flexible electrical circuit, and the flexible circuit may further comprise a first encapsulant, the film. In addition, the wafer is sealed by two, and the first wires and the first crystals are covered by the second wires, and the second wires are connected to the flexible circuit board. Furthermore, the wafer 1254462 16495twf.doc/〇〇6 can also include the board and wrap these

It is disposed on the flexible circuit based on the above purpose or in other aspects; a seven-piece package structure including a multi-layered body including a flexible circuit board, a - first connection. The mother-chip and a plurality of external connection terminals, = 曰曰, - second crystal accommodation space. In addition, the flexible circuit board is bent to form a pattern on the tractable substrate, and the plurality of through holes are disposed, which expose a portion of the patterned wei; The sheets are respectively disposed on the patterned circuit layer, and are: :: sheets and second. Further, the 'first wafer and the second wafer wiring layer are placed in the through holes::= These external connection terminals are respectively electrically connected to The 筮曰邛 connection terminal is electrically connected to the other package via the corresponding external connection terminal via the patterned 嗖 island, according to the embodiment of the invention, the stack, the common body, and the wafer structure may further comprise Electrically connected to the common carrier. In addition, the common carrier, the board or the lead frame. /, 7 can be the circuit, in the embodiment of the present invention, each chip package is more layerable The relative position between the wafer and the second wafer, and between the adhesive sheet and the second wafer. The first crystal terminal is fixed. In the embodiment of the invention, the external material of the wafer package may be solder. And the solder fills in these _.=货田型晶1254462 】6495twf.doc/006 These external connections of the mother-chip package are in accordance with the embodiment of the present invention, each -= two =: a bump, the configuration of the first wafer is more like = more The plurality of wafers may be electrically connected via the first bumps: and the first per-chip package may further include - 4th; the circuit board between the moon and the flexible circuit board, and The chip-chip package may further include a plurality of bumps. In addition, between the chip and the flexible circuit board, and: 'the second electrode is electrically connected to the touch circuit board. The second bump includes a second primer, which is disposed at the first, and the package is more likely to cover the second bumps. A replaceable circuit board according to an embodiment of the present invention, Each - the younger brother - the wire, and the first wafer includes a plurality of strips::r:. In addition, each package = to = melon limb, which is disposed on the flexible circuit board, and the younger brother In addition, each of the dies "has been followed by 14 first conductors and again" per-chip package more flexible circuit board placed Circuit board, and the package:; brother II: Colloidal Sang 'which f or the above object and other objects: two chip body: manufactured by methods r' which includes the following steps. First, the first wafer-season-day film and a flexible circuit board, and the wafer, the substrate and the flexible substrate are included in the flexible substrate to form a multi-layer circuit layer, The hole is partially patterned and the second wafer is passed through this: • - wafer bonded to the flexible circuit board 10 1254462 16495twf.doc / 006 road layer. Then, the first wafer and the second wafer are disposed on the flexible circuit board to electrically connect the first wafer and the second wafer to the patterned wiring layer, respectively. Next, the flexible circuit board is bent to form an accommodating space, wherein the first wafer and the second wafer are located in the accommodating space, and the first wafer is located above the second wafer. According to an embodiment of the invention, the method of fabricating the chip package further forms an adhesive layer between the first wafer and the second wafer to fix the relative position between the first wafer and the second wafer. According to an embodiment of the present invention, a method of manufacturing a chip package may further form a plurality of external connection terminals in the through holes, and each of the external connection terminals is electrically connected to the first wafer and/or the second via a patterned circuit layer, respectively. Wafer. Further, the method of forming these external connection terminals may be to fill solder into the through holes. Alternatively, the method of forming these external connection terminals may be to form a plurality of recorded balls. According to an embodiment of the present invention, a method of manufacturing a chip package may further form a plurality of first bumps between the first wafer and the flexible circuit board, and the first wafer is electrically connected to the flexible via the first bumps. Sex board. Then, a first primer is formed between the first wafer and the flexible circuit board to cover the first bumps. Next, a plurality of second bumps are formed between the second wafer and the flexible circuit board, and the second wafer is electrically connected to the flexible circuit board via the second bumps. Subsequently, a second primer is formed between the second wafer and the flexible circuit board to cover the second bumps. According to an embodiment of the present invention, a method of manufacturing a chip package may further form a plurality of first wires, and the first wires are respectively connected to the first wafer and may be 1254462 f 16495 twf.d〇c/〇〇6 ΐϊΐ: The flexible circuit board is formed with a first package of two wires, a plurality of wires, and a first wafer. Then, a plurality of first plates are formed, and the Q-th-first wires are respectively connected to the U-th and the flexible circuit

Iri, a second encapsulant is formed on the flexible circuit board to cover the two wires and the second wafer. In other words, the stacked wafer package structure formed by the present invention or the B-chip package 1_thick has a high degree of package integration.

The above and other objects, features and advantages of the present invention can be more clearly seen in the following examples, and are explained in detail below. [Embodiment] [First Embodiment] f 3A to 3C are schematic cross-sectional views showing a manufacturing process of a stacked type wafer in accordance with a first embodiment of the present invention. Please refer to 胄3A. The manufacturing method of the stack-type chip package structure of the present embodiment includes the following steps. First, a flexible circuit board 31G is provided, and the flexible circuit board 31A includes a flexible substrate 312 and a patterned, road layer 314 disposed on the flexible substrate 312. In this embodiment, the material of the flexible substrate 312 may be polyimide or other flexible plastic material. * Then, a plurality of through holes 312 & amps are formed in the flexible substrate 312, and these = holes 312a expose a portion of the patterned wiring layer 314. In addition, the method of forming the through holes 312a may be a process of surname or other process capable of forming a through hole. Next, the wafers 320a and 32B are provided, and the wafers 32A and 320b are disposed on the flexible circuit board 31A, so that the wafer 32 is attached to the pattern with 12 1254462 16495 twf.doc/006 320b. The circuit layer is 3μ. The wafers 320b can be electrically connected to the patterned circuit layer 314 by a flip chip bonding technique. For the present embodiment, the bumps 330a can be formed on the patterned circuit layer / 14 or on the wafer 32 〇 3 Then, it is reflowed (refl〇w) so that the knowledge piece 320a can be electrically connected to the patterned circuit layer 314 by the bumps 330a. Similarly, the bumps 33% may be formed on the pattern layer 314 or on the wafer 320b, and then reflowed so that the wafer 320b can be electrically connected to the patterned line 1 by the bumps 33〇b. 314 electrical connection. Next, in this embodiment, a primer 340a may be formed between the wafer % and the secret circuit board 31G to cover the bumps 33A. Similarly, this embodiment can also form a primer 3 lion between the wafer 3 and the slidable circuit board 310 to cover the bumps. Referring to FIG. 3B, the flexible circuit board 31 is bent to form a cavity 31〇a. At this time, the wafers 320a and 320b are located in the accommodating space 31〇a_^the wafer 32〇a is located on the wafer 32. Above 〇b. Further, before the two-way board 310 is bent, H35Q' may be formed on the wafer or the crucible to fix the relative position between the wafer 32Qa and 32%. The external connection terminals 2 ^ mother cup balls 36 are respectively passed through the patterned wiring wafer or the wafer. In addition, these three can dislike lead solder balls or tin-lead solder balls. However, it is also possible to fill the lead-lead solder, the tin-lead solder, and the 苴j into the nipple hole 312a of the ferrule or other conductive material to form the external connection end 13 1254462 16495 twf.doc/006 - Do not). Thus far, the fabrication of the chip package 300a is substantially completed. Referring to Figure 3C, the above steps are repeated to fabricate wafer entrapment bodies 300b and 300c. Then, a common carrier 22 is provided, and the shared carrier 22 has a plurality of solder ball pads 22a. In this embodiment, the shared carrier 22 can be a circuit board or other type of carrier. Then, the wafer packages 300a, 300b, and 300c are stacked on the common carrier 22. Then, the above structure is applied to the reflow process (re^) 以w pr〇cess) so that the chip packages 300a, 3(10)b and 300c are electrically connected to each other, and the wafer 5 package 3〇〇c and The shared carrier 22 is connected. It is to be noted that, in the case where the shared carrier 22 is not used, the chip packages 3 (8) a, 3 〇〇 b / , 300c may be integrally formed and integrated directly on a single electronic device on a circuit board. - In the present embodiment, the wafers 320a and 320b of the respective chip packages 3 (8) a, 3 〇〇 b and 3 〇〇 c are electrically connected to the flexible circuit board 310 by flip chip bonding. However, the wafers 320a and 320b of the respective chip packages 3a, 3(8)b and 3〇〇c can also be electrically connected to the flexible circuit board 3 by wire bonding or other chip packaging technology. Then, a plurality of solder balls 24' are formed on the solder ball pads 22a of the shared carrier 22 to complete the fabrication of the stacked wafer package structure 2''. The stacked wafer package package #20 can be disposed on a circuit board by _24. It is worth mentioning that this embodiment does not limit the number of chip packages in the stacked chip package structure 2A. The thickness of each of the chip packages 3〇〇a, 3(8)1 and 3〇(^ can be thinned, so the overall thickness of the stacked chip package structure 2〇 is also thinner with the change of 14 1254462 16495 twf.doc/006 _. In addition, the process technology used in the stacked chip package structure 20 of the present embodiment is relatively mature. In addition, since each of the chip packages 3 (8) a, 3 〇〇 b, and 300 c is difficult to manufacture, the chip package of the defective product is The body is not used in the stacked chip package structure 2 to improve the yield of the stacked chip package structure 20. [2] FIG. 4A to FIG. 4B illustrate a second embodiment according to the present invention. Schematic diagram of the manufacturing process of the stacked crystal chip package structure. Referring to FIG. 4A, the Φ example is similar to the above embodiment, and the main difference is that the 410a and 420b are respectively disposed on the flexible circuit board 31〇. Then, a plurality of wires 420a and 420b are formed. The wafer 410a is electrically connected to the patterned wiring layer 314 by the wires 420a, and the wafer 41〇b is electrically connected to the patterned wiring layer 314 by the wires 42%. Then, Flexible circuit board 31 The encapsulants 430a and 430b are respectively formed, wherein the encapsulant 430a covers the wafer 41〇a and the wires 42〇a. Further, the encapsulant 43〇b covers the wafer & 诎 and the wires 420a. _ Then, the flexible circuit is bent The board 31Q is formed to accommodate the accommodating space 310a' in which the wafers 41A and 〇b are located in the accommodating space 310a, and the wafer 410a is located above the wafer 41 〇b. Further, before the flexible circuit board 310 is bent The adhesive layer 440' may also be formed on the encapsulant 430a or 430b to fix the relative position between the wafers 410a and 410b. Thus, the fabrication of the chip package 4a is completed. Next, the solder-free solder, tin A wrong solder, other types of solder or other conductive material is filled into a portion of the through holes 312a to form a plurality of external 15 1254462 16495 twf.doc/006 connection terminals 450. Iron, μ, +, waste: #丨丄The solder ball 360 in the above-described embodiment can also replace the external connection terminal 450 of the present embodiment. The above steps are repeated to form the chip package 400b. Then, the chips are packaged. Heap of body_a, 400b and 400c The chip package _a and the terminal _a are electrically connected to each other. Further, the wafer package body * is electrically connected to the same by the external connection terminal 440 The stacked chip package structure 30 can also be disposed on a circuit board by (4) ^ solder or pre- solder (pre_s), in addition to the above embodiment, without sharing In the case of carrying the cry 22, the chip package, and her can also be directly placed on the circuit board or on the electronic device. For example, the wafers 410a and 410b of the respective chip packages 4(8)b and 4〇〇c are electrically connected to the flexible circuit board 310 by wire bonding techniques. However, each of the wafers of the above embodiments may be electrically connected to the flexible _31G by flip chip bonding, wire bonding, or other chip packaging techniques. Moreover, this embodiment does not limit the number of chip packages within the stacked wafer package structure 30. In summary, the present invention has at least the following advantages: 1. The stacked chip package structure or the chip package of the present invention has a thin thickness. 1 . The stacked chip package structure or the chip package of the present invention is applied to a flip chip bonding process or a wire bonding process. 2. The process technology used in the present invention is relatively mature, and therefore the manufacturing method of the invention 16 1254462 16495 twf.doc/006 has a better process yield. And within the scope, since this technology #, without departing from the spirit of the invention;; = two: this miscellaneous L schema early description]

^9 shows a schematic cross-sectional view of the stacking structure of the wafer. Figure. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3A to FIG. 3C are schematic cross-sectional views showing a manufacturing process of a stacked type wafer package I structure according to a first embodiment of the present invention. 4A to 4B are cross-sectional views showing the manufacturing process of the stacked type wafer package structure in accordance with the second embodiment of the present invention. [Main component symbol description] 10, 100: conventional stacked chip package structure 12, 110, 210: package substrate 20, 30: stacked chip package structure 22a, 214: zinc ball pad 24, 250, 360: solder ball 120a, 120b, 220, 320a, 320b, 410a, 410b: wafer 130: spacers 140, 420a, 420b: wires 150, 430a, 430b · encapsulants 200a, 200b, 300a, 300b, 300c, 400a, 400b, 400c 1254462 16495twf.doc/006 Chip package 212: conductive pillars 230, 330a, 330b: bumps 240, 340a, 340b: primer 310: flexible circuit board 310a: housing space 312: flexible substrate 312a :through hole 314: patterned circuit layer 350, 440: adhesive layer 450: external connection terminal

18

Claims (1)

1254462 16495twf.doc/006 X. Patent Application Range: 1. A chip package comprising: a flexible circuit board bent to form an accommodating space; a first wafer disposed on the flexible circuit And electrically connected to the flexible circuit board; and a second chip disposed on the flexible circuit board and electrically connected to the flexible circuit board, wherein the first chip and the first The second wafer is located in the accommodating space, and the first wafer is located above the second wafer. 2. The chip package of claim 1, further comprising an adhesive layer disposed between the first wafer and the second wafer to fix between the first wafer and the second wafer relative position. 3. The chip package of claim 1, wherein the flexible circuit board comprises: a flexible substrate; and a patterned circuit layer disposed on the flexible substrate, wherein The first wafer and the second wafer are respectively disposed on the patterned circuit layer and electrically connected to the patterned circuit layer. 4. The chip package of claim 3, wherein the flexible substrate has a plurality of through holes exposing a portion of the patterned wiring layer. 5. The chip package of claim 4, further comprising a plurality of external connection terminals respectively disposed in the plurality of through holes, and each of the external connection terminals is electrically connected via the patterned circuit layer Optionally connected to the first wafer and/or the second wafer. 6. The chip package of claim 5, wherein the material of the ball joints of the 19 1254462 16495 twf.d〇c/006 is filled in the solder. The chip package of the above-mentioned ===, wherein the plurality of the chip packages of the one of the first ones further comprise, and the first and second wafers and the flexible circuit board Circuit board. (5), = = electrically connected to the flexible body of the first embodiment of the first aspect of the present invention, further comprising and covering the: the first wafer and the flexible Between the boards, the plurality of chip packages described in claim 8 further includes a second chip and a circuit board of the flexible circuit board. The fourth bumps are electrically connected to the flexible package: a chip package, a package, and a plurality of special days of the chip The chip package of the first aspect, further comprising the chip to the flexible circuit board, wherein the wafer is electrically connected to the chip package according to the second item of the second aspect, more preferably The first package is provided on the flexible circuit board, and the package includes a plurality of second wires ' and the second wafer is passed through the package according to claim 12, wherein the chip package includes a plurality of second wires (4) Connect to the flexible circuit board. The chip package of claim 14, wherein the chip package includes a second package, and the (four) flexible circuit board has a second wire and the second wafer.匕复五海16. A stacked chip package structure, comprising: a plurality of chip packages electrically connected to each other, and each package comprises: a flexible circuit board sealed in a day to form a bend to form An accommodating space, and the flexible circuit board includes a flexible substrate and a patterned circuit layer disposed on the , Γΐ, wherein the flexible substrate has a plurality of two holes 'exposed portions a patterned circuit layer; a first wafer disposed on the patterned circuit patterned circuit layer electrically connected; and I and the second wafer disposed on the patterned circuit layer, and the current patterned circuit layer a connection, a Α中/, Μ 片 is located in the accommodating space and two: a cymbal and the second crystal; and a lining and a wafer are located at the plurality of external connection terminals of the second wafer, respectively configured with terminals Through the patterning; αϊί日片 and/or the second wafer, and each of the next day; the sealing is electrically connected by the corresponding external connecting terminals; and the other chip packages. w 生运接到21 1254462 16495twf.doc/006 Construction, and more includes - the 16th item of the stack of $ type wafer seal knots (4), chip package: Ask the load on the ϋ, and connect with the money. The read stack structure is described in claim 17, wherein the common carrier comprises a circuit board or a lead frame. The first layer of the second and second day of the package further includes an adhesive layer disposed between the "two:! sheets" to fix the first wafer and the second including solder, and the::== exterior The material structure of the connection terminal, the number of the external connection terminals of the stacked wafer-sealing solder ball solder chip package described in Item 16 of the second ff circumference is a plurality of structures, such as each of the frf remaining 16 The stacked wafer package of the first embodiment further includes a plurality of first bumps disposed between the first flexible circuit boards and the first wafer is routed through A % is connected to the flexible circuit board. The structure of the f-shield package includes the first-chip package, which is disposed at 24. between the board and the circuit board. Covering the first-bump structures, wherein each of the stacked wafer-on-chip junctions and the second-piece package of the 22-piece package further includes a plurality of second bumps, and the configuration 22 I254462wfd〇c/ 〇〇6 兮二门丹竣1 between the flexible circuit boards, and the first "two=convex=electrically connected to the flexible circuit board. The stacked type of the package described in the second paragraph of the patent application of the Japanese Patent Application No. 24, the chip package further includes a: -:: package package 4 - wafer and the flexible, - shift, The first wafer is encapsulated in the first aspect of the invention, and the first wafer is further encapsulated with the first wafer via the first limb, and The application is specifically for the benefit of the circuit board. The structure of each of the wafers is sealed on the flexible circuit board, and the film is coated. The first crystal structure is as described in claim 26, and the wafers are encapsulated by the wafers. The wafers are passed through the first 遂: 29. The claim m wire is electrically connected to the flexible circuit, and the gel plate is placed on the flexible circuit board. The ugly package is provided. The second wire and the first-day method include: one of the patterned circuit layers on the material, and the through hole in the flexible base. I exposed two and formed a patterned circuit layer in the 5 He &substrate; Li Xi 23 1254462 16^95twf.d〇c/〇〇6 The first wafer and the first Secondly, 'to make the first-crystal _ 日 于 于 柯 柯 柯 柯 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯 柯- crystal >; and the second wafer is located in the j-valley space 'which is located above the second wafer. X is in the valley room, and the first wafer 31 · as claimed in the patent range :%: method' Further included in the first wafer-turning, the manufacturing layer of the wafer package is used to fix the first wafer: = between the wafers to form an adhesive 32. The relative position of the patent application range. The method further includes, in a part of the manufacturing of the chip package, and each of the external connection terminals is divided into two female external connection terminals, and connected to the first wafer and/or the second crystal= The phased circuit layer is electrically connected to the through holes. The method of the invention includes the method of filling the solder into the method of the crystal material P described in Item 32 of the patent specification: the method for forming the external connection terminals includes the method: 5 is more like the package == the second item (4) And a plurality of the extractable circuits are formed between the first and second bumps; and the wafer is electrically connected to the chip package according to claim 35. Manufacture of 24 1254462 16495 twf.doc/〇〇6 method, further comprising '兮日第—primer to cover the formation of the sheet and the flexible circuit board - 37. Further, a second bump is formed in the chip package described in the image, and the flexible circuit board is formed between the nine female and the flexible circuit board. Electrically connecting to the second bumps via the second bumps, such as the patent application method, and the second primer of the "crystal" package described in (4) and 2nd, for coating the same: Between the flexible circuit boards, a 〆39丄丄~二乐二bump 0 square is formed, as in the 30th application of the patent scope, +, and ί, and further includes the manufacture of a plurality of d-th packages for the manufacture of 4Q/曰 and The flexible circuit board. The method of the U-knife is different from the patent range 39:®, +, u 4 34; the manufacture of difficult bodies, the first wires and the forming-first-package colloid, 41 4 Buri Sun and Moon. Fang Xing Shen Qing patent range 40th%, +, and green ♦ wire, and] read and connect to the touchable circuit board. The scope of patent application is 41 jg & In the manufacturing of the flexible circuit, the manufacturing of the body, the second wire, and the (3) formation - the second package includes forming a plurality of second leads, the manufacturing of the wafer body is electrically connected to the The flexible core wafer passes through the colloids 25