JP2003163324A - Unit semiconductor device and manufacturing method thereof, and three-dimensional laminated semiconductor device - Google Patents

Unit semiconductor device and manufacturing method thereof, and three-dimensional laminated semiconductor device

Info

Publication number
JP2003163324A
JP2003163324A JP2001361366A JP2001361366A JP2003163324A JP 2003163324 A JP2003163324 A JP 2003163324A JP 2001361366 A JP2001361366 A JP 2001361366A JP 2001361366 A JP2001361366 A JP 2001361366A JP 2003163324 A JP2003163324 A JP 2003163324A
Authority
JP
Japan
Prior art keywords
semiconductor device
wiring pattern
semiconductor chip
unit
dimensional stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001361366A
Other languages
Japanese (ja)
Inventor
Takao Yamazaki
隆雄 山崎
Naonori Orito
直典 下戸
Sakae Hojo
栄 北城
Yuzo Shimada
勇三 嶋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2001361366A priority Critical patent/JP2003163324A/en
Priority to PCT/JP2002/012362 priority patent/WO2003046987A1/en
Publication of JP2003163324A publication Critical patent/JP2003163324A/en
Pending legal-status Critical Current

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  • General Physics & Mathematics (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a unit semiconductor device that can mixedly mount various sizes and kinds of semiconductor chips easily and cope with change to a large memory, at the same time, can prevent decrease in a yield due to broken semiconductor chips or the like in handling, and can simply form a three- dimensional laminated semiconductor device having a compact package. <P>SOLUTION: The unit semiconductor device 14 comprises a semiconductor chip 11 having a chip electrode, a wiring pattern 16 for mounting the chip electrode on one surface, mold resin (12, 17) for covering the semiconductor chip 11 and a wiring pattern 16 in one piece, and a via plug 18 that passes through the mold resin outside the semiconductor chip 11 and whose one end comes into contact with the other surface of the wiring pattern 16 and the other is exposed from the mold resin. In this case, the other surface of the wiring pattern 16 is exposed on the surface of the mold resin. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、ユニット半導体装
置及びその製造方法並びに３次元積層型半導体装置に関
し、更に詳しくは、複数段の積層構造を簡便に得ること
ができるコンパクトなユニット半導体装置、及びこのよ
うなユニット半導体装置の製造方法、並びに、このユニ
ット半導体装置を積層した３次元積層型半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unit semiconductor device, a method of manufacturing the same, and a three-dimensional laminated semiconductor device, and more specifically, a compact unit semiconductor device capable of easily obtaining a laminated structure having a plurality of stages, and The present invention relates to a method for manufacturing such a unit semiconductor device and a three-dimensional stacked semiconductor device in which the unit semiconductor devices are stacked.

【０００２】[0002]

【従来の技術】従来の３次元積層型の半導体装置が、特
開平11-204720号公報に記載されている（第１の従来
例）。図３０は、この公報に記載の３次元積層型の半導
体装置を示す断面図である。この半導体装置では、相互
にサイズが異なる半導体チップ１０１、１０２が、フェ
ースアップでインターポーザ基板１０６上に順次に積層
されている。テープ基板１０６と半導体チップ１０１、
及び半導体チップ１０１と半導体チップ１０２が夫々、
絶縁性接着剤１０７で接着される。半導体チップ１０
１、１０２の各回路形成面の外周部に設けられた電極パ
ッドと、テープ基板１０６上の銅パターン１０４とが、
金ワイヤ１０３を介して接続される。2. Description of the Related Art A conventional three-dimensional stacked semiconductor device is described in Japanese Patent Application Laid-Open No. 11-204720 (first conventional example). FIG. 30 is a sectional view showing the three-dimensional stacked semiconductor device described in this publication. In this semiconductor device, semiconductor chips 101 and 102 having different sizes are sequentially stacked face up on an interposer substrate 106. The tape substrate 106 and the semiconductor chip 101,
And the semiconductor chip 101 and the semiconductor chip 102,
It is adhered with an insulating adhesive 107. Semiconductor chip 10
The electrode pads provided on the outer peripheral portion of each circuit forming surface of Nos. 1 and 102 and the copper pattern 104 on the tape substrate 106 are
It is connected via a gold wire 103.

【０００３】テープ基板１０６の裏面には、マザーボー
ドにフリップチップ実装するためのはんだバンプ１０５
が配列される。テープ基板１０６上の半導体チップ１０
１、１０２、銅パターン１０４及び金ワイヤ１０３が封
止樹脂１０８で覆われている。このような構成の半導体
装置では、半導体チップ１０１、１０２が２段積層され
るにも拘わらず、インターポーザ基板１０６を１枚のみ
用いることで、チップサイズに近い小型パッケージが実
現できる。On the back surface of the tape substrate 106, solder bumps 105 for flip chip mounting on a mother board are mounted.
Are arranged. Semiconductor chip 10 on tape substrate 106
1, 102, the copper pattern 104, and the gold wire 103 are covered with the sealing resin 108. In the semiconductor device having such a configuration, although the semiconductor chips 101 and 102 are stacked in two stages, by using only one interposer substrate 106, a small package close to the chip size can be realized.

【０００４】別の３次元積層型の半導体装置が、特開平
5-283608号公報に記載されている（第２の従来例）。図
３１は、この公報に記載の半導体装置を示す断面図であ
る。この半導体装置は、積層された４つのテープキャリ
アパッケージと、各テープキャリアパッケージ間に夫々
設けられたプリプレグ１１０とを有する。各テープキャ
リアパッケージは、導電バンプ１１２を介して相互に接
続された半導体チップ１０９及びフィルムキャリア１１
１を有し、各プリプレグ１１０は、中心部分に形成され
た半導体チップ収納穴１１４と、周縁部の同じ位置に形
成された穴１１５とを有する。積層したプリプレグ１１
０の穴１１５及びフィルムキャリア１１１を連続して貫
通する貫通穴に埋め込まれた導電性物質１１３により、
各半導体チップ１０９が相互に電気的に接続される。Another three-dimensional laminated semiconductor device is disclosed in
It is described in Japanese Patent Publication No. 5-283608 (second conventional example). FIG. 31 is a sectional view showing the semiconductor device described in this publication. This semiconductor device has four stacked tape carrier packages and a prepreg 110 provided between each tape carrier package. Each tape carrier package includes a semiconductor chip 109 and a film carrier 11 which are connected to each other via conductive bumps 112.
1, each prepreg 110 has a semiconductor chip housing hole 114 formed at the center portion and a hole 115 formed at the same position on the peripheral portion. Laminated prepreg 11
By the conductive material 113 embedded in the through hole that continuously penetrates the hole 115 of 0 and the film carrier 111,
The semiconductor chips 109 are electrically connected to each other.

【０００５】[0005]

【発明が解決しようとする課題】第１の従来例では、半
導体チップ１０１、１０２を複数個積層できる構造を有
するが、半導体チップ１０１、１０２は相互に導通され
ず、半導体チップ１０１、１０２が個々にインターポー
ザ基板１０６とワイヤボンディング接続されている。こ
のため、チップ回路形成面の外周部にワイヤボンディン
グのための広い空きスペースが必要になり、パッケージ
の小型化を損なう要因となっていた。The first conventional example has a structure in which a plurality of semiconductor chips 101 and 102 can be stacked, but the semiconductor chips 101 and 102 are not electrically connected to each other, and the semiconductor chips 101 and 102 are individually connected. Is connected to the interposer substrate 106 by wire bonding. Therefore, a wide empty space for wire bonding is required on the outer peripheral portion of the chip circuit formation surface, which is a factor impairing the miniaturization of the package.

【０００６】また、下段のチップサイズを上段のチップ
サイズよりも大きくしなければならず、サイズが異なる
異種チップの３次元積層型の半導体装置しか得ることが
できなかった。更に、チップサイズが限定されることに
より、封止樹脂１０８の厚みやワイヤボンディングの高
さ等を考慮しなければならず、情報機器のパッケージ厚
み仕様の1.2mm以下を満足させるには、異種チップの積
層個数は３〜４段が限界であった。このため、上段の半
導体チップほどサイズが小さくなり、メモリ大容量化に
は不利であった。Further, the lower chip size must be made larger than the upper chip size, and only a three-dimensional stacked semiconductor device of different chips having different sizes can be obtained. Further, since the chip size is limited, the thickness of the sealing resin 108, the height of wire bonding, etc. must be taken into consideration. The number of stacked layers was limited to 3 to 4 layers. Therefore, the size of the upper semiconductor chip becomes smaller, which is disadvantageous for increasing the memory capacity.

【０００７】第２の従来例では、半導体チップ１０９を
研削した後にフィルムキャリア１１１に接続するので、
例えば５０μｍ以下に研削した場合、半導体チップ１０
９をフィルムキャリア１１１に接続するハンドリング時
に半導体チップ１０９を割ることがあり、歩留まりの低
下を招くことがあった。従って、チップ厚を薄くするこ
とが技術的に可能であっても、組立て時に必要な強度を
得るために、最小でも５０μｍの厚みが必要になる。こ
のため、３次元積層型半導体装置の薄型化には限界があ
った。In the second conventional example, since the semiconductor chip 109 is ground and then connected to the film carrier 111,
For example, when ground to 50 μm or less, the semiconductor chip 10
The semiconductor chip 109 may be broken during the handling of connecting 9 to the film carrier 111, which may lead to a decrease in yield. Therefore, even if it is technically possible to reduce the chip thickness, a minimum thickness of 50 μm is required to obtain the required strength during assembly. Therefore, there has been a limit to the reduction in thickness of the three-dimensional stacked semiconductor device.

【０００８】また、第２の従来例では、フィルムキャリ
ア１１１上に半導体チップ１０９を搭載したパッケージ
を順次に積層した後、レーザで一括に穴１１５を形成し
てから、連続する穴１１５にペースト状の導電性物質１
１３を流し込み、プレス加工して３次元積層構造を得
る。このため、同種のチップやパッケージの３次元積層
型には適するものの、異種チップの積層や、異種チップ
と同種チップとを混載した３次元積層型を得ることは困
難である。更に、プリプレグ１１０やフィルムキャリア
１１１等の他の導体パターンにまで穴を形成しなければ
ならず、極めて大きなパワーを要する。このため、廉価
であるがパワーが小さい炭酸ガスレーザを用いて穴１１
５を形成することは難しく、パワーは大きいが高価なエ
キシマレーザやＵＶ−ＹＡＧレーザ等の使用を余儀なく
され、これがコストアップの要因になっていた。Further, in the second conventional example, after packages having the semiconductor chips 109 mounted thereon are sequentially laminated on the film carrier 111, holes 115 are collectively formed by a laser, and then paste is formed in the continuous holes 115. Conductive substance 1
13 is poured and pressed to obtain a three-dimensional laminated structure. Therefore, although it is suitable for a three-dimensional laminated type of chips and packages of the same type, it is difficult to obtain a laminated type of different types of chips or a mixed type of different types of chips and the same type of chips. Furthermore, holes must be formed even in other conductor patterns such as the prepreg 110 and the film carrier 111, which requires extremely large power. For this reason, it is possible to use a carbon dioxide laser that is inexpensive but has low power, and
It is difficult to form No. 5, and it is necessary to use an excimer laser, a UV-YAG laser, or the like, which has a high power but is expensive, which has been a factor of cost increase.

【０００９】本発明は、上記に鑑み、種々のサイズ及び
／又は種類の半導体チップの混載が容易にできメモリ大
容量化に対応可能な構成を有しながらも、ハンドリング
時の半導体チップの破損等に起因する歩留まりの低下を
回避すると共に、パッケージが小型の３次元積層型半導
体装置を簡便に形成できるユニット半導体装置、及びこ
のようなユニット半導体装置を製造する製造方法、並び
に、このユニット半導体装置を積層したコンパクトな３
次元積層型半導体装置を提供することを目的とする。In view of the above, the present invention has a structure in which semiconductor chips of various sizes and / or types can be easily mixed and can cope with an increase in memory capacity, but the semiconductor chips are damaged during handling. A unit semiconductor device capable of avoiding a decrease in yield due to the above-mentioned process and easily forming a three-dimensional stacked semiconductor device having a small package, a manufacturing method for manufacturing such a unit semiconductor device, and the unit semiconductor device. Stacked compact 3
An object is to provide a three-dimensional stacked semiconductor device.

【００１０】[0010]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係るユニット半導体装置は、チップ電極を
有する半導体チップと、一方の面で前記チップ電極をマ
ウントする配線パターンと、前記半導体チップ及び配線
パターンを一体的に覆うモールドレジンと、該モールド
レジンを前記半導体チップの外側で貫通し、一端が前記
配線パターンの前記一方の面に接触し、他端が前記モー
ルドレジンから露出する配線プラグとを備え、前記配線
パターンの他方の面が前記モールドレジンの表面に露出
していることを特徴とする。In order to achieve the above object, a unit semiconductor device according to the present invention comprises a semiconductor chip having a chip electrode, a wiring pattern for mounting the chip electrode on one surface, and the semiconductor. A mold resin that integrally covers the chip and the wiring pattern, and wiring that penetrates the mold resin outside the semiconductor chip, one end of which contacts the one surface of the wiring pattern and the other end of which is exposed from the mold resin A plug, and the other surface of the wiring pattern is exposed on the surface of the mold resin.

【００１１】本発明に係るユニット半導体装置では、一
のユニット半導体装置の配線プラグを、上段のユニット
半導体装置の配線パターンの露出面に接触させるだけ
で、種々のサイズ及び／又は種類の半導体チップを混載
することができ、メモリ大容量化に容易に対応すること
ができる。この場合、積層される半導体チップのサイズ
が異なっていても、各半導体チップを容易且つ確実に接
触、つまり電気的に結合させることができる。例えば、
上段のユニット半導体装置が一のユニット半導体装置よ
りもサイズが小さく、一のユニット半導体装置と上段の
ユニット半導体装置とにおける各配線プラグの位置が異
なっていても、配線パターンの露出面の面積により配線
プラグの位置ずれを吸収して、良好な接触状態を得るこ
とができる。これにより、サイズ及び／又は種類が異な
る複数のユニット半導体装置を容易に混載することがで
き、メモリ大容量化に対処することができる。また、導
電バンプと配線パターンとの接続によって半導体チップ
間の配線長が短くなるので、複数の半導体チップ相互の
接続後の導通状態がより良好になる。In the unit semiconductor device according to the present invention, semiconductor chips of various sizes and / or types can be obtained by merely bringing the wiring plug of one unit semiconductor device into contact with the exposed surface of the wiring pattern of the upper unit semiconductor device. It can be mixedly mounted and can easily cope with an increase in memory capacity. In this case, even if the semiconductor chips to be stacked have different sizes, the semiconductor chips can be easily and surely contacted, that is, electrically coupled. For example,
Even if the size of the upper unit semiconductor device is smaller than that of the unit semiconductor device and the positions of the wiring plugs in the unit semiconductor device and the unit semiconductor device in the upper stage are different from each other, wiring is performed depending on the area of the exposed surface of the wiring pattern A good contact state can be obtained by absorbing the displacement of the plug. As a result, a plurality of unit semiconductor devices having different sizes and / or types can be easily mixedly mounted, and the memory capacity can be increased. Further, since the wiring length between the semiconductor chips is shortened by the connection between the conductive bumps and the wiring pattern, the conductive state after connecting the plurality of semiconductor chips to each other becomes better.

【００１２】本発明の好ましいユニット半導体装置で
は、前記モールドレジンが、前記半導体チップと配線パ
ターンとの間に設けられた感光性接着剤を含む。例え
ば、半導体チップの回路形成面におけるチップ電極に導
電バンプが形成されている場合に、回路形成面全体に感
光性接着剤を塗布してから露光・現像することによっ
て、導電バンプの先端を容易に露出させることができ
る。In a preferred unit semiconductor device of the present invention, the mold resin contains a photosensitive adhesive provided between the semiconductor chip and the wiring pattern. For example, when conductive bumps are formed on the chip electrodes on the circuit formation surface of a semiconductor chip, the tip of the conductive bumps can be easily formed by applying a photosensitive adhesive to the entire circuit formation surface and then exposing and developing. Can be exposed.

【００１３】具体的には、前記半導体チップが５〜５０
μmの厚みを有することが好ましい。この場合、１ｍｍ
以内の厚み中に半導体チップを約２０枚実装することが
可能になり、メモリ大容量化の実現に寄与することがで
きる。Specifically, the semiconductor chip is 5 to 50.
It preferably has a thickness of μm. In this case, 1 mm
It is possible to mount about 20 semiconductor chips in the thickness within the range, and it is possible to contribute to the realization of a large memory capacity.

【００１４】本発明に係る３次元積層型半導体装置は、
前記ユニット半導体装置が複数段積層された３次元積層
型半導体装置であって、一のユニット半導体装置の前記
配線プラグが、上段のユニット半導体装置の前記配線パ
ターンの露出面に接触していることを特徴とする。The three-dimensional stacked semiconductor device according to the present invention is
A three-dimensional stacked semiconductor device in which the unit semiconductor devices are stacked in a plurality of stages, wherein the wiring plug of one unit semiconductor device is in contact with an exposed surface of the wiring pattern of the upper unit semiconductor device. Characterize.

【００１５】本発明に係る３次元積層型半導体装置で
は、一のユニット半導体装置の配線プラグが上段のユニ
ット半導体装置の配線パターンの露出面に接触する構成
を有するので、複数のユニット半導体装置を順次に積層
することで、情報機器のパッケージ厚み仕様を満足させ
た多段積層構造を容易に得ることができる。In the three-dimensional stacked semiconductor device according to the present invention, since the wiring plug of one unit semiconductor device is in contact with the exposed surface of the wiring pattern of the upper unit semiconductor device, a plurality of unit semiconductor devices are sequentially arranged. The multi-layered structure that satisfies the package thickness specification of the information device can be easily obtained by stacking the two layers.

【００１６】ここで、前記複数段積層されたユニット半
導体装置の半導体チップは、サイズ及び／又は種類が相
互に同じであることが好ましい。或いは、これに代え
て、前記複数段積層されたユニット半導体装置における
少なくとも一つの半導体チップのサイズ及び／又は種類
が、他の半導体チップのサイズ及び／又は種類と異なる
ことも好ましい態様である。これらにより、多くの混載
バリエーションを得ることができる。Here, it is preferable that the semiconductor chips of the unit semiconductor devices stacked in a plurality of stages have the same size and / or type. Alternatively, it is also a preferable aspect that the size and / or type of at least one semiconductor chip in the unit semiconductor devices stacked in multiple stages is different from the size and / or type of other semiconductor chips. With these, many mixed mounting variations can be obtained.

【００１７】また、最上段及び／又は最下段の露出する
面には絶縁膜が形成され、少なくとも一方の絶縁膜の露
出面には外部電極が形成されることも好ましい態様であ
る。これにより、最上段及び／又は最下段の露出面をよ
り確実に絶縁し、且つ積層する際の電気的結合が容易な
ユニット半導体装置を得ることができる。It is also a preferred embodiment that an insulating film is formed on the exposed surface of the uppermost stage and / or the lowermost stage, and an external electrode is formed on the exposed surface of at least one of the insulating films. As a result, it is possible to obtain a unit semiconductor device that more reliably insulates the uppermost exposed surface and / or the lowermost exposed surface and facilitates electrical coupling when stacking.

【００１８】また、最下段のユニット半導体装置が前記
絶縁膜を介してインターポーザ基板又はマザーボードに
接着され、最上段のユニット半導体装置には前記絶縁膜
上に前記外部電極が形成され、該外部電極は前記インタ
ーポーザ基板又はマザーボードに設けられた電極パッド
にワイヤボンディング接続されることが好ましい。この
場合、複数のユニット半導体装置を積層してから、最上
段の外部電極を電極パッドにワイヤボンディング接続す
ることができるので、３次元積層型半導体装置の製造が
簡便になる。Further, the lowermost unit semiconductor device is adhered to the interposer substrate or the mother board through the insulating film, and the uppermost unit semiconductor device has the external electrodes formed on the insulating film. It is preferable that the electrode pads provided on the interposer substrate or the mother board are connected by wire bonding. In this case, after stacking a plurality of unit semiconductor devices, the uppermost external electrode can be connected to the electrode pad by wire bonding, so that the manufacturing of the three-dimensional stacked semiconductor device is simplified.

【００１９】更に好ましくは、前記最上段のユニット半
導体装置上に、一の半導体チップがフェースアップで接
着され、前記一のユニット半導体装置のチップ電極と前
記電極パッドとがワイヤボンディング接続される。この
場合、３次元積層型半導体装置上に、サイズが異なる他
のユニット半導体装置を容易に搭載することができる。More preferably, one semiconductor chip is face-up bonded onto the uppermost unit semiconductor device, and the chip electrode of the one unit semiconductor device and the electrode pad are connected by wire bonding. In this case, another unit semiconductor device having a different size can be easily mounted on the three-dimensional stacked semiconductor device.

【００２０】また、前記複数段のユニット半導体装置と
前記インターポーザ基板又はマザーボードとを接着した
積層体が複数段形成されることも好ましい態様である。
この場合、パッケージ化した複数の３次元積層型半導体
装置を容易に積層、接続することができるので、メモリ
大容量化の実現が簡便になる。It is also a preferable embodiment that a plurality of stacked layers are formed by bonding the plurality of stacked unit semiconductor devices to the interposer substrate or the mother board.
In this case, it is possible to easily stack and connect a plurality of packaged three-dimensional stacked semiconductor devices, which facilitates realization of a large memory capacity.

【００２１】本発明に係る第１視点のユニット半導体装
置の製造方法は、仮基板上に配線パターンを形成する工
程と、少なくとも側部及び下部がモールドレジンで被覆
され、該モールドレジンを貫通するスルーホールを介し
て前記配線パターンに接続される半導体チップを前記配
線パターン上に搭載する工程と、前記配線パターン上
に、前記半導体チップの外側を通過し前記モールドレジ
ンを貫通する配線プラグを形成する工程と、前記仮基板
を除去する工程とを備えることを特徴とする。A method of manufacturing a unit semiconductor device according to a first aspect of the present invention is a process of forming a wiring pattern on a temporary substrate, and a through hole which penetrates the mold resin by covering at least a side portion and a lower portion with the mold resin. Mounting a semiconductor chip connected to the wiring pattern through a hole on the wiring pattern; and forming a wiring plug on the wiring pattern, the wiring plug passing through the outside of the semiconductor chip and penetrating the mold resin. And a step of removing the temporary substrate.

【００２２】本発明に係る第１視点のユニット半導体装
置の製造方法では、種々のサイズ及び／又は種類の半導
体チップの混載構造を実現し、メモリ大容量化に対応す
ることができ、パッケージをリアルチップサイズにした
３次元積層型の半導体装置を容易に得ることができる。
また、半導体チップを予め配線パターン上に搭載してか
ら半導体チップを所要の厚みに研削することが可能なの
で、従来のようにハンドリング時に半導体チップを破損
するような不具合の発生を回避することができる。更
に、配線プラグを設けるためのスルーホールを各ユニッ
ト半導体装置毎に形成できるので、廉価で小パワーの炭
酸ガスレーザ等を用いることができる。この炭酸ガスレ
ーザにより、半導体チップの極めて近い位置に配線プラ
グを位置精度良く設けることができるので、ユニット半
導体装置を積層した後にパッケージ化する際に、パッケ
ージ外形サイズをリアルチップサイズとして超小型化す
ることが可能になる。In the method of manufacturing a unit semiconductor device according to the first aspect of the present invention, it is possible to realize a mixed mounting structure of semiconductor chips of various sizes and / or types, to cope with an increase in memory capacity, and to realize a package package. It is possible to easily obtain a three-dimensional stacked semiconductor device having a chip size.
Further, since the semiconductor chip can be ground to a required thickness after being mounted on the wiring pattern in advance, it is possible to avoid the occurrence of a problem such as the conventional case where the semiconductor chip is damaged during handling. . Furthermore, since a through hole for providing a wiring plug can be formed for each unit semiconductor device, an inexpensive and small power carbon dioxide laser or the like can be used. With this carbon dioxide laser, wiring plugs can be provided at positions very close to the semiconductor chip with high positional accuracy. Therefore, when unit semiconductor devices are stacked and then packaged, the package outer size is made extremely small as a real chip size. Will be possible.

【００２３】前記モールドレジンが、前記半導体チップ
の下部を被覆する第１モールド部と、前記半導体チップ
の少なくとも側部を被覆する第２モールド部とから成
り、前記搭載工程が、前記第１モールド部の形成工程と
前記第２モールド部の形成工程とを含むことが好まし
い。この場合、半導体チップの下部を被覆してから側部
を被覆できるので、例えば半導体チップ下部に後からモ
ールドレジンを充填するような場合に比して、より確実
な被覆が実現できる。The mold resin comprises a first mold part covering the lower part of the semiconductor chip and a second mold part covering at least a side part of the semiconductor chip, and the mounting step comprises the first mold part. And the step of forming the second mold portion. In this case, since the lower part of the semiconductor chip can be covered and then the side part can be covered, more reliable covering can be realized as compared with, for example, the case where the lower part of the semiconductor chip is later filled with the mold resin.

【００２４】具体的には、前記第２モールド部の形成工
程に先立って、前記半導体チップの上部を研削し、該半
導体チップを５〜５０μmの厚みに形成することができ
る。この場合、仮基板上に形成した配線パターンに半導
体チップを接続してから半導体チップ上部を研削するこ
とができるので、半導体チップを破損することなくチッ
プ厚を、回路パターン層厚レベル（５〜１５μｍ）まで
極薄にすることが可能になる。これにより、１パッケー
ジ当たりの厚みを約５０μmまで薄くすることができ、
厚み１ｍｍ以内に半導体チップを約２０枚実装すること
が可能になる。Specifically, prior to the step of forming the second mold portion, the upper portion of the semiconductor chip can be ground to form the semiconductor chip with a thickness of 5 to 50 μm. In this case, since the semiconductor chip can be ground after the semiconductor chip is connected to the wiring pattern formed on the temporary substrate, the chip thickness can be adjusted without damaging the semiconductor chip to the circuit pattern layer thickness level (5 to 15 μm). ) Can be made ultra thin. As a result, the thickness per package can be reduced to about 50 μm,
It becomes possible to mount about 20 semiconductor chips within a thickness of 1 mm.

【００２５】また、前記配線プラグの形成工程に後続し
て、前記第２モールド部上に前記配線パターンを形成し
てから、前記搭載工程〜前記配線プラグの形成工程を繰
り返し行って３次元積層型の半導体装置に形成すること
ができる。これにより、メモリ大容量化に対応する３次
元積層型半導体装置を容易に得ることができる。After the step of forming the wiring plug, the wiring pattern is formed on the second mold portion, and then the mounting step to the step of forming the wiring plug are repeated to form a three-dimensional laminated type. Can be formed into a semiconductor device. As a result, it is possible to easily obtain a three-dimensional stacked semiconductor device that is compatible with a large memory capacity.

【００２６】本発明に係る第２視点のユニット半導体装
置の製造方法は、仮基板上に配線パターンを形成する工
程と、前記配線パターン上に半導体チップ及び該半導体
チップに隣接する配線プラグを形成する工程と、モール
ドレジンによって前記半導体チップ及び前記配線プラグ
を前記配線パターン上に埋め込む工程と、前記仮基板を
除去する工程とを備えることを特徴とする。A second aspect of the method of manufacturing a unit semiconductor device according to the present invention is a step of forming a wiring pattern on a temporary substrate, and forming a semiconductor chip and a wiring plug adjacent to the semiconductor chip on the wiring pattern. The method is characterized by including a step, a step of embedding the semiconductor chip and the wiring plug on the wiring pattern by a mold resin, and a step of removing the temporary substrate.

【００２７】本発明に係る第２視点のユニット半導体装
置の製造方法では、種々のサイズ及び／又は種類の半導
体チップの混載構造を実現し、メモリ大容量化に対応す
ることができ、パッケージをリアルチップサイズにした
３次元積層型の半導体装置を容易に得ることができる。
更に、上記第１視点のユニット半導体装置の製造方法と
同様の効果を得ることができる。In the method of manufacturing a unit semiconductor device according to the second aspect of the present invention, a mixed mounting structure of semiconductor chips of various sizes and / or types can be realized, and it is possible to cope with an increase in memory capacity and to realize a package package. It is possible to easily obtain a three-dimensional stacked semiconductor device having a chip size.
Further, it is possible to obtain the same effect as that of the method of manufacturing the unit semiconductor device according to the first aspect.

【００２８】本発明の好ましいユニット半導体装置の製
造方法では、前記モールドレジンが、前記半導体チップ
の下部を被覆する第１モールド部と、前記半導体チップ
の少なくとも側部を被覆する第２モールド部とから成
り、前記埋め込み工程が、前記第１モールド部の形成工
程と前記第２モールド部の形成工程とを含む。これによ
り、半導体チップの下部を被覆してから側部を被覆でき
るので、より信頼性が高い絶縁を実現することができ
る。In a preferred method of manufacturing a unit semiconductor device according to the present invention, the mold resin includes a first mold portion that covers a lower portion of the semiconductor chip and a second mold portion that covers at least a side portion of the semiconductor chip. The embedding step includes a step of forming the first mold portion and a step of forming the second mold portion. As a result, since the lower part of the semiconductor chip can be covered and then the side parts can be covered, more reliable insulation can be realized.

【００２９】具体的には、前記半導体チップ及び配線プ
ラグの埋め込み工程に後続して、前記半導体チップ及び
配線プラグの上部を研削し、該半導体チップを５〜５０
μmの厚みに形成することができる。これにより、仮基
板上に形成した配線パターンに半導体チップを接続して
から半導体チップ上部を研削できるので、半導体チップ
を破損することなく、チップ厚を極薄に形成することが
できる。Specifically, after the step of embedding the semiconductor chip and the wiring plug, the upper portions of the semiconductor chip and the wiring plug are ground to make the semiconductor chip 5 to 50.
It can be formed to a thickness of μm. As a result, since the semiconductor chip can be ground after the semiconductor chip is connected to the wiring pattern formed on the temporary substrate, the chip thickness can be formed extremely thin without damaging the semiconductor chip.

【００３０】本発明の好ましいユニット半導体装置の製
造方法では、前記半導体チップ及び配線プラグの研削工
程に後続して、前記第２モールド部上に前記配線パター
ンを形成してから、前記半導体チップ及び該半導体チッ
プに隣接する配線プラグの形成工程〜前記埋め込み工程
を繰り返し行って３次元積層型の半導体装置に形成す
る。これにより、メモリ大容量化に対応する３次元積層
型半導体装置が容易に得られる。In a preferred method of manufacturing a unit semiconductor device of the present invention, after the step of grinding the semiconductor chip and the wiring plug, the wiring pattern is formed on the second mold portion, and then the semiconductor chip and the wiring pattern are formed. The process of forming the wiring plug adjacent to the semiconductor chip to the embedding process are repeated to form a three-dimensional stacked semiconductor device. This makes it possible to easily obtain a three-dimensional stacked semiconductor device corresponding to an increase in memory capacity.

【００３１】前記配線パターンの形成工程では、前記仮
基板上に予め絶縁被膜を形成してから、該絶縁被膜上に
前記配線パターンを形成することができる。この場合、
ケミカルエッチング等で仮基板を除去した後に露出すべ
き配線パターンの面を絶縁被膜で予め覆った状態が得ら
れるので、この構造のユニット半導体装置を、３次元積
層型半導体装置における最下部のユニット半導体装置と
して使用することができる。In the step of forming the wiring pattern, after forming an insulating coating on the temporary substrate in advance, the wiring pattern can be formed on the insulating coating. in this case,
After removing the temporary substrate by chemical etching or the like, it is possible to obtain a state in which the surface of the wiring pattern to be exposed is covered with an insulating film in advance. It can be used as a device.

【００３２】また、前記３次元積層型の最上段のユニッ
ト半導体装置における露出面を絶縁膜で覆い、該絶縁膜
の前記配線プラグ上に別のスルーホールを形成し、該別
のスルーホール内に、前記配線プラグに接触する外部電
極を形成することができる。Further, the exposed surface of the uppermost unit semiconductor device of the three-dimensional laminated type is covered with an insulating film, another through hole is formed on the wiring plug of the insulating film, and the other through hole is formed in the other through hole. An external electrode that contacts the wiring plug can be formed.

【００３３】好ましくは、前記３次元積層型の半導体装
置を積層方向と直交する平面方向に配列するように形成
してから、各３次元積層型の半導体装置毎に分割する。
この場合、複数の３次元積層型半導体装置を平面方向に
配列させた状態で一度に形成できるので、各３次元積層
型半導体装置間で仮基板を共通に使用し、仮基板上に配
線パターンを形成する工程以降、仮基板の除去工程まで
を、各層で同時進行的に実施することができる。これに
より、複数の３次元積層型半導体装置の形成工程を簡略
化し、個々の３次元積層型半導体装置を得るまでの所要
時間を短縮することができる。Preferably, the three-dimensional stacked semiconductor devices are formed so as to be arranged in a plane direction orthogonal to the stacking direction, and then divided into each three-dimensional stacked semiconductor device.
In this case, since a plurality of three-dimensional stacked semiconductor devices can be formed at a time in a state of being arranged in the planar direction, a temporary substrate is commonly used among the three-dimensional stacked semiconductor devices and a wiring pattern is formed on the temporary substrate. After the step of forming and the step of removing the temporary substrate, the steps can be simultaneously performed in each layer. As a result, the process of forming a plurality of three-dimensional stacked semiconductor devices can be simplified and the time required to obtain each three-dimensional stacked semiconductor device can be shortened.

【００３４】[0034]

【発明の実施の形態】以下、図面を参照し、本発明に係
る実施形態例に基づいて本発明を更に詳細に説明する。
なお、以下の各実施形態例で示す、ユニット半導体装置
１４の積層段数、半導体チップ１１のサイズや種類の組
み合わせ等は、本発明の理解を容易にするための一つの
例示であり、本発明はこの例示に限定されるものではな
く、パッケージの厚み仕様の範囲内であれば図示した段
数を超える段数の積層構造が可能である。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail below with reference to the drawings on the basis of embodiments of the present invention.
Note that the number of stacked layers of the unit semiconductor device 14, the combination of the size and type of the semiconductor chip 11, and the like shown in each of the following embodiments are examples for facilitating the understanding of the present invention, and the present invention is The present invention is not limited to this example, and a laminated structure having more stages than the illustrated number is possible within the range of the package thickness specifications.

【００３５】半導体装置の第１実施形態例 図１（ａ）は本発明に係る第１実施形態例の３次元積層
型半導体装置の構成を示す断面図、図１（ｂ）はその変
形例を示す断面図、図１（ｃ）は更に別の変形例を示す
断面図である。 First Embodiment of Semiconductor Device FIG. 1A is a sectional view showing the structure of a three-dimensional stacked semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a modification thereof. The cross-sectional view shown in FIG. 1C is a cross-sectional view showing still another modification.

【００３６】図１（ａ）に示すように、本３次元積層型
半導体装置１０Ａは、サイズ及び／又は種類が同じ半導
体チップ１１を有するユニット半導体装置１４が２段積
層された構成を備える。各ユニット半導体装置１４は、
チップ電極（図示せず）を有する半導体チップ１１と、
一方の面でチップ電極をマウントする配線パターン１６
と、半導体チップ１１及び配線パターン１６を一体的に
覆うモールドレジン（１２、１７）とを備える。半導体
チップ１１の周囲の絶縁樹脂層１７には、スルーホール
２０ａを形成した部分に、銅めっき等で形成したビアプ
ラグ（配線プラグ）１８が形成されている。各ユニット
半導体装置１４の半導体チップ１１は夫々、５〜５０μ
mの厚みを有する。As shown in FIG. 1A, the present three-dimensional stacked semiconductor device 10A has a structure in which unit semiconductor devices 14 having semiconductor chips 11 of the same size and / or type are stacked in two stages. Each unit semiconductor device 14 is
A semiconductor chip 11 having a chip electrode (not shown),
Wiring pattern 16 for mounting the chip electrode on one surface
And a mold resin (12, 17) integrally covering the semiconductor chip 11 and the wiring pattern 16. In the insulating resin layer 17 around the semiconductor chip 11, a via plug (wiring plug) 18 formed by copper plating or the like is formed in a portion where the through hole 20a is formed. The semiconductor chip 11 of each unit semiconductor device 14 is 5 to 50 μm, respectively.
It has a thickness of m.

【００３７】配線パターン１６は、銅（Cu）又はアルミ
ニウム（Al）等で構成される。半導体チップ１１のチッ
プ電極には、導電バンプ１３が電気的且つ機械的に結合
している。配線パターン１６の表面には、導電バンプ１
３を接続するための電極パッド１５が形成されている。
導電バンプ１３は、金(Au)、スズ-鉛(Sn-Pb)、スズ-銀
(Sn-Ag)、Sn-Cu、Sn-Ag-Cu、スズ-ビスマス(Sn-Bi)等か
ら成るはんだで構成され、電極パッド１５は、ニッケル
/金(Ni/Au)、パラジウム(Pd)等で構成されている。導電
バンプ１３と電極パッド１５との接続は、導電バンプ１
３の構成材料によっても異なるが、約150〜350℃の温度
下の熱圧着法又はリフローによって容易に実現できる。The wiring pattern 16 is made of copper (Cu), aluminum (Al) or the like. The conductive bumps 13 are electrically and mechanically coupled to the chip electrodes of the semiconductor chip 11. The conductive bumps 1 are formed on the surface of the wiring pattern 16.
Electrode pads 15 for connecting 3 are formed.
The conductive bumps 13 are gold (Au), tin-lead (Sn-Pb), tin-silver.
(Sn-Ag), Sn-Cu, Sn-Ag-Cu, tin-bismuth (Sn-Bi), etc., and the electrode pad 15 is made of nickel.
/ It is composed of gold (Ni / Au), palladium (Pd), etc. The conductive bumps 13 and the electrode pads 15 are connected by the conductive bumps 1
Although it depends on the constituent materials of No. 3, it can be easily realized by a thermocompression bonding method or reflow under a temperature of about 150 to 350 ° C.

【００３８】ユニット半導体装置１４は更に、モールド
レジンを半導体チップ１１の外側で貫通し、一端が配線
パターン１６の上記一方の面に接触（電気的に結合）
し、他端がモールドレジンから露出するビアプラグ１８
を備え、配線パターン１６の他方の面がモールドレジン
の表面に露出している。The unit semiconductor device 14 further penetrates the mold resin outside the semiconductor chip 11 and has one end in contact with (electrically coupled to) the one surface of the wiring pattern 16.
And the other end is exposed from the mold resin via plug 18
And the other surface of the wiring pattern 16 is exposed on the surface of the mold resin.

【００３９】モールドレジンは、半導体チップ１１と配
線パターン１６との間に設けられた感光性接着剤（第１
モールド部）１２と、導体配線パターン１６及びビアプ
ラグ１８を含む半導体チップ１１上を覆う絶縁樹脂層
（第２モールド部）１７とを含んでいる。絶縁樹脂層１
７は、エポキシ系樹脂、ガラスクロスを含むエポキシ系
樹脂、又はポリイミド系樹脂等の絶縁樹脂で構成されて
いる。The mold resin is a photosensitive adhesive (first adhesive) provided between the semiconductor chip 11 and the wiring pattern 16.
The insulating resin layer (second mold portion) 17 covering the semiconductor chip 11 including the conductor wiring pattern 16 and the via plugs 18 is included. Insulating resin layer 1
7 is made of an epoxy resin, an epoxy resin containing glass cloth, or an insulating resin such as a polyimide resin.

【００４０】感光性接着剤１２によって、半導体チップ
１１の回路形成面、導電バンプ１３、電極パッド１５、
及び配線パターン１６の一部が封止される。感光性接着
剤１２には、導電バンプ１３の先端を露出させるための
スルーホール１２ａが形成される。With the photosensitive adhesive 12, the circuit forming surface of the semiconductor chip 11, the conductive bumps 13, the electrode pads 15,
And a part of the wiring pattern 16 is sealed. Through holes 12 a for exposing the tips of the conductive bumps 13 are formed in the photosensitive adhesive 12.

【００４１】上記３次元積層型半導体装置１０Ａは、ユ
ニット半導体装置１４の上面及び下面に、ソルダーレジ
スト膜（絶縁膜）２３及び絶縁膜１９が夫々形成されて
いる。上面のソルダーレジスト膜２３には、スルーホー
ル２３ａが形成されている。スルーホール２３ａ内に
は、ソルダーレジスト膜２３から露出し且つビアプラグ
１８に接触（電気的に結合）するNi/Au、Pd等から成る
外部電極２７が設けられている。絶縁膜１９は、エポキ
シ系樹脂、ガラスクロスを含むエポキシ系樹脂、ポリイ
ミド系樹脂等で構成される。In the three-dimensional stacked semiconductor device 10A, a solder resist film (insulating film) 23 and an insulating film 19 are formed on the upper surface and the lower surface of the unit semiconductor device 14, respectively. Through holes 23a are formed in the solder resist film 23 on the upper surface. An external electrode 27 made of Ni / Au, Pd, or the like, which is exposed from the solder resist film 23 and is in contact with (electrically coupled to) the via plug 18, is provided in the through hole 23a. The insulating film 19 is made of epoxy resin, epoxy resin containing glass cloth, polyimide resin, or the like.

【００４２】図１（ｂ）に示す３次元積層型半導体装置
１０Ａは、図１（ａ）の３次元積層型半導体装置１０と
基本構成は同様であるが、サイズ及び／又は種類が相互
に異なる半導体チップ１１、２４、２５を３段積層した
構成を有する点で異なる。また、図１（ｃ）の３次元積
層型半導体装置１０Ａも、図１（ａ）の３次元積層型半
導体装置１０と同様の基本構成を有するが、サイズ及び
／又は種類が同じ各２段ずつの半導体チップ１１及び２
４を合計４段積層した構成を有する点で異なる。The three-dimensional stacked semiconductor device 10A shown in FIG. 1B has the same basic structure as the three-dimensional stacked semiconductor device 10 of FIG. 1A, but the sizes and / or types are different from each other. The difference is that the semiconductor chips 11, 24 and 25 are laminated in three stages. Further, the three-dimensional stacked semiconductor device 10A of FIG. 1C also has the same basic configuration as the three-dimensional stacked semiconductor device 10 of FIG. 1A, but each two stages have the same size and / or type. Semiconductor chips 11 and 2
It is different in that it has a structure in which four layers are stacked in total of four layers.

【００４３】半導体装置の第２実施形態例 図２（ａ）、（ｂ）は夫々、本実施形態例の３次元積層
型半導体装置１０Ｂの構成を示す断面図及び平面図、図
２（ｃ）はその変形例を示す断面図、図２（ｄ）は別の
変形例を示す断面図である。 Second Embodiment of Semiconductor Device FIGS. 2A and 2B are a sectional view and a plan view showing the structure of a three-dimensional stacked semiconductor device 10B of the present embodiment, respectively, and FIG. 2C. Is a sectional view showing the modified example, and FIG. 2D is a sectional view showing another modified example.

【００４４】図２（ａ）に示すように、本実施形態例の
３次元積層型半導体装置１０Ｂは、図１（ａ）に示した
３次元積層型半導体装置１０Ａを２つ、同一平面内に隣
接して配設した構成を有する。このような３次元積層型
半導体装置１０Ｂを、個々の３次元積層型半導体装置１
０Ａに分割することによって、２個の３次元積層型半導
体装置１０Ａが得られる。As shown in FIG. 2A, the three-dimensional stacked semiconductor device 10B of the present embodiment example has two three-dimensional stacked semiconductor devices 10A shown in FIG. 1A in the same plane. It has a configuration in which it is disposed adjacently. Such a three-dimensional stacked semiconductor device 10B is used as an individual three-dimensional stacked semiconductor device 1
By dividing into 0A, two three-dimensional stacked semiconductor devices 10A are obtained.

【００４５】本実施形態例の３次元積層型半導体装置で
は、絶縁膜１９及びソルダーレジスト膜２３が、図１
（ａ）に比して約２倍の長さを有し、全体の中央部分に
位置する配線パターン１６は、双方の３次元積層型半導
体装置１０Ａで共用されている。配線パターン１６の共
用部分には、隣接する３次元積層型半導体装置１０Ａの
各ビアプラグ１８が形成されている。In the three-dimensional laminated semiconductor device of this embodiment, the insulating film 19 and the solder resist film 23 are formed as shown in FIG.
The wiring pattern 16 which is about twice as long as that in (a) and is located in the central portion of the whole is shared by both the three-dimensional stacked semiconductor devices 10A. In the shared portion of the wiring pattern 16, each via plug 18 of the adjacent three-dimensional stacked semiconductor device 10A is formed.

【００４６】図２（ｂ）では、理解を容易にするため
に、実際には平面位置が同じである絶縁膜１９とソルダ
ーレジスト膜２３との位置を若干ずらして記載してい
る。本３次元積層型半導体装置１０Ｂは、ソルダーレジ
スト膜２３における各半導体チップ１１の周囲に、複数
の外部電極２７が所定のピッチで連続して形成されてい
る。In FIG. 2B, in order to facilitate understanding, the positions of the insulating film 19 and the solder resist film 23, which are actually the same in plane position, are shown with a slight offset. In the present three-dimensional stacked semiconductor device 10B, a plurality of external electrodes 27 are continuously formed at a predetermined pitch around each semiconductor chip 11 in the solder resist film 23.

【００４７】図２（ｃ）に示す３次元積層型半導体装置
１０Ｂは、図２（ａ）の３次元積層型半導体装置１０Ｂ
と基本構成は同様であるが、中央部分に形成されたビア
プラグ１８が共用されて１つのみが配置されている点で
異なる。この構成により、図２（ａ）の３次元積層型半
導体装置１０Ｂよりも、平面方向のサイズが一層コンパ
クトになる。The three-dimensional laminated semiconductor device 10B shown in FIG. 2C is the same as the three-dimensional laminated semiconductor device 10B shown in FIG.
And the basic configuration is the same, except that the via plug 18 formed in the central portion is shared and only one is arranged. With this configuration, the size in the planar direction becomes more compact than that of the three-dimensional stacked semiconductor device 10B of FIG.

【００４８】図２（ｄ）に示す３次元積層型半導体装置
１０Ｂは、図２（ａ）の３次元積層型半導体装置１０Ｂ
と基本構成は同様であるが、平面方向に配列した３次元
積層型半導体装置１０Ａが２個ではなく３個になってい
る点で異なる。つまり、本例の３次元積層型半導体装置
１０Ｂは、同一平面内に、積層した半導体チップ１１の
サイズ及び／又は種類が異なる３次元積層型半導体装置
１０Ａを３個有している。平面上の一端部に位置する３
次元積層型半導体装置１０Ａでは、サイズ及び／又は種
類が同じ構成の半導体チップ１１を４段積層している。
他端部に位置する３次元積層型半導体装置１０Ａでは、
相互にサイズ及び／又は種類が異なる半導体チップ１
１、２４、２５、２６を４段積層している。中央部に位
置する３次元積層型半導体装置１０Ａでは、２種類の異
なる半導体チップ１１、２４を夫々２個ずつ、合計４段
積層している。The three-dimensional stacked semiconductor device 10B shown in FIG. 2D is the same as the three-dimensional stacked semiconductor device 10B shown in FIG.
And the basic configuration is the same, except that the number of the three-dimensional stacked semiconductor devices 10A arranged in the plane direction is three instead of two. That is, the three-dimensional stacked semiconductor device 10B of this example has three three-dimensional stacked semiconductor devices 10A in which the size and / or type of the stacked semiconductor chips 11 are different in the same plane. Located at one end on the plane 3
In the three-dimensional stacked semiconductor device 10A, four semiconductor chips 11 having the same size and / or type are stacked.
In the three-dimensional stacked semiconductor device 10A located at the other end,
Semiconductor chips 1 different in size and / or type from each other
Four layers of 1, 24, 25 and 26 are stacked. In the three-dimensional stacked semiconductor device 10A located in the central portion, two semiconductor chips 11 and 24 of two different types are stacked in each of four layers in total of four layers.

【００４９】半導体装置の第３実施形態例 図３（ａ）は本実施形態例の３次元積層型半導体装置１
０Ａの構成を示す断面図、図２（ｂ）はその変形例を示
す断面図である。 Third Embodiment of Semiconductor Device FIG. 3A shows a three-dimensional stacked semiconductor device 1 according to this embodiment.
FIG. 2B is a sectional view showing the configuration of 0A, and FIG. 2B is a sectional view showing a modification thereof.

【００５０】図３（ａ）に示す３次元積層型半導体装置
１０Ａは、図１（ａ）の３次元積層型半導体装置１０と
基本構成は同様であるが、下段のユニット半導体装置１
４が、下面の絶縁膜１９から露出し且つ配線パターン１
６に導通する導電バンプ３３を有する点で異なる。絶縁
膜１９には、配線パターン１６と対向する位置にスルー
ホール２０ｂが設けられ、スルーホール２０ｂ内に、Ni
/Au等から成る電極パッド３５がめっき法等で形成され
ている。この電極パッド３５上には導電バンプ（外部電
極）３３が形成されている。導電バンプ３３は、Au、Sn
-Pb、Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Bi、Sn-Zn、Sn-Zn-B
i等で構成される。The three-dimensional stacked semiconductor device 10A shown in FIG. 3A has the same basic structure as the three-dimensional stacked semiconductor device 10 shown in FIG.
4 is exposed from the insulating film 19 on the lower surface and the wiring pattern 1
6 is different in that it has conductive bumps 33 that are electrically connected to each other. A through hole 20b is provided in the insulating film 19 at a position facing the wiring pattern 16, and a Ni hole is formed in the through hole 20b.
The electrode pad 35 made of / Au or the like is formed by a plating method or the like. Conductive bumps (external electrodes) 33 are formed on the electrode pads 35. The conductive bumps 33 are Au, Sn
-Pb, Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Bi, Sn-Zn, Sn-Zn-B
i etc.

【００５１】図３（ｂ）に示す３次元積層型半導体装置
１０Ｂは、図３（ａ）の３次元積層型半導体装置１０Ａ
を２つ、同一平面内に隣接して配設した構成を有する。
このような３次元積層型半導体装置１０Ｂを、個々の３
次元積層型半導体装置１０Ａに分割することによって、
２個の３次元積層型半導体装置１０Ａが簡便に得られ
る。The three-dimensional stacked semiconductor device 10B shown in FIG. 3B is the three-dimensional stacked semiconductor device 10A shown in FIG.
2 are arranged adjacent to each other in the same plane.
Such a three-dimensional stacked semiconductor device 10B is manufactured by
By dividing the three-dimensional stacked semiconductor device 10A,
Two three-dimensional stacked semiconductor devices 10A can be easily obtained.

【００５２】本実施形態例の３次元積層型半導体装置１
０Ａ、１０Ｂでは、最上段の表面に露出する外部電極２
７と最下段に露出する導電バンプ３３とを有するので、
積層する際に、上下方向に自在に積層しつつ相互に良好
な接続を得ることができる。Three-dimensional stacked semiconductor device 1 of the present embodiment example
In 0A and 10B, the external electrode 2 exposed on the uppermost surface
7 and the conductive bumps 33 exposed at the bottom,
When laminating, it is possible to obtain good connection with each other while laminating vertically.

【００５３】半導体装置の第４実施形態例 図４（ａ）は本発明に係る第４実施形態例の３次元積層
型半導体装置１０Ａを示す断面図、図４（ｂ）は図４
（ａ）の３次元積層型半導体装置１０Ａを平面方向に２
つ配列した変形例を示す断面図である。図４（ａ）及び
（ｂ）に示す３次元積層型半導体装置１０Ａ、１０Ｂは
夫々、図３（ａ）、（ｂ）に示した３次元積層型半導体
装置１０Ａ、１０Ｂと基本構成は同様であるが、上段の
ユニット半導体装置１４表面のソルダーレジスト膜２３
にスルーホール２０ａ及び外部電極２７が形成されない
点で異なる。 Fourth Embodiment of Semiconductor Device FIG. 4A is a sectional view showing a three-dimensional stacked semiconductor device 10A according to a fourth embodiment of the present invention, and FIG. 4B is FIG.
2A of the three-dimensional stacked semiconductor device 10A of FIG.
It is sectional drawing which shows the modified example which arranged one. The three-dimensional stacked semiconductor devices 10A and 10B shown in FIGS. 4A and 4B have the same basic configuration as the three-dimensional stacked semiconductor devices 10A and 10B shown in FIGS. 3A and 3B, respectively. However, the solder resist film 23 on the surface of the upper unit semiconductor device 14
The difference is that the through hole 20a and the external electrode 27 are not formed.

【００５４】製造方法の第１実施形態例 図５（ａ）〜（ｄ）、図６（ａ）〜（ｄ）、図７（ａ）
〜（ｄ）、図８（ａ）〜（ｄ）及び図９（ａ）、（ｂ）
は夫々、図１（ａ）に示した３次元積層型半導体装置１
０Ａを製造する本実施形態例の製造方法を段階的に示す
断面図である。 First Embodiment of Manufacturing Method FIGS. 5 (a) to 5 (d), 6 (a) to 6 (d), and 7 (a)
~ (D), Fig.8 (a) ~ (d) and Fig.9 (a), (b)
Are the three-dimensional stacked semiconductor devices 1 shown in FIG.
It is sectional drawing which shows the manufacturing method of this embodiment example which manufactures 0A in steps.

【００５５】まず、図５（ａ）に示すように、Ｃｕ又は
Ｃｕ合金等から成る金属板（仮基板）３４上に、真空プ
レス法等を用いて、上面に予め銅箔２１を貼り付けた絶
縁膜１９を貼り合わせる。絶縁膜１９は、エポキシ系樹
脂、ガラスクロスを含有したエポキシ系樹脂、又は、ポ
リイミド系樹脂等で構成することができる。First, as shown in FIG. 5A, a copper foil 21 is preliminarily attached to the upper surface of a metal plate (temporary substrate) 34 made of Cu or a Cu alloy by using a vacuum pressing method or the like. The insulating film 19 is attached. The insulating film 19 can be made of an epoxy resin, an epoxy resin containing glass cloth, a polyimide resin, or the like.

【００５６】次いで、図５（ｂ）に示すように、銅箔２
１上にレジスト膜（図示せず）を形成し、このレジスト
膜をパターニングした後に、めっき法を用いて、Ni/Au
等から成る電極パッド１５を形成する。更に、レジスト
膜を除去してから、図５（ｃ）に示すように、銅箔２１
を配線パターン１６に形成する。Next, as shown in FIG. 5B, the copper foil 2
1 is used to form a resist film (not shown), and after patterning this resist film, a plating method is used to form Ni / Au.
The electrode pad 15 composed of the like is formed. Further, after removing the resist film, as shown in FIG.
Are formed on the wiring pattern 16.

【００５７】続いて、図５（ｄ）に示すように、金スタ
ッドバンプ等から成る導電バンプ１３を備えた回路形成
面に、予め感光性接着剤１２を設けた半導体チップ１１
を電極パッド１５に押し付け、熱圧着法等を用いて、導
電バンプ１３を電極パッド１５に接続しマウントする。
これにより、半導体チップ１１の下面と、配線パターン
１６の一部と、配線パターン１６上の電極パッド１５及
び導電バンプ１３とが感光性接着剤１２によって封止さ
れる。ここで、感光性接着剤１２は、所定の露光・現像
工程によって、導電バンプ１３の先端が露出するように
予めパターニングされている。Subsequently, as shown in FIG. 5D, the semiconductor chip 11 in which the photosensitive adhesive 12 is previously provided on the circuit forming surface having the conductive bumps 13 such as gold stud bumps.
Is pressed against the electrode pad 15, and the conductive bump 13 is connected to the electrode pad 15 and mounted by using a thermocompression bonding method or the like.
As a result, the lower surface of the semiconductor chip 11, a part of the wiring pattern 16, the electrode pads 15 and the conductive bumps 13 on the wiring pattern 16 are sealed with the photosensitive adhesive 12. Here, the photosensitive adhesive 12 is previously patterned by a predetermined exposure / development process so that the tips of the conductive bumps 13 are exposed.

【００５８】引き続き、導電バンプ１３を感光性接着剤
１２で封止した後に、化学機械研磨(ＣＭＰ)等を用い
て、半導体チップ１１の上部を研削し、図６（ａ）に示
すように、厚みが５〜５０μmの極めて薄い半導体チッ
プ１１を得る。続いて、熱プレス法又は真空熱プレス法
等により、図６（ｂ）に示すように、半導体チップ１１
の全体と、配線パターン１６の感光性接着剤１２から露
出した部分とを絶縁樹脂層１７で覆い、硬化させる。Subsequently, after the conductive bumps 13 are sealed with the photosensitive adhesive 12, the upper portion of the semiconductor chip 11 is ground by using chemical mechanical polishing (CMP) or the like, as shown in FIG. An extremely thin semiconductor chip 11 having a thickness of 5 to 50 μm is obtained. Subsequently, as shown in FIG. 6B, the semiconductor chip 11 is formed by a hot pressing method or a vacuum hot pressing method.
And the part of the wiring pattern 16 exposed from the photosensitive adhesive 12 are covered with an insulating resin layer 17 and cured.

【００５９】次いで、図６（ｃ）に示すように、炭酸ガ
スレーザ、ＵＶ−ＹＡＧレーザ、エキシマレーザ等を用
いて、配線パターン１６上に、半導体チップ１１の外側
を通過し絶縁樹脂層１７を貫通するスルーホール２０ｂ
を形成する。更に、Ｃｕめっき法によって、図６（ｄ）
に示すように、スルーホール２０ｂ内にビアプラグ１８
を形成したユニット半導体装置１４を得る。Then, as shown in FIG. 6C, a carbon dioxide gas laser, a UV-YAG laser, an excimer laser or the like is used to pass through the insulating resin layer 17 on the wiring pattern 16 outside the semiconductor chip 11. Through hole 20b
To form. Further, by the Cu plating method, FIG.
As shown in FIG.
A unit semiconductor device 14 having the above is obtained.

【００６０】ビアプラグ１８は、例えば図６（ａ）の工
程後に、Ｃｕめっき法等で、配線パターン１６上に直接
に形成することもできる。この場合には、ビアプラグ１
８の形成工程に続いて、ビアプラグ１８を含む全体を絶
縁樹脂層１７で覆った後に、炭酸ガスレーザ等で絶縁樹
脂層１７を除去してビアプラグ１８を露出させ、図６
（ｄ）に示す構成を得る。The via plug 18 may be directly formed on the wiring pattern 16 by Cu plating or the like after the step of FIG. 6A. In this case, via plug 1
After the step of forming 8 is covered with the insulating resin layer 17 including the via plug 18, the insulating resin layer 17 is removed by a carbon dioxide gas laser or the like to expose the via plug 18, and FIG.
The configuration shown in (d) is obtained.

【００６１】次いで、めっき法等により、図７（ａ）に
示すように、Ｃｕめっき膜３２を形成してから、図５
（ｂ）〜図６（ｄ）までの工程と同様に、図７（ｂ）〜
図７（ｄ）の工程を行う。これにより、図７（ｄ）に示
すように、図６（ｄ）に示したユニット半導体装置１４
を２段積層したユニット半導体装置１４が得られる。Then, a Cu plating film 32 is formed by a plating method or the like as shown in FIG.
7 (b) -FIG. 6 (d), the same as in FIG. 7 (b) -FIG.
The process of FIG. 7D is performed. As a result, as shown in FIG. 7D, the unit semiconductor device 14 shown in FIG.
A unit semiconductor device 14 having two stacked layers is obtained.

【００６２】引き続き、上段のユニット半導体装置１４
における、ビアプラグ１８の上端部を含む絶縁樹脂層１
７上に、図８（ａ）に示すように、ソルダーレジスト膜
２３を形成する。更に、図８（ｂ）に示すように、絶縁
膜１９に貼り合せていた金属板３４を、ケミカルエッチ
ングによって除去する。Subsequently, the upper unit semiconductor device 14
Of the insulating resin layer 1 including the upper end of the via plug 18 in
As shown in FIG. 8A, the solder resist film 23 is formed on the surface 7. Further, as shown in FIG. 8B, the metal plate 34 attached to the insulating film 19 is removed by chemical etching.

【００６３】続いて、図８（ｃ）に示すように、ソルダ
ーレジスト膜２３における上段のビアプラグ１８に対向
する位置に、炭酸ガスレーザ、ＵＶ−ＹＡＧレーザ、エ
キシマレーザ等で、スルーホール２３ａを形成する。更
に、めっき法等で、スルーホール２３ａ内に、ビアプラ
グ１８に接続する外部電極２７を形成する。引き続き、
ビアプラグ１８周囲の絶縁樹脂層１７、配線パターン１
６、ソルダーレジスト膜２３、及び絶縁膜１９をダイシ
ングすることにより、図１（ａ）に示したように外形サ
イズがコンパクトな３次元積層型半導体装置１０Ａが得
られる。Subsequently, as shown in FIG. 8C, a through hole 23a is formed at a position facing the upper via plug 18 in the solder resist film 23 by a carbon dioxide laser, a UV-YAG laser, an excimer laser or the like. . Further, an external electrode 27 connected to the via plug 18 is formed in the through hole 23a by a plating method or the like. Continuing,
Insulating resin layer 17 around the via plug 18, wiring pattern 1
By dicing 6, the solder resist film 23, and the insulating film 19, a three-dimensional stacked semiconductor device 10A having a compact outer size as shown in FIG. 1A is obtained.

【００６４】或いは、図８（ｂ）に後続して、炭酸ガス
レーザ等により、図８（ｄ）に示すように、絶縁膜１９
の電極パッド１５に対応する位置にスルーホール２０ｂ
を形成し、このスルーホール２０ｂ内に電極パッド３５
を形成することができる。この場合、電極パッド３５
は、Ｎｉ／Ａｕ、Ｐｄ等を用いた無電解めっき法等によ
って形成する。更に、リフロー等により、図９（ａ）に
示すように、電極パッド３５上に導電バンプ３３を形成
する。Alternatively, after the step shown in FIG. 8B, an insulating film 19 is formed by a carbon dioxide gas laser or the like as shown in FIG. 8D.
Through hole 20b at a position corresponding to the electrode pad 15 of
And the electrode pad 35 is formed in the through hole 20b.
Can be formed. In this case, the electrode pad 35
Is formed by an electroless plating method using Ni / Au, Pd, or the like. Further, as shown in FIG. 9A, the conductive bumps 33 are formed on the electrode pads 35 by reflow or the like.

【００６５】次いで、ビアプラグ１８周囲の絶縁樹脂層
１７、配線パターン１６、ソルダーレジスト膜２３及び
絶縁膜１９をダイシングすることによって、図４（ａ）
に示した外形サイズがコンパクトな３次元積層型半導体
装置１０Ａが得られる。Next, the insulating resin layer 17, the wiring pattern 16, the solder resist film 23, and the insulating film 19 around the via plug 18 are diced to obtain the structure shown in FIG.
As a result, the three-dimensional stacked semiconductor device 10A having a compact outer size shown in FIG.

【００６６】製造方法の第２実施形態例 図１０（ａ）〜（ｅ）、図１１（ａ）〜（ｅ）、図１２
（ａ）〜（ｄ）及び図１３（ａ）〜（ｃ）は夫々、図１
（ａ）に示した３次元積層型半導体装置１０Ａを製造す
る本実施形態例の製造方法を段階的に示す断面図であ
る。 Second Embodiment of Manufacturing Method FIGS. 10 (a) to (e), FIGS. 11 (a) to (e), and FIG.
(A)-(d) and FIG. 13 (a)-(c) are respectively FIG.
It is sectional drawing which shows the manufacturing method of the example of this embodiment which manufactures the three-dimensional laminated semiconductor device 10A shown to (a) in steps.

【００６７】まず、図１０（ａ）に示すように、Ｃｕ又
はＣｕ合金等から成る金属板（仮基板）３４上に、配線
パターン１６を直接に形成する。次いで、配線パターン
１６上にレジスト膜（図示せず）を形成し、このレジス
ト膜をパターニングした後、めっき法により、図１０
（ｂ）に示すように、Ni/Au等から成る電極パッド１５
を形成する。First, as shown in FIG. 10A, the wiring pattern 16 is directly formed on the metal plate (temporary substrate) 34 made of Cu or Cu alloy. Next, a resist film (not shown) is formed on the wiring pattern 16, the resist film is patterned, and then a plating method is performed as shown in FIG.
As shown in (b), the electrode pad 15 made of Ni / Au or the like
To form.

【００６８】続いて、レジスト膜を除去してから、図１
０（ｃ）に示すように、回路形成面に感光性接着剤１２
を設けた半導体チップ１１を電極パッド１５に押し付
け、熱圧着法等を用いて、導電バンプ１３と電極パッド
１５とを接続する。ここで、感光性接着剤１２には、導
電バンプ１３の先端を露出させるスルーホール１２aが
予め形成されている。Then, after removing the resist film, the process shown in FIG.
As shown in 0 (c), the photosensitive adhesive 12 is formed on the circuit forming surface.
The semiconductor chip 11 provided with is pressed against the electrode pad 15, and the conductive bump 13 and the electrode pad 15 are connected by a thermocompression bonding method or the like. Here, the photosensitive adhesive 12 is preliminarily formed with a through hole 12a for exposing the tip of the conductive bump 13.

【００６９】引き続き、図１０（ｄ）に示すように、半
導体チップ１１の下部を感光性接着剤１２で封止した
後、半導体チップ１１の上部を研削して、厚みが５〜５
０μmの極めて薄い半導体チップ１１を得る。Subsequently, as shown in FIG. 10D, after sealing the lower part of the semiconductor chip 11 with the photosensitive adhesive 12, the upper part of the semiconductor chip 11 is ground to a thickness of 5 to 5
An extremely thin semiconductor chip 11 of 0 μm is obtained.

【００７０】次いで、図１０（ｅ）に示すように、熱プ
レス法又は真空熱プレス法等を用いて、配線パターン１
６の露出部分を含む半導体チップ１１全体を絶縁樹脂層
１７で覆い、硬化させる。更に、炭酸ガスレーザ等を用
いて、半導体チップ１１近傍の絶縁樹脂層１７に、図１
１（ａ）に示すように、スルーホール２０ａを形成す
る。この後、めっき法により、図１１（ｂ）に示すよう
に、スルーホール２０ａ内にＣｕめっきから成るビアプ
ラグ１８を形成する。Then, as shown in FIG. 10E, the wiring pattern 1 is formed by using a hot pressing method or a vacuum hot pressing method.
The entire semiconductor chip 11 including the exposed portions of 6 is covered with the insulating resin layer 17 and cured. Further, by using a carbon dioxide gas laser or the like, the insulating resin layer 17 near the semiconductor chip 11 is formed on the insulating resin layer 17 as shown in FIG.
As shown in FIG. 1A, the through hole 20a is formed. Then, as shown in FIG. 11B, a via plug 18 made of Cu plating is formed in the through hole 20a by a plating method.

【００７１】或いは、上記に代えて、図１０（ｄ）の工
程後に、配線パターン１６上にＣｕめっき法でビアプラ
グ１８を形成してから、ビアプラグ１８及び半導体チッ
プ１１を含む全体を絶縁樹脂層１７で覆うことができ
る。この場合には、更に、炭酸ガスレーザ等を用いて、
絶縁樹脂層１７を選択的に除去してビアプラグ１８の上
端を露出させ、図１１（ｂ）の状態を得ることもでき
る。Alternatively, instead of the above, after the step of FIG. 10D, the via plug 18 is formed on the wiring pattern 16 by the Cu plating method, and then the entire insulating resin layer 17 including the via plug 18 and the semiconductor chip 11 is formed. Can be covered with. In this case, using a carbon dioxide laser, etc.,
It is also possible to selectively remove the insulating resin layer 17 to expose the upper end of the via plug 18 and obtain the state of FIG.

【００７２】次いで、めっき法により、図１１（ｃ）に
示すように、ビアプラグ１８上端面を含む絶縁樹脂層１
７上にＣｕめっき膜３２を形成してから、図１１（ｄ）
〜図１２（ａ）に示すように、図１０（ａ）〜図１１
（ｃ）と同様の工程を繰り返し行い、図１２（ｂ）に示
すように、最上面にソルダーレジスト膜２３を形成す
る。Next, as shown in FIG. 11C, the insulating resin layer 1 including the upper end surface of the via plug 18 is formed by plating.
11 (d) after forming the Cu plating film 32 on 7
~ As shown in Fig. 12 (a), Fig. 10 (a) ~ Fig. 11
The same process as in (c) is repeated to form the solder resist film 23 on the uppermost surface as shown in FIG.

【００７３】続いて、ケミカルエッチングによって、絶
縁膜１９の下面に貼り付いている金属板３４を図１２
（ｃ）に示すように除去する。更に、真空プレス法等を
用いて、図１２（ｄ）に示すように、下段のユニット半
導体装置１４における、配線パターン１６の露出面を含
む感光性接着剤１２上に、エポキシ系樹脂等から成る絶
縁膜１９を形成する。Subsequently, the metal plate 34 adhered to the lower surface of the insulating film 19 is chemically etched, as shown in FIG.
Remove as shown in (c). Further, using a vacuum pressing method or the like, as shown in FIG. 12D, an epoxy resin or the like is formed on the photosensitive adhesive 12 including the exposed surface of the wiring pattern 16 in the lower unit semiconductor device 14. The insulating film 19 is formed.

【００７４】次いで、炭酸ガスレーザ等を用いて、図１
３（ａ）に示すように、絶縁膜１９における配線パター
ン１６に対向する位置に、スルーホール２０ｂを形成す
る。更に、無電解めっき法等によって、図１３（ｂ）に
示すように、スルーホール２０ａ内に露出した配線パタ
ーン１６上に、Ni/Au、Pd等から成る電極パッド３５を
形成する。続いて、リフロー等により、電極パッド３５
上に、Sn-Pb、Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Bi、Sn-Z
n、Sn-Zn-Bi等から成る導電バンプ３３を形成する。Then, using a carbon dioxide laser or the like, as shown in FIG.
As shown in FIG. 3A, a through hole 20b is formed in the insulating film 19 at a position facing the wiring pattern 16. Further, as shown in FIG. 13B, an electrode pad 35 made of Ni / Au, Pd or the like is formed on the wiring pattern 16 exposed in the through hole 20a by an electroless plating method or the like. Then, the electrode pad 35 is formed by reflow or the like.
On top, Sn-Pb, Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Bi, Sn-Z
A conductive bump 33 made of n, Sn-Zn-Bi or the like is formed.

【００７５】引き続き、ビアプラグ１８の周囲の絶縁樹
脂層１７、配線パターン１６、ソルダーレジスト膜２３
及び絶縁膜１９をダイシングすることにより、図４
（ａ）に示した３次元積層型半導体装置１０Ａを得る。Subsequently, the insulating resin layer 17, the wiring pattern 16, and the solder resist film 23 around the via plug 18 are formed.
By dicing the insulating film 19 and the insulating film 19, as shown in FIG.
The three-dimensional stacked semiconductor device 10A shown in (a) is obtained.

【００７６】或いは、上記に代えて、図１２（ｃ）の工
程に後続して、炭酸ガスレーザ、ＵＶ−ＹＡＧレーザ、
エキシマレーザ等を用いて、ソルダーレジスト膜２３
に、ビアプラグ１８に対応するスルーホール２３ａ（図
１参照）を形成した後、無電解めっき法等で、スルーホ
ール内に電極パッド２７（図１参照）を形成することが
できる。この場合、更に、最下層の配線パターン１６下
面に、図１２（ｄ）に示す絶縁膜１９を形成する。引き
続き、電極パッド２７の周囲部分をダイシングすること
により、図１（ａ）に示した３次元積層型半導体装置１
０Ａを得る。Alternatively, instead of the above, following the step of FIG. 12C, a carbon dioxide gas laser, a UV-YAG laser,
The solder resist film 23 is formed by using an excimer laser or the like.
After forming the through hole 23a (see FIG. 1) corresponding to the via plug 18, the electrode pad 27 (see FIG. 1) can be formed in the through hole by an electroless plating method or the like. In this case, the insulating film 19 shown in FIG. 12D is further formed on the lower surface of the lowermost wiring pattern 16. Subsequently, by dicing the peripheral portion of the electrode pad 27, the three-dimensional stacked semiconductor device 1 shown in FIG.
You get 0A.

【００７７】製造方法の第３実施形態例 図１４（ａ）〜（ｄ）及び図１５（ａ）〜（ｃ）は夫
々、図４に示した３次元積層型半導体装置を製造する本
実施形態例の製造方法を段階的に示す断面図である。 Third Embodiment of Manufacturing Method FIGS. 14A to 14D and FIGS. 15A to 15C respectively show the present embodiment for manufacturing the three-dimensional stacked semiconductor device shown in FIG. It is sectional drawing which shows the manufacturing method of an example in steps.

【００７８】まず、図５（ｃ）の工程に後続して、図１
４（ｂ）に示すように、配線パターン１６の電極パッド
１５上に、導電バンプ１３を有する回路形成面に感光性
接着剤１２が設けられた半導体チップ１１を熱圧着法等
により接続する。次いで、めっき法等により、配線パタ
ーン１６上に、半導体チップに隣接する起立状態のビア
プラグ１８を形成する。First, after the step of FIG.
As shown in FIG. 4B, the semiconductor chip 11 having the photosensitive adhesive 12 provided on the circuit forming surface having the conductive bumps 13 is connected to the electrode pads 15 of the wiring pattern 16 by a thermocompression bonding method or the like. Then, a standing via plug 18 adjacent to the semiconductor chip is formed on the wiring pattern 16 by a plating method or the like.

【００７９】引き続き、熱プレス法や真空熱プレス法等
によって、図１４（ｃ）に示すように、半導体チップ１
１、ビアプラグ１８、及び配線パターン１６の露出面を
絶縁樹脂層１７で覆う。この後、図１４（ｄ）に示すよ
うに、絶縁樹脂層１７の表面側から絶縁樹脂層１７及び
半導体チップ１１を研削し、厚みが５μm〜５０μmの半
導体チップ１１を得る。Subsequently, as shown in FIG. 14C, the semiconductor chip 1 is formed by a hot pressing method or a vacuum hot pressing method.
1, the exposed surfaces of the via plug 18 and the wiring pattern 16 are covered with the insulating resin layer 17. Thereafter, as shown in FIG. 14D, the insulating resin layer 17 and the semiconductor chip 11 are ground from the surface side of the insulating resin layer 17 to obtain the semiconductor chip 11 having a thickness of 5 μm to 50 μm.

【００８０】続いて、熱プレス法や真空熱プレス法等に
よって、図１５（ａ）に示すように、絶縁樹脂層１７表
面及びビアプラグ１８上端面を含む半導体チップ１１上
部に、絶縁膜３７を形成する。更に、炭酸ガスレーザ、
ＵＶ−ＹＡＧレーザ、エキシマレーザ等を用いて、図１
５（ｂ）に示すように、ビアプラグ１８上の絶縁膜３７
にスルーホール２０ａを形成し、ビアプラグ１８を露出
させる。Subsequently, as shown in FIG. 15A, an insulating film 37 is formed on the upper part of the semiconductor chip 11 including the surface of the insulating resin layer 17 and the upper end surface of the via plug 18 by a hot pressing method or a vacuum hot pressing method. To do. In addition, carbon dioxide laser,
Using a UV-YAG laser, excimer laser, etc., FIG.
As shown in FIG. 5B, the insulating film 37 on the via plug 18
A through hole 20a is formed in the substrate and the via plug 18 is exposed.

【００８１】引き続き、図１５（ｃ）に示すように、ス
ルーホール２０ａ内を含む絶縁樹脂３７上に銅箔（３
６）を形成してから、配線パターン３６に形成する。更
に、図１４（ａ）〜図１５（ｃ）の工程を繰り返し行っ
た後、図８（ａ）〜図９（ｂ）の工程を行って、図４
（ａ）に示す３次元積層型半導体装置１０Ａを得る。Subsequently, as shown in FIG. 15C, a copper foil (3) is formed on the insulating resin 37 including the inside of the through hole 20a.
After forming 6), the wiring pattern 36 is formed. Further, after repeatedly performing the steps of FIGS. 14A to 15C, the steps of FIGS. 8A to 9B are performed, and the steps of FIG.
A three-dimensional stacked semiconductor device 10A shown in (a) is obtained.

【００８２】製造方法の第４実施形態例 図１６（ａ）〜（ｄ）及び図１７（ａ）〜（ｃ）は夫
々、図４に示した３次元積層型半導体装置１０Ａを製造
する本実施形態例の製造方法を段階的に示す断面図であ
る。 Fourth Embodiment of Manufacturing Method FIGS. 16A to 16D and FIGS. 17A to 17C respectively show the present embodiment for manufacturing the three-dimensional stacked semiconductor device 10A shown in FIG. It is sectional drawing which shows the manufacturing method of a form example in steps.

【００８３】まず、図１６（ａ）に示すように、金属板
３４上に配線パターン１６を形成し、配線パターン１６
上に電極パッド１５を形成した後、図１６（ｂ）に示す
ように、製造方法の第３実施形態例と同様に、熱圧着法
等により、フェースダウンで半導体チップ１１の導電バ
ンプ１３を電極パッド１５に接続する。First, as shown in FIG. 16A, the wiring pattern 16 is formed on the metal plate 34, and then the wiring pattern 16 is formed.
After forming the electrode pads 15 on the upper surface, as shown in FIG. 16B, the conductive bumps 13 of the semiconductor chip 11 are electrode-down face down by a thermocompression bonding method or the like, as in the third embodiment of the manufacturing method. Connect to pad 15.

【００８４】次いで、めっき法等を用いて、配線パター
ン１６上に、ビアプラグ１８を起立状態で形成する。更
に、熱プレス法や真空熱プレス法等によって、図１６
（ｃ）に示すように、半導体チップ１１、ビアプラグ１
８、及び配線パターン１６の露出面を絶縁樹脂層１７で
覆う。この後、図１６（ｄ）に示すように、絶縁樹脂層
１７の表面側から絶縁樹脂層１７及び半導体チップ１１
上部を研削し、厚みが５μm〜５０μmの半導体チップ１
１を得る。Next, a via plug 18 is formed in an upright state on the wiring pattern 16 by using a plating method or the like. Further, by a hot pressing method, a vacuum hot pressing method, or the like, as shown in FIG.
As shown in (c), the semiconductor chip 11 and the via plug 1
8 and the exposed surface of the wiring pattern 16 are covered with an insulating resin layer 17. Thereafter, as shown in FIG. 16D, the insulating resin layer 17 and the semiconductor chip 11 are arranged from the front surface side of the insulating resin layer 17.
The upper part is ground, and the semiconductor chip 1 has a thickness of 5 μm to 50 μm.
Get one.

【００８５】続いて、熱プレス法や真空熱プレス法等を
用いて、絶縁樹脂層１７と同じ材質の絶縁膜３７で、図
１７（ａ）に示すように、絶縁樹脂層１７、ビアプラグ
１８及び半導体チップ１１上部を覆う。更に、炭酸ガス
レーザ、ＵＶ−ＹＡＧレーザ、エキシマレーザ等を用い
て、絶縁膜３７にスルーホール２０ａを形成してビアプ
ラグ１８を露出させる。引き続き、めっき法等により、
スルーホール２０ａ内を含む表面全体を銅箔（３６）で
覆った後、この銅箔（３６）を配線パターン３６に形成
する。続いて、図１６（ｂ）〜図１７（ｃ）までの工程
を繰り返し行った後、図８（ａ）〜図９（ｂ）の工程を
行って、図４（ａ）に示す３次元積層型半導体装置１０
Ａを得る。Then, using an insulating film 37 made of the same material as the insulating resin layer 17 by using a hot pressing method or a vacuum hot pressing method, as shown in FIG. The upper part of the semiconductor chip 11 is covered. Further, a carbon dioxide gas laser, a UV-YAG laser, an excimer laser or the like is used to form a through hole 20a in the insulating film 37 to expose the via plug 18. Then, by plating method,
After covering the entire surface including the inside of the through hole 20a with the copper foil (36), the copper foil (36) is formed on the wiring pattern 36. Subsequently, after repeatedly performing the steps of FIGS. 16B to 17C, the steps of FIGS. 8A to 9B are performed to perform the three-dimensional stacking shown in FIG. Type semiconductor device 10
Get A.

【００８６】半導体装置の第５実施形態例 図１８（ａ）及び（ｂ）は夫々、本実施形態例の３次元
積層型半導体装置１０Ｂを示す断面図である。図１８
（ａ）に示す３次元積層型半導体装置１０Ｂは、サイズ
及び／又は種類が同じ半導体チップ１１の２段積層の３
次元積層型半導体装置１０Ｂ（図２(a)）を４段積層構
造にしたものである。この４段積層の３次元積層型半導
体装置１０Ｂは、最上段のユニット半導体装置１４の表
面を覆うソルダーレジスト膜２３に、外部電極２７（図
１８(ｂ)）は形成されず、最下段のユニット半導体装置
１４の下面を覆う絶縁膜１９に、導電バンプ３３（図３
(b)）は形成されていない。また、図１８（ｂ）は、図
２（ａ）に示した３次元積層型半導体装置１０Ｂにおけ
る導電バンプ３３を無くした形態を示している。 Fifth Embodiment of Semiconductor Device FIGS. 18A and 18B are sectional views showing a three-dimensional stacked semiconductor device 10B of the present embodiment, respectively. FIG.
The three-dimensional stacked semiconductor device 10B shown in (a) has three stacked semiconductor chips 11 of the same size and / or type.
The three-dimensional stacked semiconductor device 10B (FIG. 2A) has a four-stage stacked structure. In this three-dimensional stacked semiconductor device 10B having four stacked layers, the external electrodes 27 (FIG. 18B) are not formed on the solder resist film 23 that covers the surface of the uppermost unit semiconductor device 14, and the lowermost unit is formed. The conductive bump 33 (see FIG. 3) is formed on the insulating film 19 that covers the lower surface of the semiconductor device 14.
(b)) is not formed. Further, FIG. 18B shows a form in which the conductive bump 33 in the three-dimensional stacked semiconductor device 10B shown in FIG. 2A is eliminated.

【００８７】製造方法の第５実施形態例 図１９（ａ）、（ｂ）及び図２０（ａ）、（ｂ）は夫
々、図１８（ａ）、（ｂ）に示した３次元積層型半導体
装置１０Ｂを製造する本実施形態例の製造方法を示す断
面図である。 Fifth Embodiment of Manufacturing Method FIGS. 19A and 19B and FIGS. 20A and 20B are three-dimensional laminated semiconductors shown in FIGS. 18A and 18B, respectively. It is sectional drawing which shows the manufacturing method of the example of this embodiment which manufactures the apparatus 10B.

【００８８】図１９及び図２０に示す製造プロセスの概
要において、個々の３次元積層型半導体装置１０Ａを形
成する製造プロセスは、図５〜図９で説明した製造プロ
セスとほぼ同様である。しかし、本製造プロセスでは、
平面方向に長い金属板３４を仮基板として使用し、金属
板３４上に、ユニット半導体装置１４を４段積層して、
平面方向に複数の３次元積層型半導体装置１０Ａを一括
して作製する。In the outline of the manufacturing process shown in FIGS. 19 and 20, the manufacturing process for forming each of the three-dimensional stacked semiconductor devices 10A is substantially the same as the manufacturing process described with reference to FIGS. However, in this manufacturing process,
A metal plate 34 that is long in the plane direction is used as a temporary substrate, and four unit semiconductor devices 14 are stacked on the metal plate 34.
A plurality of three-dimensional stacked semiconductor devices 10A are collectively manufactured in the plane direction.

【００８９】図１９（ａ）、（ｂ）に示す製造プロセス
では、金属板３４上に絶縁膜１９を形成してから、ユニ
ット半導体装置１４を積層する。これに対し、図２０
（ａ）、（ｂ）に示す製造プロセスでは、金属板３４上
に絶縁膜１９を形成せずにユニット半導体装置１４を積
層するため、ケミカルエッチングで金属板３４を除去し
た際に露出する最下層の配線パターン１６を絶縁膜１９
で覆う。In the manufacturing process shown in FIGS. 19A and 19B, the insulating film 19 is formed on the metal plate 34, and then the unit semiconductor device 14 is laminated. On the other hand, FIG.
In the manufacturing process shown in (a) and (b), since the unit semiconductor device 14 is laminated without forming the insulating film 19 on the metal plate 34, the lowermost layer exposed when the metal plate 34 is removed by chemical etching. The wiring pattern 16 of the insulating film 19
Cover with.

【００９０】図１９及び図２０に示した製造プロセスで
は、金属板３４を除去した後に露出する又は新たに形成
する絶縁膜１９に、炭酸ガスレーザ等により、図９に示
すようなスルーホール２０ｂを形成し、このスルーホー
ル２０ｂ内に電極パッド３５を形成する。更に、スルー
ホール２０ｂ内に、リフロー等で導電バンプ３３を形成
して電極パッド３５に接続する。In the manufacturing process shown in FIGS. 19 and 20, through holes 20b as shown in FIG. 9 are formed in the insulating film 19 exposed or newly formed after removing the metal plate 34 by a carbon dioxide laser or the like. Then, the electrode pad 35 is formed in the through hole 20b. Further, a conductive bump 33 is formed in the through hole 20b by reflowing or the like and connected to the electrode pad 35.

【００９１】最後に、図１９（ｂ）及び図２０（ｂ）に
示す３次元積層型半導体装置１０Ｂをダイシングし、３
次元積層型半導体装置１０Ａを個別化することにより、
図１（ａ）及び図４（ａ）に示した３次元積層構造を４
段にした３次元積層型半導体装置１０Ａを、一括して得
ることができる。このようにして作製した３次元積層型
半導体装置１０Ａをダイシングする際に、同一平面内に
複数の３次元積層型半導体装置１０Ａが残るようにすれ
ば、図２（ａ）、（ｃ）、図３（ｂ）、及び図４（ｂ）
に示すような、３次元積層型半導体装置１０Aを一括で
得ることができる。Finally, the three-dimensional stacked semiconductor device 10B shown in FIGS. 19 (b) and 20 (b) is diced.
By individualizing the three-dimensional stacked semiconductor device 10A,
The three-dimensional laminated structure shown in FIG. 1A and FIG.
It is possible to collectively obtain the three-dimensional stacked semiconductor device 10A having a step. When dicing the three-dimensional stacked semiconductor device 10A produced in this manner, if a plurality of three-dimensional stacked semiconductor devices 10A are left in the same plane, FIG. 2A, FIG. 3 (b) and FIG. 4 (b)
It is possible to collectively obtain the three-dimensional stacked semiconductor device 10A as shown in FIG.

【００９２】本実施形態例によると、複数の３次元積層
型半導体装置１０Ａを平面方向に配列させた状態で一度
に形成できるので、各３次元積層型半導体装置１０Ａ間
で金属板３４を共通に使用し、金属板３４上に配線パタ
ーン１６を形成する工程以降、金属板３４の除去工程ま
でを、各層で同時進行的に実施することができる。これ
により、複数の３次元積層型半導体装置１０Ａの形成工
程を簡略化し、個々の３次元積層型半導体装置１０Ａを
得るまでに要する時間を短縮することができる。According to this embodiment, a plurality of three-dimensional stacked semiconductor devices 10A can be formed at a time in a state of being arranged in the plane direction, so that the metal plate 34 is commonly used among the three-dimensional stacked semiconductor devices 10A. After the step of forming the wiring pattern 16 on the metal plate 34 by using it, the steps up to the step of removing the metal plate 34 can be simultaneously performed in each layer. Thereby, the process of forming the plurality of three-dimensional stacked semiconductor devices 10A can be simplified, and the time required to obtain each of the three-dimensional stacked semiconductor devices 10A can be shortened.

【００９３】半導体装置の第６実施形態例 図２１は、封止絶縁膜４１で覆ってパッケージ化した本
実施形態例の３次元積層型半導体装置１０Ａを示す断面
図である。本実施形態例では、図１（ａ）に示した３次
元積層型半導体装置１０Ａが、最下層の絶縁膜１９をマ
ザーボード４７又はインターポーザ基板４９に接着され
ている。また、図１（ａ）に示したソルダーレジスト膜
２３が除去されて電極パッド２７が突出し、電極パッド
２７と、マザーボード４７又はインターポーザ基板４９
上に形成された電極パッド４５とが、金ワイヤ４０でワ
イヤボンディング接続されている。更に、金ワイヤ４０
を含む３次元積層型半導体装置１０Ａ全体が封止絶縁膜
４１で封止されてパッケージ化されている。 Sixth Embodiment of Semiconductor Device FIG. 21 is a sectional view showing a three-dimensional stacked semiconductor device 10A of the present embodiment which is packaged by being covered with a sealing insulating film 41. In the present embodiment example, the three-dimensional stacked semiconductor device 10A shown in FIG. 1A has the lowermost insulating film 19 bonded to the mother board 47 or the interposer substrate 49. Further, the solder resist film 23 shown in FIG. 1A is removed and the electrode pads 27 are projected, and the electrode pads 27 and the mother board 47 or the interposer substrate 49 are formed.
The electrode pad 45 formed above is wire-bonded to the electrode pad 45 by a gold wire 40. Furthermore, the gold wire 40
The entire three-dimensional stacked semiconductor device 10A including is sealed by the sealing insulating film 41 and packaged.

【００９４】半導体装置の第７実施形態例 図２２は、封止絶縁膜４１で覆ってパッケージ化した本
実施形態例の３次元積層型半導体装置１０Ａを示す断面
図である。本実施形態例では、図２１に示した最上層の
半導体チップ１１上に、サイズ及び／又は種類が異なる
半導体チップ２５が、絶縁膜１９を介してフェースアッ
プで接着されている。この半導体チップ２５上に形成さ
れた電極パッド２５ａと、マザーボード１７又はインタ
ーポーザ基板１９上の電極パッド４５とが、金ワイヤ４
０でワイヤボンディング接続されている。更に、金ワイ
ヤ４０を含む３次元積層型半導体装置１０Ａ全体が封止
絶縁膜４１で封止されてパッケージ化されている。 Seventh Embodiment of Semiconductor Device FIG. 22 is a sectional view showing a three-dimensional stacked semiconductor device 10A of the present embodiment which is packaged by being covered with a sealing insulating film 41. In the present embodiment example, semiconductor chips 25 of different sizes and / or types are bonded face-up via the insulating film 19 on the uppermost semiconductor chip 11 shown in FIG. The electrode pad 25a formed on the semiconductor chip 25 and the electrode pad 45 on the mother board 17 or the interposer substrate 19 are the gold wires 4
Wire bonding connection is made at 0. Furthermore, the entire three-dimensional stacked semiconductor device 10A including the gold wire 40 is sealed with a sealing insulating film 41 and packaged.

【００９５】図２２では、３次元積層型半導体装置１０
Ａ上に、この半導体装置１０Ａとはサイズが異なる半導
体チップ２５を１枚積層した例を示したが、パッケージ
の厚み仕様の範囲内であれば、２枚以上の半導体チップ
２５を同様の手法で積層することができる。In FIG. 22, the three-dimensional stacked semiconductor device 10 is shown.
An example in which one semiconductor chip 25 having a size different from that of the semiconductor device 10A is stacked on A is shown. However, if the semiconductor chip 25 is within the package thickness specification, two or more semiconductor chips 25 are formed by the same method. It can be laminated.

【００９６】半導体装置の第８実施形態例 図２３は、本実施形態例の３次元積層型半導体装置１０
Ａを示す断面図である。本実施形態例の３次元積層型半
導体装置１０Ａでは、図３に示した３次元積層型半導体
装置１０Ａ上に、図４に示した構成とは導電バンプ３３
の位置がやや異なる３次元積層型半導体装置１０Ａが積
層され、上段側の導電バンプ３３を介して相互に接続さ
れている。この構成を実現するために、上層側の３次元
積層型半導体装置１０Ａでは、導電バンプ３３がビアプ
ラグ１８の下部に形成されている。本実施形態例では、
上下の３次元積層型半導体装置１０Ａ間のスペースに、
アンダーフィル樹脂を挿入することもできる。 Eighth Embodiment of Semiconductor Device FIG. 23 shows a three-dimensional stacked semiconductor device 10 according to this embodiment.
It is sectional drawing which shows A. In the three-dimensional stacked semiconductor device 10A of the present embodiment, the conductive bumps 33 are provided on the three-dimensional stacked semiconductor device 10A shown in FIG.
The three-dimensional stacked semiconductor devices 10A whose positions are slightly different are stacked and connected to each other through the conductive bumps 33 on the upper side. In order to realize this configuration, the conductive bump 33 is formed below the via plug 18 in the upper layer three-dimensional stacked semiconductor device 10A. In this embodiment example,
In the space between the upper and lower three-dimensional stacked semiconductor devices 10A,
An underfill resin can also be inserted.

【００９７】半導体装置の第９実施形態例 図２４は、本実施形態例のパッケージ化した３次元積層
型半導体装置１０Ａを示す断面図である。本実施形態例
では、図１２（ｄ）の３次元積層型半導体装置１０Ａ上
に、これとはサイズ及び／又は種類が異なる図１（ａ）
の３次元積層型半導体装置１０Ａが、絶縁膜１９を介し
て積層され接着されている。また、下段の３次元積層型
半導体装置１０Ａの絶縁膜１９が、マザーボード４７又
はインターポーザ基板４９上に接着され、上下の各３次
元積層型半導体装置１０Ａが夫々、マザーボード４７又
はインターポーザ基板４９上の電極パッド４５に、ビア
プラグ１８及び外部電極２７を接続している。更に、金
ワイヤ４０を含む３次元積層型半導体装置１０Ａ全体が
封止絶縁膜４１で封止されて、パッケージ化されてい
る。 Ninth Embodiment of Semiconductor Device FIG. 24 is a sectional view showing a packaged three-dimensional stacked semiconductor device 10A according to this embodiment. In the present embodiment, the size and / or type of the three-dimensional stacked semiconductor device 10A of FIG. 12D is different from that of FIG.
The three-dimensional laminated semiconductor device 10A is laminated and adhered via the insulating film 19. The insulating film 19 of the lower three-dimensional stacked semiconductor device 10A is adhered onto the mother board 47 or the interposer substrate 49, and the upper and lower three-dimensional stacked semiconductor devices 10A are electrodes on the mother board 47 or the interposer substrate 49, respectively. The via plug 18 and the external electrode 27 are connected to the pad 45. Further, the entire three-dimensional stacked semiconductor device 10A including the gold wire 40 is sealed with the sealing insulating film 41 and packaged.

【００９８】半導体装置の第１０実施形態例 図２５（ａ）は本実施形態例のパッケージ化した３次元
積層型半導体装置１０Ａを示す断面図、図２５（ｂ）は
図２５（ａ）の変形例を示す断面図である。 Tenth Embodiment of Semiconductor Device FIG. 25 (a) is a sectional view showing a packaged three-dimensional stacked semiconductor device 10A of this embodiment, and FIG. 25 (b) is a modification of FIG. 25 (a). It is sectional drawing which shows an example.

【００９９】本実施形態例では、マザーボード４７又は
インターポーザ基板４９上にパッケージ化された図１
（ａ）の３次元積層型半導体装置１０Ａが２段積層さ
れ、双方の３次元積層型半導体装置１０Ａが、導電バン
プ３３を介して相互に接続されている。In this embodiment, the package is provided on the mother board 47 or the interposer substrate 49 shown in FIG.
The three-dimensional laminated semiconductor device 10A of (a) is laminated in two stages, and both the three-dimensional laminated semiconductor devices 10A are connected to each other via the conductive bumps 33.

【０１００】図２５（ａ）に示すように、上段の３次元
積層型半導体装置１０Ａでは、最下部の絶縁膜１９がマ
ザーボード４７又はインターポーザ基板４９上に接着さ
れている。上段のユニット半導体装置１４の外部電極２
７が、マザーボード４７又はインターポーザ基板４９上
の電極パッド４５に、金ワイヤ４０を介してワイヤボン
ディング接続される。マザーボード４７又はインターポ
ーザ基板４９の下面には、電極パッド４５に導通する電
極パッド５９が形成され、この電極パッド５９上に導電
バンプ３３が形成される。更に、金ワイヤ４０を含む３
次元積層型半導体装置１０Ａ全体が封止絶縁膜４１で封
止されている。As shown in FIG. 25A, in the upper three-dimensional stacked semiconductor device 10A, the lowermost insulating film 19 is adhered onto the mother board 47 or the interposer substrate 49. External electrode 2 of upper unit semiconductor device 14
7 is wire-bonded to the electrode pad 45 on the mother board 47 or the interposer substrate 49 via the gold wire 40. On the lower surface of the mother board 47 or the interposer substrate 49, electrode pads 59 that are electrically connected to the electrode pads 45 are formed, and the conductive bumps 33 are formed on the electrode pads 59. Furthermore, 3 including the gold wire 40
The entire three-dimensional stacked semiconductor device 10A is sealed with a sealing insulating film 41.

【０１０１】下段の３次元積層型半導体装置１０Ａは上
段と同様の構成を有するが、下段の半導体装置１０Ａで
は、マザーボード４７又はインターポーザ基板４９の上
面及び下面の双方に電極パッド６０ａ、６０ｂが形成さ
れている。上段と同様に、金ワイヤ４０を含む３次元積
層型半導体装置１０Ａ全体が封止絶縁膜４１で封止さ
れ、更に、封止絶縁膜４１の上面が、上段のマザーボー
ド４７又はインターポーザ基板４９の下面に接着され
る。この状態で、上段側の電極パッド５９と下段側の電
極パッド６０ａとが導電バンプ３３を介して接続され、
電極パッド６０ｂ上には、別の導電バンプ３３が形成さ
れる。The lower three-dimensional stacked semiconductor device 10A has the same structure as the upper semiconductor device, but in the lower semiconductor device 10A, electrode pads 60a and 60b are formed on both the upper surface and the lower surface of the mother board 47 or the interposer substrate 49. ing. Similar to the upper step, the entire three-dimensional stacked semiconductor device 10A including the gold wire 40 is sealed with the sealing insulating film 41, and the upper surface of the sealing insulating film 41 is the lower surface of the upper motherboard 47 or the interposer substrate 49. Glued to. In this state, the upper electrode pad 59 and the lower electrode pad 60a are connected via the conductive bump 33,
Another conductive bump 33 is formed on the electrode pad 60b.

【０１０２】図２５（ｂ）に示す変形例では、下段の３
次元積層型半導体装置１０Ａが、マザーボード４７又は
インターポーザ基板４９より厚く、上面にのみ電極パッ
ド６０が形成された絶縁樹脂層４７上に接着される点
で、図２５（ａ）の構成例と異なる。In the modification shown in FIG. 25 (b), the lower 3
The three-dimensional stacked semiconductor device 10A is thicker than the mother board 47 or the interposer substrate 49, and is bonded on the insulating resin layer 47 having the electrode pads 60 formed only on the upper surface, which is different from the configuration example of FIG.

【０１０３】半導体装置の第１１実施形態例 図２６は、本実施形態例のパッケージ化した３次元積層
型半導体装置１０Ａを示す断面図である。本実施形態例
では、図２２のパッケージ化した３次元積層型半導体装
置１０Ａを２段積層し、導電バンプ３３を介して相互に
接続している。 Eleventh Embodiment of Semiconductor Device FIG. 26 is a sectional view showing a packaged three-dimensional stacked semiconductor device 10A according to this embodiment. In the present embodiment, the packaged three-dimensional stacked semiconductor devices 10A of FIG. 22 are stacked in two stages and are connected to each other via the conductive bumps 33.

【０１０４】半導体装置の第１２実施形態例 図２７（ａ）は本実施形態例の３次元積層型半導体装置
１０Ａを示す断面図、図２７（ｂ）はその変形例を示す
断面図である。本実施形態例では、図４に示した３次元
積層型半導体装置１０Ａをマザーボード４７に実装して
いる。[0104] Twelfth embodiment of the semiconductor device Figure 27 (a) is a sectional view showing a three-dimensional stacked semiconductor device 10A of the embodiment, FIG. 27 (b) is a sectional view showing a modified example thereof. In this embodiment, the three-dimensional laminated semiconductor device 10A shown in FIG. 4 is mounted on the mother board 47.

【０１０５】図２７（ａ）に示す３次元積層型半導体装
置１０Ａでは、絶縁膜１９とマザーボード４７との間
に、アンダーフィル樹脂４８が設けられている。このア
ンダーフィル樹脂４８は、エポキシ樹脂を主成分とする
もので、パッケージの２次実装の信頼性を高めている。In the three-dimensional laminated semiconductor device 10A shown in FIG. 27A, an underfill resin 48 is provided between the insulating film 19 and the mother board 47. The underfill resin 48 contains epoxy resin as a main component and enhances the reliability of the secondary mounting of the package.

【０１０６】また、図２７（ｂ）に示す変形例では、図
２７（ａ）に示したアンダーフィル樹脂４８が形成され
ず、従って、マザーボード４７に形成された電極パッド
５５に導電バンプ３３を直接に接着して、絶縁膜１９と
マザーボード４７とで導電バンプ３３を封止している。In the modification shown in FIG. 27B, the underfill resin 48 shown in FIG. 27A is not formed, so that the conductive bump 33 is directly attached to the electrode pad 55 formed on the mother board 47. The conductive bumps 33 are sealed by the insulating film 19 and the mother board 47.

【０１０７】半導体装置の第１３実施形態例 図２８は本実施形態例のパッケージ化した３次元積層型
半導体装置１０Ａを夫々示す断面図であり、図２８
（ａ）は個々の３次元積層型半導体装置単位に分割する
前の状態を示し、図２８（ｂ）及び（ｃ）は分割後にマ
ザーボード４７に実装した異なる構成例を夫々示す。28. Thirteenth Embodiment of Semiconductor Device FIG. 28 is a sectional view showing a packaged three-dimensional stacked semiconductor device 10A according to this embodiment.
28A shows a state before being divided into individual three-dimensional stacked semiconductor device units, and FIGS. 28B and 28C show different configuration examples mounted on the motherboard 47 after the division.

【０１０８】図２８（ａ）に示す３次元積層型半導体装
置１０Ａは、積層した複数の半導体チップが全てのサイ
ズ及び種類が異なる半導体チップ１１、２４、２５、４
６を有している。この３次元積層型半導体装置１０Ａを
製造する製造プロセスでは、半導体チップの種類以外に
関する点は図１０〜図１３に示した製造プロセスと同様
である。In the three-dimensional stacked semiconductor device 10A shown in FIG. 28A, a plurality of stacked semiconductor chips are semiconductor chips 11, 24, 25, 4 having different sizes and types.
Have six. The manufacturing process for manufacturing the three-dimensional stacked semiconductor device 10A is the same as the manufacturing process shown in FIGS. 10 to 13 except for the type of semiconductor chip.

【０１０９】図２８（ｂ）に示す構成例では、個別化し
た３次元積層型半導体装置１０Ａがマザーボード４７上
にアンダーフィル樹脂４８を介して接着されている。In the configuration example shown in FIG. 28B, the individualized three-dimensional laminated semiconductor device 10A is bonded onto the mother board 47 via the underfill resin 48.

【０１１０】図２８（ｃ）の構成例では、３次元積層型
半導体装置とマザーボード４７との間にアンダーフィル
樹脂４８が形成されず、マザーボード４７に形成された
電極パッド５５に導電バンプ３３が直接に接着されて、
絶縁膜１９とマザーボード４７とで導電バンプ３３が封
止されている。In the configuration example of FIG. 28C, the underfill resin 48 is not formed between the three-dimensional laminated semiconductor device and the motherboard 47, and the conductive bumps 33 are directly attached to the electrode pads 55 formed on the motherboard 47. Glued to
The conductive bump 33 is sealed by the insulating film 19 and the mother board 47.

【０１１１】半導体装置の第１４実施形態例 図２９は本実施形態例のパッケージ化した３次元積層型
半導体装置１０Ａを示す断面図であり、図２９（ａ）は
個々の３次元積層型半導体装置１０Ａ単位に分割する前
の状態を示し、図２９（ｂ）及び（ｃ）は分割後にマザ
ーボード４７に実装した異なる構成例を夫々示す。 Fourteenth Embodiment of Semiconductor Device FIG. 29 is a sectional view showing a packaged three-dimensional stacked semiconductor device 10A according to this embodiment, and FIG. 29A shows an individual three-dimensional stacked semiconductor device. FIG. 29B and FIG. 29C show a state before being divided into units of 10 A, and FIGS. 29B and 29C show different configuration examples mounted on the mother board 47 after the division.

【０１１２】図２９（ａ）に示す３次元積層型半導体装
置１０Ａでは、サイズ及び／又は種類が同じ半導体チッ
プ１１を２段積層したユニット半導体装置１４上に、サ
イズ及び／又は種類が同じ半導体チップ２４を２段積層
したユニット半導体装置１４が積層されている。この３
次元積層型半導体装置１０Ａを製造する製造プロセスで
は、半導体チップの種類以外に関する点は図１０〜図１
３に示した製造プロセスと同様である。In the three-dimensional stacked semiconductor device 10A shown in FIG. 29A, semiconductor chips 11 of the same size and / or type are stacked on the unit semiconductor device 14 in two stages, and semiconductor chips of the same size and / or type are stacked. The unit semiconductor device 14 in which 24 is stacked in two stages is stacked. This 3
In the manufacturing process for manufacturing the three-dimensional stacked semiconductor device 10A, points other than the type of semiconductor chip are shown in FIGS.
It is similar to the manufacturing process shown in FIG.

【０１１３】図２９（ｂ）の構成例では、３次元積層型
半導体装置１０Ａとマザーボード４７との間にアンダー
フィル樹脂４８が設けられている。図２９（ｃ）の構成
例では、３次元積層型半導体装置１０Ａとマザーボード
４７とが、熱硬化性又は熱可塑性を有する絶縁膜１９を
介して接着され、これにより、最下層の導電バンプ３３
が封止されている。In the configuration example of FIG. 29B, an underfill resin 48 is provided between the three-dimensional laminated semiconductor device 10A and the mother board 47. In the configuration example of FIG. 29C, the three-dimensional stacked semiconductor device 10A and the mother board 47 are adhered to each other via the insulating film 19 having thermosetting property or thermoplastic property, whereby the conductive bumps 33 of the lowermost layer are bonded.
Is sealed.

【０１１４】以上の各実施形態例では、積層したユニッ
ト半導体装置１４の半導体チップ１１（２４、２５、４
６）をビアプラグ１８によって相互に機械的且つ電気的
に結合することができるので、半導体チップ１１を多数
段積層した高密度で大容量の構成が得られ、多機能化、
高速化に適する廉価な３次元積層型半導体装置１０Ａを
簡便に得ることができる。In each of the above embodiments, the semiconductor chips 11 (24, 25, 4) of the stacked unit semiconductor devices 14 are used.
Since 6) can be mechanically and electrically coupled to each other by the via plug 18, a high-density and large-capacity configuration in which a large number of semiconductor chips 11 are stacked can be obtained, and multi-functionalization can be achieved.
It is possible to easily obtain the inexpensive three-dimensional stacked semiconductor device 10A suitable for high speed.

【０１１５】以上、本発明をその好適な実施形態例に基
づいて説明したが、本発明に係るユニット半導体装置及
びその製造方法並びに３次元積層型半導体装置は、上記
実施形態例の構成にのみ限定されるものではなく、上記
実施形態例の構成から種々の修正及び変更を施したユニ
ット半導体装置及びその製造方法並びに３次元積層型半
導体装置も、本発明の範囲に含まれる。Although the present invention has been described based on its preferred embodiments, the unit semiconductor device, the method for manufacturing the same, and the three-dimensional stacked semiconductor device according to the present invention are limited to the configurations of the above embodiments. However, a unit semiconductor device, a method of manufacturing the same, and a three-dimensional stacked semiconductor device in which various modifications and changes are made from the configuration of the above embodiment are also included in the scope of the present invention.

【０１１６】[0116]

【発明の効果】以上説明したように、本発明によると、
種々のサイズ及び／又は種類の半導体チップの混載が容
易にできメモリ大容量化に対応可能な構成を有しながら
も、ハンドリング時の半導体チップの破損等に起因する
歩留まりの低下を回避すると共に、パッケージが小型の
３次元積層型半導体装置を簡便に形成できるユニット半
導体装置、及びこのようなユニット半導体装置を製造す
る製造方法、並びに、このユニット半導体装置を積層し
たコンパクトな３次元積層型半導体装置を得ることがで
きる。As described above, according to the present invention,
While having a configuration capable of easily mounting various sizes and / or types of semiconductor chips together and supporting a large memory capacity, while avoiding a decrease in yield due to damage of the semiconductor chips during handling, A unit semiconductor device capable of easily forming a three-dimensional stacked semiconductor device having a small package, a manufacturing method for manufacturing such a unit semiconductor device, and a compact three-dimensional stacked semiconductor device in which the unit semiconductor devices are stacked. Obtainable.

【図面の簡単な説明】[Brief description of drawings]

【図１】図１（ａ）は本発明の半導体装置の第１実施形
態例における一構成例を示す断面図、図１（ｂ）はその
変形例を示す断面図、図１（ｃ）は更に別の変形例を示
す断面図である。FIG. 1 (a) is a sectional view showing a configuration example of a first embodiment of a semiconductor device of the present invention, FIG. 1 (b) is a sectional view showing a modification thereof, and FIG. It is sectional drawing which shows another modification.

【図２】図２（ａ）、（ｂ）は夫々、本発明の半導体装
置の第２実施形態例における一構成例を示す断面図及び
平面図、図２（ｃ）はその変形例を示す断面図、図２
（ｄ）は別の変形例を示す断面図である。2A and 2B are a cross-sectional view and a plan view showing a structural example of a second embodiment of a semiconductor device according to the present invention, and FIG. 2C shows a modified example thereof. Sectional view, Figure 2
(D) is sectional drawing which shows another modification.

【図３】図３（ａ）は本発明の半導体装置の第３実施形
態例における一構成例を示す断面図、図２（ｂ）はその
変形例を示す断面図である。FIG. 3 (a) is a sectional view showing a configuration example of a semiconductor device according to a third embodiment of the present invention, and FIG. 2 (b) is a sectional view showing a modification thereof.

【図４】図４（ａ）は本発明の半導体装置の第４実施形
態例における一構成例を示す断面図、図４（ｂ）は図４
（ａ）の３次元積層型半導体装置１０Ａを平面方向に２
つ配列した変形例を示す断面図である。FIG. 4A is a sectional view showing a configuration example of a fourth embodiment of a semiconductor device of the present invention, and FIG. 4B is FIG.
2A of the three-dimensional stacked semiconductor device 10A of FIG.
It is sectional drawing which shows the modified example which arranged one.

【図５】図５（ａ）〜（ｄ）は本発明の製造方法の第１
実施形態例における製造工程を段階的に示す断面図であ
る。5 (a) to 5 (d) are diagrams showing the first manufacturing method of the present invention.
It is sectional drawing which shows the manufacturing process in an example of an embodiment in steps.

【図６】図６（ａ）〜（ｄ）は本発明の製造方法の第１
実施形態例における製造工程を段階的に示す断面図であ
る。6 (a) to 6 (d) are diagrams showing a first manufacturing method of the present invention.
It is sectional drawing which shows the manufacturing process in an example of an embodiment in steps.

【図７】図７（ａ）〜（ｄ）は本発明の製造方法の第１
実施形態例における製造工程を段階的に示す断面図であ
る。7 (a) to 7 (d) are diagrams showing the first manufacturing method of the present invention.
It is sectional drawing which shows the manufacturing process in an example of an embodiment in steps.

【図８】図８（ａ）〜（ｄ）は本発明の製造方法の第１
実施形態例における製造工程を段階的に示す断面図であ
る。FIG. 8 (a) to FIG. 8 (d) are the first part of the manufacturing method of the present invention.
It is sectional drawing which shows the manufacturing process in an example of an embodiment in steps.

【図９】図９（ａ）、（ｂ）は本発明の製造方法の第１
実施形態例における製造工程を段階的に示す断面図であ
る。FIG. 9 (a) and FIG. 9 (b) are the first of the manufacturing method of the present invention.
It is sectional drawing which shows the manufacturing process in an example of an embodiment in steps.

【図１０】図１０（ａ）〜（ｅ）は本発明の製造方法の
第２実施形態例における製造工程を段階的に示す断面図
である。10 (a) to 10 (e) are sectional views showing step by step the manufacturing process in the second embodiment of the manufacturing method of the present invention.

【図１１】図１１（ａ）〜（ｅ）は本発明の製造方法の
第２実施形態例における製造工程を段階的に示す断面図
である。11 (a) to 11 (e) are sectional views showing step by step the manufacturing steps in the second embodiment of the manufacturing method of the present invention.

【図１２】図１２（ａ）〜（ｄ）は本発明の製造方法の
第２実施形態例における製造工程を段階的に示す断面図
である。12 (a) to 12 (d) are cross-sectional views showing step by step the manufacturing process in the second embodiment of the manufacturing method of the present invention.

【図１３】図１３（ａ）〜（ｃ）は本発明の製造方法の
第２実施形態例における製造工程を段階的に示す断面図
である。13 (a) to 13 (c) are sectional views showing step by step the manufacturing steps in the second embodiment of the manufacturing method of the present invention.

【図１４】図１４（ａ）〜（ｄ）は本発明の製造方法の
第３実施形態例における製造工程を段階的に示す断面図
である。14 (a) to 14 (d) are cross-sectional views showing stepwise a manufacturing process in a third embodiment of the manufacturing method of the present invention.

【図１５】図１５（ａ）〜（ｃ）は本発明の製造方法の
第３実施形態例における製造工程を段階的に示す断面図
である。15 (a) to 15 (c) are cross-sectional views showing step by step the manufacturing process in the third embodiment of the manufacturing method of the present invention.

【図１６】図１６（ａ）〜（ｄ）は本発明の製造方法の
第４実施形態例における製造工程を段階的に示す断面図
である。16 (a) to 16 (d) are sectional views showing step by step the manufacturing steps in the fourth embodiment of the manufacturing method of the present invention.

【図１７】図１７（ａ）〜（ｃ）は本発明の製造方法の
第４実施形態例における製造工程を段階的に示す断面図
である。17 (a) to 17 (c) are sectional views showing step by step the manufacturing steps in the fourth embodiment of the manufacturing method of the present invention.

【図１８】図１８（ａ）、（ｂ）は本発明の半導体装置
の第５実施形態例における一構成例を示す断面図であ
る。18A and 18B are cross-sectional views showing a configuration example of a fifth embodiment of the semiconductor device of the present invention.

【図１９】図１９（ａ）、（ｂ）は本発明の製造方法の
第５実施形態例における製造工程を段階的に示す断面図
である。19 (a) and 19 (b) are sectional views showing step by step the manufacturing steps in the fifth embodiment of the manufacturing method of the present invention.

【図２０】図２０（ａ）、（ｂ）は本発明の製造方法の
第５実施形態例における製造工程を段階的に示す断面図
である。20 (a) and 20 (b) are sectional views showing step by step the manufacturing process in the fifth embodiment of the manufacturing method of the present invention.

【図２１】本発明の半導体装置の第６実施形態例におけ
る構成例を示す断面図である。FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to a sixth embodiment of the present invention.

【図２２】本発明の半導体装置の第７実施形態例におけ
る構成例を示す断面図である。FIG. 22 is a cross-sectional view showing a configuration example of a semiconductor device according to a seventh embodiment of the present invention.

【図２３】本発明の半導体装置の第８実施形態例におけ
る構成例を示す断面図である。FIG. 23 is a cross-sectional view showing a configuration example of an eighth embodiment of the semiconductor device of the present invention.

【図２４】本発明の半導体装置の第９実施形態例におけ
る構成例を示す断面図である。FIG. 24 is a sectional view showing a configuration example of a semiconductor device according to a ninth embodiment of the present invention.

【図２５】本発明の半導体装置の第１０実施形態例にお
ける構成例を示す断面図である。FIG. 25 is a sectional view showing a structural example of a semiconductor device according to a tenth exemplary embodiment of the present invention.

【図２６】本発明の半導体装置の第１１実施形態例にお
ける構成例を示す断面図である。FIG. 26 is a sectional view showing a configuration example of an eleventh exemplary embodiment of a semiconductor device of the present invention.

【図２７】本発明の半導体装置の第１２実施形態例にお
ける構成例を示す断面図である。FIG. 27 is a cross-sectional view showing a configuration example of a twelfth embodiment of the semiconductor device of the present invention.

【図２８】本発明の半導体装置の第１３実施形態例にお
ける構成例を示す断面図であり、図２８（ａ）は各３次
元積層型半導体装置単位に分割する前の状態を示し、図
２８（ｂ）及び（ｃ）は夫々、分割後にマザーボード４
７に実装した異なる構成例を示す。28 is a cross-sectional view showing a structural example of a semiconductor device according to a thirteenth embodiment of the present invention, and FIG. 28A shows a state before being divided into respective three-dimensional stacked semiconductor device units; (B) and (c) respectively show the mother board 4 after division.
7 shows a different configuration example implemented in FIG.

【図２９】本発明の半導体装置の第１４実施形態例にお
ける構成例を示す断面図であり、図２９（ａ）は各３次
元積層型半導体装置単位に分割する前の状態を示し、図
２９（ｂ）及び（ｃ）は夫々、分割後にマザーボード４
７に実装した異なる構成例を示す。29 is a cross-sectional view showing a structural example of a semiconductor device according to a fourteenth embodiment of the present invention, and FIG. 29 (a) shows a state before being divided into respective three-dimensional stacked semiconductor device units, and FIG. (B) and (c) respectively show the mother board 4 after division.
7 shows a different configuration example implemented in FIG.

【図３０】従来の半導体装置の一構成例を示す断面図で
ある。FIG. 30 is a cross-sectional view showing a configuration example of a conventional semiconductor device.

【図３１】従来の半導体装置の別の構成例を示す断面図
である。FIG. 31 is a sectional view showing another configuration example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１０Ａ、１０Ｂ：３次元積層型半導体装置 １１、２４、２５、４６：半導体チップ １２：感光性接着剤（第１モールド部） １３：導電バンプ １４：ユニット半導体装置 １５、３５、４５：電極パッド １６：配線パターン １７：絶縁樹脂層（第２モールド部） １８：ビアプラグ（配線プラグ） １９：絶縁膜 ２０ａ、２０ｂ、２３ａ：スルーホール ２１：銅箔 ２３：ソルダーレジスト膜 ２５ａ：電極パッド ２７：外部電極 ３２：銅めっき膜 ３３：導電バンプ（外部電極） ３４：金属板（仮基板） ３７：絶縁膜 ４０：金ワイヤ線 ４１：封止樹脂 ４７：マザーボード ４８：アンダーフィル樹脂 ４９：インターポーザ基板 ５５、５９、６０ａ、６０ｂ：電極パッド １０１、１０２：半導体チップ １０３：金ワイヤ １０４：銅パターン １０５：バンプ １０６：テープ基板 １０７：絶縁性接着剤 １０８：封止樹脂 １０９：半導体チップ １１０：プリプレグ １１１：フィルムキャリア １１２：導電バンプ １１３：導電性物質 １１４：半導体チップ収納穴 １１５：穴 10A, 10B: Three-dimensional stacked semiconductor device 11, 24, 25, 46: Semiconductor chip 12: Photosensitive adhesive (first mold part) 13: Conductive bump 14: Unit semiconductor device 15, 35, 45: Electrode pad 16: Wiring pattern 17: Insulating resin layer (second mold part) 18: Via plug (wiring plug) 19: Insulating film 20a, 20b, 23a: through holes 21: Copper foil 23: Solder resist film 25a: Electrode pad 27: External electrode 32: Copper plating film 33: Conductive bump (external electrode) 34: Metal plate (temporary substrate) 37: Insulating film 40: Gold wire wire 41: Sealing resin 47: Motherboard 48: Underfill resin 49: Interposer substrate 55, 59, 60a, 60b: electrode pads 101, 102: semiconductor chip 103: Gold wire 104: Copper pattern 105: bump 106: tape substrate 107: Insulating adhesive 108: sealing resin 109: Semiconductor chip 110: prepreg 111: Film carrier 112: Conductive bump 113: conductive substance 114: Semiconductor chip storage hole 115: hole

───────────────────────────────────────────────────── フロントページの続き (72)発明者 北城 栄 東京都港区芝五丁目７番１号 日本電気株 式会社内 (72)発明者 嶋田 勇三 東京都港区芝五丁目７番１号 日本電気株 式会社内   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Sakae Kitajo             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company (72) Inventor Yuzo Shimada             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company

Claims (21)

【特許請求の範囲】[Claims] 【請求項１】 チップ電極を有する半導体チップと、一
方の面で前記チップ電極をマウントする配線パターン
と、前記半導体チップ及び配線パターンを一体的に覆う
モールドレジンと、該モールドレジンを前記半導体チッ
プの外側で貫通し、一端が前記配線パターンの前記一方
の面に接触し、他端が前記モールドレジンから露出する
配線プラグとを備え、前記配線パターンの他方の面が前
記モールドレジンの表面に露出していることを特徴とす
るユニット半導体装置。1. A semiconductor chip having a chip electrode, a wiring pattern for mounting the chip electrode on one surface, a mold resin integrally covering the semiconductor chip and the wiring pattern, and the mold resin of the semiconductor chip. A wiring plug penetrating on the outside, having one end in contact with the one surface of the wiring pattern and the other end exposed from the mold resin, and the other surface of the wiring pattern exposed on the surface of the mold resin. A unit semiconductor device characterized in that 【請求項２】 前記モールドレジンが、前記半導体チッ
プと配線パターンとの間に設けられた感光性接着剤を含
むことを特徴とする、請求項１に記載のユニット半導体
装置。2. The unit semiconductor device according to claim 1, wherein the mold resin contains a photosensitive adhesive provided between the semiconductor chip and the wiring pattern. 【請求項３】 前記半導体チップが５〜５０μmの厚み
を有することを特徴とする、請求項１又は２に記載のユ
ニット半導体装置。3. The unit semiconductor device according to claim 1, wherein the semiconductor chip has a thickness of 5 to 50 μm. 【請求項４】 請求項１に記載のユニット半導体装置が
複数段積層された３次元積層型半導体装置であって、 一のユニット半導体装置の前記配線プラグが、上段のユ
ニット半導体装置の前記配線パターンの露出面に接触し
ていることを特徴とする３次元積層型半導体装置。4. A three-dimensional stacked semiconductor device in which the unit semiconductor device according to claim 1 is stacked in a plurality of stages, wherein the wiring plug of one unit semiconductor device is the wiring pattern of the upper unit semiconductor device. A three-dimensional stacked semiconductor device, which is in contact with the exposed surface of the. 【請求項５】 前記複数段積層されたユニット半導体装
置の半導体チップは、サイズ及び／又は種類が相互に同
じであることを特徴とする、請求項４に記載の３次元積
層型半導体装置。5. The three-dimensional stacked semiconductor device according to claim 4, wherein the semiconductor chips of the unit semiconductor devices stacked in a plurality of stages have the same size and / or type. 【請求項６】 前記複数段積層されたユニット半導体装
置における少なくとも一つの半導体チップのサイズ及び
／又は種類が、他の半導体チップのサイズ及び／又は種
類と異なることを特徴とする、請求項４に記載の３次元
積層型半導体装置。6. The size and / or type of at least one semiconductor chip in the unit semiconductor device having a plurality of stacked layers is different from the size and / or type of other semiconductor chips. The three-dimensional stacked semiconductor device described. 【請求項７】 最上段及び／又は最下段の露出する面に
は絶縁膜が形成され、少なくとも一方の絶縁膜の露出面
には外部電極が形成されることを特徴とする、請求項４
〜６の内の何れか１項に記載の３次元積層型半導体装
置。7. The insulating film is formed on the exposed surface of the uppermost stage and / or the lowermost stage, and the external electrode is formed on the exposed surface of at least one insulating film.
The three-dimensional stacked semiconductor device according to any one of items 1 to 6. 【請求項８】 最下段のユニット半導体装置が前記絶縁
膜を介してインターポーザ基板又はマザーボードに接着
され、最上段のユニット半導体装置には前記絶縁膜上に
前記外部電極が形成され、該外部電極は前記インターポ
ーザ基板又はマザーボードに設けられた電極パッドにワ
イヤボンディング接続されることを特徴とする、請求項
７に記載の３次元積層型半導体装置。8. The lowermost unit semiconductor device is adhered to an interposer substrate or a mother board through the insulating film, and the uppermost unit semiconductor device is formed with the external electrode on the insulating film. The three-dimensional stacked semiconductor device according to claim 7, wherein the three-dimensional stacked semiconductor device is wire-bonded to an electrode pad provided on the interposer substrate or the mother board. 【請求項９】 前記最上段のユニット半導体装置上に、
一の半導体チップがフェースアップで接着され、前記一
のユニット半導体装置のチップ電極と前記電極パッドと
がワイヤボンディング接続されることを特徴とする、請
求項８に記載の３次元積層型半導体装置。9. The unit semiconductor device at the uppermost stage,
9. The three-dimensional stacked semiconductor device according to claim 8, wherein one semiconductor chip is bonded face-up, and a chip electrode of the one unit semiconductor device and the electrode pad are connected by wire bonding. 【請求項１０】 前記複数段のユニット半導体装置と前
記インターポーザ基板又はマザーボードとを接着した積
層体が複数段形成されることを特徴とする、請求項８又
は９に記載の３次元積層型半導体装置。10. The three-dimensional stacked semiconductor device according to claim 8, wherein a plurality of stacked bodies are formed by bonding the plurality of stacked unit semiconductor devices to the interposer substrate or the mother board. . 【請求項１１】 仮基板上に配線パターンを形成する工
程と、 少なくとも側部及び下部がモールドレジンで被覆され、
該モールドレジンを貫通するスルーホールを介して前記
配線パターンに接続される半導体チップを前記配線パタ
ーン上に搭載する工程と、 前記配線パターン上に、前記半導体チップの外側を通過
し前記モールドレジンを貫通する配線プラグを形成する
工程と、 前記仮基板を除去する工程とを備えることを特徴とする
ユニット半導体装置の製造方法。11. A step of forming a wiring pattern on a temporary substrate, wherein at least a side portion and a lower portion are covered with a mold resin,
Mounting a semiconductor chip connected to the wiring pattern on the wiring pattern through a through hole penetrating the mold resin; and penetrating the molding resin on the wiring pattern outside the semiconductor chip. And a step of removing the temporary substrate, and a method of manufacturing a unit semiconductor device, comprising: 【請求項１２】 前記モールドレジンが、前記半導体チ
ップの下部を被覆する第１モールド部と、前記半導体チ
ップの少なくとも側部を被覆する第２モールド部とから
成り、前記搭載工程が、前記第１モールド部の形成工程
と前記第２モールド部の形成工程とを含むことを特徴と
する、請求項１１に記載のユニット半導体装置の製造方
法。12. The molding resin comprises a first molding portion that covers a lower portion of the semiconductor chip and a second molding portion that covers at least a side portion of the semiconductor chip, and the mounting step includes the first molding portion. The method of manufacturing a unit semiconductor device according to claim 11, further comprising a forming step of a mold part and a forming step of the second mold part. 【請求項１３】 前記第２モールド部の形成工程に先立
って、前記半導体チップの上部を研削し、該半導体チッ
プを５〜５０μmの厚みに形成することを特徴とする、
請求項１２に記載のユニット半導体装置の製造方法。13. Prior to the step of forming the second mold portion, the upper portion of the semiconductor chip is ground to form the semiconductor chip with a thickness of 5 to 50 μm.
The method for manufacturing a unit semiconductor device according to claim 12. 【請求項１４】 前記配線プラグの形成工程に後続し
て、前記第２モールド部上に前記配線パターンを形成し
てから、前記搭載工程〜前記配線プラグの形成工程を繰
り返し行って３次元積層型の半導体装置に形成すること
を特徴とする、請求項１１〜１３の内の何れか１項に記
載のユニット半導体装置の製造方法。14. A three-dimensional stacking type, wherein after the step of forming the wiring plug, the wiring pattern is formed on the second mold portion, and then the mounting step to the step of forming the wiring plug are repeated. 14. The method for manufacturing a unit semiconductor device according to claim 11, wherein the unit semiconductor device is formed on the semiconductor device. 【請求項１５】 仮基板上に配線パターンを形成する工
程と、 前記配線パターン上に半導体チップ及び該半導体チップ
に隣接する配線プラグを形成する工程と、 モールドレジンによって前記半導体チップ及び前記配線
プラグを前記配線パターン上に埋め込む工程と、 前記仮基板を除去する工程とを備えることを特徴とする
ユニット半導体装置の製造方法。15. A step of forming a wiring pattern on a temporary substrate, a step of forming a semiconductor chip and a wiring plug adjacent to the semiconductor chip on the wiring pattern, and a step of forming the semiconductor chip and the wiring plug by a mold resin. A method of manufacturing a unit semiconductor device, comprising: a step of embedding on the wiring pattern; and a step of removing the temporary substrate. 【請求項１６】 前記モールドレジンが、前記半導体チ
ップの下部を被覆する第１モールド部と、前記半導体チ
ップの少なくとも側部を被覆する第２モールド部とから
成り、前記埋め込み工程が、前記第１モールド部の形成
工程と前記第２モールド部の形成工程とを含むことを特
徴とする、請求項１５に記載のユニット半導体装置の製
造方法。16. The mold resin comprises a first mold portion that covers a lower portion of the semiconductor chip and a second mold portion that covers at least a side portion of the semiconductor chip, and the embedding step includes the first mold portion. The method for manufacturing a unit semiconductor device according to claim 15, further comprising a forming step of a mold part and a forming step of the second mold part. 【請求項１７】 前記半導体チップ及び配線プラグの埋
め込み工程に後続して、前記半導体チップ及び配線プラ
グの上部を研削し、該半導体チップを５〜５０μmの厚
みに形成することを特徴とする、請求項１６に記載のユ
ニット半導体装置の製造方法。17. The step of embedding the semiconductor chip and the wiring plug is followed by grinding the upper portions of the semiconductor chip and the wiring plug to form the semiconductor chip to a thickness of 5 to 50 μm. Item 17. A method for manufacturing a unit semiconductor device according to item 16. 【請求項１８】 前記半導体チップ及び配線プラグの研
削工程に後続して、前記第２モールド部上に前記配線パ
ターンを形成してから、前記半導体チップ及び該半導体
チップに隣接する配線プラグの形成工程〜前記埋め込み
工程を繰り返し行って３次元積層型の半導体装置に形成
することを特徴とする、請求項１７に記載のユニット半
導体装置の製造方法。18. A step of forming the wiring pattern on the second mold part, after the step of grinding the semiconductor chip and the wiring plug, and then forming the semiconductor chip and a wiring plug adjacent to the semiconductor chip. The method of manufacturing a unit semiconductor device according to claim 17, wherein the embedding step is repeated to form a three-dimensional stacked semiconductor device. 【請求項１９】 前記配線パターンの形成工程では、前
記仮基板上に予め絶縁被膜を形成してから、該絶縁被膜
上に前記配線パターンを形成することを特徴とする、請
求項１５〜１８の内の何れか１項に記載のユニット半導
体装置の製造方法。19. The method according to claim 15, wherein in the step of forming the wiring pattern, an insulating coating is formed in advance on the temporary substrate, and then the wiring pattern is formed on the insulating coating. 9. The method for manufacturing a unit semiconductor device according to any one of the above. 【請求項２０】 前記３次元積層型の最上段のユニット
半導体装置における露出面を絶縁膜で覆い、該絶縁膜の
前記配線プラグ上に別のスルーホールを形成し、該別の
スルーホール内に、前記配線プラグに接触する外部電極
を形成することを特徴とする、請求項１４又は１８に記
載のユニット半導体装置の製造方法。20. An exposed surface of the uppermost unit semiconductor device of the three-dimensional stacked type is covered with an insulating film, another through hole is formed on the wiring plug of the insulating film, and the other through hole is formed in the other through hole. 19. The method for manufacturing a unit semiconductor device according to claim 14, wherein an external electrode that contacts the wiring plug is formed. 【請求項２１】 前記３次元積層型の半導体装置を積層
方向と直交する平面方向に配列するように形成してか
ら、各３次元積層型の半導体装置毎に分割することを特
徴とする、請求項１４及び１８〜２０の内の何れか１項
に記載のユニット半導体装置の製造方法。21. The three-dimensional stacked semiconductor device is formed so as to be arranged in a plane direction orthogonal to the stacking direction, and then divided for each three-dimensional stacked semiconductor device. 21. A method for manufacturing a unit semiconductor device according to any one of items 14 and 18 to 20.
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Cited By (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US7906838B2 (en) 2007-07-23 2011-03-15 Headway Technologies, Inc. Electronic component package and method of manufacturing same
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US8358015B2 (en) 2011-06-09 2013-01-22 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8426946B2 (en) 2010-06-28 2013-04-23 Headway Technologies, Inc. Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
US8426948B2 (en) 2010-08-02 2013-04-23 Headway Technologies, Inc. Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
US8441112B2 (en) 2010-10-01 2013-05-14 Headway Technologies, Inc. Method of manufacturing layered chip package
US8455349B2 (en) 2010-04-28 2013-06-04 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US8541887B2 (en) 2010-09-03 2013-09-24 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8629543B2 (en) 2007-06-11 2014-01-14 Invensas Corporation Electrically interconnected stacked die assemblies
US8652877B2 (en) 2010-12-06 2014-02-18 Headway Technologies, Inc. Method of manufacturing layered chip package
US8653639B2 (en) 2011-06-09 2014-02-18 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8680687B2 (en) 2009-06-26 2014-03-25 Invensas Corporation Electrical interconnect for die stacked in zig-zag configuration
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US8729690B2 (en) 2004-04-13 2014-05-20 Invensas Corporation Assembly having stacked die mounted on substrate
US8884403B2 (en) 2008-06-19 2014-11-11 Iinvensas Corporation Semiconductor die array structure
US8912661B2 (en) 2009-11-04 2014-12-16 Invensas Corporation Stacked die assembly having reduced stress electrical interconnects
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
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US12033983B2 (en) 2023-05-12 2024-07-09 Intel Corporation Method for interconnecting stacked semiconductor devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793482B2 (en) * 1988-12-12 1995-10-09 シャープ株式会社 Circuit board connection method
JP3500995B2 (en) * 1998-12-18 2004-02-23 株式会社デンソー Manufacturing method of laminated circuit module
JP2001274324A (en) * 2000-03-24 2001-10-05 Hitachi Chem Co Ltd Semiconductor mounting substrate for multilayer semiconductor device, and semiconductor device and multilayer semiconductor device
JP2001298115A (en) * 2000-04-13 2001-10-26 Seiko Epson Corp Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment

Cited By (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
JP2008198972A (en) * 2007-02-15 2008-08-28 Headway Technologies Inc Method of manufacturing electronic component package, and wafer and basic structure used for manufacturing its electronic component package
US7927920B2 (en) * 2007-02-15 2011-04-19 Headway Technologies, Inc. Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package
US20110115079A1 (en) * 2007-02-15 2011-05-19 Headway Technologies, Inc. Wafter and substructure for use in manufacturing electronic component packages
US8415793B2 (en) 2007-02-15 2013-04-09 Headway Technologies, Inc. Wafer and substructure for use in manufacturing electronic component packages
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US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US8629543B2 (en) 2007-06-11 2014-01-14 Invensas Corporation Electrically interconnected stacked die assemblies
US7906838B2 (en) 2007-07-23 2011-03-15 Headway Technologies, Inc. Electronic component package and method of manufacturing same
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
KR101458538B1 (en) 2007-07-27 2014-11-07 테세라, 인코포레이티드 A stacked microelectronic unit, and method of fabrication thereof
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US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package using recycled wafer
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US9252116B2 (en) 2007-09-10 2016-02-02 Invensas Corporation Semiconductor die mount by conformal die coating
US9824999B2 (en) 2007-09-10 2017-11-21 Invensas Corporation Semiconductor die mount by conformal die coating
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
JP2009141010A (en) * 2007-12-04 2009-06-25 Hitachi Chem Co Ltd Semiconductor device and method of manufacturing the same
US9305862B2 (en) 2008-03-12 2016-04-05 Invensas Corporation Support mounted electrically interconnected die assembly
US9508689B2 (en) 2008-05-20 2016-11-29 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8884403B2 (en) 2008-06-19 2014-11-11 Iinvensas Corporation Semiconductor die array structure
WO2010111825A1 (en) * 2009-03-30 2010-10-07 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Electronic package and method of fabrication thereof
US8680687B2 (en) 2009-06-26 2014-03-25 Invensas Corporation Electrical interconnect for die stacked in zig-zag configuration
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
US9490230B2 (en) 2009-10-27 2016-11-08 Invensas Corporation Selective die electrical insulation by additive process
US8912661B2 (en) 2009-11-04 2014-12-16 Invensas Corporation Stacked die assembly having reduced stress electrical interconnects
JP2011181861A (en) * 2010-03-04 2011-09-15 Casio Computer Co Ltd Semiconductor device and method for manufacturing the same
US8455349B2 (en) 2010-04-28 2013-06-04 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8426946B2 (en) 2010-06-28 2013-04-23 Headway Technologies, Inc. Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
US8426948B2 (en) 2010-08-02 2013-04-23 Headway Technologies, Inc. Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
US8541887B2 (en) 2010-09-03 2013-09-24 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8441112B2 (en) 2010-10-01 2013-05-14 Headway Technologies, Inc. Method of manufacturing layered chip package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP2012094587A (en) * 2010-10-25 2012-05-17 Hitachi Chem Co Ltd Method for manufacturing optical semiconductor device and optical semiconductor device
US8652877B2 (en) 2010-12-06 2014-02-18 Headway Technologies, Inc. Method of manufacturing layered chip package
US8358015B2 (en) 2011-06-09 2013-01-22 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8653639B2 (en) 2011-06-09 2014-02-18 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US9899354B2 (en) 2013-09-27 2018-02-20 Intel Corporation Method for interconnecting stacked semiconductor devices
US9627358B2 (en) 2013-09-27 2017-04-18 Intel Corporation Method for interconnecting stacked semiconductor devices
DE102014113299B4 (en) 2013-09-27 2024-02-22 Intel Corporation METHOD FOR CONNECTING STACKED SEMICONDUCTOR COMPONENTS AND STACKED SEMICONDUCTOR COMPONENT
US11676944B2 (en) 2013-09-27 2023-06-13 Intel Corporation Method for interconnecting stacked semiconductor devices
US11024607B2 (en) 2013-09-27 2021-06-01 Intel Corporation Method for interconnecting stacked semiconductor devices
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US10643975B2 (en) 2013-09-27 2020-05-05 Intel Corporation Method for interconnecting stacked semiconductor devices
US9666513B2 (en) 2015-07-17 2017-05-30 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
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US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
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US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
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