JP2988045B2 - Bare chip structure and bare chip mounting structure - Google Patents

Abstract

PURPOSE:To make a printed circuit board unit small in size and light in weight by packaging laminated bare chips on a wiring board, regarding a semiconductor chip packaging structure of the printed circuit board unit which is used for circuit construction of various electronic apparatuses. CONSTITUTION:An insulating film 13 is provided on the surface of a base 12-1 of a bare chip 12 except a connection terminal 12-1a formed on one side of the chip, a conductor pattern 14 is formed on the surface of the insulating film 13 from the exposed connection terminal 12-1a to a position on the other side corresponding to the connection terminal 12-1a, and a pllurality of bare chips 12 are laminated by connecting the conductor pattern 14 with the connection terminal 12-1a. The connection terminal 12-1a of the bare chip 12 positioned on one end side of a laminated body is connected with a foot pattern 1-1 of a printed wiring board 1 so as to package the chips.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure of a printed circuit board unit used for circuit construction of various electronic devices.

2. Description of the Related Art Recently, as electronic devices such as hand-held terminals, word processors, personal computers, and the like are required to be further miniaturized and have many functions, a large number of semiconductor devices are required for a printed board unit mounted on these devices. It is necessary to mount devices at high density.

For this reason, a semiconductor chip body (hereinafter abbreviated as a bare chip) for miniaturizing a printed board unit is directly surface-mounted on a printed wiring board (hereinafter abbreviated as a wiring board). There is a demand for a new semiconductor chip mounting structure capable of high-density mounting.

[0004]

2. Description of the Related Art As shown in FIG. 4 (b), in a semiconductor device 2 of a four-way flat lead package type (QFP), for example, as shown in FIG. The semiconductor device 2 is mounted on a wiring board 1 in which a plurality of fine-width foot patterns 1-1 are arranged in a matrix at positions corresponding to a plurality of leads 2-2 arranged so as to protrude from the side surface of the package 2-1. The semiconductor device 2 is mounted on the wiring board 1 by aligning the lead 2-2 with the foot pattern 1-1, and solder (not shown) applied to the foot pattern 1-1 is melted by reflow bonding or the like. As shown in FIG. 4A, a large number of semiconductor devices 2 are surface-mounted on the main surface of the wiring board 1.

[0005]

The problem with the conventional semiconductor device mounting structure described above is that the foot pattern formed on the surface of the wiring board 1 as shown in FIG.
1-1 and lead of package 2-1 covering semiconductor element 2-3
Since a large number of semiconductor devices 2 are mounted by bonding 2-2, the external dimensions of the semiconductor device 2 to be mounted must be larger due to the package 2-1 and the wiring board 1 to be mounted must be larger. Therefore, there is a problem that miniaturization of the apparatus is hindered.

Further, a package 2 which covers the semiconductor element 2-3 is provided.
1 causes the problem that the semiconductor device 2 becomes heavy and the weight of the printed board unit increases. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a new semiconductor chip mounting structure capable of reducing the size and weight of a printed board unit by stacking bare chips and mounting them on a wiring board. .

[0007]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
The invention described in the claims, as shown in FIG.
On the board surface except for the connection terminals provided on one main surface of the
The conductor pattern connected to the connection terminal is formed by applying an edge film.
The other main part of the bare chip formed on the surface of the insulating film
A bare chip is provided on a surface. Ma
As shown in FIG. 2, one main surface is placed on the other side of the wiring board.
A plurality of through-holes provided with conducting conductors on the main surface of the front and back
Bare chips are stacked, and the adjacent upper
Bare with connection terminal on the underside of through hole of Achip
Connect directly to the connection terminals on the top of the chip and
Independent external leads are provided for each
Provide a bare chip to be performed.

[0008]

According to the present invention, an insulating film 13 is formed on the surface of the substrate 12-1 of the bare chip 12, and the connection terminals 12 exposed from the insulating film 13 are formed.
-1a and the conductor pattern 14 is wired to a position corresponding to the connection terminal 12-1a on the other surface.
14 and the connection terminals 12-1a formed on the other bare chip 12 are connected to each other, so that a plurality of the connection terminals 12-1a are connected to each other. By connecting with foot pattern 1-1,
Each foot pattern 1-1 formed on the wiring board 1
On the other hand, a plurality of bare chips 12 are mounted, so that the size and weight of the printed board unit can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a side sectional view showing a mounting structure of a semiconductor chip according to a first embodiment, FIG. 2 is a side sectional view showing a mounting structure of a second embodiment, and FIG. 3 is a through hole formation of a bare chip used in the second embodiment. 4A and 4B are cross-sectional views in the order of steps for explaining the method. In the figure, the same members as those in FIG. 4 are denoted by the same reference numerals, but the other 12 is a bare chip used for the mounting structure of the first embodiment, and 22 is It is a bare chip used for the mounting structure of the second embodiment.

As shown in FIG. 1, a bare chip 12 is formed by forming an integrated circuit of a semiconductor element in the center of a thin substrate 12-1 made of single-crystal silicon or the like, and forming a plurality of connection parts drawn from the integrated circuit on the periphery. This is an element body of the semiconductor device in which the terminal 12-1a is provided.

As shown in FIG. 1A, the mounting structure of the semiconductor chip according to the first embodiment using the above-described members is a connection terminal 12-1a formed on one surface of the substrate 12-1 of the bare chip 12.
The connection terminal 12-1a is exposed by applying an insulating film 13 made of an insulating resin to the entire surface except for the connection terminal 12-1a exposed from the surface of the insulating film 13 to make the connection terminal 12-1a conductive. A conductor pattern 14 is formed from an epoxy-based conductive paint to the other surface at a position corresponding to 1a.

The plurality of bare chips 12 and the bare chip 12 'provided with the leads 12-2 by TAB with the connection terminals 12-1a in the same direction are connected to the conductor pattern 14 and the connection terminals.
12-1a or the respective conductor patterns 14 are connected to form a laminated body of bare chips 12, 12 ', and the connection terminals 12-1a of the laminated body are directed upward, and the bare chip positioned at the lowermost layer is formed.
The lead 12-2 wired by bonding of 12 'or the like is mounted on the printed wiring board 1 by bonding it to the foot pattern 1-1.

Further, as shown in FIG.
a) in the same direction, a plurality of the bare chips 12 are connected and laminated by the conductor pattern 14, and the connection terminals of the laminate are
The bare chip 12 located on the lowermost layer with 12-1a facing downward
The connection terminal 12-1a or the conductor pattern 14 is connected to the foot pattern 1-1 of the wiring board 1 by a conductive adhesive 15 and mounted.

The method of forming the bare chip 22 used in the second embodiment is as follows. As shown in FIG. 3 (a), one side of the bare chip substrate 22-1 formed from single crystal silicon to a thickness of, for example, 400 μm is etched. A resist 22-4 is applied, the etching resist 22-4 having a diameter of, for example, 100 μm is removed at a position where conduction between the front and back is required, and etching is performed in a vacuum chamber to a depth of 100 μm as shown in FIG. After forming a through hole 22-1b of 320 μm and removing the etching resist 22-4 as shown in FIG. 3 (c), the front and back conductive conductors 22-1d are filled in the through hole 22-1b by vapor deposition or the like. At the same time, an electrode pad 22-1c having a diameter of 150 μm is formed at the entrance.

Then, as shown in FIG. 3D, the lower surface of the substrate 22-1, which is filled with the front and back conductive conductors 22-1d, ie, the electrode pads
By polishing the surface opposite to 22-1c by 100 μm to expose the end surface of the front and back conductive conductor 22-1d, an integrated circuit of a semiconductor element is formed on the surface of the substrate 22-1, and each connection is made. A plurality of fine leads are wired to the terminals by ATB, and connection bumps made of solder or the like are formed on the electrode pads 22-1c or on the end surfaces of the front and back conductive conductors 22-1d.

As shown in FIG. 2, the mounting structure of the semiconductor chip according to the second embodiment using the bare chip 22 is such that the wiring side of the lead 22-2 is in the same direction and the connection bump 22- A plurality of bare chips 22 are connected and laminated by 3 and the bare chips 22 of the lowermost layer are fixed to the wiring board 1 with an adhesive or the like with the leads 22-2 of the laminated bare chips 22 facing upward, and each bare chip 22 Lead 22-2 of the wiring substrate 1 by bonding or the like.
Connected to

[0017]

As is apparent from the above description, according to the present invention, since a plurality of bare chips are mounted on each foot pattern formed on the wiring board with a very simple structure, the printed circuit board unit It has advantages such as downsizing and weight reduction, and is extremely economical and
It is possible to provide a semiconductor chip mounting structure that can be expected to improve reliability.

[Brief description of the drawings]

FIG. 1 is an enlarged side sectional view showing a mounting structure of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is an enlarged side sectional view showing a mounting structure of a second embodiment.

FIG. 3 is a side sectional view illustrating a method of forming a through hole in a bare chip used in a second embodiment in the order of steps;

FIG. 4 is a perspective view showing a conventional semiconductor mounting structure.

[Explanation of symbols]

1 is a wiring board, 1-1 is a foot pattern, 12, 12 ', 22 are bare chips, 12-1, 22-1 are boards, 12-1
a and 22-1a are connection terminals, 12-2 and 22-2 are leads, 13 is an insulating film, 14 is a conductor pattern, 15 is a conductive adhesive, 22-1b is a through hole 22-1a, and 22-1c is a Electrode pad, 22-1
d is front and back conductive conductor, 22-3 is connection bump, 22-4 is etching resist,

Claims (4)

(57) [Claims] A contact provided on one main surface of a bare chip.
Apply an insulating film to the board surface except for the connection terminals, and
After forming the connected conductor pattern on the surface of the insulating film,
Characterized in that it extends to the other main surface of the bare chip.
The structure of the bare chip. 2. A stack of a plurality of bare chips according to claim 1.
And a conductor pattern provided on one main surface of the first bare chip.
At the corresponding position on the other main surface of the second bare chip.
Wiring board in the form of a conductor pattern
A bare chip mounting structure characterized by being mounted on the above. 3. The bare chip mounting structure according to claim 1,
With the one main surface on which the connection terminals are provided facing upward and the other
The conductor pattern extended on the other main surface on the wiring board.
Features connection to a preformed foot pattern
The mounting structure of the bare chip. 4. The method according to claim 1 , wherein the first main surface and the second main surface are arranged on the wiring board.
A plurality of bear chips having through holes with front and back conductive conductors
Formed by laminating the up, connection of the through-hole lower surface of the bare chip located adjacent the upper
Directly connect the terminal to the connection terminal on the top of the bare chip located below
Connect and provide independent external leads for each bare chip to
Of bare chips, characterized in that the connection of
Mounting structure.