JP2001267490A - Semiconductor module - Google Patents
Semiconductor moduleInfo
- Publication number
- JP2001267490A JP2001267490A JP2000070246A JP2000070246A JP2001267490A JP 2001267490 A JP2001267490 A JP 2001267490A JP 2000070246 A JP2000070246 A JP 2000070246A JP 2000070246 A JP2000070246 A JP 2000070246A JP 2001267490 A JP2001267490 A JP 2001267490A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- board
- semiconductor chip
- circuit
- flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Combinations Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップを三
次元実装した半導体モジュールに関する。The present invention relates to a semiconductor module in which a semiconductor chip is three-dimensionally mounted.
【０００２】[0002]
【従来の技術及びその問題点】半導体チップを内部に実
装した構成として、例えば特開平５−２２６５１８号公
報や特開平６−４５７６３号公報に記載のものがある。
これらは、例えば図１０に示すように平坦回路基板１上
に半導体チップ２を実装し、開口部３を有する枠型の基
板４をその半導体チップ２を内部に収容するようにして
重ね、これに更に平坦回路基板１を重ねた構成である。
これらの構成では、上下の回路基板間を電気的に接続す
る構造に困難があり、実際には高密度なモジュール化が
困難である。また、１つの半導体チップ２を実装するた
めに２枚の基板１，４が必要であるから、半導体チップ
の実装数が増大すると、基板数が大幅に増加し、製造上
の困難が生じてくる。2. Description of the Related Art As a configuration in which a semiconductor chip is mounted inside, there are, for example, those described in JP-A-5-226518 and JP-A-6-45763.
For example, as shown in FIG. 10, a semiconductor chip 2 is mounted on a flat circuit board 1, and a frame-shaped substrate 4 having an opening 3 is stacked so as to house the semiconductor chip 2 therein. Further, the flat circuit board 1 is stacked.
In these configurations, there is a difficulty in a structure for electrically connecting the upper and lower circuit boards, and in practice, it is difficult to form a high-density module. In addition, since two substrates 1 and 4 are required to mount one semiconductor chip 2, when the number of mounted semiconductor chips increases, the number of substrates increases significantly, which causes difficulty in manufacturing. .
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記事情に鑑
みてなされたもので、その目的は、回路基板を多層化し
て内部に半導体チップを実装するようにした半導体モジ
ュールにおいて、回路基板間の層間接続を高密度で行う
ことができ、しかも、回路基板数を削減して容易に製造
できるようになすことである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor module in which a circuit board is multilayered and a semiconductor chip is mounted inside. An object is to enable high-density interlayer connection and to reduce the number of circuit boards to facilitate manufacture.
【０００４】[0004]
【課題を解決するための手段】上記課題の解決のため、
請求項１の発明は、回路基板を複数枚積層して内部に半
導体チップを収容した状態に構成されるものであって、
前記回路基板の一方の面には導体回路が形成されるとと
もに、前記半導体チップがその導体回路と接続されて前
記一方の面に実装され、他方の面には積層される他の回
路基板に実装された半導体チップを逃げるための収容凹
部が形成され、その収容凹部から外れた位置にはその回
路基板を貫通して前記導体回路に連なるビアバンプが形
成され、他の回路基板との積層状態で前記ビアバンプに
より前記回路基板間の層間接続がされている構成とした
ところに特徴を有する。Means for Solving the Problems To solve the above problems,
The invention according to claim 1 is configured such that a plurality of circuit boards are stacked and a semiconductor chip is housed therein.
A conductor circuit is formed on one surface of the circuit board, and the semiconductor chip is connected to the conductor circuit and mounted on the one surface, and mounted on another circuit board laminated on the other surface. A receiving recess for escaping the removed semiconductor chip is formed, and a via bump penetrating the circuit board and continuing to the conductor circuit is formed at a position deviated from the receiving recess, and the via bump is formed in a laminated state with another circuit board. It is characterized in that the interlayer connection between the circuit boards is made by via bumps.
【０００５】請求項２の発明は、前記回路基板の収容凹
部を、開口部を有する枠型基板と平坦基板とを貼り合わ
せることにより枠型基板の開口部により形成される構成
としたところに特徴を有する。また、請求項３の発明
は、回路基板の収容凹部を、平坦基板の一方の面をざぐ
り加工することにより形成したところに特徴を有するも
のである。The invention according to claim 2 is characterized in that the accommodation recess of the circuit board is formed by the opening of the frame substrate by bonding a frame substrate having an opening to a flat substrate. Having. The invention according to claim 3 is characterized in that the accommodation recess of the circuit board is formed by counterboring one surface of the flat board.
【０００６】[0006]
【発明の作用及び効果】本発明によれば、回路基板を貫
通して形成されたビアバンプにより層間接続が可能にな
り、小型・高密度化することができる。また、１個の半
導体チップ毎に１枚の回路基板を使用することになるか
ら、多数の半導体チップを三次元実装して高密度化を図
っても、積層される回路基板数を削減することができ、
製造が容易になる。According to the present invention, interlayer connection is enabled by the via bumps formed through the circuit board, and miniaturization and high density can be achieved. In addition, since one circuit board is used for each semiconductor chip, the number of circuit boards to be stacked can be reduced even when a large number of semiconductor chips are three-dimensionally mounted to increase the density. Can be
Manufacturing becomes easier.
【０００７】[0007]
【発明の実施の形態】以下、本発明をメモリモジュール
に適用した第１実施形態について図１〜図６を参照して
説明する。図１に中間層に積層される中間回路基板１０
を示した。これは図２に示すように平坦基板１１と、四
角の開口部１２Ａを備えた枠型基板１２とを貼り合わせ
ることにより形成されたもので、上記開口部１２Ａによ
って後述する半導体チップ１３を収容する収容凹部１４
が下面に形成されている。これらの回路基板１１，１２
は厚さ例えば７５μｍで、ガラスエポキシを絶縁基材と
したもので、平坦基板１１には予め銅箔をエッチングす
ることにより所要の回路パターン１５が形成されてい
る。そして、この平坦基板１１の表面には例えばＩＣメ
モリの半導体チップ１３が回路パターン１５上にフリッ
プチップ実装されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to a memory module will be described below with reference to FIGS. FIG. 1 shows an intermediate circuit board 10 laminated on an intermediate layer.
showed that. This is formed by bonding a flat substrate 11 and a frame type substrate 12 having a square opening 12A as shown in FIG. 2, and accommodates a semiconductor chip 13 described later by the opening 12A. Housing recess 14
Are formed on the lower surface. These circuit boards 11 and 12
Has a thickness of, for example, 75 μm and is made of glass epoxy as an insulating base material. A required circuit pattern 15 is formed on the flat substrate 11 by etching a copper foil in advance. On the surface of the flat substrate 11, for example, a semiconductor chip 13 of an IC memory is flip-chip mounted on the circuit pattern 15.
【０００８】また、収容凹部１４を取り囲む周囲部分に
は、互いに貼り合わされた平坦基板１１と枠型基板１２
との双方を貫通してビアホール１６が枠型基板１２側か
ら回路パターン１５に届くようにレーザー照射によって
形成され、その内部に例えば電解銅メッキと電解スズメ
ッキとを順に行うことによってビアホール１６を充填す
るビアバンプ１７が形成されている。このビアバンプ１
７の一端側は回路パターン１５に接触しており、他端側
は枠型基板１２の下面から僅かに突出した状態となって
いる。このような構成の中間回路基板１０は本実施形態
では例えば３枚準備される。A flat substrate 11 and a frame type substrate 12 bonded to each other are
Are formed by laser irradiation so as to reach the circuit pattern 15 from the frame type substrate 12 side, and the via holes 16 are filled by performing, for example, electrolytic copper plating and electrolytic tin plating in this order. Via bumps 17 are formed. This via bump 1
One end of 7 is in contact with the circuit pattern 15, and the other end is slightly projected from the lower surface of the frame type substrate 12. In the present embodiment, for example, three intermediate circuit boards 10 having such a configuration are prepared.
【０００９】一方、モジュールの最下層に位置する下層
回路基板２０は、２枚の平坦基板２１，２２を貼り合わ
せて構成されている。上側の平坦基板２１は上述の中間
回路基板１０の平坦基板１１と同一構成で、上面に半導
体チップ１３がフリップチップ実装されている。また、
下側の平坦基板２２は開口部を備えず、下面側に接続用
の回路パターン２３を備え、半導体チップ１３に連なる
上側の回路パターン２４と下側の回路パターン２３とは
前記中間回路基板１０と同様に形成したビアバンプ２５
によって接続されている。On the other hand, the lower circuit board 20 located at the lowermost layer of the module is constituted by bonding two flat substrates 21 and 22 together. The upper flat substrate 21 has the same configuration as the flat substrate 11 of the above-described intermediate circuit substrate 10, and the semiconductor chip 13 is flip-chip mounted on the upper surface. Also,
The lower flat substrate 22 does not have an opening, has a connection circuit pattern 23 on the lower surface side, and the upper circuit pattern 24 and the lower circuit pattern 23 connected to the semiconductor chip 13 are the same as the intermediate circuit substrate 10. Via bump 25 formed similarly
Connected by
【００１０】また、モジュールの最上層に位置する上層
回路基板３０は、中間回路基板１０と同様に互いに貼り
合わされた平坦基板３１と枠型基板３２とによって構成
されており、枠型基板３２の開口部３２Ａによって下層
の中間回路基板１０に実装された半導体チップ１３を逃
げるための収容凹部３３が形成されている。そして、平
坦基板３１の上面には図４に示すように銅箔のエッチン
グにより多数のパッド３４とこれに連なるビアバンプ３
５とが形成されている。The upper circuit board 30 located at the uppermost layer of the module is composed of a flat board 31 and a frame board 32 bonded together like the intermediate circuit board 10. An accommodation recess 33 for allowing the semiconductor chip 13 mounted on the lower intermediate circuit board 10 to escape is formed by the portion 32A. On the upper surface of the flat substrate 31, as shown in FIG. 4, a large number of pads 34 and via bumps 3 connected thereto are etched by copper foil.
5 are formed.
【００１１】以上の構成の上層回路基板３０，中間回路
基板１０及び下層回路基板２０は互いに位置合わせさ
れ、相互間に例えばエポキシ系の接着剤４０を挟んで加
熱真空プレスされ、これを硬化させることで図５に示す
ように各回路基板１０，２０，３０を相互に固着して一
体化される。その後、上層回路基板３０のパッド３４上
に半田ボール３６を付着させてメモリモジュールが完成
する（図６参照）。The upper circuit board 30, the intermediate circuit board 10, and the lower circuit board 20 having the above-described structure are aligned with each other, and are heated and vacuum-pressed with, for example, an epoxy-based adhesive 40 therebetween, and are cured. As shown in FIG. 5, the circuit boards 10, 20, 30 are fixed to each other and integrated. Thereafter, solder balls 36 are attached to the pads 34 of the upper circuit board 30 to complete the memory module (see FIG. 6).
【００１２】このような本実施形態の構成によれば、各
回路基板１０，２０，３０を貫通して形成されたビアバ
ンプ１７，２５，３５により層間接続が可能になり、モ
ジュールの小型・高密度化が可能になる。また、１個の
半導体チップ１３毎に１枚の回路基板１０，２０を使用
することになるから、多数の半導体チップ１３を三次元
実装して高密度化を図っても、積層される回路基板数を
削減することができ、製造が容易になる。According to the configuration of the present embodiment, interlayer connection is enabled by the via bumps 17, 25, and 35 formed through the circuit boards 10, 20, 30, and the module is compact and high-density. Becomes possible. In addition, since one circuit board 10 and 20 is used for each semiconductor chip 13, even if a large number of semiconductor chips 13 are three-dimensionally mounted to increase the density, the circuit boards to be stacked can be stacked. The number can be reduced, and manufacturing becomes easier.
【００１３】図７ないし図９は本発明の第２実施形態を
示す。前記第１実施形態との相違は、各回路基板の構造
である。すなわち、第１実施形態では各回路基板は２枚
の基板の貼り合わせにより形成したが、この第２実施形
態では１枚のガラスエポキシ基材の銅張積層板から構成
している。図７に示した中間回路基板５０は、例えば１
５０μｍ程度の厚さで両面が平坦なガラスエポキシ基板
の下面側をザグリ加工することにより下層の半導体チッ
プ５１のための収容凹部５０Ａを形成してある。その中
間回路基板５０の上面には予め銅箔をエッチングするこ
とにより、所要の回路パターン５２が形成され、この回
路パターン５２上に例えばＩＣメモリの半導体チップ５
１がフリップチップ実装されている。また、収容凹部５
０Ａを取り囲む周囲部分には、例えばレーザ照射によっ
てビアホール５３が形成され、その内部に例えば電解銅
メッキ層５４Ａと電解スズメッキ層５４Ｂとを順に重ね
ることによってビアバンプ５４が充填されている。この
ビアバンプ５４の上端側の電解銅メッキ層５４Ａは回路
パターン５２に接触しており、下端側は中間回路基板５
０の下面から僅かに突出した状態となっている。このよ
うな構成の中間回路基板５０は本実施形態では例えば３
枚準備される。FIGS. 7 to 9 show a second embodiment of the present invention. The difference from the first embodiment is the structure of each circuit board. That is, in the first embodiment, each circuit board is formed by laminating two boards. In the second embodiment, however, each circuit board is formed of one glass-epoxy-based copper-clad laminate. The intermediate circuit board 50 shown in FIG.
A recess 50A for the lower semiconductor chip 51 is formed by counterboring the lower surface of a glass epoxy substrate having a thickness of about 50 μm and flat on both sides. A predetermined circuit pattern 52 is formed on the upper surface of the intermediate circuit board 50 by etching a copper foil in advance, and, for example, a semiconductor chip 5 of an IC memory is formed on the circuit pattern 52.
1 is flip-chip mounted. Also, the accommodation recess 5
Via holes 53 are formed, for example, by laser irradiation in the peripheral portion surrounding 0A, and are filled with via bumps 54 by, for example, sequentially laminating an electrolytic copper plating layer 54A and an electrolytic tin plating layer 54B. The electrolytic copper plating layer 54A on the upper end of the via bump 54 is in contact with the circuit pattern 52, and the lower end is on the intermediate circuit board 5
0 protrudes slightly from the lower surface. In the present embodiment, the intermediate circuit board 50 having such a configuration is, for example, 3
Are prepared.
【００１４】一方、モジュールの最下層に位置する下層
回路基板６０は、図８に示すように、下面をザグリ加工
していないところのみが上記中間回路基板５０と相違す
るもので、やはり上面に回路パターン６１を形成すると
ともに、ここに半導体チップ５１がフリップチップ実装
されている。また、下面側には接続用の回路パターン６
２が形成されており、半導体チップ５１に連なる上側の
回路パターン６１と下側の回路パターン６２とは前記中
間回路基板５０と同様に形成したビアバンプ６３によっ
て接続されている。また、モジュールの最上層に位置す
る上層回路基板７０は、中間回路基板５０と同様に下面
にザグリ加工により形成した収容凹部７０Ａを備える。
そして、上面には銅箔のエッチングにより多数のパッド
７１とこれに連なるビアバンプ７２とが形成されてい
る。On the other hand, as shown in FIG. 8, the lower circuit board 60 located at the lowermost layer of the module is different from the intermediate circuit board 50 only in that the lower surface is not counterbored. The pattern 61 is formed, and the semiconductor chip 51 is flip-chip mounted thereon. On the lower surface side, a circuit pattern 6 for connection is provided.
2 are formed, and the upper circuit pattern 61 connected to the semiconductor chip 51 and the lower circuit pattern 62 are connected by via bumps 63 formed similarly to the intermediate circuit board 50. The upper circuit board 70 located at the uppermost layer of the module has a receiving recess 70A formed on the lower surface thereof by counterboring as in the case of the intermediate circuit board 50.
A large number of pads 71 and via bumps 72 connected to the pads 71 are formed on the upper surface by etching the copper foil.
【００１５】以上の構成の上層回路基板７０，中間回路
基板５０及び下層回路基板６０は、前記第１実施形態と
同様に、互いに位置合わせされ、相互間に例えばエポキ
シ系の接着剤８０を挟んで加熱真空プレスされ、これを
硬化させることで図９に示すように各回路基板７０，５
０，６０を相互に固着して一体化される。その後、上層
回路基板７０のパッド７１上に半田ボールを付着させて
メモリモジュールが完成する。この第２実施形態によれ
ば、３種類の各回路基板５０，６０，７０を１枚のガラ
スエポキシ基板から製造できるから、第１実施形態に比
べて基板の取扱い枚数が減少し、製造コスト上、有利と
なる。The upper circuit board 70, the intermediate circuit board 50, and the lower circuit board 60 having the above-described configuration are aligned with each other, similarly to the first embodiment, with an epoxy adhesive 80 interposed therebetween. The circuit boards 70 and 5 are heated and vacuum-pressed and cured, as shown in FIG.
0, 60 are fixed to each other and integrated. Thereafter, solder balls are attached to the pads 71 of the upper circuit board 70 to complete the memory module. According to the second embodiment, the three types of circuit boards 50, 60, and 70 can be manufactured from one glass epoxy board, so that the number of boards to be handled is reduced as compared with the first embodiment, and the manufacturing cost is reduced. , Would be advantageous.
【００１６】本発明は上記記述及び図面によって説明し
た実施の形態に限定されるものではなく、例えば次のよ
うな実施の形態も本発明の技術的範囲に含まれ、さら
に、下記以外にも要旨を逸脱しない範囲内で種々変更し
て実施することができる。 （１）上記各実施形態では、半導体チップ１３をフリッ
プチップ実装により回路基板１０，２０に装着したが、
これに限らず、ワイヤボンディング法によって実装して
もよい。 （２）また、半導体チップ１３はメモリＩＣに限らず、
例えばロジックＩＣ、マイクロプロセッサ、汎用や専用
のデジタルシグナルプロセッサ、アナログＩＣ、ハイブ
リッドＩＣ等の半導体集積回路であってもよく、さら
に、例えばメモリＩＣ及びロジックＩＣのような異種の
半導体チップを組み合わせた混在型としてもよい。The present invention is not limited to the embodiments described with reference to the above description and the drawings. For example, the following embodiments are also included in the technical scope of the present invention. Various changes can be made without departing from the scope of the present invention. (1) In the above embodiments, the semiconductor chip 13 is mounted on the circuit boards 10 and 20 by flip-chip mounting.
However, the present invention is not limited to this, and may be mounted by a wire bonding method. (2) The semiconductor chip 13 is not limited to a memory IC,
For example, it may be a semiconductor integrated circuit such as a logic IC, a microprocessor, a general-purpose or special-purpose digital signal processor, an analog IC, a hybrid IC, or the like, and may be a combination of different types of semiconductor chips such as a memory IC and a logic IC. It may be a type.
【図１】 本発明の第１実施形態に係る中間回路基板を
示す断面図FIG. 1 is a sectional view showing an intermediate circuit board according to a first embodiment of the present invention.
【図２】 同じく中間回路基板の分解斜視図FIG. 2 is an exploded perspective view of the same intermediate circuit board.
【図３】 モジュールの分解断面図FIG. 3 is an exploded sectional view of the module.
【図４】 モジュールの分解斜視図FIG. 4 is an exploded perspective view of the module.
【図５】 完成したモジュールの断面図FIG. 5 is a cross-sectional view of the completed module.
【図６】 完成したモジュールの斜視図FIG. 6 is a perspective view of a completed module.
【図７】 本発明の第２実施形態を示す中間回路基板の
断面図FIG. 7 is a sectional view of an intermediate circuit board according to a second embodiment of the present invention.
【図８】 同じく第２実施形態に係るモジュールの分解
斜視図FIG. 8 is an exploded perspective view of the module according to the second embodiment.
【図９】 同じく第２実施形態に係る完成したモジュー
ルの断面図FIG. 9 is a sectional view of a completed module according to the second embodiment.
【図１０】従来のモジュール構造を示す断面図FIG. 10 is a sectional view showing a conventional module structure.
１０，２０，３０、５０，６０，７０……回路基板 １１……平坦基板 １２……枠型基板 １２Ａ……開口部 １３……半導体チップ １４……収容凹部 １７……ビアバンプ ４０，８０……接着剤 10, 20, 30, 50, 60, 70 ... circuit board 11 ... flat board 12 ... frame type board 12A ... opening 13 ... semiconductor chip 14 ... accommodating recess 17 ... via bump 40, 80 ... adhesive
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 1/14 Ｈ０１Ｌ 23/52 Ｃ 1/18 3/46 Ｆターム(参考） 5E336 AA04 AA08 BB03 CC34 CC58 5E344 AA01 BB06 CC09 CC24 CD40 EE13 5E346 AA12 CC04 CC09 CC31 CC32 DD12 EE02 EE12 EE13 FF14 FF45 GG15 GG22 GG40 HH22 HH25 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H05K 1/14 H01L 23/52 C 1/18 3/46 F term (Reference) 5E336 AA04 AA08 BB03 CC34 CC58 5E344 AA01 BB06 CC09 CC24 CD40 EE13 5E346 AA12 CC04 CC09 CC31 CC32 DD12 EE02 EE12 EE13 FF14 FF45 GG15 GG22 GG40 HH22 HH25
Claims (3)
チップを収容した状態に構成されるものであって、前記
回路基板の一方の面には導体回路が形成されるととも
に、前記半導体チップがその導体回路と接続されて前記
一方の面に実装され、他方の面には積層される他の回路
基板に実装された半導体チップを逃げるための収容凹部
が形成され、その収容凹部から外れた位置にはその回路
基板を貫通して前記導体回路に連なるビアバンプが形成
され、他の回路基板との積層状態で前記ビアバンプによ
り前記回路基板間の層間接続がされていることを特徴と
する半導体モジュール。1. A circuit board comprising a plurality of circuit boards stacked and semiconductor chips housed therein, wherein a conductor circuit is formed on one surface of the circuit board and the semiconductor chip Is connected to the conductor circuit and mounted on the one surface, and the other surface is formed with a housing recess for escaping a semiconductor chip mounted on another circuit board to be laminated, and is detached from the housing recess. A semiconductor module, wherein a via bump is formed at a position to penetrate the circuit board and is connected to the conductor circuit, and an interlayer connection between the circuit boards is provided by the via bump in a laminated state with another circuit board. .
する枠型基板と平坦基板とを貼り合わせることにより前
記枠型基板の前記開口部により形成されていることを特
徴とする請求項１記載の半導体モジュール。2. The circuit board according to claim 1, wherein the housing concave portion is formed by bonding the frame substrate having an opening and a flat substrate together with the opening of the frame substrate. The semiconductor module as described in the above.
一方の面をざぐり加工することにより形成されているこ
とを特徴とする請求項１記載の半導体モジュール。3. The semiconductor module according to claim 1, wherein the housing recess of the circuit board is formed by counterboring one surface of a flat board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000070246A JP4074040B2 (en) | 2000-03-14 | 2000-03-14 | Semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000070246A JP4074040B2 (en) | 2000-03-14 | 2000-03-14 | Semiconductor module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001267490A true JP2001267490A (en) | 2001-09-28 |
| JP4074040B2 JP4074040B2 (en) | 2008-04-09 |
Family
ID=18589012
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000070246A Expired - Fee Related JP4074040B2 (en) | 2000-03-14 | 2000-03-14 | Semiconductor module |
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