JP2002313996A - Substrate for semiconductor package, and its manufacturing method - Google Patents

Substrate for semiconductor package, and its manufacturing method

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Publication number
JP2002313996A
JP2002313996A JP2001120254A JP2001120254A JP2002313996A JP 2002313996 A JP2002313996 A JP 2002313996A JP 2001120254 A JP2001120254 A JP 2001120254A JP 2001120254 A JP2001120254 A JP 2001120254A JP 2002313996 A JP2002313996 A JP 2002313996A
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semiconductor
copper
bump
height
package
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JP2001120254A
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Japanese (ja)
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Yasuhiro Takeyama
保博 竹山
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Toshiba Chem Corp
東芝ケミカル株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor package where a load is not applied to a semiconductor chip at stacking by reducing the dispersion of the height of a bump.
SOLUTION: A copper-laminated plate 15, where the thickness of a copper foil 11 is selected optimally in consideration of the height requested for a bump 6, is prepared, and the copper foil 11 of this copper-laminated plate 15 is selectively removed thereby forming the bump 6. The bump 6 where height accuracy on approximately the same level as the copper foil 11 is obtained, and a highly reliable semiconductor package where a load is not applied to a semiconductor part 12 can be provided, and also the margin to be added at decision of the height of the bump can be reduced, and the package can be made thin as a whole.
COPYRIGHT: (C)2002,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、三次元積層に適した半導体パッケージ用基板とその製造方法に関する。 The present invention relates to a substrate for a semiconductor package suitable for three-dimensional stacked and a manufacturing method thereof.

【0002】 [0002]

【従来の技術】近年、電子機器の小型化、多機能化につれ、LSI等の半導体チップの高集積化が進み、半導体チップの形態においても端子数の増加および端子間の狭ピッチ化等が図られている。 In recent years, miniaturization of electronic devices, as multifunctional, progress in high integration of semiconductor chips such as LSI, pitch and the like between the even number of terminals increases and the terminal in the form of the semiconductor chip in FIG. It is. また一方で、半導体ベアチップをリードを介さず基板に直接実装するFCB(Flip On the other hand, FCB directly mounted on the substrate without using the lead semiconductor bare chip (Flip
Chip Bonding)技術の研究が進められている。 Chip Bonding) study of the technology has been advanced.

【0003】ところで、今後更なる実装密度の向上に向け、従来の平面構造から三次元積層による半導体パッケージが必要となる。 [0003] Toward the further improvement in mounting density future, semiconductor packages by the three dimensional stacked from a conventional planar structure is required. 三次元積層パッケージには、チップを積層して一つのパッケージに収めたものと、複数の半導体パッケージを積層したものとがある。 The three-dimensional stacked package, there are those of matches in one package by stacking chips, and formed by laminating a plurality of semiconductor packages.

【0004】 [0004]

【発明が解決しようとする課題】半導体パッケージを積層する方法はいくつか提案されているおり、コネクタなどの他の部品を使用するタイプ、バンプを使用するタイプ、TABの技術を応用するタイプなどがある。 Method of stacking a semiconductor package [0008] is have been proposed, the type to use other parts, such as connectors, the type of using bumps, such as the type of application of TAB technology is there.

【0005】パッケージ間の間隙を確保しながら、薄型化や積層数の増加に対応するにはバンプを使用する方法が有利と考えられるが、このタイプもパッケージへバンプを後から形成するタイプとあらかじめ基板にバンプを形成しておくタイプに分けられる。 [0005] while ensuring a gap between the package, a method of using bumps to accommodate the increase in the thickness and number of stacked is considered advantageous in advance the type of forming this later type bumps also to the package It is divided into type to be formed a bump on a substrate.

【0006】ところで、バンプの高さによって他層の半導体パッケージとの間において確保される空間内に半導体チップを配置する方法においては、製造誤差等によるパンプ厚の不足によって、積層半導体パッケージにおいて本来バンプで受けなければならない負荷の少なくとも一部がチップに加わり、最悪の場合、その負荷によってチップにクラックが入るおそれがある。 [0006] In the method of placing the semiconductor chip in the space reserved between the semiconductor package of the other layer by the height of the bumps, by the lack of bump thickness due to manufacturing error or the like, original bump in the laminated semiconductor package at least a portion of the load which must be received in is applied to the chip, in the worst case, there is a possibility that cracks in the chip by the load. このため、バンプ高さの決定に際して、製造誤差を考慮した十分なマージンを加味する必要があり、結果的にパッケージ全体の厚みが大きくなってしまうという問題があった。 Therefore, in determining the bump height, it is necessary to considering the sufficient margin in consideration of manufacturing errors, resulting in the overall package thickness is disadvantageously increased.

【0007】本発明は、このような事情を鑑みてなされたものであり、バンプの高さのバラツキを低減して、半導体部品に負荷が加わることのない信頼性の高い半導体パッケージ用基板およびその製造方法の提供を目的とする。 [0007] The present invention has been made in view of such circumstances, to reduce the variation in height of the bump, substrate and that no highly reliable semiconductor package load is applied to the semiconductor component and an object thereof is to provide a manufacturing method.

【0008】 [0008]

【課題を解決するための手段】請求項1の発明は、上記目的を達成するために、基材とこの基材の少なくとも一方面に張りつけられた銅箔とからなる銅箔張り材と、この銅箔張り材の前記基材の他方面に形成された導体パターンと、前記銅箔張り材の前記銅箔を選択的に除去することによって形成され、前記導体パターンとビア接続され、かつ前記基材に搭載される半導体部品の高さよりも突出した複数の外部接続端子とを具備することを特徴とする。 Means for Solving the Problems of claims 1 invention, in order to achieve the above object, a copper foil-clad material comprising a base material and copper foil affixed to at least one surface of the substrate, this a conductive pattern formed on the other surface of the base material of a copper foil-clad substrate, formed by selectively removing the copper foil of the copper foil-clad substrate, the conductor pattern is via connection, and the base characterized by comprising a plurality of external connection terminals projecting than the height of the semiconductor components mounted on wood.

【0009】本発明によれば、銅箔とほぼ同等の高さ精度が保証された外部接続端子が得られるので、これらの外部接続端子が半導体部品よりも厚み方向にて突出するように銅箔の厚みを最適に選定しておくことによって、 According to the present invention, the copper foil as since the copper foil and the external connection terminal is almost the same height accuracy is guaranteed to obtain, these external connection terminals are protruded in the thickness direction than the semiconductor component by keeping it selects the thickness optimally,
半導体部品に負荷の加わらない、信頼性の高い半導体パッケージを提供することができる。 Not applied load to the semiconductor component, it is possible to provide a highly reliable semiconductor package. また、製造誤差を考慮して外部接続端子の高さに加味すべきマージンが少なくて済むことから、パッケージ全体の厚みを薄くすることができる。 Moreover, since fewer be adding to the height margin of the external connection terminals in consideration of the manufacturing error, it is possible to reduce the overall thickness of package.

【0010】請求項2の発明は、上記目的を達成するために、請求項1記載の半導体パッケージにおいて、前記基材の一方面から前記基材の他方面に形成された導体パターンへ達する穴を有する、前記基材の一方面に搭載される前記半導体部品の外部端子が前記穴内に挿入され前記導体パターンと接続可能なことを特徴とする。 [0010] The second aspect of the present invention, in order to achieve the above object, in a semiconductor package according to claim 1, a hole from one surface of the substrate reaches the conductor pattern formed on the other surface of the substrate having an external terminal of the semiconductor components mounted on one surface of the substrate is inserted into said hole, characterized in that connectable to the conductor pattern.

【0011】本発明はこのような構成を持つことで、半導体部品を基材面に接した状態で搭載できる。 [0011] The present invention is by having such a structure, can be mounted in contact with each other when the semiconductor component to the substrate surface. これにより、パッケージ全体の厚みをさらに薄くすることができる。 This makes it possible to further reduce the overall thickness of package.

【0012】請求項3の発明は、請求項1または2記載の半導体パッケージ用基板において、前記基材の他方面に、他の半導体パッケージ用基板の外部接続端子を接合するパッドが形成されていることを特徴とするものである。 [0012] A third aspect of the present invention, a semiconductor package substrate according to claim 1 or 2, wherein the other surface of the substrate, the pad for bonding the external connection terminal of another semiconductor package substrate are formed it is characterized in.

【0013】この発明によれば、外部接続端子の高さ精度として銅箔と同等の十分な精度が保証されるので、多層化した場合、半導体パッケージ内の半導体部品に他層の半導体パッケージからの負荷が加わることを回避することができ、信頼性の高い積層半導体パッケージを提供することができる。 According to this invention, since the height copper foil equivalent sufficient accuracy as the accuracy of the external connection terminals is guaranteed, when the multilayered, from the semiconductor package of another layer in the semiconductor component in the semiconductor package it is possible to avoid that the load is applied, it is possible to provide a highly reliable semiconductor package stack. また、製造誤差を考慮して外部接続端子の高さに加味すべきマージンが少なくて済むことから、積層半導体パッケージ全体の厚みを薄くすることができる。 Moreover, since fewer margin should consideration the height of the external connection terminals in consideration of the manufacturing error, it is possible to reduce the thickness of the entire semiconductor package stack.

【0014】請求項4の発明は、上記目的を達成するために、複数の外部接続端子を同一面に有する半導体パッケージ用基板の製造方法において、基材と、この基材の少なくとも一方面に張りつけられ、実装される半導体部品よりも厚い銅箔とからなる銅箔張り材を用意し、この銅箔張り材の他方面に導体パターンを形成する一方、前記銅箔張り材の銅箔を選択的に除去することによって前記複数の外部接続端子を形成することを特徴とする。 [0014] A fourth aspect of the present invention, in order to achieve the above object, affixed in the manufacturing method of a substrate for a semiconductor package having a plurality of external connection terminals on the same surface, a substrate, at least one surface of the substrate It is, while providing a copper foil-clad material composed of thick copper foil than the semiconductor components to be mounted, to form a conductive pattern on the other surface of the foil coverings, selectively copper foil of the copper foil coverings and forming a plurality of external connection terminals by removing the.

【0015】本発明によれば、銅箔張り材の銅箔を選択的に除去することによって、銅箔と同等の厚み精度が保証された複数の外部接続端子を得ることができるので、 According to the present invention, by selectively removing the copper foil of a copper foil-clad material, it is possible to obtain a plurality of external connection terminals copper foil equivalent thickness accuracy is guaranteed,
これらの外部接続端子が半導体部品よりも厚み方向に突出するように銅箔の厚みを最適に選定しておくことによって、半導体部品に負荷の加わらない、信頼性の高い半導体パッケージを提供することができる。 By these external connection terminals keep optimally selecting the thickness of the copper foil so as to protrude in the thickness direction than the semiconductor parts, not applied load to the semiconductor component, to provide a highly reliable semiconductor package it can. また、製造誤差を考慮して外部接続端子の高さに加味すべきマージンが少なくて済むことから、パッケージ全体の厚みを薄くすることができる。 Moreover, since fewer be adding to the height margin of the external connection terminals in consideration of the manufacturing error, it is possible to reduce the overall thickness of package.

【0016】 [0016]

【発明の実施の形態】以下、本発明の実施の形態を図面に基づき説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be explained based on the embodiment of the present invention with reference to the drawings.

【0017】図1は、本発明を実施した形態の一例である半導体パッケージの構成を示す断面図である。 [0017] Figure 1 is a sectional view showing a structure of a semiconductor package, which is an example of embodiment to which the present invention.

【0018】同図に示すように、本実施形態の半導体パッケージ100において、基材1の第1の主面(以下、 As shown in the figure, in the semiconductor package 100 of the present embodiment, the first main surface (hereinafter the substrate 1,
パターン面と呼ぶ)には、銅箔2と銅めっき層3とからなる導体パターンが設けられており、さらに当該導体パターンは、パッケージ接続パッド4の領域を除き、たとえばソルダーレジスト等からなる絶縁保護膜5によって覆われている。 The called a pattern surface), is provided with a conductor pattern made of copper foil 2 and the copper plating layer 3, further the conductive pattern, except for the region of the package connection pads 4, for example an insulating protection made of solder resist or the like It is covered by a membrane 5.

【0019】一方、基材1の、前記第1の主面の反対面となる第2の主面(以下、バンプ面と呼ぶ)には、半導体パッケージ100の外部接続端子であるバンプ6が複数設けられている。 Meanwhile, the substrate 1, the first opposite side to become the second major surface of the main surface (hereinafter, referred to as bump surface), the bump 6 is more an external connection terminal of the semiconductor package 100 It is provided. このバンプ6は、両面銅張り板の銅箔をエッチングなどにより選択的に除去し、残存銅箔部であるバンプ基体11aの表面に、たとえば、無電解のニッケル下地金めっき、もしくは電解半田めっきなどによる表面処理7を施してなるものである。 The bumps 6, the copper foil of the double-sided copper clad laminate is selectively removed by etching or the like, on the surface of the bump base 11a is residual copper foil portion, for example, electroless nickel undercoat gold plating, or electrolytic solder plating it is made of surface-treated 7 by. そして、このバンプ6はビア8を通じてパターン面の回路パターンと接続されている。 Then, the bumps 6 are connected to the circuit pattern of the pattern surface the via 8.

【0020】また、この半導体パッケージ100には、 [0020] In addition, in the semiconductor package 100,
半導体チップ12の外部接続端子13を接続するチップ接続パッド9が設けられている。 Chip connection pads 9 for connecting the external connection terminals 13 of the semiconductor chip 12 is provided. このチップ接続パッド9は、基材1のバンプ面側から、パターン面の銅箔2を露出させるための穴10を開け、この穴10を通じて露出した銅箔層2の表面に、無電解または電解のニッケルを下地とする金めっきによる表面処理15を施してなるものである。 The chip connection pads 9, from the bump side of the substrate 1, a hole 10 for exposing the copper foil 2 of the pattern surface, the exposed surface of the copper foil layer 2 through the holes 10, electroless or electrolytic the nickel is made by performing surface treatment 15 by gold plating to the base.

【0021】図2に、本実施形態の半導体パッケージ1 [0021] Figure 2, the semiconductor package 1 of this embodiment
00の製造手順を示す。 00 showing a manufacturing procedure of.

【0022】まず、バンプ6に要求される高さを考慮して銅箔11の厚みが最適に選定された両面銅張り板15 [0022] First, double-sided copper-clad laminate 15 in which the thickness of the copper foil 11 are optimally selected in consideration of the height required for the bumps 6
を用意する(図2(a))。 The prepared (FIG. 2 (a)). ここで、両面銅張り板15 Here, double-sided copper-clad laminate 15
としては、たとえば、半導体サブストレート用の両面銅張りガラス基材積層板または両面銅張りフレキシブル板などが用いられる。 As, for example, double-sided copper-clad glass substrate laminate or double-sided copper-clad flexible sheet for semiconductor substrates are used. 基材1は、その厚みがレーザー加工可能な程度のものであることが好ましく、たとえば、ガラス基材積層板で0.1mm以下、フレキシブルフィルムで0.05mm以下のものが好ましい。 Substrate 1 preferably has a thickness is of an extent that can be laser processing, for example, 0.1 mm or less in the glass substrate laminate is preferred for 0.05mm or less flexible film.

【0023】この両面銅張り板15のパターン面よりレーザー加工等によってバンプ面の銅箔11の表面に達する穴16を明ける(図2(b))。 [0023] The holes 16 reaching the surface of the copper foil 11 of the bump surface by laser machining or the like from the pattern surface of the double-sided copper clad laminate 15 punching (Figure 2 (b)). このとき、パターン面の銅箔2をエッチングによって穴明けした後で、基材1をレーザーで穴明けしてもよい。 At this time, the copper foil 2 of the pattern surface after drilling by etching, may be drilling a substrate 1 with laser.

【0024】次に、パターン面に無電解めっきを施した後、バンプ面をめっきレジストによって全面保護しつつ、パターン面にめっき処理によって銅めっき層3を形成する(図2(c))。 Next, after the electroless plating on the pattern surface, while the entire surface protecting bump surface by the plating resist, thereby forming a copper plating layer 3 by plating on the pattern surface (FIG. 2 (c)). このパターン面へのめっき処理はパネルめっき、パターンめっきのどちらで行ってもよい。 Plating treatment to the pattern surface panel plating may be performed in either pattern plating. この際、本実施形態では、基材1に開けられた穴1 At this time, the hole 1 in the present embodiment, opened in the substrate 1
6を銅めっきにより充填してビア8を形成し、開口部を平坦化することによって、積層用に適した半導体パッケージ100を得ている。 6 was filled with copper plating to form a via 8, by flattening the opening, to obtain a semiconductor package 100 suitable for lamination.

【0025】なお、パターン面に銅箔のない片面銅張り板を用いた場合は、パターン面よりバンプ面の銅箔11 [0025] In the case of using a one-sided copper-clad board without copper foil pattern surface, a copper foil 11 of the bump surface than the pattern surface
に達する穴16を開けた後に、無電解めっきに代えてスパッタリングにより穴16の表面を含むパターン面全体に導体層を形成しても構わない。 After a hole 16 reaching the, by sputtering in place of the electroless plating may be formed a conductive layer on the entire pattern surface including the surface of the bore 16.

【0026】続いて、バンプ面のめっきレジスト(図示せず)を剥離した後、エッチングによりパターン面に所望の導体パターンを形成する(図2(d))。 [0026] Subsequently, after removing the plating resist bumps surface (not shown), to form the desired conductive pattern on the pattern surface by etching (Figure 2 (d)).

【0027】次に、パッケージ接続パッド4の形成予定位置を除き、パターン面の必要な部分に、たとえばソルダーレジスト等をコーティングすることにより絶縁保護膜5を形成する(図2(e))。 Next, except for the formation planned location of the package connection pads 4, necessary portions of the pattern surface, an insulating protective film 5 by coating, for example a solder resist or the like (FIG. 2 (e)).

【0028】この後、パターン面をエッチングレジストで全面保護した状態で、バンプ面の銅箔11をエッチングによって選択的に除去することによってバンプ基体1 [0028] Thereafter, while the entire surface protecting pattern surface with an etching resist, bump substrate by selectively removing the copper foil 11 of the bump surface by etching 1
1aを形成する(図2(f))。 1a to the formation (FIG. 2 (f)). この後、必要に応じて、ハーフエッチングによってバンプ基体11aの高さを調整する。 Thereafter, if necessary, adjust the height of the bump base 11a by half etching.

【0029】次に、図1に示したように、チップ接続パッド9を形成するために、基材1の該当部分をバンプ面側からレーザー加工によって穴明けしてパターン面の銅箔2の表面2aを露出させる(図2(g))。 Next, as shown in FIG. 1, the chip connected to form a pad 9, the surface of the copper foil 2 of the pattern surface by drilling by laser processing that portion of the substrate 1 from the bump side exposing the 2a (FIG. 2 (g)).

【0030】続いて、バンプ基体11aの表面と、パッケージ接続パッド4およびチップ接続パッド9の形成予定部に、各々の仕様に準拠した表面処理を行う。 [0030] Subsequently, the the surface of the bump base 11a, a formation planned section of the package connection pads 4 and the chip connection pad 9, the surface treatment conforming to the respective specifications. たとえば、チップ接続パッド9の形成予定部には無電解または電解のニッケルを下地とする金めっきによる表面処理1 For example, surface treatment with gold plating for forming scheduled portion of the chip connection pads 9 for the electroless or electrolytic nickel base 1
5が行われ、バンプ基体11aの表面とパッケージ接続パッド4の形成予定部には無電解のニッケルを下地とする金めっき、もしくは電解半田めっきによる表面処理7、14が行われる。 5 is performed, for forming scheduled portion of the surface and the package connection pads 4 of the bump base 11a gold plating to the electroless nickel as a base or a surface treatment 7,14 by electrolytic solder plating is performed. なお、このように異なる表面処理を採用した場合、先に処理した面をマスキング材で保護した状態で次の処理を行えばよい。 In the case of adopting different surface thus treated, while protecting a surface treated previously with a masking material may be performed next processing.

【0031】その後、外形加工、各種検査を経て、半導体パッケージ用基板が完成する。 [0031] Then, trimmed, through a variety of inspection, semiconductor package substrate is completed. この半導体パッケージ用基板のチップ接続パッド9に半導体チップ12の外部接続端子13を接続して図1に示した半導体パッケージ100が完成する。 The semiconductor package substrate chip connection pads 9 by connecting the external connection terminals 13 of the semiconductor chip 12 the semiconductor package 100 shown in FIG. 1 is completed.

【0032】図3に示すように、本実施形態の半導体パッケージ100は、複数積層して一つの積層半導体パッケージ200として構成し提供することが可能である。 As shown in FIG. 3, the semiconductor package 100 of this embodiment can be provided configured as a single semiconductor package stack 200 by stacking a plurality.
バンプ6の高さは半導体チップ12の厚みより大きいので、バンプ6は上下の半導体パッケージ100どうしを導通接続するとともに、各々の半導体パッケージ100 Since the height of the bumps 6 is greater than the thickness of the semiconductor chip 12, along with the bumps 6 is conductively connected to and what the upper and lower semiconductor packages 100, each of the semiconductor package 100
の半導体チップ12とその直下の半導体パッケージ10 The semiconductor chip 12 of the semiconductor package 10 immediately below the
0との間の隙間を保証するスペーサとして機能する。 0 functions as a spacer to ensure a gap between the.

【0033】本実施形態の半導体パッケージ100におけるバンプ6は、両面銅張り材の銅箔11をエッチングにより選択的に除去することによって形成される。 The bumps 6 of the semiconductor package 100 of the present embodiment is formed by a copper foil 11 of the double-sided copper clad substrate is selectively removed by etching. このため、銅箔11の厚み精度とほぼ同等の高さ精度が保証されたバンプ6が得られる。 Therefore, the bump 6 almost equal height accuracy and thickness precision of the copper foil 11 is guaranteed can be obtained. このようにバンプ6の十分な高さ精度が保証されることによって、バンプ6の高さ寸法の決定に際し加味すべきマージンを少なくすることができ、パッケージ全体を薄くすることができる。 By thus sufficiently high accuracy of the bumps 6 is ensured, it is possible to reduce the margin to be taken into account in determining the height of the bumps 6, it is possible to reduce the overall package.

【0034】 [0034]

【実施例】次に、本発明の実施例を説明する。 EXAMPLES Next, an example of the present invention.

【0035】厚さ0.025mmの基材のバンプ面側に厚さ70μmの銅箔を、パターン面側に厚さ12μmの銅箔をつけた厚さ18μmのポリイミドフレキシブル両面銅張り板を用意し、この両面銅張り板のパターン面側の銅箔に直径0.1mmの開口をエッチングによって明け、この開口をマスクとして炭酸ガスレーザーによって、バンプ面側の銅箔の表面に達する非貫通穴を形成した。 [0035] The copper foil with a thickness of thickness of 70μm on the bump side of the base material of 0.025 mm, prepared thickness 18μm polyimide flexible double-sided copper clad laminate wearing thick copper foil 12μm on the pattern surface side , drilled openings with a diameter of 0.1mm copper foil pattern surface side of the double-sided copper clad laminate by etching, the carbon dioxide laser the opening as a mask, forming a non-through hole reaching the surface of the copper foil of the bump surface did.

【0036】次に、バンプ面全体にドライフィルムめっきレジストをラミネートし、パターン面に銅パネルめっきにより厚さ20μmのめっき層を形成し、合せて非貫通穴を銅めっきで充填後、ハーフエッチングによってパターン面のめっき層の厚さを10μmにまで薄くした。 Next, a dry film was laminated plating resist on the entire bump surface to form a plating layer having a thickness of 20μm of copper panel plating on the pattern surface, after filling the non-through holes with copper plating together by half-etching the thickness of the plating layer of the pattern surface was thinned to 10 [mu] m.

【0037】この後、バンプ面のレジストを剥がし、両面にドライフィルムエッチングレジストをラミネートし、バンプ面のレジストを全面露光するとともにパターン面側のレジストを選択的に露光し、エッチングによってパターン面に所定の導体パターンを形成した。 [0037] Thereafter, peeling off the resist bumps surface, a dry film was laminated etching resist on both surfaces, and selectively exposing the resist pattern surface with the entire surface exposing a resist bumps surface, a predetermined pattern surface by etching and the formation of conductor patterns.

【0038】続いて、エッチングレジストを剥がし、パターン面に形成された導体パターン上の必要な部分に絶縁保護のためのソルダーレジストを被覆し、続いて、両面にドライフィルムエッチングレジストをラミネートし、パターン面を全面露光後、バンプ面の銅箔をエッチングによって選択的に除去してバンプを形成した。 [0038] Subsequently, peeling the etching resist, to cover the solder resist for insulation protection necessary part on the conductor pattern formed on the pattern surface, followed by laminating a dry film etching resist on both surfaces, the pattern after flood exposure surface, to form a bump copper foil bump surface is selectively removed by etching.

【0039】次に、チップ接続パッドを形成するため、 Next, in order to form the chip connection pads,
バンプ面側から炭酸ガスレーザーによって基材に穴を明けてパターン面側の銅箔の裏面を露出させた後、バンプの表面と、チップ接続パッドおよびパッケージ接続パッドとなる両面の導体露出面に無電解ニッケル−金めっきを施した。 After the bump side by a hole in the substrate by a carbon dioxide laser to expose the rear surface of the copper foil pattern surface side, and the surface of the bumps, no the conductive exposed surface of the double-sided as the chip connection pads and package connection pads electroless nickel - plated with gold.

【0040】最後に外形加工を行って、所定形状の半導体パッケージ用基板を完成させた。 [0040] Finally, by performing outline processing, to complete the semiconductor package substrate having a predetermined shape. 上記実施例で得られた半導体パッケージ用基板のバンプ高さのバラツキを測定したところ、バラツキは原材料の銅箔とほぼ同等の精度である±7μmの範囲に収まっていた。 Measurement of the variation in the bump height of the semiconductor package substrate obtained in Examples, the variation was within the range of ± 7 [mu] m is approximately the same accuracy as the copper raw materials. また、銅張り基板全体の厚さは130±15μm、バンプとパターン面パッドとの間の高さも120±15μmの範囲に収まっていた。 Further, the total thickness of the copper-clad substrate was not fall height range of even 120 ± 15 [mu] m between 130 ± 15 [mu] m, bump and the pattern surface pad.

【0041】そして、この半導体パッケージ用基板に、 [0041] Then, in the semiconductor package substrate,
高さ35μmの金バンプを有する厚さ50μmの半導体フリップチップを異方性導電ペーストを用いて接続したところ、バンプ高さ内に半導体フリップチップが収まることを確認できた。 When the semiconductor flip chip with a thickness of 50μm with a gold bump height 35μm connected using an anisotropic conductive paste, it was confirmed that the semiconductor flip chip is within the bump height.

【0042】さらに、このようにして得られた半導体パッケージを異方性導電ペーストを用いて複数積層したところ、半導体チップとその直下の半導体パッケージとの間には約10μmの間隙を確保でき、半導体チップのクラックの発生も発見されなかった。 [0042] Furthermore, was thus a semiconductor package obtained by using the anisotropic conductive paste was stacked, it can secure a gap of approximately 10μm between the semiconductor chip and the semiconductor package immediately below the semiconductor the occurrence of cracks in the chip also has not been found.

【0043】 [0043]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
外部接続端子の高さ精度として銅箔と同等の十分な精度が保証されるので、これらの外部接続端子が半導体部品よりも厚み方向にて突出するように銅箔の厚みを最適に選定しておくことによって、半導体部品に負荷の加わらない、信頼性の高い半導体パッケージ用基板および積層半導体パッケージを提供することができる。 Since the external connection height copper foil equivalent sufficient accuracy as the accuracy of the terminals is guaranteed, these external connection terminals are optimally selected thickness of the copper foil so as to protrude in the thickness direction than the semiconductor component by placing, not applied load to the semiconductor component, it is possible to provide a substrate for a highly reliable semiconductor package and semiconductor package stack. また、製造誤差を考慮して外部接続端子の高さに加味すべきマージンが少なくて済むことから、パッケージ全体の厚みを薄くすることができる。 Moreover, since fewer be adding to the height margin of the external connection terminals in consideration of the manufacturing error, it is possible to reduce the overall thickness of package.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施形態である半導体パッケージの構成を示す断面図である。 Is a sectional view showing a structure of a semiconductor package according to an embodiment of the present invention; FIG.

【図2】図1の半導体パッケージの製造手順を示す断面図である。 2 is a cross-sectional view showing the manufacturing procedure of the semiconductor package of FIG.

【図3】図1の半導体パッケージを用いた積層半導体パッケージの構成を示す断面図である。 3 is a cross-sectional view showing a structure of a stacked semiconductor package using the semiconductor package of FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 基材 2 銅箔 3 銅めっき層 4 パッケージ接続パッド 5 絶縁保護膜 6 バンプ 8 ビア 9 チップ接続パッド 11 銅箔 12 半導体チップ 13 半導体チップの外部接続端子 15 両面銅張り板 16 穴 100 半導体パッケージ 200 積層半導体パッケージ 1 substrate 2 foil 3 copper plating layer 4 package connection pads 5 insulating protective film 6 bumps 8 via 9 chip connection pads 11 copper foil 12 semiconductor chips 13 external connection terminal 15 double-sided copper-clad laminate 16 holes 100 semiconductor package 200 of the semiconductor chip the stacked semiconductor package

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 基材とこの基材の少なくとも一方面に張りつけられた銅箔とからなる銅箔張り材と、 この銅箔張り材の前記基材の他方面に形成された導体パターンと、 前記銅箔張り材の前記銅箔を選択的に除去することによって形成され、前記導体パターンとビア接続され、かつ前記基材に搭載される半導体部品の高さよりも突出した複数の外部接続端子とを具備することを特徴とする半導体パッケージ用基板。 And 1. A base material and the copper foil-clad material comprising at least copper foil affixed on one surface of the substrate, a conductor pattern formed on the other surface of the base material of the foil coverings, the formed by the copper foil of a copper foil-clad substrate is selectively removed, the conductive pattern and the via connection, and a plurality of external connection terminals projecting than the height of the semiconductor components mounted on the substrate the semiconductor package substrate, characterized by comprising.
  2. 【請求項2】 前記基材の一方面から前記基材の他方面に形成された導体パターンへ達する穴を有する、前記基材の一方面に搭載される前記半導体部品の外部端子が前記穴内に挿入され前記導体パターンと接続可能なことを特徴とする請求項1記載の半導体パッケージ用基板。 2. A with holes in which the reach from one surface of the substrate to a conductor pattern formed on the other surface of the substrate, wherein the semiconductor component external terminals within the bore of which is mounted on one surface of the substrate inserted a semiconductor package substrate according to claim 1, wherein the connectable to the conductor pattern.
  3. 【請求項3】 前記基材の他方面に、他の半導体パッケージ用基板の外部接続端子を接合するパッドが形成されていることを特徴とする請求項1または2記載の半導体パッケージ用基板。 Wherein the other surface, a semiconductor package substrate according to claim 1 or 2, wherein the pad for bonding the external connection terminal of another semiconductor package substrate are formed of the base material.
  4. 【請求項4】 複数の外部接続端子を同一面に有する半導体パッケージ用基板の製造方法において、 基材と、この基材の少なくとも一方面に張りつけられ、 4. A method of manufacturing a substrate for a semiconductor package having a plurality of external connection terminals on the same surface, a base material, affixed to at least one surface of the substrate,
    実装される半導体部品よりも厚い銅箔とからなる銅箔張り材を用意し、この銅箔張り材の他方面に導体パターンを形成する一方、前記銅箔張り材の銅箔を選択的に除去することによって前記複数の外部接続端子を形成することを特徴とする半導体パッケージ用基板の製造方法。 Providing a copper foil-clad material composed of thick copper foil than the semiconductor components to be mounted, while forming a conductor pattern on the other surface of the foil coverings, selectively removing the copper foil of the copper foil coverings the method of manufacturing a semiconductor package substrate, characterized by forming the plurality of external connection terminals by.
JP2001120254A 2001-04-18 2001-04-18 Substrate for semiconductor package, and its manufacturing method Pending JP2002313996A (en)

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WO2004056162A1 (en) * 2002-12-18 2004-07-01 K-Tech Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
JP2008504696A (en) * 2004-06-25 2008-02-14 テッセラ,インコーポレイテッド Component having a post and pad
JP2010062430A (en) * 2008-09-05 2010-03-18 Shinko Electric Ind Co Ltd Method for producing electronic part package
US8046912B2 (en) 2003-10-06 2011-11-01 Tessera, Inc. Method of making a connection component with posts and pads
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
JP2012195612A (en) * 2012-07-09 2012-10-11 Shinko Electric Ind Co Ltd Manufacturing method of electronic component package and the electronic component package
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8531039B2 (en) 2003-12-30 2013-09-10 Tessera, Inc. Micro pin grid array with pin motion isolation
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8884448B2 (en) 2007-09-28 2014-11-11 Tessera, Inc. Flip chip interconnection with double post
JP2014229855A (en) * 2013-05-27 2014-12-08 新光電気工業株式会社 Electronic component device, and manufacturing method thereof
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WO2004056162A1 (en) * 2002-12-18 2004-07-01 K-Tech Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
US8046912B2 (en) 2003-10-06 2011-11-01 Tessera, Inc. Method of making a connection component with posts and pads
US8604348B2 (en) 2003-10-06 2013-12-10 Tessera, Inc. Method of making a connection component with posts and pads
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US8531039B2 (en) 2003-12-30 2013-09-10 Tessera, Inc. Micro pin grid array with pin motion isolation
JP2008504696A (en) * 2004-06-25 2008-02-14 テッセラ,インコーポレイテッド Component having a post and pad
US8884448B2 (en) 2007-09-28 2014-11-11 Tessera, Inc. Flip chip interconnection with double post
JP2010062430A (en) * 2008-09-05 2010-03-18 Shinko Electric Ind Co Ltd Method for producing electronic part package
US8723318B2 (en) 2010-07-08 2014-05-13 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9397063B2 (en) 2010-07-27 2016-07-19 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9030001B2 (en) 2010-07-27 2015-05-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US9496236B2 (en) 2010-12-10 2016-11-15 Tessera, Inc. Interconnect structure
JP2012195612A (en) * 2012-07-09 2012-10-11 Shinko Electric Ind Co Ltd Manufacturing method of electronic component package and the electronic component package
JP2014229855A (en) * 2013-05-27 2014-12-08 新光電気工業株式会社 Electronic component device, and manufacturing method thereof
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9818713B2 (en) 2015-07-10 2017-11-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles

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