CN215266271U - Front and back chip integrated packaging structure based on copper foil carrier plate - Google Patents
Front and back chip integrated packaging structure based on copper foil carrier plate Download PDFInfo
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- CN215266271U CN215266271U CN202121371302.1U CN202121371302U CN215266271U CN 215266271 U CN215266271 U CN 215266271U CN 202121371302 U CN202121371302 U CN 202121371302U CN 215266271 U CN215266271 U CN 215266271U
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Abstract
The utility model discloses a front and back chip integrated packaging structure based on a copper foil carrier plate, which comprises a copper foil carrier plate; the first rewiring layer and the radiating element are positioned on one side of the copper foil carrier plate, and the first rewiring layer is flush with the radiating element; the first chip is inversely arranged on the first rewiring layer, and the second chip is adhered to the radiating element through the solid crystal glue; the first plastic packaging layer wraps the first chip and the second chip, and the first plastic packaging layer is provided with a connecting hole for exposing the first rewiring layer along the thickness direction of the first plastic packaging layer; and the electric connection structure is positioned on one surface of the first plastic packaging layer, which is far away from the first rewiring layer, and is electrically connected with the first chip and the second chip respectively. The utility model discloses a positive and negative integrated packaging structure of chip, non-sensitive type chip adopt the mode of just adorning, and sensitive type chip then adopts the mode of flip-chip, avoids the laser trompil to lead to the chip to damage, just the utility model discloses be provided with radiating element, can derive the heat of chip fast, improved the radiating efficiency of chip.
Description
Technical Field
The utility model relates to an integrated circuit packaging technology field, concretely relates to positive and negative chip integrated package structure based on copper foil carrier plate.
Background
In recent years, in order to increase the mounting density of printed wiring boards and to achieve miniaturization, multilayering of printed wiring boards has been widely performed. Such multilayer printed wiring boards are used in many portable electronic devices for the purpose of weight reduction and size reduction. Thus, the multilayer printed wiring board is required to be further reduced in thickness of the interlayer insulating layer and further reduced in weight as a wiring board. However, the heat dissipation of the chip is mainly performed through the large-area substrate, and the heat dissipation surface area of the chip is also reduced due to the reduction of the package size, which requires that the heat conduction performance of the packaged chip is sufficiently good.
Generally speaking, when a fan-out package structure is manufactured, firstly, a chip needs to be plastically packaged, then, a laser hole is formed on a plastic packaging layer to expose an I/O interface of the chip, and a conductive column is formed in a through hole through electroplating to lead out the electrical property of the chip.
Therefore, it becomes very important to develop a new high heat dissipation chip packaging technology.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a positive and negative chip integrated package structure based on copper foil support plate improves the radiating efficiency of chip, solves the chip problem of scrapping that the laser trompil leads to.
To achieve the purpose, the utility model adopts the following technical proposal:
the utility model provides a positive and negative side chip integrated package structure based on copper foil carrier plate, includes:
a copper foil carrier;
the first rewiring layer and the heat dissipation element are positioned on one side of the copper foil carrier plate, and the first rewiring layer is flush with the heat dissipation element;
the first chip is inversely arranged on the first rewiring layer, and the second chip is adhered to the heat dissipation element through solid crystal glue;
the first plastic packaging layer wraps the first chip and the second chip, and the first plastic packaging layer is provided with a connecting hole for exposing the first rewiring layer along the thickness direction of the first plastic packaging layer;
and the electric connection structure is positioned on one surface of the first plastic packaging layer, which is far away from the first rewiring layer, and is respectively electrically connected with the first chip and the second chip.
As a preferred scheme of the front-back chip integrated package structure based on the copper foil carrier, the connecting holes are filled with conductive columns, one end of each conductive column is electrically connected with the first redistribution layer, and the other end of each conductive column is electrically connected with the electrical connection structure.
As a preferred scheme of the front-back chip integrated package structure based on the copper foil carrier, the electrical connection structure comprises:
the second redistribution layer is positioned on one surface, far away from the first redistribution layer, of the first plastic packaging layer and is electrically connected with the conductive column and the second chip respectively;
the second plastic packaging layer coats the second rewiring layer;
the first chip is connected with the second chip through the first redistribution layer, the conductive pillar and the second redistribution layer.
As a preferred scheme of the front-back chip integrated package structure based on the copper foil carrier, the second chip includes a bare chip, an I/O interface located in the bare chip, and a metal bump protruding from the bare chip and electrically connected to the I/O interface, the metal bump is exposed out of the first plastic package layer, and one end of the metal bump, which is far away from the bare chip, is electrically connected to the second redistribution layer.
The copper foil carrier comprises a carrier, copper layers pressed on the upper surface and the lower surface of the carrier and copper foils attached to the copper layers on one surface, and the first redistribution layer is located on the copper foils.
As a preferred scheme of the front-back chip integrated packaging structure based on the copper foil carrier plate, the metal bump is tin solder, copper solder, silver solder or gold-tin alloy solder.
As a preferred scheme of the front-back chip integrated package structure based on the copper foil carrier, the die bond adhesive is solder paste, copper paste, sintering paste, graphene, silver adhesive, non-conductive adhesive or conductive adhesive.
As a preferred scheme of the front-back chip integrated packaging structure based on the copper foil carrier plate, the heat dissipation element is a copper block.
As a preferable scheme of the front-back chip integrated package structure based on the copper foil carrier, the number of the first chips and the second chips is one or more.
As a preferable scheme of the front-back chip integrated package structure based on the copper foil carrier, the first redistribution layer and the second redistribution layer are of one-layer or multi-layer structure.
The utility model has the advantages that:
(1) the utility model discloses a positive and negative integrated packaging structure of chip, non-sensitive type chip adopt the mode and the electrical connection structural connection of just adorning, and sensitive type chip then adopts the mode and the electrical connection structural connection of flip-chip, avoids the too high chip condemned problem even of chip of laser trompil lead to the chip.
(2) The utility model discloses a second chip is glued through solid crystal and is attached on radiator element, and the heat that the chip during operation produced is through solid crystal gluey transmission to radiator element on, and radiator element can derive the heat of chip fast, has improved the radiating efficiency of chip.
(3) The utility model discloses contain two-layer plastic envelope layer, first plastic envelope layer carries out the plastic envelope to the chip, and the second plastic envelope layer carries out the plastic envelope to second rewiring layer, protects second rewiring layer, has improved packaging structure's stability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic cross-sectional view of a copper foil carrier according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of an intermediate product after manufacturing a first redistribution layer according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of an intermediate product after the heat dissipation element is implanted according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of an intermediate product after the first chip and the second chip are mounted according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of an intermediate product after manufacturing the first plastic package layer according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of an intermediate product after a second redistribution layer is fabricated according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of an intermediate product after a second plastic package layer is manufactured according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of the front-back chip integrated package structure based on a copper foil carrier after the copper foil carrier is removed.
In fig. 1 to 8:
1. a copper foil carrier; 11. a carrier plate; 12. a copper layer; 13. copper foil;
2. a first rewiring layer; 3. a heat dissipating element; 4. a first chip;
5. a second chip; 51. a bare chip; 52. an I/O interface; 53. a metal bump;
6. die bonding glue; 7. a first plastic packaging layer; 8. a conductive post; 9. a second rewiring layer; 10. a second plastic packaging layer;
100. and connecting the holes.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 7, the utility model provides a positive and negative chip integrated package structure based on copper foil carrier plate, include:
a copper foil carrier 1;
the first rewiring layer 2 and the heat dissipation element 3 are positioned on one side of the copper foil carrier plate 1, and the first rewiring layer 2 is flush with the heat dissipation element 3;
the first chip 4 and the second chip 5, the first chip 4 is upside down mounted on the first rewiring layer 2, the second chip 5 is pasted on the heat dissipation element 3 through the die bond adhesive 6;
the first plastic package layer 7 wraps the first chip 4 and the second chip 5, the first plastic package layer 7 is provided with a connecting hole 100 exposed out of the first rewiring layer 2 along the thickness direction of the first plastic package layer, and the connecting hole 100 is formed by communicating adjacent conical holes at the upper small hole end and the lower small hole end;
and the electric connection structure is positioned on one surface of the first plastic package layer 7, which is far away from the first rewiring layer 2, and is electrically connected with the first chip 4 and the second chip 5 respectively.
Specifically, the connection hole 100 is filled with the conductive pillar 8, one end of the conductive pillar 8 is electrically connected to the first redistribution layer 2, and the other end is electrically connected to the electrical connection structure.
Alternatively, the material of the conductive post 8 in the present embodiment may adopt Cu, Ag or Au.
The utility model discloses a positive and negative integrated packaging structure of chip, second chip 5 (non-sensitive chip) adopt the mode and the electric connection structure of just adorning to be connected, and first chip 4 (sensitive chip) then adopt the mode and the electric connection structure of flip-chip to be connected, and the utility model discloses a second chip 5 glues 6 attached on radiator element 3 through solid crystal, and the heat that second chip 5 during operation produced is through solid crystal glue 6 transmission to radiator element 3 on, and radiator element 3 can derive the heat of second chip 5 fast, avoids the laser trompil to lead to the too high chip of temperature of chip condemned problem even, and first chip 4 then with first rewiring layer 2 direct contact, the heat that its produced also can be derived through first rewiring layer 2, has improved the radiating efficiency of chip.
Specifically, the electrical connection structure includes:
the second redistribution layer 9 is positioned on one surface, away from the first redistribution layer 2, of the first plastic package layer 7, and the second redistribution layer 9 is electrically connected with the conductive columns 8 and the second chip 5 respectively;
the second plastic packaging layer 10, the second plastic packaging layer 10 coats the second rewiring layer 9;
the first chip 4 is connected to the second chip 5 through the first redistribution layer 2, the conductive pillar 8, and the second redistribution layer 9.
The utility model discloses contain two-layer plastic envelope layer, first plastic envelope layer 7 carries out the plastic envelope to first chip 4 and second chip 5, and second plastic envelope layer 10 then carries out the plastic envelope to second rewiring layer 9, protects second rewiring layer 9, has improved packaging structure's stability.
Specifically, the second chip 5 includes a bare chip 51, an I/O interface 52 located in the bare chip 51, and a metal bump 53 protruding from the bare chip 51 and electrically connected to the I/O interface 52, wherein the metal bump 53 is exposed out of the first molding compound layer 7, and one end of the metal bump 53 away from the bare chip 51 is electrically connected to the second redistribution layer 9.
As shown in fig. 1, the copper foil carrier 1 includes a carrier 11, copper layers 12 laminated on the upper and lower surfaces of the carrier 11, and a copper foil 13 attached to one of the copper layers 12, wherein the first redistribution layer 2 is disposed on the copper foil 13.
Alternatively, the metal bump 53 is solder, brazing material, silver solder or gold-tin alloy solder, and the metal bump 53 of the present embodiment is preferably made of brazing material as a copper pillar.
Optionally, the die attach adhesive 6 is solder paste, copper paste, sintering paste, graphene, silver paste, non-conductive adhesive or conductive adhesive, and has functions of adhesion, electrical conduction, thermal conduction, and the like.
Optionally, the first Molding Compound layer 7 and the second Molding Compound layer 10 are made of polyimide, silicone or EMC (Epoxy Molding Compound), and the EMC is preferred in this embodiment, so that the stability of the package structure of the first chip 4 and the second chip 5 can be improved, and the chip can be protected.
Optionally, the heat dissipating element 3 is a copper block.
Optionally, the number of the first chip 4 and the second chip 5 is one or more.
Alternatively, the first rewiring layer 2 and the second rewiring layer 9 are each a one-layer or multi-layer structure.
The utility model also provides a positive and negative chip integrated package structure's preparation method based on copper foil support plate, including following step:
s10, providing the copper foil carrier plate 1 and the first photosensitive dry film, and attaching the first photosensitive dry film to the copper foil carrier plate 1;
s20, forming a first patterning hole on the first photosensitive dry film through exposure and development;
s30, performing electroplating process, forming a first redistribution layer 2 in the first patterned hole, and removing the remaining first photosensitive dry film, referring to fig. 2;
s40, providing the heat dissipation element 3, and implanting the heat dissipation element 3 between the first redistribution layers 2, referring to fig. 3;
s50, providing a first chip 4 and a second chip 5, flip-chip mounting the first chip 4 on the first redistribution layer 2, and attaching the second chip 5 to the heat dissipation element 3 through the die attach adhesive 6, referring to fig. 4;
s60, carrying out plastic package on the first chip 4 and the second chip 5 to form a first plastic package layer 7, and grinding the first plastic package layer 7 to expose the metal bump 53 of the second chip 5;
s70, opening the first plastic package layer 7 to form a connection hole 100 exposing the first redistribution layer 2, referring to fig. 5;
s80, forming a seed layer (not shown in the figure) on the surface of the first molding compound layer 7 and the hole wall of the connection hole 100 by vacuum sputtering;
s90, providing a second photosensitive dry film, and attaching the second photosensitive dry film to the seed layer;
s100, forming a second graphical hole on the second photosensitive dry film through exposure and development processing;
s110, performing an electroplating process, forming a conductive pillar 8 in the connection hole 100, forming a second redistribution layer 9 in the second patterned hole, and removing the remaining second photosensitive dry film and the seed layer, referring to fig. 6;
and S120, performing plastic package on the second redistribution layer 9 to form a second plastic package layer 10, and referring to FIG. 7.
When the packaging structure is used, the copper foil carrier 1 under the first redistribution layer 2 is removed, referring to fig. 8.
Compared with a common carrier, the copper foil carrier 1 of the embodiment does not need to manufacture a seed layer on the copper foil carrier 1 when manufacturing the first redistribution layer 2, the copper foil 13 on the surface of the copper foil carrier 1 can be used as the seed layer, and the first redistribution layer 2 can be formed by directly pasting a photosensitive dry film on the copper foil carrier 1 and then carrying out exposure, development and electroplating treatment, which is simpler in process.
It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (10)
1. The utility model provides a positive and negative side chip integrated package structure based on copper foil carrier plate which characterized in that includes:
a copper foil carrier;
the first rewiring layer and the heat dissipation element are positioned on one side of the copper foil carrier plate, and the first rewiring layer is flush with the heat dissipation element;
the first chip is inversely arranged on the first rewiring layer, and the second chip is adhered to the heat dissipation element through solid crystal glue;
the first plastic packaging layer wraps the first chip and the second chip, and the first plastic packaging layer is provided with a connecting hole for exposing the first rewiring layer along the thickness direction of the first plastic packaging layer;
and the electric connection structure is positioned on one surface of the first plastic packaging layer, which is far away from the first rewiring layer, and is respectively electrically connected with the first chip and the second chip.
2. The front-back side chip integrated package structure based on a copper foil carrier according to claim 1, wherein the connecting holes are filled with conductive pillars, one end of each conductive pillar is electrically connected to the first redistribution layer, and the other end of each conductive pillar is electrically connected to the electrical connection structure.
3. The front-back side chip integrated package structure based on copper foil carrier of claim 2, wherein the electrical connection structure comprises:
the second redistribution layer is positioned on one surface, far away from the first redistribution layer, of the first plastic packaging layer and is electrically connected with the conductive column and the second chip respectively;
the second plastic packaging layer coats the second rewiring layer;
the first chip is connected with the second chip through the first redistribution layer, the conductive pillar and the second redistribution layer.
4. The integrated package structure of front and back surfaces of chip based on copper foil carrier of claim 3, wherein the second chip comprises a bare chip, an I/O interface located inside the bare chip, and a metal bump protruding from the bare chip and electrically connected to the I/O interface, the metal bump is exposed out of the first plastic-sealed layer, and one end of the metal bump away from the bare chip is electrically connected to the second redistribution layer.
5. The front-back side chip integrated package structure based on copper foil carrier of claim 4, wherein the copper foil carrier comprises a carrier, copper layers laminated on the upper and lower sides of the carrier, and a copper foil attached on one of the copper layers, and the first redistribution layer is disposed on the copper foil.
6. The front-back side chip integrated package structure based on copper foil carrier according to claim 4, wherein the metal bump is tin solder, copper solder, silver solder or gold-tin alloy solder.
7. The front-back side chip integrated package structure based on a copper foil carrier according to any one of claims 1-6, wherein the die bond paste is solder paste, copper paste, sintering paste, graphene, silver paste, non-conductive paste or conductive paste.
8. The front-back side chip integrated package structure based on copper foil carrier according to any one of claims 1-6, wherein the heat dissipation element is a copper block.
9. The front-back side chip integrated package structure based on copper foil carrier according to any one of claims 1 to 6, wherein the number of the first chip and the second chip is one or more.
10. The front-back side chip integrated package structure based on copper foil carrier according to any one of claims 3 to 6, wherein the first redistribution layer and the second redistribution layer are one or more layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121371302.1U CN215266271U (en) | 2021-06-18 | 2021-06-18 | Front and back chip integrated packaging structure based on copper foil carrier plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121371302.1U CN215266271U (en) | 2021-06-18 | 2021-06-18 | Front and back chip integrated packaging structure based on copper foil carrier plate |
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| Publication Number | Publication Date |
|---|---|
| CN215266271U true CN215266271U (en) | 2021-12-21 |
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|---|---|---|---|
| CN202121371302.1U Active CN215266271U (en) | 2021-06-18 | 2021-06-18 | Front and back chip integrated packaging structure based on copper foil carrier plate |
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| CN (1) | CN215266271U (en) |
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- 2021-06-18 CN CN202121371302.1U patent/CN215266271U/en active Active
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Effective date of registration: 20230420 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |