1378520 六、發明說明： * 【發明所屬之技術領域】 ， 纟發明係有關於半導體裝置，特別係有關於一種長銲 . 線組合方法與結構。 【先前技術】 隨著微小化及高運作速度需求的增加，在曰新月異的 電子裝置中，越來越常見到許多的多晶片堆疊封裝結 構。多晶片堆疊封裝結構可藉由將兩個或兩個以上之晶 鲁片組合在單_封裝結構巾，來提升之運作速度。因 此多曰曰片堆疊封裝結構要如何才能減少晶片間連接線 路之長度，進而降低訊號延遲以及存取時間，便是取決 於半導體晶片本身銲墊的配置結構以及銲線組合的方 式。 目前的半導體晶片通常具有兩種不同的銲墊配置結 構，一種是周圍銲墊配置架構，銲墊是形成在晶片的周 Φ 圍區域上；另一種則是中間銲墊配置架構，銲墊是形成 在晶片的中央區域上。如第！圖所示，一種習知的以周 圍銲墊配置的短銲線組合結構，晶片是正面垂直堆疊， 主要包含一第一晶片210、一第二晶片220、一電路基板 230、複數個短銲線以及一間隔物250。由於該第一晶片 210之周邊銲墊211係位於該第一晶片21〇之主動面212 的兩侧’並利用設於該第一晶片2 i 〇與該第二晶片22〇 之間的該間隔物250來提供該些短銲線240之線弧所需 的間隙，故該間隔物250的厚度必須大於該些短銲線24〇 1378520 之弧高。因此，在打線製程中毋須擔心該些短銲線240 • 會碰觸至該第一晶片210之主動面211，而造成短路之 . 問題。一般而言，該間隔物250之材料係為環氧樹脂 • (epoxy)或膠帶（tape)。然以中間銲墊配置架構的晶片進 行多晶片堆疊需要更長的鲜線，故會有更多的封裝問 題。請參閱第2圖所示，一種習知的以中間鲜塾配置的 長銲線組合結構，主要包含一第一晶片31〇、一笛-曰 片320、一電路基板330 —長銲線340以及一覆線膠層 鲁 （Film Over Wire layer，FOW)350。該長銲線組合結構係 經由打線製程，形成該長銲線340以連接該第一晶片31〇 的主動面3 12之中間銲墊311與該電路基板330之接指 331。接著，執行熱壓合製程，壓合該第二晶片32〇與該 覆線膠層350 ,以使該覆線膠層350黏合該第二晶片320 與該第一晶片310,並同時包覆住部分之該長銲線34〇β 一般而言’在設置該第二晶片320的製程中，該第二晶 φ 片3 2 0受到向下的壓力之後，會順勢壓迫到該覆線膠層 350°在壓力與熱之相互作用之下，該覆線膠層35〇會從 原本的固態逐漸轉換為膠稠態，故能順勢往下並黏合該 第一晶片310 ^雖然該覆線膠層350呈現膠稠態，但仍 會產生一定的應力，擠壓到該長銲線340，導致該長銲 線340變形或坍塌，進而直接接觸至該第一晶片31〇的 主動面312’進而發生了短路之情況。 另一種習知的以中央銲墊配置的銲線組合方法與結 構’揭示於證書號數第〗25 8 823號專利案「半導體多晶 1378520 片封裝及製造方法」所示之設計，其主要传 文货'由下晶片、 緣支撐結構、長銲線以及上晶片所組忐 樘社姑^ '取其中絕緣支 .穿結構係呈圖案狀局部配置於下晶片 勒面上，而位 於第一晶片之中間銲墊的外側’例如條狀或丘狀， 直接支撐上晶片，在上下晶片之間提供 用以 * ^ ^ A 深工間。然而， 為了能提供足夠的絕緣空間，絕緣支撐結構必須具 定高度，故使得晶片堆疊的高度増加， ^ 抖姑一Λ 热决有致地降低 =裝商度。此外，雖然藉由絕緣支撐結構能夠維持第一 晶片與第二晶片之間的黏著層之、 隙m ^ &制 又u預留足夠的間 障進订打線製程。但是無論絕緣支撐 诉να稱係从何種型態 呈現，皆僅是將第一晶片盘第二日 矛日日片^、弟一曰日片作局部性的隔離， 都不能有效地免除長銲線因覆線膠層的擠壓而變形❹ 塌’導致長銲線直接碰觸至第一晶片的主動面而發生短 路之問題。 【發明内容】 由於％知在叹置上層晶片時，覆線谬層的擠厘會造成 長銲線的變形或枬塌，本發明之主要目的係在於提供一 種長銲線組合方法輿社搂，-p# , e 兴結構可防止長銲線碰觸至下層晶 片的主動面，以防止短路之情形發生。 本發明之次一目的係在於提供一種長銲線組合方法 與結構’可以增加始晶曰u 堆疊晶片之間的黏著強度，並能有效 縮短整體的製程時間。 本發月的目的及解決其技術問題是採用以下技術方 案來實現#纟發明揭示一種長銲線組合方法主要包 1378520 含有以下步靜：提供一半導 片，在該些第一晶片的主動 植設複數個&塊組於該些中 層於該些第一晶片的主動面 該絕緣塗佈層的塗佈厚度係 以局部顯露該些凸塊組β切 些第一晶片。設置該第一晶 體晶圓，具有複數個第一晶 面上設有複數個中間銲墊。 間銲墊上。覆蓋一絕緣塗佈 並使其沾附至該些凸塊組， 不超過該些凸塊組之高度， 割該半導體晶圓，以分離該 片於一電路基板上，該電路1378520 VI. Description of the invention: * [Technical field to which the invention pertains] The invention relates to a semiconductor device, and in particular to a method and structure for long soldering. [Prior Art] With the increase in the demand for miniaturization and high operation speed, many multi-wafer stacked package structures are becoming more and more common in the ever-changing electronic devices. The multi-wafer stacked package structure can be improved in speed by combining two or more crystal pieces in a single-package structure. Therefore, how to reduce the length of the connection line between the wafers, thereby reducing the signal delay and access time, depends on the configuration of the pads of the semiconductor wafer itself and the combination of the bonding wires. Current semiconductor wafers typically have two different pad configurations, one is a surrounding pad configuration, the pads are formed on the perimeter of the wafer, and the other is an intermediate pad configuration, where the pads are formed. On the central area of the wafer. As the first! The figure shows a conventional short wire bonding structure configured by a surrounding pad. The wafer is vertically stacked on the front side, and mainly includes a first wafer 210, a second wafer 220, a circuit substrate 230, and a plurality of short bonding wires. And a spacer 250. The peripheral pads 211 of the first wafer 210 are located on both sides of the active surface 212 of the first wafer 21 and utilize the interval between the first wafer 2 i and the second wafer 22 The spacer 250 provides the clearance required for the arcs of the short bonding wires 240, so the thickness of the spacers 250 must be greater than the arc height of the short bonding wires 24〇1378520. Therefore, in the wire bonding process, there is no need to worry that the short wire 240 will touch the active surface 211 of the first wafer 210, causing a short circuit. Generally, the material of the spacer 250 is epoxy (epoxy) or tape. However, multi-wafer stacking of wafers with an intermediate pad configuration requires longer fresh lines, so there are more packaging issues. Referring to FIG. 2 , a conventional long wire bonding structure configured with a middle fresh squid mainly includes a first wafer 31 , a flute-chip 320 , a circuit substrate 330 — a long bonding wire 340 , and A Film Over Wire Layer (FOW) 350. The long wire bonding structure is formed by a wire bonding process to form the long bonding wire 340 to connect the intermediate pad 311 of the active surface 312 of the first wafer 31 与 with the finger 331 of the circuit substrate 330. Then, the thermal bonding process is performed to press the second wafer 32 and the overcoat layer 350 to bond the second adhesive layer 350 to the first wafer 310 and cover the same The portion of the long bonding wire 34 〇 β is generally 'in the process of disposing the second wafer 320, after the second crystal φ sheet 320 is subjected to downward pressure, it is pressed to the coating layer 350. ° Under the interaction of pressure and heat, the coating layer 35 逐渐 will gradually change from the original solid state to the colloidal state, so that the first wafer 310 can be pulled down and adhered to the surface, although the coating layer 350 Presenting a colloidal state, but still generating a certain stress, pressing to the long bonding wire 340, causing the long bonding wire 340 to deform or collapse, and then directly contacting the active surface 312' of the first wafer 31〇 and then occurs. Short circuit condition. Another conventional wire bonding method and structure configured by a central pad is disclosed in the design shown in the "Semiconductor Polycrystalline 1378520 Chip Package and Manufacturing Method" of the certificate No. 25 8 823. The goods 'from the lower wafer, the edge support structure, the long bond wire and the upper wafer set 忐樘 忐樘 ^ ' 其中 其中 其中 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 . . . 穿 穿 穿 穿 穿 穿 穿 穿 穿 穿 穿 穿 穿 穿 穿The outer side of the intermediate pad, for example, strip or mound, directly supports the upper wafer, and provides a deep working space between the upper and lower wafers. However, in order to provide sufficient insulation space, the insulation support structure must have a certain height, so that the height of the wafer stack is increased, and the heat is reduced to a certain degree. In addition, although the gap between the first wafer and the second wafer can be maintained by the insulating support structure, a sufficient gap can be reserved for the bonding process. However, no matter what type of insulation support v. να is derived, it is only the partial isolation of the first wafer plate, the second day of the spear, and the Japanese one, which cannot effectively eliminate the long welding. The deformation and collapse of the wire due to the extrusion of the coating of the covered wire causes the long wire to directly contact the active surface of the first wafer to cause a short circuit. SUMMARY OF THE INVENTION Since it is known that when the upper layer wafer is slanted, the squeezing of the covered wire layer causes deformation or collapse of the long wire. The main object of the present invention is to provide a long wire bonding method. -p# , e structure prevents the long wire from touching the active surface of the lower wafer to prevent short circuit. A second object of the present invention is to provide a long wire bonding method and structure which can increase the adhesion strength between the wafers of the starting wafer and can effectively shorten the overall process time. The purpose of this month and the solution to its technical problems are realized by the following technical solutions. The invention discloses a long wire bonding method. The main package 1378520 contains the following steps: providing half of the guides, active planting on the first wafers The coating thickness of the insulating coating layer on the active faces of the first wafers of the plurality of & block groups is such that the first wafers are partially exposed by the bump groups β. The first crystal wafer is disposed, and a plurality of intermediate pads are provided on the plurality of first crystal faces. On the pad. Covering an insulating coating and adhering it to the plurality of bump groups, cutting the semiconductor wafer to separate the chip on a circuit substrate without exceeding the height of the bump groups, the circuit
基板係具有複數個接指。打線形成複數個第一銲線，連 接在該第一晶片上的凸塊組與該些接指。設置一第二晶 片於該第一晶片上’其中一覆線膠層形成於該第一晶片 一該第—晶片之間，用以黏接該第一晶片上的絕緣塗佈 層與該第二晶片之背面’藉由該絕緣塗佈層的隔離在 該第一晶片的設置過程中該些第一銲線不會接觸至該第 一晶片的主動面並且該覆線膠層包覆該些第一銲線的長 度二分之一以上。本發明另揭示依照上述方法所製成之 長銲線組合結構。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之長銲線組合方法中，每一凸塊組係可選自於 打線形成之單顆結線凸塊與複數顆縱向疊置之結線凸塊 之其中之一。 在前述之長銲線組合方法中，該些第一銲線係可為逆 打形成，以使該些第一銲線的結球端設置於該些接指。 在前述之長銲線組合方法中’可另包含之步驟為：打 1378520 % 線形成複數個第二銲線，係電性連接該 路基板。 Ba5興該電 在前述之長銲線组合方法中，可另包含之步 成一封裝體於贫雷政马·形 二晶片。板以密封該第-晶片與該第 在前述之長料組合方法中，制緣塗佈層係可 與該覆線膠層黏合之非平坦表面。 、 在别述之長銲線組合方法中，在上述設置該 之步驟中，一斑s思及阳片 路基板》 β面與該電 由以上技術方案可以看出，本發明之長銲線组合 與構造’有以下優點與功效： 一、可藉由植設凸塊組與塗佈絕緣塗佈層作為其中—技 術手段，由於絕緣塗佈層的塗佈厚度係不超過凸塊 組之高度，以局部顯露凸塊組。因此，可防止在設 置上層晶片時，長銲線因覆線膠層的擠壓而變形或 坍塌，碰觸至下層晶片的主動面，以防止短路之情 形發生。 一、 可藉由塗佈絕緣塗佈層與形成覆線膠層作為其中一 技術手段，由於覆線膠層黏接第一晶片上的絕緣塗 佈層與第二晶片之背面，並且絕緣塗佈層係具有與 該覆線膠層黏合之非平坦表面，故可以增加堆疊晶 片之間的黏著強度。 二、 可藉由植設凸塊組與塗佈絕緣塗佈層作為其中一技 1378520 . 術手段，由於絕緣塗佈層的隔離，以局部顯露凸塊 . 組。在第二晶片的設置過程中，毋須擔心第二晶片 • 壓迫覆線膠層後’造成覆線膠層擠壓銲線而碰觸至 . 第一晶 的主動面’故能有效縮短整體的製程時間。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例’然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 ® 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種長銲線組合方法舉 例說明於第3圖之流程方塊圖與第4A至4J圖之元件截 φ 面示意圖。該長銲線組合方法根據第3圖，主要包含以 下步驟： 提供半導體晶圓」之步驟1、「植設凸塊組於 中間鮮塾上」之步驟2、「覆蓋絕緣塗佈層」之步驟3、「切 割半導體晶圓以分離第一晶片」之步驟4、「設置第一曰 片於電路基板上」之步驟5、「打線連接第一晶片與電路 基板」之步驟6以及 線膠層黏接第一晶片The substrate has a plurality of fingers. The wire is formed into a plurality of first bonding wires, and the bump groups connected to the first wafer and the fingers are connected. Forming a second wafer on the first wafer, wherein one of the coating layers is formed between the first wafer and the first wafer for bonding the insulating coating layer on the first wafer and the second The back surface of the wafer is separated from the active surface of the first wafer by the isolation of the insulating coating layer during the setting of the first wafer, and the coating layer covers the first surface The length of a wire is more than one-half. The present invention further discloses a long wire bonding assembly constructed in accordance with the above method. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing long wire bonding method, each of the bump groups may be selected from one of a single wire bump formed by wire bonding and a plurality of longitudinally stacked wire bumps. In the foregoing long wire bonding method, the first bonding wires may be formed in reverse, so that the ball ends of the first bonding wires are disposed on the fingers. In the foregoing long wire bonding method, the step of additionally includes: forming 1378520% of the wires to form a plurality of second bonding wires, and electrically connecting the substrate. In the above-mentioned long wire bonding method, the battery may additionally include a package in a Leyue Zhengma-shaped two-chip. The plate is used to seal the first wafer and the first long-side combination method, and the edge coating layer is a non-flat surface to which the coating layer is adhered. In the long welding wire combination method described above, in the above-mentioned step of setting the above, the β 思 思 思 思 思 思 思 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 》 The structure has the following advantages and effects: 1. It can be used as a technical means by implanting a bump set and coating an insulating coating layer, since the coating thickness of the insulating coating layer does not exceed the height of the bump group, The bump group is partially exposed. Therefore, it is possible to prevent the long bonding wire from being deformed or collapsed due to the pressing of the coating layer of the upper layer when the upper layer wafer is disposed, and the active surface of the lower layer wafer is touched to prevent the occurrence of a short circuit. 1. By coating the insulating coating layer and forming the coating layer as one of the technical means, the coating layer of the coating is adhered to the back surface of the first wafer and the back surface of the second wafer, and the coating is insulated and coated. The layer has a non-flat surface bonded to the coating layer, so that the adhesion strength between the stacked wafers can be increased. Second, by implanting a bump set and coating an insulating coating layer as one of the techniques 1378520. By means of isolation of the insulating coating layer, the bumps are partially exposed. In the process of setting up the second wafer, there is no need to worry about the second wafer. After pressing the coating layer, the coating layer is pressed and the welding line is touched. The active surface of the first crystal can effectively shorten the overall process. time. [Embodiment] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Therefore, only the components and combinations related to this case® are displayed. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some scale ratios are proportional to other related dimensions or are exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to an embodiment of the present invention, a long wire bonding method is illustrated in the flow block diagram of Fig. 3 and the element cross-sectional view of Figs. 4A to 4J. According to FIG. 3, the long bonding wire assembly method mainly includes the following steps: Step 1 of providing a semiconductor wafer, Step 2 of "planting a bump group on the middle fresh slab", and "Step of covering the insulating coating layer" 3. Step 4 of "Cutting the semiconductor wafer to separate the first wafer", Step 5 of "Setting the first wafer on the circuit substrate", Step 6 of "Wire bonding the first wafer and the circuit substrate", and bonding the adhesive layer First chip
至41圖’說明如下所示。 首先，執行步驟丨。請參閱第4A圖所示，提供—半 1378520 導體晶圓110。該半導體晶圓110係具有複數個第一晶 片111，在該些第一晶片的主動面112上設有複數個 中間銲墊113。該半導體晶圓11〇已完成所需積體電路 的製作，並以該些中間銲墊丨丨3作為對外端子。 接著，執行步驟2»請參閱第4B圖所示，植設複數 個凸塊組120於該些中間銲墊113上。在一較佳實施例 中，每一凸塊組120係可選自於打線形成之單顆結線凸 塊121(stUd bump)與複數顆縱向疊置之結線凸塊i2i之 其中之一。也就是說，在本發明中，可植設一個或一個 以上的結線凸塊121，使其相互縱向堆疊以構成該些凸 塊組120。該些凸塊組12〇選用單（多）顆結線凸塊，可與 打線形成之銲線相同材質與熔點，以達到良好接合與降 低污染。在本實施例中，該些凸塊組丨2〇之材質係可選 自金。該些凸塊組120亦可為電鍍形成之金凸塊或是表 面有鎳金之銅凸塊，相對於錫鉛凸塊更耐壓合焊接以 避免凸塊成份沾附於銲針。 執打步驟3。請參閱第4(：圖所示，覆蓋一絕緣塗佈 層13〇於該m片⑴的主動面112並使其沾附至 該些凸塊組12G，該絕緣塗佈層13()的塗佈厚度係不超 過該些凸塊組12〇之高度，以局部顯露該些凸塊組12〇。 在-實施例中’該絕緣塗佈$ 13〇在形成時係為高流動 性的液態環氧化合物。更具體地，該絕緣塗佈層可 選用既有的半導體液態黏晶材料，例如SA2〇〇,或者是 底部填充膠（imderfillh具體而論，該絕緣塗佈層13〇 = 1378520 可利用印刷方式形成在該些該些第一晶片u丨的主動面 112上，而非使用沉積方式形成。在一較佳實施例中， 上述的塗佈厚度約為該些凸塊組12〇之高度的二分 — 至四分之三，以利於後續打線製程之進行。之後，以加 熱或照射UV光方式使該絕緣塗佈層丨3 〇完全固化或局 部固化。該絕緣塗佈層130除了可以保護該些第一晶片The description of Fig. 41 is as follows. First, perform the steps 丨. Referring to Figure 4A, a semi-1378520 conductor wafer 110 is provided. The semiconductor wafer 110 has a plurality of first wafers 111, and a plurality of intermediate pads 113 are disposed on the active faces 112 of the first wafers. The semiconductor wafer 11 has been fabricated with the required integrated circuit, and the intermediate pads 3 are used as external terminals. Then, step 2 is performed as shown in FIG. 4B, and a plurality of bump sets 120 are implanted on the intermediate pads 113. In a preferred embodiment, each of the bump sets 120 is selected from one of a stud bumps 121 formed by wire bonding and a plurality of longitudinally stacked wire bumps i2i. That is, in the present invention, one or more wire bumps 121 may be implanted so as to be stacked longitudinally to each other to constitute the bump groups 120. The bump sets 12〇 use single (multiple) wire bumps, which can be the same material and melting point as the wire formed by the wire to achieve good bonding and reduce pollution. In this embodiment, the materials of the bump groups 可选2〇 are selected from gold. The bump groups 120 may also be gold bumps formed by electroplating or copper bumps with nickel gold on the surface, and are more resistant to pressure bonding than the tin-lead bumps to prevent the bump components from adhering to the solder pins. Go to step 3. Referring to FIG. 4 (:, an insulating coating layer 13 is covered on the active surface 112 of the m piece (1) and adhered to the bump groups 12G, and the insulating coating layer 13 is coated. The thickness of the cloth does not exceed the height of the plurality of bump groups 12 , to partially expose the bump groups 12 〇. In the embodiment, the insulating coating is 13 〇 is a high-flow liquid ring when formed. Oxygen compound. More specifically, the insulating coating layer may be selected from an existing semiconductor liquid crystalline material such as SA2 crucible or an underfill (imderfillh, specifically, the insulating coating layer 13〇= 1378520 is available The printing method is formed on the active surfaces 112 of the first wafers, instead of using a deposition method. In a preferred embodiment, the coating thickness is about the height of the bumps 12〇. Two points - three-quarters to facilitate the subsequent wire-drawing process. Thereafter, the insulating coating layer is fully cured or partially cured by heating or irradiating UV light. The insulating coating layer 130 can protect the First wafer
111的主動面112不受後續打線形成銲線之碰傷，也能 進一步固定該些凸塊組120的形狀，不受打線時銲針的 壓迫而過度變形。此外，該絕緣塗佈& m亦有增加與 覆線膠層黏著強度之作用。由於該絕緣塗佈層130是形 成於晶圓上’而非形成於單顆已分離之晶4，在膜厚與 均勻度的控制會更趨理想。 執行步驟4。請參閱第4D圖所示，藉由一刀具 切割該半導體晶圓no,以分離該些第一晶片lu。在本 實施例中，在分離後，每一第一晶片U1的主動面u2 係完全被該絕緣塗佈層130所覆蓋，僅顯露出該凸塊組 120。 執行步驟5。請參閱第4E圖所示，設置該第一晶片 111於一電路基板140上，該電路基板14〇係具有複數 個接指141、142 〇在此步驟中，一黏晶層116係黏合該 第一晶片111之背面II4與該電路基板14〇之上表面。 在本實施例中，該些接指14卜142係可設置於該電路基 板1 4 0之同一側邊。 執行步驟6。請參閱第4F圖所示，打線形成複數個 10 1378520 第一銲線150，連接在該第一晶片ill上的凸塊組120 與該些接指141。由一銲針152提供該些第一銲線150。 該些第一銲線150係可為金線。在本實施例中，該些第 一銲線150係可為逆打形成，以使該些第一銲線150的 結球端151設置於該些接指141» 執行步驟7。請參閱第4G圖所示，設置一第二晶片 160於該第一晶片111上，其中一覆線膠層170(Film〇ver Wire，FOW)形成於該第一晶片U1與該第二晶片16〇之 間，用以黏接該第一晶片111上的絕緣塗佈層丨3 〇與該 第一晶片160之背面161(如第4H圖所示）。藉由該絕緣 塗佈層130的隔離，在該第二晶片16〇的設置過程中該 些第一銲線150不會接觸至該第一晶片U1的主動面 112,並且該覆線膠層17〇包覆該些第一銲線15〇的長度 二分之一以上。在一實施例中，該覆線膠層17〇係為預 型片（preform)，此步驟可藉由熱壓合的方式，將該第二 晶片160與該覆線膠層ι7〇同時壓合至該第一晶片m, 並使得該覆線膠層170緊密地黏合於該絕緣塗佈層13〇 上。在另一實施例中’該覆線膠層170係可在晶圓等級 預先形成於該第二晶片16〇之背面161。較佳地，該絕 緣塗佈層130係可具有一與該覆線膠層170黏合之非平 坦表面’故可以增加堆疊晶片之間的黏著強度。詳細而 言，該覆線膠層170係可具有多階段熱固化特性，一旦 受熱之後，會從固態轉而呈現膠稠態，並保持一定的形 狀，故不會任意流動而汙染至周邊。在一較佳實施例中， 1378520 該第二晶片160與該第一晶片j i i係可為相同尺寸大小。 • 更進一步地，如第41圖所示，再進行一打線製程， • 以打線形成複數個第二銲線180,其係電性連接該第二 晶片160與該電路基板140 ^可由該銲針152提供該些 第二銲線18〇。具體而言，在該第二晶片之中間銲墊^ 上係設有複數個凸塊164,並藉由該些第二銲線ΐ8〇連 接該些凸塊164與該電路基板ι41之該些接指ι42。在 本實施例中’同樣係以逆打方式形成該些第二銲線 • 18〇’故該些第二銲線180的結球端181設置於該電路基 板14〇之該些接指142。最後，如第〇圖所示，可再形 成一封裝體19〇於該電路基板14〇上，以密封該第一晶 片111肖該第二晶4 160，~完成本發明之長鲜線組合 結構。更進-步地，該封裝體190還包覆了該第一鲜線 150與該第二銲線180，並完全覆蓋該電路基板14〇之該 些接指141、i 42。該封裝體！ 9〇可由模封形成。 • 在本發明令，利用植設該些凸塊組與塗佈該絕緣塗佈 層作為其中一技術手段，當塗佈該絕緣塗佈層13〇時， 該絕緣塗佈層130之厚度係不超過該些凸塊組12〇之高 度，故使得該些凸塊組120能局部顯露於該絕緣塗佈層 130之外。因此，能夠防止在進行熱壓合以設置該第二 曰曰片16〇時，該第一銲線150因為受到該覆線膠層170 的擠壓而變形或坍塌，導致該第-銲線150碰觸至該第 一晶片111的主動面112,以避免短路之情形發生。此 外，該絕緣塗佈層13〇係完全覆蓋於該些第一晶片iu 12 1378520 \ 的主動面112上，以完全免除外界碰觸或汙染至該主動 • 面112之問題，故在該第二晶片160的設置過程中，毋 • 須擔，^會發生上述短路之情形，能有效地縮短整體的製 程時間。此外，本發明不局限於兩個晶片之堆疊，可利 用第/晶片與第二晶片的上述堆疊方法往上堆疊更多晶 片。 本發明還揭示使用前述方法所製成之長銲線組合結 構舉例說明於第4J圖。該長鲜線組合結構主要包含一第 • 一晶片111、複數個凸塊組12〇、一絕緣塗佈層130、一 電路基板140、複數個第一銲線150、一覆線膠層170 以及一第二晶片160。在該第一晶片lu的主動面u2 上設有複數個中間銲墊113。該些凸塊組12〇係植設於 該些中間銲墊113上。在本實施例中，每一凸塊組120 係可選自於打線形成之單顆結線凸塊121與複數顆縱向 疊置之結線凸塊121之其中之一。該絕緣塗佈層13〇係 _ 覆蓋該第一晶片111的主動面112並沾附至該些打線形 成之凸塊組1 2 0，該絕緣塗佈層13 0的塗佈厚度係不超 過該些凸塊組120之高度，以局部顯露該些凸塊組120。 該電路基板140係具有複數個接指141、142，該第一晶 片111係設置於該電路基板140上。在本實施例中，玎 另包含一黏晶層11 6，係黏合該第一晶片111之背面11 4 與該電路基扳140。該些打線形成之第一銲線150係速 接在該第一晶片111上的凸塊組120與該些接指341。 在本實施例中，該些第一銲線150係可為逆打形成，以 13 1378*520 使該些第一銲線150的結球端351設置於該些接指 . 341。該覆線膠層170係形成於該第一晶片111上的絕緣 _ 塗佈層130上。在本實施例中，該絕緣塗佈層130係可 具有一與該覆線膠層170黏合之非平坦表面。該第二晶 片160係設置於該第一晶片^上，其中該覆線膠層170 黏接該第一晶片111上的絕緣塗佈層130與該第二晶片 160之背面161，藉由該絕緣塗佈層13〇的隔離，該些第 一銲線150不會接觸至該第一晶片m的主動面112並 •且該覆線膠層170包覆該些第一銲線15〇的長度二分之 一以上。在本實施例中，可另包含複數個第二銲線18〇, 係電性連接該第二晶片16〇與該電路基板14〇 ^並且， 可另包含一封裝體190，係形成於該電路基板14〇上， 以密封該第一晶片m與該第二晶片16〇。更進一步地， 該封裝體190係完全包覆該第一銲線15〇、該第二銲線 180與該些接指141、142。 • 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然、本發明已以較佳實施例 揭露如i，然而並非用以限定本發明，任何熟悉本項技 術者’在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾’均仍屬於本發明的技 内。 【圖式簡單說明】 第i圖：為習知的一種短銲線組合結構之截面示意圖。 第2圖：為習知的一種長銲線組合結構之截面示意圖。 14 1378520 第3圖：依據本發明之一具體實施例的長銲線組合方法 之流程方塊圖。 第4A至4J圖：依據本發明之一具體實施例的長銲線組 合方法之元件截面示意圖。 [ 主 要. 元件符 號 說 明 步 驟 1 提供 半 導 體 晶 圓 步 驟 2 植設 凸 塊 組 於 中 間 銲 墊上 步 驟 3 覆蓋 絕 緣 塗 佈 層 步 驟 4 切割 半 導 體 晶 圓 以 分 離第 一晶 片 步 驟 5 設置 第 一 晶 片 於 電 路 基板 上 步 驟 6 打線連接 第 一 晶 片 與 電路 基板 步 驟 7 設置 第 二 晶 片 於 第 一 晶片 上以 覆線膠層黏接 第一 晶 片 110 半導體晶圓 111 第一晶片 112 主動面 113 中間銲墊 114 背面 115 刀具 116 黏晶層 120 凸塊組 121 結線凸塊 130 絕緣塗佈層 140 電路基板 141 接指 142 接指 150 第一銲線 151 結球端 152 銲針 160 第二晶片 161 背面 162 主動面 163 中間銲墊 164 凸塊 170 覆線膠層 180 第二銲線 181 結球端 15 1378520 190 封 裝 體 210 第 一 晶 片 211 周 220 第 二 晶 片 221 周 230 電 路 基 板 240 短 銲 線 3 10 第 一 晶 片 311 中 320 第 二 晶 片 321 中 330 電 路 基 板 340 長 銲 線 邊銲 墊 212 主 動 面 邊 銲 塾 222 背 面 231 接 指 250 間 隔 物 間 銲 墊 3 12 主 動 面 間 銲 墊 322 背 面 331 接指 350 覆 線 膠層The active surface 112 of the 111 is not damaged by the subsequent bonding of the bonding wires, and the shape of the bumps 120 can be further fixed without being excessively deformed by the pressing of the soldering pins during wire bonding. In addition, the insulating coating & m also has an effect of increasing the adhesion strength to the coating layer. Since the insulating coating layer 130 is formed on the wafer instead of being formed on a single separated crystal 4, the control of film thickness and uniformity is more desirable. Go to step 4. Referring to FIG. 4D, the semiconductor wafer no is cut by a cutter to separate the first wafers lu. In the present embodiment, after the separation, the active surface u2 of each of the first wafers U1 is completely covered by the insulating coating layer 130, and only the bump group 120 is exposed. Go to step 5. Referring to FIG. 4E, the first wafer 111 is disposed on a circuit substrate 140. The circuit substrate 14 has a plurality of fingers 141, 142. In this step, a die layer 116 is bonded to the first substrate. The back surface II4 of a wafer 111 and the upper surface of the circuit substrate 14 are. In this embodiment, the fingers 14 can be disposed on the same side of the circuit board 140. Go to step 6. Referring to FIG. 4F, the wire is formed into a plurality of 10 1378520 first bonding wires 150, and the bump group 120 and the connecting fingers 141 are connected to the first wafer ill. The first bonding wires 150 are provided by a soldering pin 152. The first bonding wires 150 may be gold wires. In this embodiment, the first bonding wires 150 may be formed by reverse striking so that the ball end 151 of the first bonding wires 150 is disposed on the fingers 141». Referring to FIG. 4G, a second wafer 160 is disposed on the first wafer 111, and a film overlay layer 170 is formed on the first wafer U1 and the second wafer 16. Between the crucibles, the insulating coating layer 丨3 上 on the first wafer 111 and the back surface 161 of the first wafer 160 are bonded (as shown in FIG. 4H). By the isolation of the insulating coating layer 130, the first bonding wires 150 do not contact the active surface 112 of the first wafer U1 during the setting process of the second wafer 16 , and the coating layer 17 The bismuth covers the length of the first bonding wires 15〇 by more than one-half. In one embodiment, the coating layer 17 is a preform, and the second wafer 160 and the coating layer ι7 are simultaneously pressed by thermocompression bonding. To the first wafer m, and the bonding layer 170 is tightly bonded to the insulating coating layer 13A. In another embodiment, the blanketant layer 170 can be preformed on the back side 161 of the second wafer 16 at the wafer level. Preferably, the insulating coating layer 130 can have a non-flat surface bonded to the coating layer 170 so that the adhesion between the stacked wafers can be increased. In detail, the wire coating layer 170 can have a multi-stage heat curing property, and once heated, it will turn from a solid state to a gel-like state and maintain a certain shape, so that it does not flow to the periphery without any flow. In a preferred embodiment, 1378520 the second wafer 160 and the first wafer j i can be the same size. Further, as shown in FIG. 41, a one-line process is further performed, and a plurality of second bonding wires 180 are formed by wire bonding, and electrically connected to the second wafer 160 and the circuit substrate 140. 152 provides the second bonding wires 18〇. Specifically, a plurality of bumps 164 are disposed on the middle pad of the second wafer, and the bumps 164 and the circuit board ι41 are connected by the second bonding wires ΐ8〇. Refers to ι42. In the present embodiment, the second bonding wires 18 are formed in a reverse manner. Therefore, the ball end 181 of the second bonding wires 180 is disposed on the fingers 142 of the circuit board 14 . Finally, as shown in the figure, a package body 19 can be formed on the circuit substrate 14 to seal the first wafer 111 to form the second crystal 4 160, and the long-line composite structure of the present invention is completed. . Further, the package 190 further covers the first fresh wire 150 and the second bonding wire 180, and completely covers the fingers 141, i 42 of the circuit substrate 14 . The package! 9〇 can be formed by molding. In the present invention, by using the set of bumps and coating the insulating coating layer as one of the technical means, when the insulating coating layer 13 is coated, the thickness of the insulating coating layer 130 is not The height of the bump groups 12 超过 is exceeded, so that the bump groups 120 can be partially exposed outside the insulating coating layer 130 . Therefore, it is possible to prevent the first bonding wire 150 from being deformed or collapsed by being pressed by the coating tape layer 170 when the thermal pressing is performed to set the second die 16 , resulting in the first bonding wire 150 . The active surface 112 of the first wafer 111 is touched to avoid a short circuit. In addition, the insulating coating layer 13 is completely covered on the active surface 112 of the first wafer iu 12 1378520 \ to completely avoid the problem of contact or contamination to the active surface 112, so in the second During the setting process of the wafer 160, the above-mentioned short circuit occurs, and the overall process time can be effectively shortened. Further, the present invention is not limited to the stacking of two wafers, and more wafers may be stacked upward by the above-described stacking method of the /wafer and the second wafer. The present invention also discloses that the long wire bond assembly fabricated using the foregoing method is illustrated in Figure 4J. The long-line combination structure mainly includes a first wafer 111, a plurality of bump groups 12A, an insulating coating layer 130, a circuit substrate 140, a plurality of first bonding wires 150, a coating layer 170, and A second wafer 160. A plurality of intermediate pads 113 are disposed on the active surface u2 of the first wafer lu. The bump groups 12 are implanted on the intermediate pads 113. In this embodiment, each of the bump sets 120 is selected from one of a single wire bump 121 formed by wire bonding and a plurality of longitudinally stacked wire bumps 121. The insulating coating layer 13 covers the active surface 112 of the first wafer 111 and is adhered to the bump group 120 formed by the wire bonding. The coating thickness of the insulating coating layer 130 is not more than The height of the bump groups 120 is such that the bump groups 120 are partially exposed. The circuit board 140 has a plurality of fingers 141, 142, and the first wafer 111 is disposed on the circuit board 140. In this embodiment, 玎 further includes a die layer 116, which is bonded to the back surface 11 4 of the first wafer 111 and the circuit board 140. The first bonding wires 150 formed by the wires are fastened to the bump group 120 on the first wafer 111 and the fingers 341. In this embodiment, the first bonding wires 150 may be formed by reverse striking, and the ball end 351 of the first bonding wires 150 is disposed on the fingers 341 at 13 1378*520. The wire coating layer 170 is formed on the insulating coating layer 130 on the first wafer 111. In this embodiment, the insulating coating layer 130 may have a non-flat surface bonded to the wire coating layer 170. The second wafer 160 is disposed on the first wafer, wherein the coating layer 170 is adhered to the insulating coating layer 130 on the first wafer 111 and the back surface 161 of the second wafer 160 by the insulation. Isolation of the coating layer 13〇, the first bonding wires 150 do not contact the active surface 112 of the first wafer m and the coating layer 170 covers the length of the first bonding wires 15〇 More than one. In this embodiment, a plurality of second bonding wires 18 〇 are electrically connected to the second chip 16 〇 and the circuit substrate 14 , and may further include a package 190 formed on the circuit. The substrate 14 is turned on to seal the first wafer m and the second wafer 16A. Further, the package 190 completely covers the first bonding wire 15 , the second bonding wire 180 and the connecting fingers 141 , 142 . The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. However, the present invention has been disclosed in the preferred embodiments, but is not intended to limit the present invention. Any simple modifications, equivalent changes, and modifications made by the skilled artisan within the technical scope of the present invention are still within the skill of the present invention. [Simple description of the drawing] Fig. i is a schematic cross-sectional view of a conventional short wire bonding structure. Figure 2 is a schematic cross-sectional view of a conventional long wire bond assembly. 14 1378520 FIG. 3 is a flow block diagram of a long bond wire assembly method in accordance with an embodiment of the present invention. 4A to 4J are cross-sectional views showing the components of the long wire bonding method according to an embodiment of the present invention. [Main. Component Symbol Description Step 1 Provide Semiconductor Wafer Step 2 Implant Bulb Set on Intermediate Pad Step 3 Cover Insulation Coating Layer Step 4 Cut Semiconductor Wafer to Separate First Wafer Step 5 Set First Wafer on Circuit Board Step 6: Connect the first wafer to the circuit substrate. Step 7: Place the second wafer on the first wafer and bond the first wafer with the coating layer. The first wafer 112. The first wafer 112. The active surface 113. The intermediate pad 114. Tool 116 Bonded layer 120 Bump set 121 Junction bump 130 Insulation coating layer 140 Circuit board 141 Finger 142 Finger 150 First wire 151 Ball end 152 Solder pin 160 Second wafer 161 Back 162 Active surface 163 Intermediate welding Pad 164 bump 170 wire coating layer 180 second bonding wire 181 ball end 15 1378520 190 package 210 first wafer 211 circumference 220 second wafer 221 circumference 230 circuit substrate 240 short bonding wire 3 10 in the first wafer 311 320 second wafer 321 330 circuit board base plate 340 long wire edge pad 212 main surface edge welding 222 222 back surface 231 finger 250 spacers pad 3 12 main surface pad 322 back 331 finger 350 line glue layer
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