201112339 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於-種長銲 線組合方法與結構。 【先前技術】 隨著微小化及高運作速度需求的增加，在日新月異的 電子裝置中，《來越常見到許多的多晶片堆叠封裝結 構多晶片堆疊封裝結構可藉由將兩個或兩個以上之曰曰 片組合在單—封裝結财，來提㈣統之運作速度。^ 此多曰曰片堆疊封裝結構要如何才能減少晶片間連接線 路=長纟’進而降低訊號延遲以及存取時間便是取決 於半導體晶片本身銲墊的配置結構以及銲線組合的方 目前的半導體晶片通常具有兩種不同的銲墊配置結 構，一種是周圍銲墊配置架構，銲塾是形成在晶片的周 圍區域上；另一種則是中間銲墊配置架構，銲墊是形成 在晶片#中央區域上。如第i圖所示，一種習知的以周 圍銲墊配置的短銲線組合結構，晶片是正面垂直堆疊， 主要包含一第一晶片210、一第二晶片22〇、一電路基板 23〇複數個短銲線以及一間隔物25〇β由於該第一晶片 210之周邊銲墊211係位於該第一晶片21〇之主動面212 的兩側，並利用設於該第一晶片210與該第二晶片22〇 之間的該間隔物250來提供該些短銲線240之線弧所需 的間隙，故該間隔物250的厚度必須大於該些短銲線24〇 201112339 之弧高。因此，在打線製程中毋須擔心該些短銲線240 會碰觸至該第一晶片210之主動面211，而造成短路之 問題。一般而言，該間隔物250之材料係為環氧樹脂 (epoxy)或膠帶（tape)。然以中間銲墊配置架構的晶片進 行多晶片堆疊需要更長的銲線，故會有更多的封裝問 題。請參閱第2圖所示，一種習知的以中間銲墊配置的 長鲜線組合結構’主要包含一第一晶片310、一第二晶 片320、一電路基板330 —長銲線340以及一覆線膠層 (Film Over Wire layer，FOW)350。該長銲線組合結構係 經由打線製程’形成該長銲線340以連接該第一晶片31〇 的主動面312之中間銲墊311與該電路基板330之接指 33 1。接著，執行熱壓合製程，壓合該第二晶片32〇與該 覆線膠層350,以使該覆線膠層350黏合該第二晶片32〇 與該第一晶片310,並同時包覆住部分之該長銲線34〇。 一般而言，在設置該第二晶片320的製程中，該第二晶 片320受到向下的壓力之後，會順勢壓迫到該覆線膠層 3 50 °在壓力與熱之相互作用之下，該覆線膠層35〇會從 原本的固態逐漸轉換為膠稠態，故能順勢往下並黏合該 第一晶片3 1〇。雖然該覆線膠層35〇呈現膠稠態，但仍 會產生一疋的應力，擠壓到該長銲線340，導致該長銲 線340變形或坍塌，進而直接接觸至該第一晶片31〇的 主動面312,進而發生了短路之情況。 另一種習知的以中央銲墊配置的銲線組合方法與結 構，揭示於證書號數第1258823號專利案「半導體多晶 201112339 片封裝及製造方法」所示之設計，其主要係由下晶片、 絕緣支揮結構、長銲線以及上晶片所組成，其中絕緣支 撐結構係呈圖案狀局部配置於下晶片之主動面上，而位 於第-晶片之中間銲墊的外側，例如條狀或丘狀，用以 直接支撐上晶片，在上下晶片之間提供絕緣空間。然而， 為了能提供足夠的絕緣空間，絕緣支撐結構必須具有一 定高度，故使得晶月堆疊的高度增加，無法有效地降低 =裝高度。此外，雖然藉由絕緣切結構能夠維持第一 晶片與第二晶片之間的黏著層之厚度，以預留足夠的間 隙進行打線製帛。但是無論絕緣支撑結構係以何種型態 呈現，皆僅是將第-晶片與第二晶片作局部性的隔離， 都不能有效地免除長銲線因覆線膠層的擠壓而變形或坍 塌’導致長鲜、線直接碰觸至第-晶片&主動面而發生短 路之問題。 【發明内容】 由於習知在設置上層晶片時，覆線膠層的擠壓會造成 長銲線的變形或坍塌，本發明之主要目的係在於提供一 種長銲線組合方法與結構，可防止長銲線碰觸至下層晶 片的主動面’以防止短路之情形發生。 本發月之-人一目的係在於提供一種長銲線組合方法 與結構’可以增加堆疊晶片之間的黏著強度，並能有效 縮短整體的製程時間。 本發月的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示—種長銲線組合方法主要包 201112339 含有以下步驟：提供一半導體晶圓，具有複數個第一晶 片 在該些第一晶片的主動面上設有複數個中間錄塾。 植設複數個凸塊組於該些中間銲墊上。覆蓋一絕緣塗佈 層於該些第一晶片的主動面並使其沾附至該些凸塊組， 該絕緣塗佈層的塗佈厚度係不超過該些凸塊組之高度， 以局部顯露該些凸塊組。切割該半導體晶圓，以分離該 二第曰曰片。設置該第一晶片於一電路基板上，該電路 基板係具有複數個接指。打線形成複數個第一銲線，連 接在該第—晶片上的凸塊組與該些接指。設置一第二晶 片於該第—晶片上，其中一覆線膠層形成於該第一晶片 與該第一晶片之間，用以黏接該第一晶片上的絕緣塗佈 層輿· —a υ . °弟一0曰片之背面，藉由該絕緣塗佈層的隔離，在 該第一晶片的設置過程中該些第一銲線不會接觸至該第 一晶片的主動面並且該覆線膠層包覆該些第一銲線的長 又一 77之—以上。本發明另揭示依照上述方法所製成之 長銲線組合結構。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在别述之長銲線組合方法中，每一凸塊組係可選自於 打線形成之單顆結線凸塊與複數顆縱向疊置之結線凸塊 之其中之一。 在則述之長銲線組合方法中，該些第一銲線係可為逆 打形成’以使該些第一銲線的結球端設置於該些接指。 在則述之長銲線組合方法中，可另包含之步驟為：打 201112339 - 線形成複數個第二銲線，係電性連接該第二晶片與該電 路基板。 在前述之長銲線組合方法中’可另包含之步驟為：形 成一封裝體於該電路基板上，以密封該第一晶片與該第 二晶片9 在前述之長銲線組合方法中’該絕緣塗佈層係可具有 一與該覆線膠層黏合之非平坦表面。 在前述之長銲線組合方法中，在上述設置該第一晶片 籲之步驟中，-黏晶層係可黏合該第一晶片之背面與該電 路基板》 由以上技術方案可以看出，本發明之長銲線組合方法 與構造’有以下優點與功效： 一、 可藉由植設凸塊組與塗佈絕緣塗佈層作為其中一技 術手段，由於絕緣塗佈層的塗佈厚度係不超過凸塊 組之高度，以局部顯露凸塊組。因此，可防止在設 • 置上層晶片時，長銲線因覆線膠層的擠壓而變形或 掛知碰觸至下層晶片的主動面’以防止短路之情 形發生。 二、 可藉由塗佈絕緣塗佈層與形成覆線膠層作為其中一 技術手段，由於覆線膠層黏接第一晶片上的絕緣塗 佈層與第二晶片之背面，並且絕緣塗佈層係具有與 該覆線膠層黏合之非平坦表面，故可以增加堆疊晶 片之間的黏著強度。 三、 可藉由植設凸塊組與塗佈絕緣塗佈層作為其中一技 7 201112339 術手段，由於絕緣塗佈層的隔離，以局部顯露凸塊 組。在第二晶片的設置過程中，毋須擔心第二晶片 壓迫覆線膠層後’造成覆線膠層擠壓銲線而碰觸至 第一晶片的主動面’故能有效縮短整體的製程時間。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來説明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種長銲線組合方法舉 例說明於第3圖之流程方塊圖與第4A至4J圖之元件截 面不意圖。該長銲線組合方法根據第3圖，主要包含以 下步驟.提供半導體晶圓」之步驟i、「植設凸塊組於 中間銲墊上」之步驟2、「覆蓋絕緣塗佈層」之步驟3、「切 創半導體晶圓以分離第-晶片」t步驟4、「設置第一晶 片於電路基板上」之步驟5、「打線連接第-晶>{與電路 基板」《步驟6以及「設置第二晶片於第-晶片上以覆 線夥層黏接第一晶片」之步驟7，詳細步驟請參閱第4A 至41圖，說明如下所示。 首先執行步驟請參閱第4A圖所示，提供一半 201112339 導體晶圓110。該半導體晶圓110係具有複數個第一晶 片111，在該些第一晶片111的主動面112上設有複數個 中間鲜整U3。該半導體晶圓110已完成所需積體電路 的製作’並以該些中間銲墊113作為對外端子。 接著，執行步驟2。請參閱第43圖所示，植設複數 個凸塊組120於該些中間輝塾113上。在一較佳實施例 中，每-凸塊組12〇係可選自於打線形成之單顆結線凸 塊121(stud bump)與複數顆縱向疊置之結線.凸塊ι2ΐ之 其中之一。也就是說，在本發明中，可植設一個或一個 以上的結線凸塊121，使其相互縱向堆疊以構成該些凸 塊組12〇。該些凸塊組120選用單（多）顆結線凸塊，可與 打線形成之辉線相同材質與炫點，以達到良好接合與降 低污染。在本實施例中，該些凸塊組12〇之材質係可選 自金。該些凸塊組120亦可為電鍍形成之金凸塊或是表 面有鎳金之銅凸塊，相對於錫鉛凸塊更耐壓合焊接以 避免凸塊成份沾附於銲針。 執行步驟3。請參閱第4C圖所干，爱$ 圃所不，覆蓋一絕緣塗佈 層130於該些第一晶片ill的主叙 叩主動面112並使其沾附至 該些凸塊組120，該絕緣塗佈屉从a & 坤層13〇的塗佈厚度係不超 過該些凸塊組120之高度’以局部顯露該些凸塊組120。 在一實施例中，該絕緣塗佈層】m * 押增130在形成時係為高流動 性的液態環氡化合物。更具體地’該絕緣塗佈層η" 選用既有的半導體液態黏晶#料，例# SA2QQ m 底部填充膠(Underfill)。具體而論，該絕緣塗佈層13〇: 201112339 可利用印刷方式形成在該些該些第一晶片n丨的主動面 11 2上，而非使用沉積方式形成。在一較佳實施例中， 上述的塗佈厚度約為該些凸塊組i 2〇之高度的二分之一 至四分之三，以利於後續打線製程之進行。之後，以加 熱或照射UV光方式使該絕緣塗佈層i 3 〇完全固化或局 部固化。該絕緣塗佈層13 〇除了可以保護該些第一晶片 1 Π的主動面112不受後續打線形成銲線之碰傷，也能 $ 進一步固定該些凸塊組丨2〇的形狀’不受打線時銲針的 壓逍而過度變形。此外，該絕緣塗佈層13〇亦有增加與 覆線膠層黏著強度之作用。由於該絕緣塗佈層13〇是形 成於晶圓上，而非形成於單顆已分離之晶片，在膜厚與 均勻度的控制會更趨理想。 執行步驟4。請參閱第4D圖所示，藉由一刀具U5 切割該半導體晶圓11 〇，以分離該些第一晶片111。在本 實施例中，在分離後，每一第一晶片u j的主動面u 2 • 係完全被該絕緣塗佈層130所覆蓋，僅顯霧出該凸塊組 120 〇 執行步驟5。請參閱第4E圖所示，設置該第一晶片 111於一電路基板14〇上該電路基板14〇係具有複數 個接指141、142。在此步驟中，一黏晶層116係黏合該 第一晶片111之背面114與該電路基板140之上表面。 在本實施例中，該些接指141、142係可設置於該電路基 板140之同-側邊。 執行步驟6。請參閱第4F圖所示，打線形成複數個 10 201112339 第一銲線150，連接在該第一晶片111上的凸塊組120 與該些接指141。由一銲針152提供該些第一銲線150。 該些第一銲線150係可為金線。在本實施例中，該些第 一銲線150係可為逆打形成，以使該些第一銲線15〇的 結球端151設置於該些接指141。 執行步驟7。請參閱第4G圖所示，設置一第二晶片 160於該第一晶片111上，其中一覆線膠層17〇(Film 〇ver Wire，FOW)形成於該第一晶片U1與該第二晶片wo之 間，用以黏接該第一晶片i丨丨上的絕緣塗佈層丨3 〇與該 第二晶片160之背面161(如第4H圖所示）。藉由該絕緣 塗佈層130的隔離，在該第二晶片16〇的設置過程中該 些第一鲜線150不會接觸至該第一晶片m的主動面 112’並且該覆線膠層17〇包覆該些第一銲線15〇的長度 言，該覆線膠層 170係可具有多階段熱固化特性，一旦201112339 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a method and structure for combining a long solder wire. [Prior Art] With the increasing demand for miniaturization and high operating speed, in the ever-changing electronic devices, "the more common multi-wafer stacked package structure multi-wafer stacked package structure can be made by two or more The combination of the chips in the single-package is rich, to mention the operating speed of the (four) system. ^ How to reduce the inter-chip connection line = long 纟 ' and thus reduce the signal delay and access time depends on the configuration of the pad of the semiconductor chip itself and the current semiconductor of the wire bond combination The wafer usually has two different pad configurations, one is a surrounding pad configuration, the pad is formed on the surrounding area of the wafer, and the other is an intermediate pad configuration, the pad is formed in the central area of the wafer # on. As shown in FIG. 1 , a conventional short wire bonding structure configured by surrounding pads, the wafer is vertically stacked on the front side, and mainly includes a first wafer 210 , a second wafer 22 , and a circuit substrate 23 . a short bonding wire and a spacer 25 〇β, since the peripheral pad 211 of the first wafer 210 is located on both sides of the active surface 212 of the first wafer 21, and is disposed on the first wafer 210 and the first The spacers 250 between the two wafers 22 are provided to provide the gaps required for the arcs of the short bonding wires 240, so the thickness of the spacers 250 must be greater than the arc height of the short bonding wires 24〇201112339. Therefore, in the wire bonding process, there is no need to worry that the short bonding wires 240 will touch the active surface 211 of the first wafer 210, causing a short circuit problem. Generally, the material of the spacer 250 is epoxy or tape. However, multi-wafer stacking of wafers with an intermediate pad configuration requires longer bond wires, so there are more packaging issues. Referring to FIG. 2, a conventional long-line combination structure configured by an intermediate pad mainly includes a first wafer 310, a second wafer 320, a circuit substrate 330, a long bonding wire 340, and a cover. Film Over Wire Layer (FOW) 350. The long bond wire assembly structure forms the long bond wire 340 via a wire bonding process to connect the intermediate pad 311 of the active surface 312 of the first wafer 31A with the finger 33 1 of the circuit substrate 330. Then, the thermal bonding process is performed to press the second wafer 32 and the overcoat layer 350 to bond the second adhesive layer 350 to the first wafer 310 and simultaneously coated. The long part of the wire is 34 住. In general, in the process of disposing the second wafer 320, after the second wafer 320 is subjected to the downward pressure, it will be pressed to the overlying adhesive layer 3 50 ° under the interaction of pressure and heat. The layer of the overlying glue layer 35 逐渐 gradually changes from the original solid state to the colloidal state, so that the first wafer 3 1 〇 can be placed down and down. Although the coating layer 35 is in a colloidal state, a stress is generated, which is pressed to the long bonding wire 340, causing the long bonding wire 340 to deform or collapse, thereby directly contacting the first wafer 31. The active surface 312 causes a short circuit. Another conventional wire bonding method and structure configured by a central pad is disclosed in the design of the "Semiconductor Polycrystalline 201112339 Package and Manufacturing Method" of the certificate No. 1258823, which is mainly composed of a lower wafer. The insulating support structure is formed by a pattern partially localized on the active surface of the lower wafer and on the outer side of the intermediate pad of the first wafer, such as a strip or a mound. The shape is used to directly support the upper wafer to provide an insulating space between the upper and lower wafers. However, in order to provide sufficient insulation space, the insulating support structure must have a certain height, so that the height of the crystal moon stack is increased, and the height of the mounting cannot be effectively reduced. Further, although the thickness of the adhesive layer between the first wafer and the second wafer can be maintained by the insulating cut structure, a sufficient gap is reserved for wire bonding. However, no matter what type of insulation support structure is present, only the first wafer and the second wafer are partially isolated, which cannot effectively eliminate the deformation or collapse of the long solder wire due to the extrusion of the coating layer. 'Causes the problem of a short circuit caused by the long fresh line and the line directly touching the first wafer & active surface. SUMMARY OF THE INVENTION It is conventionally known that when the upper layer wafer is disposed, the extrusion of the coating layer may cause deformation or collapse of the long bonding wire. The main object of the present invention is to provide a long bonding wire combination method and structure, which can prevent long The bonding wire touches the active surface of the underlying wafer to prevent a short circuit from occurring. The purpose of this month is to provide a long wire bonding method and structure that can increase the adhesion strength between stacked wafers and effectively shorten the overall process time. The purpose of this month and the resolution of its technical problems are achieved using the following technical solutions. The invention discloses a long wire bonding method main package 201112339 comprising the steps of: providing a semiconductor wafer having a plurality of first wafers; and a plurality of intermediate recordings on the active faces of the first wafers. A plurality of bumps are implanted on the intermediate pads. Covering an active coating layer on the active surface of the first wafer and adhering it to the bump groups, the coating thickness of the insulating coating layer not exceeding the height of the bump groups to be partially exposed The set of bumps. The semiconductor wafer is diced to separate the two dies. The first wafer is disposed on a circuit substrate having a plurality of fingers. The wire is formed into a plurality of first bonding wires, and the bump groups connected to the first wafer and the fingers are connected. A second wafer is disposed on the first wafer, wherein a coating layer is formed between the first wafer and the first wafer for bonding the insulating coating layer on the first wafer. The back surface of the 一 曰 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The glue layer covers the length of the first bonding wires and further 77. The present invention further discloses a long wire bonding assembly constructed in accordance with the above method. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the long wire bonding method described above, each of the bump groups may be selected from one of a single wire bump formed by wire bonding and a plurality of longitudinally stacked wire bumps. In the long wire bonding method described above, the first bonding wires may be reversely formed so that the ball ends of the first bonding wires are disposed on the fingers. In the long wire bonding method described above, the method further comprises the steps of: forming a plurality of second bonding wires by using the 201112339-line, electrically connecting the second wafer and the circuit substrate. In the foregoing method of assembling a long bonding wire, the method may further include: forming a package on the circuit substrate to seal the first wafer and the second wafer 9 in the foregoing method of combining the long bonding wires. The insulating coating layer may have a non-flat surface bonded to the wire coating layer. In the foregoing method of assembling a long bonding wire, in the step of disposing the first wafer, the bonding layer can bond the back surface of the first wafer and the circuit substrate. As can be seen from the above technical solution, the present invention The long bonding wire combination method and structure 'has the following advantages and effects: 1. By using a bump set and a coating insulating coating layer as one of the technical means, since the coating thickness of the insulating coating layer is not more than The height of the bump set to partially expose the bump set. Therefore, it is possible to prevent the long bonding wire from being deformed by the extrusion of the coating layer or by touching the active surface of the lower wafer when the upper wafer is disposed to prevent the occurrence of a short circuit. 2. The insulating coating layer and the surface of the second wafer can be adhered by the coating of the insulating coating layer and the coating of the coating layer, and the coating is adhered to the back surface of the second wafer. The layer has a non-flat surface bonded to the coating layer, so that the adhesion strength between the stacked wafers can be increased. Third, the bump set and the coated insulating coating layer can be used as one of the techniques. According to the isolation of the insulating coating layer, the bump group is partially exposed. In the process of disposing the second wafer, there is no need to worry that after the second wafer presses the overlying adhesive layer, causing the overlying adhesive layer to press the bonding wire and touch the active surface of the first wafer, the overall process time can be effectively shortened. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with an embodiment of the present invention, a long wire bonding method is illustrated by way of example in the block diagram of FIG. 3 and the components of Figs. 4A through 4J. According to FIG. 3, the long bonding wire assembly method mainly includes the following steps: step i of providing a semiconductor wafer, step 2 of "planting a bump group on the intermediate pad", and step 3 of "covering the insulating coating layer" Step 4: "Cut the semiconductor wafer to separate the first wafer", step 4, "Set the first wafer on the circuit board", "Wire bonding connection - Crystal" and "circuit substrate", "Step 6 and "Setting Step 7 of bonding the first wafer to the second wafer on the first wafer is performed on the first wafer. For detailed steps, please refer to Figures 4A to 41, and the description is as follows. First perform the steps shown in Figure 4A, providing half of the 201112339 conductor wafer 110. The semiconductor wafer 110 has a plurality of first wafers 111, and a plurality of intermediate refreshing U3 are disposed on the active surfaces 112 of the first wafers 111. The semiconductor wafer 110 has completed the fabrication of the desired integrated circuit and uses the intermediate pads 113 as external terminals. Then, go to step 2. Referring to Figure 43, a plurality of bump sets 120 are implanted on the intermediate illuminators 113. In a preferred embodiment, each of the bump sets 12 can be selected from one of the stud bumps formed by the wire bonding and one of the plurality of longitudinally stacked clad wires. That is, in the present invention, one or more wire bumps 121 may be implanted so as to be stacked longitudinally to each other to constitute the bump groups 12A. The bump sets 120 are selected from single (multiple) knot bumps, which can be the same material and dazzle as the glow lines formed by the wires to achieve good bonding and reduce pollution. In this embodiment, the materials of the bump groups 12 are selected from gold. The bump groups 120 may also be gold bumps formed by electroplating or copper bumps with nickel gold on the surface, and are more resistant to pressure bonding than the tin-lead bumps to prevent the bump components from adhering to the solder pins. Go to step 3. Referring to FIG. 4C, the insulating coating layer 130 is coated on the main active surface 112 of the first wafer ill and adhered to the bump groups 120. The insulation is The coating thickness of the coating tray from the a & Kun layer 13 不 does not exceed the height of the bump groups 120 to partially expose the bump groups 120. In one embodiment, the insulating coating layer m* is increased by 130 when formed to be a highly fluid liquid cyclic ruthenium compound. More specifically, the insulating coating layer η" uses an existing semiconductor liquid adhesive material, such as # SA2QQ m Underfill. Specifically, the insulating coating layer 13: 201112339 can be formed by printing on the active faces 11 2 of the first wafers n, instead of using a deposition method. In a preferred embodiment, the coating thickness is about one-half to three-quarters of the height of the bump groups i 2 , to facilitate the subsequent wire bonding process. Thereafter, the insulating coating layer i 3 〇 is completely cured or partially cured by heating or irradiating with UV light. The insulating coating layer 13 can protect the active surface 112 of the first wafer 1 不受 from being damaged by subsequent wire bonding, and can further fix the shape of the bumps ' 2 ' The welding pin is over-deformed when the wire is wound. In addition, the insulating coating layer 13 has an effect of increasing the adhesion strength to the coating layer. Since the insulating coating layer 13 is formed on the wafer instead of being formed on a single separated wafer, the control of film thickness and uniformity is more desirable. Go to step 4. Referring to FIG. 4D, the semiconductor wafer 11 is diced by a cutter U5 to separate the first wafers 111. In this embodiment, after the separation, the active surface u 2 of each first wafer u j is completely covered by the insulating coating layer 130, and only the bump group 120 is fogged out. Step 5 is performed. Referring to FIG. 4E, the first wafer 111 is disposed on a circuit substrate 14 and has a plurality of fingers 141, 142. In this step, a die layer 116 is bonded to the back surface 114 of the first wafer 111 and the upper surface of the circuit substrate 140. In this embodiment, the fingers 141, 142 can be disposed on the same side of the circuit board 140. Go to step 6. Referring to FIG. 4F, the wires are formed into a plurality of 10 201112339 first bonding wires 150, and the bump groups 120 connected to the first wafer 111 and the fingers 141 are connected. The first bonding wires 150 are provided by a soldering pin 152. The first bonding wires 150 may be gold wires. In this embodiment, the first bonding wires 150 may be formed by reverse striking so that the ball ends 151 of the first bonding wires 15A are disposed on the fingers 141. Go to step 7. Referring to FIG. 4G, a second wafer 160 is disposed on the first wafer 111, and a first varnish layer of germanium (FW) is formed on the first wafer U1 and the second wafer. And between the insulating coating layer 丨3 丨丨 on the first wafer 丨丨 and the back surface 161 of the second wafer 160 (as shown in FIG. 4H). By the isolation of the insulating coating layer 130, the first fresh lines 150 do not contact the active surface 112' of the first wafer m during the setting process of the second wafer 16 and the coating layer 17长度 covering the length of the first bonding wires 15〇, the coating tape layer 170 can have multi-stage heat curing characteristics, once
至周邊。在一較佳實施例中， —分之以上。在一實施例中，該覆線膠層17〇係為預 型片（pref〇rm)，此步驟可藉由熱壓合的方式，將該第二 晶片160與該覆線膠層17〇同時壓合至該第一晶片ui， 並使得該覆線膠層17〇緊密地黏合於該絕緣塗佈層 上。在另—實施例中，該覆線膠層170係可在晶圓等級 預先形成於該第二晶片16〇之背面。較佳地該絕 緣塗佈層130係可具有-與該覆線膠層170黏合之非平 I表面故可以增加堆疊晶片之間的黏著強度。詳細而 201112339 • . 該第二晶片1 60與該第一晶片111係可為相同尺寸大小。 更進一步地，如第41圖所示，再進行一打線製程， 以打線形成複數個第二銲線180，其係電性連接該第二 晶片160與該電路基板140。可由該銲針152提供該些 第二銲線180。具體而言，在該第二晶片之中間銲墊163 上係設有複數個凸塊164，並藉由該些第二銲線18〇連 接該些凸塊164與該電路基板141之該些接指ι42〇在 本實施例中，同樣係以逆打方式形成該些第二鲜線 籲 180’故該些第二銲線180的結球端181設置於該電路基 板140之該些接指142。最後，如第4J圖所示，可再形 成一封裝體190於該電路基板140上，以密封該第一晶 片111與該第二晶片160’即完成本發明之長銲線組合 結構。更進一步地’該封裝體190還包覆了該第一銲線 150與該第二銲線18〇’並完全覆蓋該電路基板14〇之該 些接指141、142。該封裝體190可由模封形成。 φ 在本發明中’利用植設該些凸塊組與塗佈該絕緣塗佈 層作為其中一技術手段，當塗佈該絕緣塗佈層13〇時， 該絕緣塗佈層130之厚度係不超過該些凸塊組12〇之高 度，故使得該些凸塊組120能局部顯露於該絕緣塗佈層 130之外。因此，能夠防止在進行熱壓合以設置該第二 晶片160時，該第一銲線150因為受到該覆線膠層17〇 的擠壓而變形或坍塌，導致該第一銲線15〇碰觸至該第 一晶片111的主動面112,以避免短路之情形發生。此 外，該絕緣塗佈層130係完全覆蓋於該些第一晶片^ 12 201112339 的主動面112上，以完全免除外界碰觸或汙染至該主動 面112之問題，故在該第二晶片16〇的設置過程中，毋 須擔心會發生上述短路之情形，能有效地縮短整體的製 程時間。此外’本發明不局限於兩個晶片之堆疊，可利 用第一晶片與第二晶片的上述堆疊方法往上堆疊更多晶 片。 日日 本發明還揭示使用前述方法所製成之長銲線組合結 • 構舉例說明於第4J圖。該長銲線組合結構主要包含一= 一晶片in、複數個凸塊組120、一絕緣塗佈層13〇、一 電路基板140、複數個第—銲線15〇、一覆線膠層17〇 以及一第二晶片160。在該第一晶片U1的主動面ιΐ2 上設有複數個中間銲墊113«該些凸塊組12〇係植設於 該些中間銲墊113上。在本實施例中，每一凸塊組12〇 係可選自於打線形成之單顆結線凸塊121與複數顆縱向 疊置之結線凸塊1 2 1之其中之一。該絕緣塗佈層〗3 〇係 % 覆蓋該第一晶片111的主動面112並沾附至該些打線形 成之凸塊組120’該絕緣塗佈層130的塗佈厚度係不超 過該些凸塊組120之高度’以局部顯露該些凸塊組12〇。 該電路基板140係具有複數個接指141、142，該第一晶 片111係設置於該電路基板140上。在本實施例中，可 另包含一黏晶層11 6 ’係黏合該第一晶片1 i丨之背面1 i 4 與該電路基板140。該些打線形成之第一銲線150係連 接在該第一晶片111上的凸塊組120與該些接指341。 在本實施例中’該些第一銲線1 50係可為逆打形成，以 201112339 • 使該些第一緙線150的結球端351設置於該些接指 341°該覆線膠層170係形成於該第一晶片111上的絕緣 塗佈層1 3 0上。在本實施例中’該絕緣塗佈層丨3 〇係可 具有一與該覆線膠層170黏合之非平坦表面。該第二晶 片160係設置於該第一晶片m上，其中該覆線膠層17〇 黏接該第一晶片111上的絕緣塗佈層13 0與該第二晶片 160之背面161，藉由該絕緣塗佈層130的隔離，該些第 鲁一鲜線150不會接觸至該第一晶片m的主動面112並 且該覆線膠層170包覆該些第一銲線150的長度二分之 一以上。在本實施例中，可另包含複數個第二銲線18〇， 係電性連接該第二晶片160與該電路基板14〇。並且， 可另包含一封裝體190,係形成於該電路基板14〇上， 以密封該第一晶片U1與該第二晶片16〇。更進一步地， 該封裝體190係完全包覆該第一銲線15〇、該第二銲線 180與該些接指141、142。 % 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者，在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖·為習知的一種短銲線組合結構之截面示意圖。 第2圖·為I知的一種長銲線組合結構之截面示意圖。 14 201112339 第3圖：依據本發明之一具體實施例的長銲線組合方法 之流程方塊圖。 第4A至4J圖：依據本發明之一具體實施例的長銲線組 合方法之元件截面示意圖。To the surroundings. In a preferred embodiment, the above is above. In one embodiment, the coating layer 17 is a pre-flake, and the second wafer 160 and the coating layer 17 can be simultaneously pressed by thermocompression. The first wafer ui is pressed to the first wafer ui, and the bonding tape layer 17 is tightly bonded to the insulating coating layer. In another embodiment, the blanketant layer 170 can be preformed on the back side of the second wafer 16 at the wafer level. Preferably, the insulating coating layer 130 can have a non-flat I surface bonded to the coating layer 170 to increase the adhesion between the stacked wafers. In detail, 201112339 • The second wafer 160 and the first wafer 111 may be the same size. Further, as shown in Fig. 41, a wire bonding process is further performed to form a plurality of second bonding wires 180 by wire bonding, which electrically connects the second wafer 160 and the circuit substrate 140. The second bonding wires 180 may be provided by the solder pins 152. Specifically, a plurality of bumps 164 are disposed on the middle pad 163 of the second wafer, and the bumps 164 and the circuit board 141 are connected by the second bonding wires 18? In the present embodiment, the second ball line 180 is formed in the reverse manner, so that the ball end 181 of the second wire 180 is disposed on the fingers 142 of the circuit substrate 140. Finally, as shown in FIG. 4J, a package body 190 can be formed on the circuit substrate 140 to seal the first wafer 111 and the second wafer 160' to complete the long bond wire assembly structure of the present invention. Further, the package body 190 further covers the first bonding wire 150 and the second bonding wire 18A and completely covers the connecting fingers 141, 142 of the circuit substrate 14. The package 190 can be formed by molding. In the present invention, the use of the plurality of bump groups and the application of the insulating coating layer as one of the technical means, when the insulating coating layer 13 is coated, the thickness of the insulating coating layer 130 is not The height of the bump groups 12 超过 is exceeded, so that the bump groups 120 can be partially exposed outside the insulating coating layer 130 . Therefore, it is possible to prevent the first bonding wire 150 from being deformed or collapsed due to the pressing of the coating tape layer 17 when the second wafer 160 is thermally pressed, thereby causing the first bonding wire 15 to bump. The active surface 112 of the first wafer 111 is touched to avoid a short circuit condition. In addition, the insulating coating layer 130 completely covers the active surface 112 of the first wafers 12 201112339 to completely avoid the problem of contact or contamination to the active surface 112, so the second wafer 16〇 During the setting process, there is no need to worry about the above short circuit, which can effectively shorten the overall process time. Further, the present invention is not limited to the stacking of two wafers, and more wafers may be stacked upward by the above-described stacking method of the first wafer and the second wafer. The present invention also discloses a long wire bond assembly fabricated using the foregoing method as illustrated in Figure 4J. The long wire bonding structure mainly comprises a = one wafer in, a plurality of bump groups 120, an insulating coating layer 13A, a circuit substrate 140, a plurality of first bonding wires 15〇, and a coating tape layer 17〇 And a second wafer 160. A plurality of intermediate pads 113 are disposed on the active surface ι2 of the first wafer U1. The bump groups 12 are implanted on the intermediate pads 113. In this embodiment, each of the bump sets 12 can be selected from one of a single wire bump 121 formed by wire bonding and a plurality of longitudinally stacked wire bumps 1 2 1 . The insulating coating layer 3 covers the active surface 112 of the first wafer 111 and is adhered to the plurality of wire-formed bump groups 120'. The coating thickness of the insulating coating layer 130 does not exceed the convex portions. The height of the block set 120 is to partially expose the bump sets 12A. The circuit board 140 has a plurality of fingers 141, 142, and the first wafer 111 is disposed on the circuit board 140. In this embodiment, a die layer 11 6 ′ is further bonded to the back surface 1 i 4 of the first wafer 1 i and the circuit substrate 140 . The first bonding wires 150 formed by the wires are connected to the bump group 120 on the first wafer 111 and the fingers 341. In the present embodiment, the first bonding wires 150 may be formed by reverse striking to 201112339. The ball ends 351 of the first wires 150 are disposed on the fingers 341°. The insulating coating layer 130 is formed on the first wafer 111. In the present embodiment, the insulating coating layer 3 may have a non-flat surface bonded to the coating layer 170. The second wafer 160 is disposed on the first wafer m, wherein the wire coating layer 17 is adhered to the insulating coating layer 130 on the first wafer 111 and the back surface 161 of the second wafer 160. The isolation of the insulating coating layer 130 does not contact the active surface 112 of the first wafer m and the length of the first bonding wire 150 is covered by the coating layer 170. More than one. In this embodiment, a plurality of second bonding wires 18A may be further included to electrically connect the second wafer 160 and the circuit substrate 14A. Moreover, a package body 190 may be further formed on the circuit substrate 14 to seal the first wafer U1 and the second wafer 16A. Further, the package 190 completely covers the first bonding wire 15 , the second bonding wire 180 and the connecting fingers 141 , 142 . The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed above by way of preferred embodiments, it is not intended to limit the invention, It is still within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications made by the skilled artisan without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional short wire bonding structure. Fig. 2 is a schematic cross-sectional view showing a long wire bonding structure known as I. 14 201112339 FIG. 3 is a flow block diagram of a long wire bonding method in accordance with an embodiment of the present invention. 4A to 4J are cross-sectional views showing the components of the long wire bonding method according to an embodiment of the present invention.
[ 主 要元件符 號 說 明 ] 步 驟 1 提供 半 導 體 晶 圓 步 驟 2 植 設 凸 塊 組 於 中 間 銲 墊 上 步 驟 3 覆 蓋 絕 緣 塗 佈 層 步 驟 4 切 割 半 導 體 晶 圓 以 分 離 第一晶 片 步 驟 5 設 置 第 一 晶 片 於 電 路 基板上 步 驟 6 打 線連接 第 一 晶 片 與 電 路基板 步 驟 7 設 置 第 二 晶 片 於 第 一 晶 片上以 覆線膠層黏接 第 一 晶 片 110 半 導 體 晶 圓 111 第 — 晶 片 112 主 動面 113 中 間 銲墊 114 背 面 115 刀 具 116 黏 晶 層 120 凸 塊 組 121 結 線凸塊 130 絕 緣 塗 佈 層 140 電 路 基板 141 接 指 142 接指 150 第 — 銲 線 151 結 球端 152 銲 針 160 第 -- 晶 片 161 背 面 162 主 動 面 163 中 間 銲 墊 164 凸 塊 170 覆 線 膠 層 180 第 _ . 銲 線 181 結 球端 15 201112339 190 封 裝 體 210 第 一 晶片 211 周 邊 銲 塾 212 主 動 面 220 第 二 晶片 221 周 邊 銲 墊 222 背 面 230 電 路 基板 231 接 指 240 短 銲 線 250 間 隔 物 3 10 第 一 晶片 3 11 中 間 銲 墊 3 12 主 動 面 320 第 二 晶片 321 中 間 銲 墊 322 背 面 330 電 路 基板 331 接指 340 長 銲 線 350 覆 線 膠層 16[Main component symbol description] Step 1 Provide semiconductor wafer Step 2 Implant bump set on the intermediate pad Step 3 Cover the insulating coating layer Step 4 Cut the semiconductor wafer to separate the first wafer Step 5 Set the first wafer on the circuit substrate Step 6: Connect the first wafer to the circuit substrate. Step 7: Place the second wafer on the first wafer and bond the first wafer with the coating layer. The semiconductor wafer 111. The wafer 112 active surface 113 The intermediate pad 114 The back surface 115 Tool 116 Bonding layer 120 Bump group 121 Bonding bump 130 Insulation coating layer 140 Circuit board 141 Finger 142 Finger 150 First - Bonding wire 151 Ball end 152 Solder pin 160 No. - Wafer 161 Back 162 Active surface 163 Middle Pad 164 Bump 170 Overlay Layer 180 _ . Bond 181 Ball End 15 201112339 190 Package 210 First Wafer 211 Peripheral Weld 212 Moving surface 220 second wafer 221 peripheral pad 222 back surface 230 circuit board 231 finger 240 short wire 250 spacer 3 10 first wafer 3 11 intermediate pad 3 12 active surface 320 second wafer 321 intermediate pad 322 back 330 Circuit board 331 finger 340 long bonding wire 350 wire coating layer 16