1310596 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種晶片封裝結構，特別是一種可重新分配 ’ (redistribution)之晶片封裝結構及其製法。 【先前技術】 晶圓級封裝是在晶片切割前，就進行封裝、測試的作業， 晶圓級封裴整合前、後段製程，沒有打金線作業、沒有基板、 • 沒有介電材料（underfill)，部分前段製程技術的再延伸。與傳 統晶片封裝方式不同之處，在於晶圓級封裝技術可先在整片晶 圓上進行封裝和測試之後，再切割成個別的晶粒。 曰曰圓級晶片尺寸封裝採用晶粒與印刷電路板直接連結，打 金線之製程已然省略，I/O墊就不需放置在四週；若能運用整 個晶片面積做為I/O之區域，則不僅提高可容納的I/C)數，印 刷電路板的製作密度亦可獲得有效之改善。重新分配技術的基 本概念即是運用金屬薄層形成導通路線，將位於晶片四週之連 Φ 接點’重新分佈於所要之位置。 【發明内容】 ^本發明目的之一係提供一種晶片封裝結構，係可取代晶圓 級封叢（wafer level package，WLP)之重新分配功能，其成本較 低且製程較晶圓級封裝簡單。 乂本發明目的之一係知供一種晶片封裝結構，除具有可重新 分配功能外，亦可簡易的製作晶片堆疊封裝結構。 ，為了達到上述目的，本發明一實施例之一種晶片封裝結 構，包括：一基板；一第一晶片，係黏著設置於基板上且第一 5 1310596 晶片之一主動面具有複數個焊墊環繞設置於主動面周緣上；一 黏著層，係設置於第一晶片之主動面中央區域上；一印刷電路 板，係設置於黏著層上；複數個焊線，係電性連接第一晶片上 之焊墊至印刷電路板上且電性連接印刷電路板與基板；以及一 封膠體，係設置於基板上用以密封第一晶片、印刷電路板與焊 線。 本發明又一實施例之一種晶片封裝結構，包括：一基板； 一第一晶片，係黏著設置於基板上且第一晶片之一主動面具有 複數個焊墊環繞周緣設置於主動面上；一黏著層，係設置於第 一晶片之主動面中央區域上；一圖案化金屬電路層，係設置於 黏著層上；複數個焊線，係電性連接第一晶片上之焊墊至金屬 電路層上且電性連接圖案化金屬電路層與基板；以及一封膠 體，係設置於基板上用以密封第一晶片、圖案化金屬電路層與 焊線。 【實施方式】 第1圖所示為根據本發明晶片封裝結構一實施例之剖面 示意圖，此晶片封裝結構包括一基板10，此基板10係可為一 印刷電路板或是一導線架。一第一晶片20黏著設置於基板10 上。其中，第一晶片20之一主動面具有複數個焊墊22環繞設 置於主動面之周緣。一黏著層30設置於第一晶片20主動面之 中央區域上。一印刷電路板40設置於黏著層30上。複數個焊 線50用以電性連接第一晶片20上焊墊22至印刷電路板40 上，且電性連接印刷電路板40與基板10。一封膠體80設置 於基板10上用以密封包覆第一晶片20、印刷電路板40與焊 線50。 接續上述說明，第2A圖、第2B圖與第2C圖為根據第1 6 1310596 【所；：:：裝結構製法之剖面示意圖。如第Μ圖所示，首 上。接著阳於利用一黏著層（圖上未示）固設於基板1〇 並於主動面中動面周緣設置複數個焊藝22， 程:咖電路板4。。之後，如第-圖所示，利 ί f St緙線5G電性連接第―晶^上焊墊22至印 开 板4°與基板丨。。最後， 線50曰η密封包覆第一晶片20、印刷電路板40與焊 線5〇凡成晶片封裝結構，如第！圖所示。 面示Ϊ園圖所不為根據本發明晶片封裝結構另-實施例之剖 此芙‘ 10 r於本實施例中，&晶片封裝結構包括一基板10， 心就可為一印刷電路板或是-導線架。-第-晶片20 ^^"。”，第-晶片⑼之-主動面具有複 一曰：%繞3又置於主動面之周緣。-黏著層3〇設置於第 於魅签廢動面^中央區域上一圖案化金屬電路層42設置 上。⑨數料線5G m㈣接第-晶片2〇上 ί=;Γ金屬電路層42上，且電性連接圖案化金屬電 霜二一曰…10。一封膠體80言史置於基板10上用以密封包 覆弟-日日片2G、圖案化金屬電路層42與焊線5〇。 圖所接?上述說明’第4Α圖、第4Β圖與第4C圖為根據第3 ，所^片封裝結構製法之剖面示意圖。如第4a圖所示，首 ^弟一晶片20係利—黏著層（圖上未示）固設於基板10上。 接者’於第-晶片20之主動面周緣設置複數個焊塾22，並於 ^動面中央區域設置黏著層3〇。接著，參照第4bk，利用一 ΜΡ程序於黏著層3G上轉印圖案化金屬電路層42。之後，移 =體6〇’如第4C圖所示，並利用一打線程序以焊線50電 性連接苐-晶片20上輝墊22至圖案化金屬電路層仏上，且 電性連接圖案化金屬電路層42與基板1Q。最後，形成一封膠 7 !310596 此基板〗。係可為一印刷電路板；是—裝導:構7 黏著設置於基板1〇上。其中，曰、水条。一第一曰曰片20 數個焊塾22環繞設置於主動 ^ 2G之—主動面具有複 —晶片加主動面之中央區Τ。:黏著層3。設置於第 30上且具有複數個谭墊72 f —日日片7。設置於黏著層 案化金屬電路層42設置於勒著第層—3^^之主動面上。一圖 緣。複數個焊線5〇 _ 7環繞第二晶片70周 二曰L=:2:圖案化金屬電路層42上，且電性連接 10上用以密封勺：第22曰至基板10。一封膠體80設置於基板 上用以在封包覆弟一晶片2〇、第二晶片7〇與焊線5〇。 接續上述說明，第6A圖、第6β圖、1310596 IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure, and more particularly to a redistribution chip package structure and a method of fabricating the same. [Prior Art] Wafer-level packaging is the process of packaging and testing before wafer cutting. Wafer-level packaging is integrated before and after the process, without gold wire work, no substrate, • no dielectric material (underfill) , the extension of some of the front-end process technology. The difference from the traditional chip packaging method is that the wafer level packaging technology can be packaged and tested on the entire wafer before being cut into individual dies. The round wafer size package uses a die to directly connect to the printed circuit board. The process of gold wire has been omitted, and the I/O pad does not need to be placed around. If the entire wafer area can be used as the I/O area, Not only is the number of I/Cs that can be accommodated increased, but the production density of the printed circuit board can also be effectively improved. The basic concept of the redistribution technique is to use a thin layer of metal to form a via line that redistributes the Φ junctions around the wafer at the desired location. SUMMARY OF THE INVENTION One object of the present invention is to provide a chip package structure that can replace the wafer level package (WLP) redistribution function, which is low in cost and simple in process-to-wafer level packaging. One of the objects of the present invention is to provide a wafer package structure which, in addition to having a redistributable function, can be easily fabricated into a wafer stack package structure. In order to achieve the above object, a chip package structure according to an embodiment of the invention includes: a substrate; a first wafer adhered to the substrate and one of the first 5 1310596 wafers has a plurality of pads arranged around the active surface On the periphery of the active surface; an adhesive layer is disposed on the central area of the active surface of the first wafer; a printed circuit board is disposed on the adhesive layer; and a plurality of bonding wires are electrically connected to the solder on the first wafer Padded to the printed circuit board and electrically connected to the printed circuit board and the substrate; and a glue body disposed on the substrate for sealing the first wafer, the printed circuit board and the bonding wire. A chip package structure according to another embodiment of the present invention includes: a substrate; a first wafer is adhesively disposed on the substrate; and an active surface of the first wafer has a plurality of pads disposed on the active surface around the periphery; The adhesive layer is disposed on a central area of the active surface of the first wafer; a patterned metal circuit layer is disposed on the adhesive layer; and the plurality of bonding wires are electrically connected to the solder pad on the first wafer to the metal circuit layer And electrically connecting the patterned metal circuit layer and the substrate; and a gel is disposed on the substrate for sealing the first wafer, the patterned metal circuit layer and the bonding wire. [Embodiment] FIG. 1 is a cross-sectional view showing an embodiment of a chip package structure according to the present invention. The chip package structure includes a substrate 10, which may be a printed circuit board or a lead frame. A first wafer 20 is adhesively disposed on the substrate 10. The active surface of one of the first wafers 20 has a plurality of pads 22 disposed around the periphery of the active surface. An adhesive layer 30 is disposed on a central region of the active surface of the first wafer 20. A printed circuit board 40 is disposed on the adhesive layer 30. A plurality of soldering wires 50 are electrically connected to the pads 22 on the first wafer 20 to the printed circuit board 40, and electrically connected to the printed circuit board 40 and the substrate 10. A glue body 80 is disposed on the substrate 10 for sealingly covering the first wafer 20, the printed circuit board 40, and the bonding wires 50. Following the above description, FIG. 2A, FIG. 2B, and FIG. 2C are schematic cross-sectional views of the method according to the first embodiment of the method. As shown in the figure, first. Then, the anode is fixed on the substrate 1 by an adhesive layer (not shown), and a plurality of soldering arts 22 are disposed on the periphery of the active surface of the active surface. . Thereafter, as shown in the first figure, the 5G of the LFF is electrically connected to the first bonding pad 22 to the printed board 4° and the substrate 丨. . Finally, the line 50曰n seals the first wafer 20, the printed circuit board 40 and the bonding wires 5 into a chip package structure, such as the first! The figure shows. In the present embodiment, the wafer package structure includes a substrate 10, and the core may be a printed circuit board or Yes - lead frame. - the first wafer 20 ^ ^ ". The first active surface of the first wafer (9) has a complex surface: the % winding is placed on the periphery of the active surface. The adhesive layer 3 is disposed on the central region of the first surface of the charm surface. 42 set up. 9 number of material lines 5G m (four) connected to the first - wafer 2 ί ί =; Γ metal circuit layer 42, and electrically connected to the patterned metal electric cream 2 曰 ... 10. A colloid 80 history placed The substrate 10 is used for sealing and coating the brother-day piece 2G, the patterned metal circuit layer 42 and the bonding wire 5〇. The above description is shown in the fourth figure, the fourth picture and the fourth picture C, according to the third. A cross-sectional view of the method for fabricating a package structure. As shown in Fig. 4a, a first-stage wafer 20-bond-adhesive layer (not shown) is fixed on the substrate 10. The connector is on the first wafer 20 A plurality of solder fillets 22 are disposed on the periphery of the active surface, and an adhesive layer 3 is disposed in the central portion of the movable surface. Next, referring to the fourth step, the patterned metal circuit layer 42 is transferred onto the adhesive layer 3G by a process. = body 6 〇 ' as shown in Figure 4C, and electrically connected to the glow pad 22 on the 苐-wafer 20 to the patterned metal circuit by a wire bonding process using a wire bonding process 50仏, and electrically connected to the patterned metal circuit layer 42 and the substrate 1Q. Finally, a piece of glue 7! 310596 is formed. The substrate can be a printed circuit board; is - the guide: the structure 7 is adhesively disposed on the substrate 1 〇上. Among them, 曰, water bar. A first cymbal piece 20 a plurality of welding borings 22 are arranged around the active ^ 2G - the active surface has a central region of the complex-wafer plus active surface.: Adhesive layer 3. Setting On the 30th and having a plurality of Tan pads 72 f - the Japanese film 7. The adhesive layer metal circuit layer 42 is disposed on the active surface of the first layer - 3 ^ ^. A picture edge. Line 5〇_7 surrounds the second wafer 70 on Tuesday 曰L=:2: on the patterned metal circuit layer 42, and the electrical connection 10 is used to seal the spoon: the 22nd to the substrate 10. A gel 80 is disposed on the substrate The upper cover is used to seal the wafer 2, the second wafer 7 and the bonding wire 5〇. The above description, the sixth figure, the sixth figure,
=據第:ΓΓ片封裂結構製法之剖面示意圖’。如第6A 於基板i 〇上。接著片第!0曰^利黏著層（圖上未示）固設 悝埶99 、 日日片20之主動面周緣設置複數個 ^塾22 ’讀线財㈣域設難著層3G。接著，參 關，：用-轉印程序於黏著層3〇上轉印圖 ： ❿之後’移除載體60’參照第6Cffl，設置一第二晶片7曰〇 於黏者廣3G上亚形成複數個焊塾72於第二晶片％之主動面 上。如第6D圖所不，並利用一打線程序以焊線％ 第-晶片2〇上焊㈣與第二晶片7G上焊墊72至圖宰化$ 電路層42上，且電性連接第一晶片2〇上之焊_至基板1〇。 最後，形成一封膠體80密封包覆第一晶片2〇、第二 與焊線50完成晶片封裝結構，如第5圖所示。 1310596 、=合上述，本發明係可取代晶圓級封裝之重新分配功能， 二成，較低且製程較晶圓級封裝簡單，本發明目的之—係提供 作曰片封裝結構，除具有可重新分配功能外，亦可簡易的f 作晶片堆疊封裝結構。 〕匆㈣ 點，^實施難係為說日林發明之技術思想及特 據以無施\使熟Μ項技藝之人士能夠瞭解本發明之内容並 2不能以之μ本發明之專利範圍，即大凡依本發 專利範^内:神所作之均等變化或修飾，仍應涵蓋在本發明之 【圖式簡單說明】 第1圖所示為根據本發明晶片封裝結構一實施例之剖面示意圖。 圖與第2C圖為根據第1圖所示晶片封裝結構製法之 ί圖3圖所不為根據本發明晶片封裝結構另-實施例之剖面示 第4Α圖、第4Β圖與第4C HI炎j上 製法之剖面示意圖。、 ”、、\據第3圖所示晶片封裝結構 Ϊ圖5。圖所不為根據本發明晶片封敦結構又一實施例之剖面示 第6Α圖、第6Β圖、第6c圖與繁 片封裝結構製法之剖面示意圖D圖為根據第5圖所示晶 1310596 【主要元件符號說明】 10 基板 20 第一晶片 22 焊墊 30 黏著層 40 印刷電路板 42 圖案化金屬電路層 50 焊線 60 載體 70 第二晶片 72 焊墊 80 封膠體= According to the section: Schematic diagram of the method of making a cracked structure. For example, the 6A is on the substrate i 〇. Then the film is the first! 0曰^利 adhesion layer (not shown) is fixed 悝埶99, and the active surface of the Japanese film 20 is set to a plurality of edges. ^塾22 ‘Reading line (4) domain is difficult to layer 3G. Next, the reference, the transfer process is carried out on the adhesive layer 3 by the transfer process: after the ', the 'removal carrier 60' is referred to the sixth Cffl, and a second wafer 7 is placed on the viscous 3G to form a plurality The solder bumps 72 are on the active side of the second wafer. As shown in FIG. 6D, a wire bonding process is used to solder the wire (1) to the second wafer 7G to the circuit layer 42 and electrically connect the first wafer. 2 soldering _ to the substrate 1 〇. Finally, a colloid 80 is formed to seal the first wafer 2, and the second and bonding wires 50 complete the wafer package structure, as shown in FIG. 1310596, = In combination, the present invention can replace the re-distribution function of the wafer level package, 20%, lower and the process is simpler than the wafer level package, and the object of the present invention is to provide a chip package structure, in addition to having In addition to the redistribution function, it is also easy to use as a wafer stack package structure. 〕 急(四)点,^Implementation is difficult to say that the technical ideas and special features of the invention of the Japanese forest can not understand the content of the invention and can not be used to understand the scope of the invention. In the present invention, the equivalent variation or modification of God is still covered in the present invention. [Fig. 1 is a schematic cross-sectional view showing an embodiment of a chip package structure according to the present invention. FIG. 2 and FIG. 2C are diagrams showing a method of fabricating a package structure according to FIG. 1. FIG. 3 is a cross-sectional view showing another embodiment of the chip package structure according to the present invention, FIG. 4, FIG. 4, and FIG. 4C HI. Schematic diagram of the upper system. According to the wafer package structure shown in Fig. 3, Fig. 5 is a cross-sectional view showing a sixth embodiment, a sixth drawing, a sixth drawing, and a conventional piece according to another embodiment of the wafer sealing structure according to the present invention. Schematic diagram of the package structure method D is shown in Fig. 5 crystal 1310596 [main component symbol description] 10 substrate 20 first wafer 22 pad 30 adhesive layer 40 printed circuit board 42 patterned metal circuit layer 50 wire 60 carrier 70 second wafer 72 solder pad 80 sealant
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