JP2008235314A - Manufacturing process of semiconductor device, and the semiconductor device - Google Patents

Manufacturing process of semiconductor device, and the semiconductor device Download PDF

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Publication number
JP2008235314A
JP2008235314A JP2007068210A JP2007068210A JP2008235314A JP 2008235314 A JP2008235314 A JP 2008235314A JP 2007068210 A JP2007068210 A JP 2007068210A JP 2007068210 A JP2007068210 A JP 2007068210A JP 2008235314 A JP2008235314 A JP 2008235314A
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Japan
Prior art keywords
pad electrode
conductive material
semiconductor device
wire
manufacturing
Prior art date
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Application number
JP2007068210A
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Japanese (ja)
Inventor
Futoshi Fukaya
太 深谷
Ryoji Kotaki
良次 小瀧
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2007068210A priority Critical patent/JP2008235314A/en
Publication of JP2008235314A publication Critical patent/JP2008235314A/en
Withdrawn legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing process of a semiconductor device which can attain compaction and cost reduction while preventing occurrence of wire detachment, and to provide a semiconductor device. <P>SOLUTION: The manufacturing process of a semiconductor device comprises a step for forming a pad electrode on a substrate, a step for forming a conductive material on the pad electrode to cover probing marks formed thereon, and a step for bonding a wire to the pad electrode where the probing marks are covered with the conductive material. In the step for forming a conductive material, the conductive material is applied to the tip of the wire, and then the wire is pressed against the pad electrode, so that the conductive material is formed to cover the probing marks. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、プローブ検査によりプロービング跡が形成された半導体チップを具備する半導体装置、該半導体装置の製造方法に関する。   The present invention relates to a semiconductor device including a semiconductor chip on which a probing mark is formed by probe inspection, and a method for manufacturing the semiconductor device.

プローブ検査では、ＩＣテスタに接続されたプローブを半導体チップの電極パッドに接触させて半導体チップの良否選別を行う。前記プローブは針状であるため、パッド電極の上面に針で突いた跡のようなプロービング跡（凹部）が残ってしまい、このプロービング跡の上にワイヤをボンディングしようとすると（図７Ａ及び図７Ｂ）、ワイヤ剥離が発生するという問題があった。前記ワイヤ剥離の発生を防止するために、ワイヤボンディング用の電極パッドとプローブ検査用の電極パッドとを分離することや、電極パッドを長方形にすること等がなされていた（図８Ａ及び図８Ｂ）。しかし、近年、半導体チップの小型化（取り数増大）の要求が高まっており、プローブ検査用の電極パッドとワイヤボンディング用の電極パッドとを分離したり、電極パッドを長方形にすると、半導体チップの面積が大きくなり、１枚のウエハから取得できる半導体チップの取り数が減少し、前記要求に反することとなる。   In the probe inspection, the probe connected to the IC tester is brought into contact with the electrode pad of the semiconductor chip to select the semiconductor chip. Since the probe has a needle shape, a probing mark (concave part) like a mark protruding with a needle remains on the upper surface of the pad electrode, and an attempt is made to bond a wire on the probing mark (FIGS. 7A and 7B). ), And there was a problem that wire peeling occurred. In order to prevent the occurrence of the wire peeling, the electrode pad for wire bonding and the electrode pad for probe inspection were separated, or the electrode pad was made rectangular (FIGS. 8A and 8B). . However, in recent years, there has been an increasing demand for miniaturization (increase in the number of semiconductor chips) of the semiconductor chip. When the electrode pad for probe inspection and the electrode pad for wire bonding are separated or the electrode pad is rectangular, The area becomes large, and the number of semiconductor chips that can be obtained from one wafer is reduced, which is contrary to the above requirement.

ワイヤ剥離の発生を防止すると共に前記要求を満たすために、プロービング跡を金属層（特許文献１参照）や保護膜パターン(特許文献２参照)で覆うことがなされているが、これらの金属層や保護膜パターンは、スパッタ法や蒸着法によって形成されているため、プロービング跡を金属層や保護膜パターンで覆う工程をプロセス工程中に追加する必要があり、コストや時間がかかってしまうという問題があった。   In order to prevent the occurrence of wire peeling and satisfy the above requirements, the probing marks are covered with a metal layer (see Patent Document 1) or a protective film pattern (see Patent Document 2). Since the protective film pattern is formed by sputtering or vapor deposition, it is necessary to add a process for covering the probing marks with a metal layer or a protective film pattern to the process process, which increases costs and time. there were.

特許第３６３８０８５号公報Japanese Patent No. 3638085 国際公開第０４／００１８３９号パンフレットInternational Publication No. 04/001839 Pamphlet

本発明は、前記従来に於ける諸問題を解決し、以下の目的を達成することを課題とする。即ち、本発明は、ワイヤ剥離の発生を防止すると共に小型化及びコストの低減を図ることができる半導体装置の製造方法及び該半導体装置を提供することを目的とする。   An object of the present invention is to solve the problems in the prior art and achieve the following objects. That is, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device which can prevent the occurrence of wire peeling and can be reduced in size and cost.

前記課題を解決するための手段としては、以下の通りである。即ち、
本発明の半導体装置の製造方法は、基板上にパッド電極を形成するパッド電極形成工程と、前記パッド電極に形成されたプロービング跡が覆われるように導電性材料を前記パッド電極上に形成する導電性材料形成工程と、前記プロービング跡が覆われたパッド電極にワイヤをボンディングするワイヤボンディング工程とを含む半導体装置の製造方法であって、前記導電性材料形成工程に於いて、前記導電性材料を前記ワイヤの先端に塗布し、前記先端に導電性材料が塗布されたワイヤを前記パッド電極に押圧することにより、前記導電性材料を前記プロービング跡が覆われるように形成することを特徴とする。 Means for solving the problems are as follows. That is,
The method of manufacturing a semiconductor device according to the present invention includes a pad electrode forming step for forming a pad electrode on a substrate, and a conductive material for forming a conductive material on the pad electrode so as to cover a probing mark formed on the pad electrode. A method of manufacturing a semiconductor device, comprising: a conductive material forming step; and a wire bonding step of bonding a wire to a pad electrode covered with the probing mark, wherein the conductive material is formed in the conductive material forming step. The conductive material is formed so as to cover the probing marks by applying to the tip of the wire and pressing a wire having a conductive material applied to the tip against the pad electrode.

該半導体装置の製造方法では、前記パッド電極形成工程に於いて、前記基板上に前記パッド電極が形成される。前記導電性材料形成工程に於いて、前記導電性材料が前記ワイヤの先端に塗布され、前記先端に導電性材料が塗布されたワイヤが前記パッド電極に押圧されることにより、前記導電性材料が前記プロービング跡を覆うように形成される。前記ワイヤボンディング工程に於いて、前記パッド電極に前記ワイヤがボンディングされる。その結果、ワイヤ剥離の発生が防止されると共に、小型化及びコストの低減が図られる。   In the method for manufacturing a semiconductor device, the pad electrode is formed on the substrate in the pad electrode forming step. In the conductive material forming step, the conductive material is applied to the tip of the wire, and the wire having the conductive material applied to the tip is pressed against the pad electrode, whereby the conductive material becomes It is formed so as to cover the probing mark. In the wire bonding step, the wire is bonded to the pad electrode. As a result, occurrence of wire peeling is prevented, and downsizing and cost reduction are achieved.

本発明の半導体装置の製造方法は、基板上にパッド電極を形成するパッド電極形成工程と、前記パッド電極に形成されたプロービング跡が覆われるように導電性材料を前記パッド電極上に形成する導電性材料形成工程と、前記プロービング跡が覆われたパッド電極にワイヤをボンディングするワイヤボンディング工程とを含む半導体装置の製造方法であって、前記導電性材料形成工程に於いて、前記導電性材料を前記パッド電極上に塗布し、前記塗布された導電性材料を前記プロービング跡が覆われるように形成することを特徴とする。   The method of manufacturing a semiconductor device according to the present invention includes a pad electrode forming step for forming a pad electrode on a substrate, and a conductive material for forming a conductive material on the pad electrode so as to cover a probing mark formed on the pad electrode. A method of manufacturing a semiconductor device, comprising: a conductive material forming step; and a wire bonding step of bonding a wire to a pad electrode covered with the probing mark, wherein the conductive material is formed in the conductive material forming step. It is coated on the pad electrode, and the coated conductive material is formed so as to cover the probing marks.

該半導体装置の製造方法では、前記パッド電極形成工程に於いて、前記基板上に前記パッド電極が形成される。前記導電性材料形成工程に於いて、前記導電性材料が前記パッド電極に塗布され、前記塗布された導電性材料が前記プロービング跡を覆うように形成される。前記ワイヤボンディング工程に於いて、前記パッド電極に前記ワイヤがボンディングされる。その結果、ワイヤ剥離の発生が防止されると共に、小型化及びコストの低減が図られる。   In the method for manufacturing a semiconductor device, the pad electrode is formed on the substrate in the pad electrode forming step. In the conductive material forming step, the conductive material is applied to the pad electrode, and the applied conductive material is formed to cover the probing mark. In the wire bonding step, the wire is bonded to the pad electrode. As a result, occurrence of wire peeling is prevented, and downsizing and cost reduction are achieved.

本発明の半導体装置は、半導体基板と、前記半導体基板上に形成されたパッド電極と、前記パッド電極上の一部に形成された導電性樹脂と、前記パッド電極上及び前記導電性樹脂上に形成された外部接続端子とを備えることを特徴とする。   The semiconductor device of the present invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a conductive resin formed on a part of the pad electrode, the pad electrode, and the conductive resin. And an external connection terminal formed.

該半導体装置に於いては、前記導電性樹脂がパッド電極上の一部に形成され、前記外部接続端子が前記パッド電極上及び前記導電性樹脂上に形成されるので、ワイヤ剥離の発生が防止されると共に、小型化及びコストの低減が図られる。   In the semiconductor device, since the conductive resin is formed on a part of the pad electrode and the external connection terminal is formed on the pad electrode and the conductive resin, occurrence of wire peeling is prevented. In addition, downsizing and cost reduction are achieved.

本発明によれば、前記従来に於ける諸問題を解決し、前記目的を達成することができ、ワイヤ剥離の発生を防止すると共に小型化及びコストの低減を図ることができる半導体装置の製造方法及び該半導体装置を提供することができる。   According to the present invention, a method of manufacturing a semiconductor device that can solve the problems in the prior art, achieve the object, prevent the occurrence of wire peeling, and reduce the size and cost. And the semiconductor device can be provided.

以下、本発明の半導体装置の製造方法及び該半導体装置について、実施例をもって詳細に説明するが、本発明は下記実施例に何ら限定されるものではない。   Hereinafter, although the manufacturing method of the semiconductor device of this invention and this semiconductor device are demonstrated in detail with an Example, this invention is not limited to the following Example at all.

（実施例１）
本発明の半導体装置の製造方法の第１の実施例を以下に図面を用いて説明する。 (Example 1)
A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

実施例１では、まず、図１Ａに示すように、トランジスタ及び多層配線（図示せず）が形成された半導体基板１０の表面の周縁部に、電子ビーム蒸着法またはスパッタリング法によってアルミニウム膜を形成し、これをパターニングすることによりパッド電極１１を形成する（パッド電極形成工程）。次に、前記パッド電極１１上に保護膜となる窒化珪素膜１２を、前記パッド電極１１を被覆するように形成し、さらに前記保護膜１２中に開口部を、前記パッド電極１１が露出するように形成して（保護膜形成工程）、半導体チップ１４を形成する。前記半導体チップ１４を形成した後、電気的な信号の確認のためにプローブ検査を行う（プローブ検査工程）。その結果、前記プローブ検査後には前記パッド電極１１上に、プローブ針を押し当てたことによる凹状の傷であるプロービング跡１３が残る。   In Example 1, first, as shown in FIG. 1A, an aluminum film is formed by electron beam evaporation or sputtering on the periphery of the surface of the semiconductor substrate 10 on which transistors and multilayer wiring (not shown) are formed. The pad electrode 11 is formed by patterning this (pad electrode forming step). Next, a silicon nitride film 12 serving as a protective film is formed on the pad electrode 11 so as to cover the pad electrode 11, and an opening is formed in the protective film 12 so that the pad electrode 11 is exposed. Then, the semiconductor chip 14 is formed. After the semiconductor chip 14 is formed, a probe inspection is performed to confirm an electrical signal (probe inspection process). As a result, after the probe inspection, a probing mark 13 which is a concave scratch caused by pressing a probe needle remains on the pad electrode 11.

次に、前記プローブ検査された半導体チップ１４をリードフレーム（不図示）上に接着剤（不図示）を介して載置し（ダイス付け工程）、１５０℃に加熱することにより、前記半導体チップ１４と前記リードフレームとの間にある前記接着剤を硬化させる（キュア工程）。   Next, the probe-inspected semiconductor chip 14 is placed on a lead frame (not shown) via an adhesive (not shown) (dicing step) and heated to 150 ° C. And the adhesive between the lead frame and the lead frame is cured (curing step).

さらに、図１Ｂに示すように、液状の導電性材料１５を金ワイヤ１６（外部接続端子）の先端（金ボール）１６ａに塗布し（導電性材料塗布工程）、前記先端に導電性材料１５が塗布された金ワイヤ１６を前記電極パッド１１に押圧して１５０℃〜３５０℃に加熱することにより、図１Ｃに示すように、前記金ワイヤ１６を前記パッド電極１１にボンディングさせると共に、前記導電性材料１５に於ける熱硬化性樹脂を硬化させ（ワイヤボンディング工程）、１７０℃に加熱してモールド樹脂などで前記ワイヤボンディングされた半導体チップ１４を封入する（モールド工程）。なお、前記導電性材料１５は、エポキシ系、シリコーン系、ポリイミド系の熱硬化性樹脂と、Ａｕ、Ｎｉ、Ａｇ、Ａｌ、カーボン等の導電性フィラとを含む。また、前記導電性フィラの含有量は、前記導電性材料１５に対して５０〜７０％である。   Further, as shown in FIG. 1B, the liquid conductive material 15 is applied to the tip (gold ball) 16a of the gold wire 16 (external connection terminal) (conductive material application step), and the conductive material 15 is applied to the tip. The applied gold wire 16 is pressed against the electrode pad 11 and heated to 150 ° C. to 350 ° C., thereby bonding the gold wire 16 to the pad electrode 11 as shown in FIG. The thermosetting resin in the material 15 is cured (wire bonding process), and heated to 170 ° C. to enclose the semiconductor chip 14 wire-bonded with a mold resin or the like (molding process). The conductive material 15 includes an epoxy-based, silicone-based, or polyimide-based thermosetting resin, and a conductive filler such as Au, Ni, Ag, Al, or carbon. Further, the content of the conductive filler is 50 to 70% with respect to the conductive material 15.

（実施例２）
本発明の半導体装置の製造方法の第２の実施例を以下に図面を用いて説明する。 (Example 2)
A second embodiment of the semiconductor device manufacturing method of the present invention will be described below with reference to the drawings.

実施例２では、実施例１と同様に、パッド電極形成工程、保護膜形成工程、及びプローブ検査工程を行う（図２Ａ）。   In Example 2, the pad electrode formation process, the protective film formation process, and the probe inspection process are performed as in Example 1 (FIG. 2A).

次に、プローブ検査された半導体チップ１４をリードフレーム（不図示）上に接着剤（不図示）を介して載置し（ダイス付け工程）、１５０℃に加熱することにより、前記半導体チップ１４と前記リードフレームとの間にある前記接着剤を硬化させる（キュア工程）。   Next, the probe-inspected semiconductor chip 14 is placed on a lead frame (not shown) via an adhesive (not shown) (dicing step) and heated to 150 ° C. The adhesive between the lead frame is cured (curing step).

さらに、図２Ｂに示すように、液状の導電性材料１５をパッド電極１１に塗布し（導電性材料塗布工程）、前記金ワイヤ１６を前記電極パッド１１に押圧して１５０℃〜３５０℃に加熱することにより、図２Ｃに示すように、前記金ワイヤ１６を前記パッド電極１１にボンディングさせると共に、前記導電性材料１５に於ける熱硬化性樹脂を硬化させ（ワイヤボンディング工程）、１７０℃に加熱してモールド樹脂などで前記ワイヤボンディングされた半導体チップ１４を封入する（モールド工程）。   Further, as shown in FIG. 2B, a liquid conductive material 15 is applied to the pad electrode 11 (conductive material application step), and the gold wire 16 is pressed against the electrode pad 11 and heated to 150 ° C. to 350 ° C. As a result, as shown in FIG. 2C, the gold wire 16 is bonded to the pad electrode 11, and the thermosetting resin in the conductive material 15 is cured (wire bonding step), and heated to 170 ° C. Then, the wire-bonded semiconductor chip 14 is sealed with a molding resin or the like (molding process).

（実施例３）
本発明の半導体装置の製造方法の第３の実施例を以下に図面を用いて説明する。 (Example 3)
A third embodiment of the semiconductor device manufacturing method of the present invention will be described below with reference to the drawings.

実施例３では、実施例１と同様に、パッド電極形成工程、保護膜形成工程、及びプローブ検査工程を行う（図３Ａ）。   In Example 3, as in Example 1, a pad electrode formation process, a protective film formation process, and a probe inspection process are performed (FIG. 3A).

次に、プローブ検査された半導体チップ１４をリードフレーム（不図示）に接着剤（不図示）を介して載置し（ダイス付け工程）、図３Ｂに示すように、導電性材料１５をパッド電極１１に塗布し（導電性材料塗布工程）、１５０℃に加熱することにより、前記半導体チップ１４と前記リードフレームとの間にある前記接着剤を硬化させると共に、前記導電性材料１５を硬化状態にする（キュア工程）。   Next, the probe-inspected semiconductor chip 14 is placed on a lead frame (not shown) via an adhesive (not shown) (dicing step), and the conductive material 15 is pad electrode as shown in FIG. 3B. 11 (conductive material application step) and heated to 150 ° C. to cure the adhesive between the semiconductor chip 14 and the lead frame and to bring the conductive material 15 into a cured state. (Cure process).

さらに、前記金ワイヤ１６を前記電極パッド１１に押圧して１５０℃〜３５０℃に加熱することにより、図３Ｃに示すように、前記金ワイヤ１６をパッド電極１１（導電性材料１５）にボンディングさせ（ワイヤボンディング工程）、１７０℃に加熱してモールド樹脂などで前記ワイヤ付けされた半導体チップ１４を封入する（モールド工程）。   Further, the gold wire 16 is pressed against the electrode pad 11 and heated to 150 ° C. to 350 ° C., thereby bonding the gold wire 16 to the pad electrode 11 (conductive material 15) as shown in FIG. 3C. (Wire bonding step) The semiconductor chip 14 wire-bonded with a mold resin or the like after being heated to 170 ° C. is encapsulated (molding step).

（実施例４）
本発明の半導体装置の製造方法の第４の実施例を以下に図面を用いて説明する。 Example 4
A fourth embodiment of the semiconductor device manufacturing method of the present invention will be described below with reference to the drawings.

実施例４では、実施例１と同様に、パッド電極形成工程、保護膜形成工程、及びプローブ検査工程を行う（図４Ａ）。   In Example 4, the pad electrode formation process, the protective film formation process, and the probe inspection process are performed as in Example 1 (FIG. 4A).

次に、プローブ検査された半導体チップ１４をリードフレーム（不図示）に接着剤（不図示）を介して載置し（ダイス付け工程）、図４Ｂに示すように、導電性材料１５をパッド電極１１に塗布し（導電性材料塗布工程）、１５０℃に加熱することにより、前記半導体チップ１４と前記リードフレームとの間にある前記接着剤を硬化させると共に、前記導電性材料１５を半硬化状態にする（キュア工程）。   Next, the probe-inspected semiconductor chip 14 is placed on a lead frame (not shown) via an adhesive (not shown) (dicing step), and the conductive material 15 is pad electrode as shown in FIG. 4B. 11 (conductive material application step) and heated to 150 ° C. to cure the adhesive between the semiconductor chip 14 and the lead frame, and the conductive material 15 in a semi-cured state. (Cure process).

さらに、前記金ワイヤ１６を前記電極パッド１１に押圧して１５０℃〜３５０℃に加熱することにより、図４Ｃに示すように、前記金ワイヤ１６を前記パッド電極１１にボンディングさせ（ワイヤボンディング工程）、１７０℃に加熱してモールド樹脂などで前記ワイヤ付けされた半導体チップ１４を封入する（モールド工程）。   Further, the gold wire 16 is pressed against the electrode pad 11 and heated to 150 ° C. to 350 ° C. to bond the gold wire 16 to the pad electrode 11 as shown in FIG. 4C (wire bonding step). , Heated to 170 ° C. and encapsulated with the wire-attached semiconductor chip 14 with a molding resin or the like (molding process).

（実施例５）
本発明の半導体装置の製造方法の第５の実施例を以下に図面を用いて説明する。 (Example 5)
A fifth embodiment of the semiconductor device manufacturing method of the present invention will be described below with reference to the drawings.

実施例５では、前記金ワイヤ１６をパッド電極１１にボンディングさせて、パッド電極１１上にワイヤを形成する（実施例１〜４、例えば図５Ａ及び図５Ｂ）代わりに、図６に示すように、ボールバンプ５０を形成する。   In Example 5, instead of bonding the gold wire 16 to the pad electrode 11 to form a wire on the pad electrode 11 (Examples 1 to 4, for example, FIGS. 5A and 5B), as shown in FIG. Then, the ball bump 50 is formed.

以上、本発明の半導体装置の製造方法によれば、前記パッド電極１１に於ける前記プロービング跡１３を前記導電性材料１５で覆って、前記プロービング跡１３が前記導電性材料１５で覆われた前記電極パッド１１に前記金ワイヤ１６をボンディングしてワイヤ又はボールバンプを形成するので、前記半導体チップ１４の面積を縮小して、前記半導体チップ１４の取り数を増加することができる。例えば、従来の半導体装置の製造方法により作製された半導体チップは、パッド電極のサイズが６０μｍ×１２０μｍ、半導体チップのサイズが５ｍｍ四方、半導体チップの取り数が１，８６０個であったのに対し、本発明の半導体装置の製造方法により作製された半導体チップ１４に於いては、パッド電極１１のサイズを６０μｍ四方、半導体チップ１４のサイズを４.８８ｍｍ四方、半導体チップ１４の取り数を１，９８４個（従来の１，８６０個に対して、６．７％増加）とすることができる。   As described above, according to the method for manufacturing a semiconductor device of the present invention, the probing trace 13 in the pad electrode 11 is covered with the conductive material 15, and the probing trace 13 is covered with the conductive material 15. Since the gold wire 16 is bonded to the electrode pad 11 to form a wire or a ball bump, the area of the semiconductor chip 14 can be reduced and the number of the semiconductor chips 14 can be increased. For example, a semiconductor chip manufactured by a conventional method for manufacturing a semiconductor device has a pad electrode size of 60 μm × 120 μm, a semiconductor chip size of 5 mm square, and the number of semiconductor chips obtained is 1,860. In the semiconductor chip 14 manufactured by the method of manufacturing a semiconductor device of the present invention, the size of the pad electrode 11 is 60 μm square, the size of the semiconductor chip 14 is 4.88 mm square, the number of the semiconductor chips 14 is 1, It can be 984 (an increase of 6.7% over the conventional 1,860).

また、本発明の半導体装置の製造方法によれば、前記導電性材料１５として熱硬化性樹脂及び導電性フィラを含むものを使用しているので、ワイヤボンディング条件及びワイヤ材の変更が可能となる。具体的には、従来、超音波併用高温熱圧着により行っていたワイヤボンディングを低温熱圧着により行うことができ、また、ワイヤ材として金だけでなく銅を用いることができ、前記ワイヤ材として銅を用いることによりワイヤの材料費を２０〜３０％低減することができる。   Further, according to the method for manufacturing a semiconductor device of the present invention, since the conductive material 15 containing a thermosetting resin and a conductive filler is used, the wire bonding conditions and the wire material can be changed. . Specifically, wire bonding, which has been conventionally performed by high-temperature thermocompression bonding combined with ultrasonic waves, can be performed by low-temperature thermocompression bonding, and not only gold but also copper can be used as the wire material. By using the wire, the material cost of the wire can be reduced by 20 to 30%.

また、本発明の半導体装置の製造方法によれば、前記パッド電極１１に於ける汚染状態の影響を少なくすると共に前記導電性材料１５に含まれる熱硬化性樹脂により前記パッド電極１１と前記金ワイヤ１６との接着力を向上することができ、もってボンディング剥離を低減することができる。   In addition, according to the method for manufacturing a semiconductor device of the present invention, the influence of the contamination state on the pad electrode 11 is reduced, and the pad electrode 11 and the gold wire are formed by the thermosetting resin contained in the conductive material 15. Adhesive strength with 16 can be improved, and bonding peeling can be reduced.

また、本発明の半導体装置の製造方法によれば、プローブ検査の回数の制限がなくなることから、前記半導体チップ１４が電気的に正常な動作を示すことを十分に確認することができ（コンタクトミスをなくすことができ）、もって前記半導体チップ１４の歩留まりを向上することができる。   In addition, according to the method for manufacturing a semiconductor device of the present invention, since the limit of the number of probe inspections is eliminated, it can be sufficiently confirmed that the semiconductor chip 14 exhibits an electrically normal operation (contact mistake). Therefore, the yield of the semiconductor chip 14 can be improved.

また、本発明の半導体装置の製造方法によれば、プローブ検査の回数を増やすことができることから、テスターが異なる多様な試験項目（例えば、アナログなど）を実施することができる。   Further, according to the method for manufacturing a semiconductor device of the present invention, since the number of probe inspections can be increased, various test items (for example, analog) having different testers can be performed.

また、本発明の半導体装置の製造方法によれば、前記導電性材料１５として熱硬化性樹脂及び導電性フィラを含むものを使用しているので、金属間化合物が生成しにくい又は生成しないことから、前記半導体チップ１４を長期間放置しても、金属拡散を抑制することができる。   Further, according to the method for manufacturing a semiconductor device of the present invention, since the conductive material 15 containing a thermosetting resin and a conductive filler is used, an intermetallic compound is hardly generated or does not generate. Even if the semiconductor chip 14 is left for a long period of time, metal diffusion can be suppressed.

（実施例６）
本発明の半導体装置を製造する製造装置の実施例を説明する。 (Example 6)
An embodiment of a manufacturing apparatus for manufacturing a semiconductor device of the present invention will be described.

半導体装置の製造装置は、シリンジ等によるディスペンス供給によって前記金ワイヤ１６の先端又は前記パッド電極１１上に前記導電性材料１５を塗布する塗布部（不図示）と、前記パッド電極１１に前記金ワイヤ１６をボンディングするワイヤボンディング部（不図示）と、前記プロービング跡１３の位置を検出する検出手段（不図示）と、前記パッド電極１１にボンディングされた前記金ワイヤ１６の接続状態を検知する検知手段（不図示）とを備える。   The semiconductor device manufacturing apparatus includes a coating part (not shown) for applying the conductive material 15 on the tip of the gold wire 16 or on the pad electrode 11 by dispensing with a syringe or the like, and the gold wire on the pad electrode 11. A wire bonding portion (not shown) for bonding 16, a detection means (not shown) for detecting the position of the probing mark 13, and a detection means for detecting the connection state of the gold wire 16 bonded to the pad electrode 11. (Not shown).

以上、本発明の半導体装置の製造装置によれば、前記導電性材料１５を塗布する塗布部と、前記パッド電極１１に前記金ワイヤ１６をボンディングするワイヤボンディング部とを備えるので、一連のボンディング作業工程（アッセンブリ工程）に前記導電性材料１５の塗布工程を組み込むことができる。また、前記ボンディング部が前記パッド電極１５に前記金ワイヤ１６をボンディングする際に、前記塗布部により塗布された前記導電性材料１５を硬化することができる。   As described above, according to the semiconductor device manufacturing apparatus of the present invention, since the coating portion for applying the conductive material 15 and the wire bonding portion for bonding the gold wire 16 to the pad electrode 11 are provided, a series of bonding operations are performed. An application process of the conductive material 15 can be incorporated in the process (assembly process). Further, when the bonding part bonds the gold wire 16 to the pad electrode 15, the conductive material 15 applied by the application part can be cured.

本発明の好ましい態様を付記すると、以下の通りである。
（付記１） 基板上にパッド電極を形成するパッド電極形成工程と、前記パッド電極に形成されたプロービング跡が覆われるように導電性材料を前記パッド電極上に形成する導電性材料形成工程と、前記プロービング跡が覆われたパッド電極にワイヤをボンディングするワイヤボンディング工程とを含む半導体装置の製造方法であって、前記導電性材料形成工程に於いて、前記導電性材料を前記ワイヤの先端に塗布し、前記先端に導電性材料が塗布されたワイヤを前記パッド電極に押圧することにより、前記導電性材料をプロービング跡が覆われるように形成することを特徴とする半導体装置の製造方法。
（付記２） 基板上にパッド電極を形成するパッド電極形成工程と、前記パッド電極に形成されたプロービング跡が覆われるように導電性材料を前記パッド電極上に形成する導電性材料形成工程と、前記プロービング跡が覆われたパッド電極にワイヤをボンディングするワイヤボンディング工程とを含む半導体装置の製造方法であって、前記導電性材料形成工程に於いて、前記導電性材料を前記パッド電極上に塗布し、前記塗布された導電性材料をプロービング跡が覆われるように形成することを特徴とする半導体装置の製造方法。
（付記３） 導電性材料は、熱硬化性樹脂を含むことを特徴とする付記１又は２に記載の半導体装置の製造方法。
（付記４） 導電性材料は、ワイヤボンディング工程に於ける熱によって硬化することを特徴とする付記３記載の半導体装置の製造方法。
（付記５） 導電性材料は、導電性フィラを含むことを特徴とする付記１乃至４のいずれかに記載の半導体装置の製造方法。
（付記６） 導電性材料形成工程に於いて、プロービング跡が覆われるように形成された導電性材料は液状であることを特徴とする付記１乃至５のいずれかに記載の半導体装置の製造方法。
（付記７） パッド電極上にバンプを形成することを特徴とする付記１乃至６のいずれかに記載の半導体装置の製造方法。
（付記８） 半導体基板と、前記半導体基板上に形成されたパッド電極と、前記パッド電極上の一部に形成された導電性樹脂と、前記パッド電極上及び前記導電性樹脂上に形成された外部接続端子とを備えることを特徴とする半導体装置。
（付記９） 半導体基板と、前記半導体基板上に形成されたパッド電極と、前記パッド電極上に形成された導電性材料とを備える半導体装置を製造する半導体装置の製造装置であって、前記導電性材料を塗布する塗布手段と、前記パッド電極にワイヤをボンディングするワイヤボンディング手段とを備えることを特徴とする半導体装置の製造装置。
（付記１０） 塗布手段は、ワイヤの先端に導電性材料を塗布することを特徴とする付記９に記載の半導体装置の製造装置。
（付記１１） 塗布手段は、導電性材料をパッド電極上に塗布することを特徴とする付記９に記載の半導体装置の製造装置。
（付記１２） プロービング跡の位置を検出する検出手段をさらに備えることを特徴とする付記９乃至１１のいずれかに記載の半導体装置の製造装置。
（付記１３） パッド電極にボンディングされたワイヤの接続状態を検知する検知手段をさらに備えることを特徴とする付記９乃至１２のいずれかに記載の半導体装置の製造装置。 The preferred embodiments of the present invention are as follows.
(Additional remark 1) The pad electrode formation process which forms a pad electrode on a board | substrate, The conductive material formation process which forms a conductive material on the said pad electrode so that the probing trace formed in the said pad electrode may be covered, A method of manufacturing a semiconductor device including a wire bonding step of bonding a wire to a pad electrode covered with the probing mark, wherein the conductive material is applied to a tip of the wire in the conductive material forming step. A method of manufacturing a semiconductor device, wherein the conductive material is formed so as to cover a probing mark by pressing a wire having a conductive material applied to the tip against the pad electrode.
(Additional remark 2) The pad electrode formation process which forms a pad electrode on a board | substrate, The conductive material formation process which forms a conductive material on the said pad electrode so that the probing trace formed in the said pad electrode may be covered, A method of manufacturing a semiconductor device including a wire bonding step of bonding a wire to a pad electrode covered with the probing mark, wherein the conductive material is applied onto the pad electrode in the conductive material forming step. And forming the applied conductive material so as to cover the probing marks.
(Additional remark 3) The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by a conductive material containing a thermosetting resin.
(Additional remark 4) The manufacturing method of the semiconductor device of Additional remark 3 characterized by a conductive material hardening | curing with the heat | fever in a wire bonding process.
(Supplementary note 5) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 4, wherein the conductive material includes a conductive filler.
(Supplementary Note 6) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 5, wherein in the conductive material forming step, the conductive material formed so as to cover the probing marks is in a liquid state. .
(Supplementary note 7) The method of manufacturing a semiconductor device according to any one of supplementary notes 1 to 6, wherein bumps are formed on the pad electrode.
(Appendix 8) A semiconductor substrate, a pad electrode formed on the semiconductor substrate, a conductive resin formed on a part of the pad electrode, and formed on the pad electrode and the conductive resin. A semiconductor device comprising an external connection terminal.
(Additional remark 9) It is a manufacturing apparatus of the semiconductor device which manufactures a semiconductor device provided with a semiconductor substrate, the pad electrode formed on the said semiconductor substrate, and the electroconductive material formed on the said pad electrode, Comprising: An apparatus for manufacturing a semiconductor device, comprising: an applying means for applying a conductive material; and a wire bonding means for bonding a wire to the pad electrode.
(Supplementary note 10) The semiconductor device manufacturing apparatus according to supplementary note 9, wherein the applying means applies a conductive material to the tip of the wire.
(Supplementary note 11) The semiconductor device manufacturing apparatus according to supplementary note 9, wherein the applying means applies a conductive material onto the pad electrode.
(Additional remark 12) The manufacturing apparatus of the semiconductor device in any one of Additional remark 9 thru | or 11 further provided with the detection means which detects the position of a probing trace.
(Additional remark 13) The manufacturing apparatus of the semiconductor device in any one of Additional remark 9 thru | or 12 further provided with the detection means to detect the connection state of the wire bonded to the pad electrode.

本発明の第１の実施例（実施例１）の半導体装置の製造方法を説明するための工程図（その１）。Process drawing (1) for demonstrating the manufacturing method of the semiconductor device of the 1st Example (Example 1) of this invention. 本発明の第１の実施例（実施例１）の半導体装置の製造方法を説明するための工程図（その２）。Process drawing (2) for demonstrating the manufacturing method of the semiconductor device of 1st Example (Example 1) of this invention. 本発明の第１の実施例（実施例１）の半導体装置の製造方法を説明するための工程図（その３）。Process drawing (3) for demonstrating the manufacturing method of the semiconductor device of 1st Example (Example 1) of this invention. 本発明の第２の実施例（実施例２）の半導体装置の製造方法を説明するための工程図（その１）。Process drawing (1) for demonstrating the manufacturing method of the semiconductor device of the 2nd Example (Example 2) of this invention. 本発明の第２の実施例（実施例２）の半導体装置の製造方法を説明するための工程図（その２）。Process drawing for demonstrating the manufacturing method of the semiconductor device of the 2nd Example (Example 2) of this invention (the 2). 本発明の第２の実施例（実施例２）の半導体装置の製造方法を説明するための工程図（その３）。Process drawing (3) for demonstrating the manufacturing method of the semiconductor device of the 2nd Example (Example 2) of this invention. 本発明の第３の実施例（実施例３）の半導体装置の製造方法を説明するための工程図（その１）。Process drawing (1) for demonstrating the manufacturing method of the semiconductor device of the 3rd Example (Example 3) of this invention. 本発明の第３の実施例（実施例３）の半導体装置の製造方法を説明するための工程図（その２）。Process drawing (2) for demonstrating the manufacturing method of the semiconductor device of the 3rd Example (Example 3) of this invention. 本発明の第３の実施例（実施例３）の半導体装置の製造方法を説明するための工程図（その３）。Process drawing (3) for demonstrating the manufacturing method of the semiconductor device of the 3rd Example (Example 3) of this invention. 本発明の第４の実施例（実施例４）の半導体装置の製造方法を説明するための工程図（その１）。Process drawing (1) for demonstrating the manufacturing method of the semiconductor device of the 4th Example (Example 4) of this invention. 本発明の第４の実施例（実施例４）の半導体装置の製造方法を説明するための工程図（その２）。Process drawing (2) for demonstrating the manufacturing method of the semiconductor device of the 4th Example (Example 4) of this invention. 本発明の第４の実施例（実施例４）の半導体装置の製造方法を説明するための工程図（その３）。Process drawing (3) for demonstrating the manufacturing method of the semiconductor device of the 4th Example (Example 4) of this invention. 本発明の半導体装置の断面図。Sectional drawing of the semiconductor device of this invention. 本発明の半導体装置の平面図。1 is a plan view of a semiconductor device of the present invention. 本発明の第５の実施例（実施例５）の半導体装置の製造方法を説明するための図。The figure for demonstrating the manufacturing method of the semiconductor device of the 5th Example (Example 5) of this invention. 従来のワイヤボンディングの一例を説明するための半導体装置の断面図。Sectional drawing of the semiconductor device for demonstrating an example of the conventional wire bonding. 従来のワイヤボンディングの一例を説明するための半導体装置の平面図。The top view of the semiconductor device for demonstrating an example of the conventional wire bonding. 従来のワイヤボンディングの他の例を説明するための半導体装置の断面図。Sectional drawing of the semiconductor device for demonstrating the other example of the conventional wire bonding. 従来のワイヤボンディングの他の例を説明するための半導体装置の平面図。The top view of the semiconductor device for demonstrating the other example of the conventional wire bonding.

符号の説明Explanation of symbols

１０ 半導体基板
１１ パッド電極
１２ 保護膜（窒化珪素膜）
１３ プロービング跡
１４ 半導体チップ
１５ 導電性材料
１６ 金ワイヤ
１６ａ 金ボール
５０ ボールバンプ 10 Semiconductor substrate 11 Pad electrode 12 Protective film (silicon nitride film)
13 Probing mark 14 Semiconductor chip 15 Conductive material 16 Gold wire 16a Gold ball 50 Ball bump

Claims (5)

基板上にパッド電極を形成するパッド電極形成工程と、
前記パッド電極に形成されたプロービング跡が覆われるように導電性材料を前記パッド電極上に形成する導電性材料形成工程と、
前記プロービング跡が覆われたパッド電極にワイヤをボンディングするワイヤボンディング工程と
を含む半導体装置の製造方法であって、
前記導電性材料形成工程に於いて、前記導電性材料を前記ワイヤの先端に塗布し、前記先端に導電性材料が塗布されたワイヤを前記パッド電極に押圧することにより、前記導電性材料を前記プロービング跡が覆われるように形成することを特徴とする半導体装置の製造方法。 A pad electrode forming step of forming a pad electrode on the substrate;
A conductive material forming step of forming a conductive material on the pad electrode so as to cover a probing mark formed on the pad electrode;
A method of manufacturing a semiconductor device including a wire bonding step of bonding a wire to a pad electrode covered with the probing mark,
In the conductive material forming step, the conductive material is applied to the tip of the wire, and the wire coated with the conductive material on the tip is pressed against the pad electrode, whereby the conductive material is A method of manufacturing a semiconductor device, wherein the probing marks are covered. 基板上にパッド電極を形成するパッド電極形成工程と、
前記パッド電極に形成されたプロービング跡が覆われるように導電性材料を前記パッド電極上に形成する導電性材料形成工程と、
前記プロービング跡が覆われたパッド電極にワイヤをボンディングするワイヤボンディング工程と
を含む半導体装置の製造方法であって、
前記導電性材料形成工程に於いて、前記導電性材料を前記パッド電極上に塗布し、前記塗布された導電性材料を前記プロービング跡が覆われるように形成することを特徴とする半導体装置の製造方法。 A pad electrode forming step of forming a pad electrode on the substrate;
A conductive material forming step of forming a conductive material on the pad electrode so as to cover a probing mark formed on the pad electrode;
A method of manufacturing a semiconductor device including a wire bonding step of bonding a wire to a pad electrode covered with the probing mark,
In the conductive material forming step, the conductive material is applied onto the pad electrode, and the applied conductive material is formed so as to cover the probing marks. Method. 導電性材料は、熱硬化性樹脂を含むことを特徴とする請求項１又は２に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the conductive material includes a thermosetting resin. 導電性材料形成工程に於いて、プロービング跡が覆われるように形成された導電性材料は液状であることを特徴とする請求項１乃至３のいずれかに記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein in the conductive material forming step, the conductive material formed so as to cover the probing marks is liquid. 半導体基板と、
前記半導体基板上に形成されたパッド電極と、
前記パッド電極上の一部に形成された導電性樹脂と、
前記パッド電極上及び前記導電性樹脂上に形成された外部接続端子と
を備えることを特徴とする半導体装置。 A semiconductor substrate;
A pad electrode formed on the semiconductor substrate;
A conductive resin formed on a part of the pad electrode;
A semiconductor device comprising: an external connection terminal formed on the pad electrode and the conductive resin.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009060028A (en) * 2007-09-03 2009-03-19 Fujikura Ltd Semiconductor device and method of manufacturing the same
ITMI20100843A1 (en) * 2010-05-12 2011-11-13 St Microelectronics Srl PROCESS OF MANUFACTURING OF INTEGRATED ELECTRONIC CIRCUITS AND CIRCUITS SO OBTAINED
KR101195265B1 (en) 2010-09-09 2012-11-14 에스케이하이닉스 주식회사 Method for wire bonding
JP2014187087A (en) * 2013-03-22 2014-10-02 Toshiba Corp Semiconductor device manufacturing method
KR102057721B1 (en) 2013-04-29 2019-12-19 엘지이노텍 주식회사 Light emitting device package and lighting system
CN113161319A (en) * 2021-04-23 2021-07-23 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009060028A (en) * 2007-09-03 2009-03-19 Fujikura Ltd Semiconductor device and method of manufacturing the same
ITMI20100843A1 (en) * 2010-05-12 2011-11-13 St Microelectronics Srl PROCESS OF MANUFACTURING OF INTEGRATED ELECTRONIC CIRCUITS AND CIRCUITS SO OBTAINED
US9275962B2 (en) 2010-05-12 2016-03-01 Stmicroelectronics S.R.L. Probe pad with indentation
US10186463B2 (en) 2010-05-12 2019-01-22 Stmicroelectronics S.R.L. Method of filling probe indentations in contact pads
KR101195265B1 (en) 2010-09-09 2012-11-14 에스케이하이닉스 주식회사 Method for wire bonding
JP2014187087A (en) * 2013-03-22 2014-10-02 Toshiba Corp Semiconductor device manufacturing method
KR102057721B1 (en) 2013-04-29 2019-12-19 엘지이노텍 주식회사 Light emitting device package and lighting system
CN113161319A (en) * 2021-04-23 2021-07-23 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
CN113161319B (en) * 2021-04-23 2022-03-22 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

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