US20020098620A1 - Chip scale package and manufacturing method thereof - Google Patents

Chip scale package and manufacturing method thereof Download PDF

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Publication number
US20020098620A1
US20020098620A1 US09/767,904 US76790401A US2002098620A1 US 20020098620 A1 US20020098620 A1 US 20020098620A1 US 76790401 A US76790401 A US 76790401A US 2002098620 A1 US2002098620 A1 US 2002098620A1
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Prior art keywords
substrate
acf
plurality
method
wafer
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US09/767,904
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Yi-Chuan Ding
Xin Lee
Kun-Ching Chen
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to US09/767,904 priority Critical patent/US20020098620A1/en
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, KUN-CHING, DING, YI-CHUAN, LEE, XIN HUI
Publication of US20020098620A1 publication Critical patent/US20020098620A1/en
Application status is Abandoned legal-status Critical

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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2924/013Alloys
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    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
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    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/30Technical effects
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    • H01L2924/30107Inductance
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base
    • Y10T29/49149Assembling terminal to base by metal fusion bonding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171Assembling electrical component directly to terminal or elongated conductor with encapsulating

Abstract

A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates to a chip scale package (CSP), and more specifically to a method of making the chip scale package at the wafer level. [0002]
  • 2. Description of the Related Art [0003]
  • As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and thin small outline package (TSOP). Typically, a CSP is 20 percent larger than the chip itself. The most obvious advantage of CSP is the size of the package; that is, the package is slightly larger than the chip. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path. [0004]
  • However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. No. 5,977,624 and 6,004,867. Usually, methods of making wafer-level CSPs mainly comprise a step of attaching a substrate directly onto a wafer that is used prior to being diced into individual chips. The substrate includes a plurality of units corresponding to the chips on the wafer, and the dimensions thereof are substantially the same as the wafer. [0005]
  • Normally, the wafer is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm/°C. and the substrate is usually formed of polymer having a coefficient of thermal expansion of 20-30 ppm/°C. Since there is a significant difference between the wafer and the substrate in CTE, the wafer and the substrate expand and contract in different amounts along with temperature fluctuations. This imposes both shear and bend stresses on the interface between the wafer and the substrate. Since the dimensions of the substrate are substantially the same as the wafer, the destructive stresses will accumulate. This greatly magnifies the reliability problems associated therewith. [0006]
  • Typically, the chips on the wafer go through a test to determine whether the chips are defective or not. After completing the testing process, at least some chips will be evaluated as defective. Therefore, in the conventional techniques described above, the substrate units attached on the defective chips are wasted. Similarly, it is very difficult to provide 100% good units on the substrate. Therefore, in the conventional techniques described above, the chips corresponding to defective units are also wasted. [0007]
  • Consequently, there is a need existed for a method of manufacturing chip scale packages at the wafer-level which reduces the problems and disadvantages associated with the above-described technique. [0008]
  • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to overcome, or at least reduce the problems and disadvantages associated with the above-described technique for fabricating chip scale packages at the wafer-level. [0009]
  • It is another objective of the present invention to provide a method for fabricating chip scale packages at the wafer-level in which the packaging yield is significantly enhanced. [0010]
  • The chip scale package in accordance with the present invention[0011] 1 mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The semiconductor chip has a plurality of bonding pads formed on the active surface thereof. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body.
  • According to the present invention, the method for manufacturing chip scale packages at the wafer-level comprises steps of: (a) providing a substrate strip including a plurality of substrates; (b) forming a plurality of metal bumps on the contact pads provided on the lower surface of each substrate; (c) attaching an anisotropic conductive adhesive film (ACF) onto the lower surface of the substrate strip to form a ACF/strip assembly; (d) cutting the ACF/strip assembly into individual substrates having ACF formed on the lower surface thereof (e) attaching the substrates onto the chips of a wafer through the ACF formed on each substrate such that the metal bumps on each substrate are electrically coupled to corresponding bonding pads on each chip; (f) forming grooves corresponding to boundary regions between the chips; (g) sealing the grooves; and (h) cutting along the sealing grooves so as to obtain individual chip scale packages. [0012]
  • According to the present invention, the CSP manufacturing method is characterized in that each of the substrates is attached onto the chips of the wafer one by one. This greatly reduces the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield. Furthermore, we could attach only accepted substrates onto the wafer so as to avoid wasting good chips of the wafer.[0013]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. [0014]
  • FIGS. [0015] 1-13 illustrate a method for manufacturing chip scale packages according to a preferred embodiment of the present invention; and
  • FIG. 14 is a cross sectional view of a chip scale package according to a preferred embodiment of the present invention.[0016]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIG. 14 shows a chip scale package [0017] 100 in accordance with a preferred embodiment of the present invention. The CSP 100 mainly comprises a substrate attached to the active surface of a semiconductor chip 130 through an anisotropic conductive adhesive film (ACF) 120. The lower surface of the substrate 110 is provided with a plurality of contact pads 110 a. A plurality of metal bumps 140 formed on the contact pads 110 a. Preferably, the metal bumps 140 are stud bumps formed from conventional wire bonding techniques. The semiconductor chip 130 has a plurality of bonding pads 130 a formed on the active surface thereof. The metal bumps 140 on the substrate are electrically coupled to corresponding bonding pads 130 a through the ACF 120. The side portions of the substrate 110 and the ACF 120 are sealed in a package body 150. One type of anisotropic adhesive suitable for forming the ACF 120 is known as a “z-axis anisotropic adhesive”. Z-axis anisotropic adhesives are filled with conductive particles 120 a to a low level such that the particles do not contact each other in the xy plane. Therefore, compression of the material in the z direction establishes an electrical path.
  • According to the present invention, the upper surface of the substrate [0018] 110 is provided with a plurality of solder pads (not shown) adapted for mounting solder balls. The contact pads 110 a on the lower surface of the substrate 110 are electrically coupled to corresponding solder pads through conductive lines (not shown) formed in the substrate. The substrate use with the invention can include any number of layers of conductor circuits if desired. Preferably, the substrate is a BGA substrate formed by any of a number of build-up technologies. The substrate may be formed from a core layer made of fiberglass reinforced BT (bismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin. Alternatively, the substrate may be a multi-layer ceramic substrate or a polyimide film substrate.
  • FIGS. [0019] 1-13 illustrate a method for manufacturing chip scale packages at the wafer-level according to a preferred embodiment of the present invention.
  • Referring to FIG. 1, in mass production, it is desirable to integrally form a plurality of substrates [0020] 110 in a strip (typically referred to as a “substrate strip 200”) preferably having street lines 200 a between the substrates for dicing.
  • FIG. 2 shows a plurality of metal bumps [0021] 140 formed on the substrate strip 200. The metal bumps 140 are disposed on the contact pads 110 a of each substrate 110. Preferably, the metal bumps 140 are stud bumps formed from conventional wire bonding techniques. Alternatively, the metal bumps 140 may be formed by a conventional bumping technology comprising the steps of: (a) forming an under bump metallurgy (UBM) on the contact pads of each substrate by, e.g., electroless nickel/gold plating, and (b) forming metal bumps on the UBM by, e.g., vapor deposition, electroplating or printing.
  • FIG. 5 shows an anisotropic conductive adhesive film (ACF) [0022] 120 with a release film on the lower surface of the ACF attached on an adhesive sheet 210. Usually, the anisotropic conductive adhesive film is shipped in the form of having release films protecting the upper and lower surfaces thereof. Firstly, the ACF with the release films thereon is attached onto the adhesive sheet 210 with the release film on the lower surface thereof facing the adhesive sheet. Then, the release film on the upper surface of the ACF is removed. Preferably, the adhesive sheet is a blue tape supported by a ring frame adapted to be used in wafer dicing.
  • Referring to FIG. 5 and FIG. 6, the substrate strip [0023] 200 with metal bumps formed on the lower surface thereof is attached onto the ACF 120 to form an ACF/strip assembly (see FIG. 6).
  • Referring to FIG. 7, the ACF/strip complex is cut into individual units. It is noted that the cutting depth is larger than the thickness of the substrate [0024] 110 and ACF 120, but are not deeper than the thickness of the substrate 110, ACF 120 and the release film 120 b on the lower surface of the ACF. Since the adhesive force between the ACF 120 is far less than the adhesive force between the release film 120 b and the adhesive sheet 210. So individual substrates 110 as well as ACF 120 thereon will release from the sawed-apart ACF/strip complex very easily.
  • Referring to FIG. 8, an automatic pick and place machine [0025] 230 picks one substrate 110 as well as ACF 120 thereon and accurately places it to the predetermined area of the wafer 240 (see FIG. 9). Usually, defective substrates of the substrate strip 200 are marked with white ink so that the defective substrates can be distinguished from other normal substrates. Therefore, the pick and place machine 230 can sort the normal substrates by recognizing the bad-substrate marks. Then, we may decide that only accepted substrates are attached onto the wafer so as to avoid wasting good chips of the wafer. Furthermore, defective chips of the wafer may also be attached with dummy substrates 235 (see FIG. 9) via common adhesives such as epoxy so as to avoid wasting good substrates and ACF thereon. It is noted that the dummy substrate has the same material as the substrate described above. However, wiring is not required for the dummy substrate thereby reducing cost.
  • Then, after conducting a thermocompression bonding, the substrate [0026] 110 is adhered to the chips 130 of the wafer 240 through the ACF 120 on the substrate, and the metal bumps 140 on each substrate 110 are electrically coupled to corresponding bonding pads 130 a on the chip 130 (see FIG. 10). It could be understood that the ACF may be thermosetting or thermoplastic. Thermal plastic anisotropic adhesives are heated to soften for use and then cooled for curing. Thermal setting anisotropic adhesives require heat curing at temperatures from 100° C. -300° C. for from several minutes to an hour or more.
  • Referring to FIG. 11, grooves [0027] 254 are formed corresponding to the boundary regions between chips 130 by a dicing blade 250. It is noted that the grooves 254 are defined deeper than the thickness of the substrate 110 and ACF 120, but are not deeper than the thickness of the substrate 110, ACF 120 and wafer 240. Preferably, the grooves 254 have a depth substantially equal to the thickness of the substrate 110 and ACF 120.
  • Referring to FIG. 12, underfill material is laid down along the grooves [0028] 254 by using an automated underfill dispense system. Then, the assembly of FIG. 12 is placed into an underfill curing oven, and then the underfill is cured to form a package body 150.
  • Preferably, the CSP manufacturing method of the present invention further comprises a step of mounting a plurality of solder balls (not shown) on the solder pads of the substrate. The mounting step is preferably performed after curing the underfill. The solder balls may be formed on the solder pads of the substrate by solder ball placing technique or stencil printing process. The solder balls act as external I/O electrodes of the chip scale package in accordance with the present invention. [0029]
  • Finally, referring to FIG. 13, another dicing blade [0030] 252 cuts the sealed groove and the wafer into individual chip scale packages 100 (see FIG. 14). It is noted that the dicing blade 252 is thinner than the dicing blade 250 used to form the grooves 254 such that the side portions of the ACF 120 is sealed by the package body 150 for protecting the package 100 against moisture and/or contamination from outside.
  • According to the present invention, the CSP manufacturing method is characterized in that each of the substrates is attached onto the chips of the wafer one by one. This greatly reduces the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield. [0031]
  • Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. [0032]

Claims (23)

What is claimed is:
1. A chip scale package comprising:
a substrate having opposing upper and lower surfaces, the substrate having a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads;
a plurality of metal bumps provided on the contact pads of the substrate;
a semiconductor chip having a plurality of bonding pads formed on the active surface thereof;
the substrate being attached to the active surface of the chip through an anisotropic conductive adhesive film (ACF) such that the metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip; and
a package body sealing the side portions of the substrate and the ACF.
2. The chip scale package as claimed in claim 1, wherein the substrate is a BGA (ball grid array) substrate.
3. The chip scale package as claimed in claim 1, wherein the package body is formed from an underfill material.
4. The chip scale package as claimed in claim 1, further comprising a plurality of solder balls bonded to the solder pads of the substrate.
5. The chip scale package as claimed in claim 1, wherein the metal bumps are stud bumps formed from conventional wire bonding techniques.
6. A method for manufacturing chip scale packages at the wafer-level, comprising steps of:
providing a substrate strip including a plurality of substrates, each substrate having opposing upper and lower surfaces, a plurality of contact pads on the lower surface of each substrate and a plurality of solder pads on the upper surface of each substrate wherein the contact pads are electrically coupled to corresponding solder pads;
forming a plurality of metal bumps on the contact pads of each substrate;
attaching an anisotropic conductive adhesive film (ACF) onto the lower surface of the substrate strip to form a ACF/strip assembly;
cutting the ACF/strip assembly into individual substrates having ACF formed on the lower surface thereof;
providing a wafer including a plurality of semiconductor chips wherein each chip has a plurality of bonding pads on the active surface thereof;
attaching the substrates onto the chips of the wafer through the ACF formed on each substrate such that the metal bumps on each substrate are electrically coupled to corresponding bonding pads on the chip;
forming grooves corresponding to boundary regions between the semiconductor chips;
sealing the grooves; and
cutting along the sealing grooves so as to obtain individual chip scale packages.
7. The method as claimed in claim 6, wherein the grooves are defined deeper than the thickness of the substrate and ACF, but are not deeper than the thickness of the substrate, ACF and wafer.
8. The method as claimed in claim 6, wherein the grooves have a depth substantially equal to the thickness of the substrate and ACF.
9. The method as claimed in claim 6, wherein the step of forming the grooves includes using a first blade and the step of cutting the wafer and the sealing grooves includes using a second blade having a thickness thinner than the first blade.
10. The method as claimed in claim 6, wherein the substrate is a BGA (ball grid array) substrate.
11. The method as claimed in claim 6, wherein the grooves are sealed by an underfill material.
12. The method as claimed in claim 6, further comprising the step of mounting a plurality of solder balls on the solder pads of the substrate.
13. The method as claimed in claim 6, wherein the metal bumps are stud bumps formed from conventional wire bonding techniques.
14. A method for manufacturing chip scale packages at the wafer-level, comprising steps of:
providing a substrate strip including a plurality of substrates, each substrate having opposing upper and lower surfaces, a plurality of contact pads on the lower surface of each substrate and a plurality of solder pads on the upper surface of each substrate wherein the contact pads are electrically coupled to corresponding solder pads;
forming a plurality of metal bumps on the contact pads of each substrate;
providing an anisotropic conductive adhesive film (ACF) with both upper and lower surfaces protected by a release film;
removing the release film from the upper surface of the ACF and attaching the ACF to an adhesive sheet with the release film on the lower surface thereof facing the adhesive sheet;
attaching the substrate strip to the ACF with the metal bumps on the lower surface of the substrate strip facing the ACF to form a ACF/strip assembly;
cutting the ACF/strip assembly into individual substrates having ACF formed on the lower surface thereof;
providing a wafer including a plurality of semiconductor chips wherein each chip has a plurality of bonding pads on the active surface thereof;
attaching the substrates onto the chips of the wafer through the ACF formed on each substrate such that the metal bumps on each substrate are electrically coupled to corresponding bonding pads on the chip;
forming grooves corresponding to boundary regions between the semiconductor chips;
sealing the grooves; and
cutting along the sealing grooves so as to obtain individual chip scale packages.
15. The method as claimed in claim 14, wherein the grooves are defined deeper than the thickness of the substrate and ACF, but are not deeper than the thickness of the substrate, ACF and wafer.
16. The method as claimed in claim 14, wherein the grooves have a depth substantially equal to the thickness of the substrate and ACF.
17. The method as claimed in claim 14, wherein the forming of the grooves includes using a first blade and the cutting of the wafer and the sealing grooves includes using a second blade, the second blade being thinner than the first blade.
18. The method as claimed in claim 14, wherein the substrate is a BGA (ball grid array) substrate.
19. The method as claimed in claim 14, wherein the grooves are sealed by an underfill material.
20. The method as claimed in claim 14, further comprising the step of mounting a plurality of solder balls on the solder pads of the substrate.
21. The method as claimed in claim 20, wherein the solder balls mounting step is performed after sealing the grooves and before cutting along the sealing grooves.
22. The method as claimed in claim 14, wherein the metal bumps are stud bumps formed from conventional wire bonding techniques.
23. The method as claimed in claim 14, wherein the adhesive sheet is a blue tape adapted to be used in wafer dicing.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030226640A1 (en) * 2001-03-30 2003-12-11 Osamu Yamazaki Method for manufacturing semiconductor device using adhesive sheet with embedded conductor bodies
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