TW451455B - Stacked semiconductor packaging - Google Patents

Abstract

The present invention discloses a structure and method of stacked semiconductor packaging for satisfying the requirement of high packaging density, flexible utilization space and simple processes. In the structure of stacked semiconductor packaging of the present invention, a plurality of semiconductor packaging devices are stacked up sequentially in chip-to-chip, substrate-to-substrate manner. The stacked devices are bonded by bonding glue, and substrates are connected by connecting circuits to form a device module. The device module can be connected to a circuit board through solder balls. Also, the device module can be erected on a circuit board depending on the requirement of the system space, and then the connecting circuit on one side of the device module is connected to the circuit board by soldering material and bonding glue.

Description

Λ 5 455 Five 'Invention Description (1) [Application Field of the Invention] Others = ㈣ About the structure and method, special structure and method of Γ stacked semiconductor structures. A semiconductor structure knot that stacks semiconductor structure elements [Background of the Invention] The conductor 22 sub products continue to develop toward the trend of lightness, thinness, fins, and smallness, and the half-size: also continues to develop with high density and multifunction Trend, small pieces: stack: ^ 11 becomes a combination of requirements for electronic products and semiconductor packaging, ϊ = carcass packaging, performance of components or wafers stacked up and down. Biography ΓΓί: Surface mounting method has higher mounting density and lead frame type dd: Stacked semiconductor mounting technology, for example, standard components: stack: and 2Ϊ are formed into a thinner mounting component, Then simply and electrically connect the outer legs of the wire frame. However, this technology has some disadvantages that limit its development. However, it is still stacked and cannot meet the extremely thin requirements, which is then achieved, and it lacks flexibility in application space. Keeping up the connection of Zhu's outer feet Therefore, in order to solve the above-mentioned simple 3 self-assembly method, a new stack of 4 semiconductors is required, and the development trend of arranging the connector + conductor structure is shown. [Objective and Summary of the Invention] The main purpose of the present invention, A w, structure and method, can achieve the structure of high-cardioid body structure.

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V. Description of the invention (2) Simple requirements. According to the semiconductor stacking structure of the present invention, a plurality of semiconductor-structured components are directly stacked with each other to be bonded to each other with a bonding glue, wherein the component includes a substrate and a wafer mounted on the substrate. The stacking method is to sequentially stack 7G pieces in a wafer-to-wafer 'substrate-to-substrate manner. The wafer is a thin and ultra-thin component, and the substrate is also manufactured using ultra-thin technology.' The density is required and the process is simple. According to the semiconductor stacking structure of the present invention, the substrates of the stacked components need to be pre-matched to complete the layout of the appropriate wires and I / O pads, and the overlapping substrates are connected to each other by the wiring phase. The connection to achieve a signal link has a large flexibility in the use of the structure. According to the structure of the semiconductor stack structure of the present invention, a heat sink can be sandwiched between the stacked 7C pieces' to improve the heat dissipation effect. In addition, the heat sink can have a supporting function, increase the strength of the stacked structure and facilitate assembly. A method for stacking structures according to the present invention includes the following steps: providing a plurality of semiconductor-structured components, wherein each of the components 1 has a substrate, and the substrate is pre-completed with the layout of the wires and the input / output pads, and -Wafer-on-chip structure is mounted on one surface of each substrate ±; the substrates of the plurality of components are connected in series by f: #; and 'the plurality of components are sequentially phased in a wafer-to-wafer, substrate-to-substrate manner The components are stacked, bonded between the bonding surfaces and bonded with a bonding adhesive to form a component module. According to the invention, a component module stacked in the above-mentioned method can be used, and the lowermost substrate is soldered to a circuit board by a solder ball.

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Five * Description of the invention (3) According to the requirements of the system space, the stacked component modules can also be erected on a circuit board, and then a connection line between the component module substrates is soldered to the circuit board with solder to achieve a signal connection. . The component module formed by the above-mentioned stacked configuration can be combined with another component module or another component, and a new component module is formed by overlapping solder balls. In order to make the objects, structural features and functions of the present invention useful, Further understanding is described in detail with the following illustrations: [Detailed description of the embodiment] "Figures 1A, 1B" shows the first embodiment of the present invention, in which four flip-chip components 10, 20, 30, and 40 'are assembled into a component module in a stacked manner and soldered to a circuit board 50 with solder balls 13. As shown in "Figure 1A", a first component 10 includes a first substrate 11 and a first: wafer 12, wherein the first wafer 12 is mounted on the chip in a FUp Chip manner. One surface of the first substrate 丨, and the first substrate 11 is pre-completed with proper wiring and I / O pad layout. On the other surface of the first substrate Π, solder balls 3 are attached. Similarly, the first component 20 includes a second substrate 21 and a second wafer 2. The second wafer 22 is mounted on a surface of the second substrate j 1 ^ in a flip-chip manner. The substrate 丨 丨 has also completed the layout of appropriate wires and input pads (I / 〇Pad) in advance. The first substrate 11 and the second substrate U can be connected between two adjacent sides' by a connection signal 101 on the flexible substrate 100. In addition, a third element 30 can also be serially connected to the second element 20 through a second connection line 102 in the same manner. And-the fourth element 40 is also the same through a third connection line

Page 6 451455 Five «Explanation of Invention (4) 1 03 is connected in series with the third element 30. The third element 30 also includes a third substrate 31 and a third wafer 32 on the third substrate 31, and the fourth element 40 also includes a fourth substrate 40. The substrate 41 and a fourth wafer 42 are flip-chip mounted on the fourth substrate 4 丨. When performing the stacking structure ', the bonding head 61 is coated with the dispensing head 60 on the bonding surface, and then the pieces are sequentially stacked in a wafer-to-crystal moon and substrate-to-substrate manner. The substrate configured by the aforementioned wafer may be a hard board or a soft board. As shown in "Figure 1B", the stacked structure according to the first embodiment of the present invention, the first element 丨 0 and the second element 20 are stacked in a wafer-to-wafer manner, wherein the first A wafer 丄 2 and the second wafer 22 are bonded with a bonding adhesive 61, and the first substrate 217 and the second substrate 21 are connected by the first connection line 101. The second element 20 and the third element 30 are stacked in a substrate-to-substrate manner, wherein the second substrate 21 and the third substrate 31 are bonded with a bonding adhesive 61, and the second substrate 21 and the third substrate 30 are bonded together. The three substrates are connected by the second connection line 02. The third component 30 and the fourth component 40 are stacked in a wafer-to-wafer manner, wherein the third wafer 32 and the fourth wafer 42 are bonded with a bonding adhesive 62, and the third substrate 31 and the The fourth substrates 41 are connected by the third connection line [03]. The first substrate 11 is combined with the circuit board 50 through the solder balls 13. In the above-mentioned first embodiment, a heat sink can also be sandwiched between the stacked components as shown in "Figure 1C". A first heat sink 71 is sandwiched between the first wafer 12 and the second wafer 22 and adhered to each other with a bonding adhesive 61. A second heat sink 7 2 is sandwiched between the second substrate 21 and the third substrate 31 and is bonded to each other with a bonding adhesive 61. In the third wafer 32 and the fourth crystal

戽 5 1 45 5 --------- 5. Description of the invention (5) A third heat sink 73 is sandwiched between the sheets 42 and adhered to each other with a bonding adhesive 61. "Figure 2A" is a schematic diagram of a stacking structure according to a second embodiment of the present invention. A first component module 1 is bonded to an electrical pole 50 through a solder ball 3, and a second component module 2 is stacked on the first component module 1 with a solder ball in between.丨 3 combined. The first component module includes a first component and a second component, which are stacked in the same manner as described in the first embodiment. The first component 10 includes a first substrate 11 and a first wafer 12 mounted on the first substrate. The second element 20 includes a second substrate 21 and a second wafer 22 that are mounted on the second substrate 21. The first element 10 and the second element 20 are stacked in a wafer-to-wafer manner, wherein the first wafer j 2 and the second wafer 2 are bonded with a bonding glue 61 and the first The substrate u and the second substrate 2! Are connected by a first connection line 104. The first substrate 丨 丨 is combined with the circuit board 50 through the solder balls 13 therebetween. The second component module 2 includes a third component 30 and a fourth component 40, which are constructed in the same manner as described in the first embodiment. The third component 30 includes a third substrate 31 and a third wafer 32 mounted on the first substrate 11. The fourth component 40 includes a fourth substrate 41 and a fourth wafer 42 mounted on the fourth substrate 41. Wherein, the third element 30 and the fourth element 40 are in a wafer-to-wafer manner, wherein the third wafer 32 and the fourth wafer 42 are bonded with a bonding adhesive 62, and the third The substrate 31 and the fourth substrate 41 are connected by a second connection line 105. The third substrate 31 is combined with the second substrate 21 of the first element module 1 by the solder balls 3 interposed therebetween.

Page 8 V. Description of the invention (6) In the second embodiment described above, the first element and the second element may be sandwiched between the third element and the fourth element. heat sink. As shown in "Figure 2B". A first heat sink 74 is sandwiched between the first wafer 12 and the second wafer 22 and adhered to each other with a bonding adhesive 61. A second heat sink 75 is sandwiched between the third wafer 32 and the fourth wafer 42 and is bonded to each other with a bonding adhesive 61. "Fig. 3A" shows the stacked structure of the third embodiment of the present invention. A stacked component module 3 is coupled to a circuit board 50 in an upright manner. The component module 3. Includes four components (first, second, third, and fourth components) 10, 20, 30, and 40 sequentially stacked in a wafer-to-wafer, substrate-to-substrate manner , The components are bonded to each other with a bonding glue 6 丨. The edge of the substrate of the first element 10 and the second element 20 is connected by a first connection line 106. The edge of the substrate of the second element 20 and the third element 30 is connected by a second connection line 107. The third element 30 and the edge of the substrate of the fourth element 40 are connected by a third connection line 08. Preferably, the first connection line 106 and the third connection line are located on the same side of the component module 3, and the second connection line; 〇7 is on the other side, and the middle part of the first connection line 106 is soldered to the circuit board by soldering 丨 5 to connect with a signal, and the third connection line 〇〇8 is joined by bonding Adhesive 6 丨 is fixed to the circuit board 50. σ # In the third embodiment described above, a heat sink can also be integrated between the components, as shown in "Figure 3B". A heat radiation month 76, 77, 78 is sandwiched between each of the components 10, 20: 3, 4'0 ', and is bonded to each other with a bonding adhesive 6 丨. In addition, the component die stage in the second embodiment described above can also be directly

Page 9 4 δ 1 45 5 * ----- 5. Description of the invention (7) The above-mentioned method is combined with a system circuit board, which is only for the purpose of this invention and not to limit the spirit of the invention. In the following, when it can be used as a suitable component, it is not limited to be replaced by a flip-chip structure. For example, it can be a mounted structure, it can also be a tape-and-reel structure, or it can be directly assembled on the base structure with a wafer. Therefore, all the inventions and modifications according to the present invention are the preferred embodiments of the invention patents, and those skilled in the art can make modifications without departing from, for example, the components of the semiconductor structure, but can use other methods. Equivalent changes made in the scope of the patent application for the assembly of wire bonding and tape bonding (Chip On Substrate) are covered.

Page 10 451455 Brief description of the drawings [Simplified description of the drawings] Figure 1A is a schematic diagram of the structure of each component before being stacked in the first embodiment of the present invention, and there is a glue head to apply bonding glue to the components. FIG. 1B is a schematic diagram of a stacked structure according to the first embodiment of the present invention. FIG. 1C is a schematic diagram of sandwiching a heat sink between components in the stacked structure of the first embodiment. FIG. 2A is a schematic diagram of a stacked structure of a second embodiment of the present invention. FIG. 2B is a schematic diagram of a heat sink being sandwiched between the first element, the second element, and the third element and the fourth element in the stacked structure of the second embodiment. FIG. 3A is a schematic diagram of a stacked structure according to a third embodiment of the present invention. FIG. 3B is a schematic diagram of a heat sink sandwiched between components in the stacked structure of the third embodiment. [Illustration of Symbols]

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1,2,3 component module 1 0,2 0,3 0,40 component 11,21,31,41 substrate 1 2, 2 2, 3 2, 42 wafer 13 solder ball 15 solder 50 circuit board 60 dispensing head 61 Glue 71, 72, 73 Heatsink Page 1 〖Page 4 5 1 45 5

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Claims (1)

451455 VI. Application for Patent Scope 1. A complex structure, a first covering is a surface glue phase line, a third-the first surface glue phase wiring other components such as the application of special phase stacking structure as the application The method of stacking special components is to apply at least half of the components in the stack of special components, the structural components, the two substrate surfaces, the bonding, the connecting components, the three substrate surfaces, the bonding, the road connecting components, the upper stacking area. Semiconducting composition. The semiconducting composition of the profit range. A semiconductor-embedded first substrate on which semiconductor-constructed components are stacked, and a first wafer is formed on a surface of the first substrate; and the first component is stacked and the second component is stacked Including Xi = and—the second wafer is configured on the second substrate == the wafer and the first wafer are bonded to each other by bonding r ~ the substrate and the first substrate are superimposed with a first connected Fendro two element The third element includes the plutonium, and the second wafer is configured between the two substrates of the third substrate and the second substrate through a bonding plate and the second substrate in a -second connection, which is the same as the above-mentioned elements. The method is in the order described in the third item 1 of the structure of a plurality of semi-conductor structures, the structure of '° structure, and the 70 pieces in the eighth, with the flip-chip i1 structure. Elementary structure of a plurality of conductor structures, in which the element is a tape and tape 11 Item: The elementary structure of a plurality of semiconductor structures is described, in which the element is a wafer Page 13 451455 -------- 6. The composition of the patent application scope is directly composed of the substrate ° 5. The semiconductor structure in which a plurality of semiconductor structured components are stacked as described in item 1 of the patent application scope The mounting structure, wherein the connection line is formed on a flexible substrate. 6. The structure of a semiconductor structure in which a plurality of semiconductor structured components are stacked as described in item 1 of the scope of the patent application, wherein the substrate on which the wafer is structured is a rigid plate. 7. The structure of a semiconductor structure in which a plurality of semiconductor structured components are stacked as described in item 1 of the scope of the patent application, wherein the substrate on which the wafer is structured is a flexible board. The semiconductor device structure described in the item, wherein a plurality of semiconductor device components are stacked, wherein the device is a thin device. 9. A semiconductor structure structure in which a plurality of semiconductor structured elements are stacked, comprising at least: a first element including a first substrate, and a first wafer structured on a surface of the first substrate A first component including a second substrate and a second wafer configured on a surface of the first substrate, 'the second wafer and the first wafer are bonded by a bonding adhesive' to The second component and the first component are overlapped and bonded; and a first connection line is formed on a flexible substrate, and a signal connects the first substrate and the second substrate. 1 1 〇. The semiconductor structure structure in which a plurality of semiconductor structures are stacked as described in item 9 of the scope of the application for a patent, wherein the element is denoted by = 1 see B 6-Scope of patent application 11. The zirconium structure of a semiconductor structure, in which a plurality of semiconductor structured components are stacked, as described in item 9 of the scope of the patent application, wherein the component is composed of a tape and reel structure. 1 2. The structure of a semiconductor structure in which a plurality of semiconductor structured components are stacked as described in item 9 of the scope of the patent application, wherein the component is composed of a wafer directly assembled on a substrate. 1 3. The structure of a semiconductor structure in which a plurality of semiconductor structured components are stacked as described in item 9 of the scope of the patent application, wherein the substrate on which the wafer is structured is a rigid plate. 14. The structure of a semiconductor structure in which a plurality of semiconductor structured components are stacked as described in item 9 of the scope of the patent application, wherein the substrate on which the wafer is structured is a flexible board. 15. The structure of a semiconductor structure in which a plurality of semiconductor structures are stacked as described in item 9 of the scope of the patent application, wherein the component is a thin component. 16. A semiconductor-structured structure in which a plurality of semiconductor-structured components are stacked as described in item 9 of the scope of the patent application, wherein the other surface of the first substrate and a circuit board are interposed by solder balls in between. Linked. 1 7. The structure of a semiconductor structure in which a plurality of semiconductor structured elements are stacked as described in item 9 of the scope of the patent application, further includes: a second element, which is stacked on the aforementioned second element, and the second element package 3 a third substrate and a second wafer are mounted on the winter surface of the second substrate, and the other surface of the third substrate is bonded to the other surface of the second substrate with a bonding adhesive; and Page 15 6. The patent application park The second connection line is formed on a flexible substrate, and the signal connects the aforementioned second substrate and the aforementioned third substrate. • The structure of a semiconductor structure in which a plurality of semiconductor structures are stacked as described in item i 7 of the scope of the patent application, further includes: a fourth element stacked on the third element, the fourth element A fourth substrate and a fourth wafer are configured on the fourth substrate, and the fourth wafer and the second wafer are bonded with each other by a bonding adhesive; and a third connection line is formed on a flexible The 'on-substrate' signal connects the second substrate and the fourth substrate. 19. The structure of the semiconductor structure in which a plurality of semiconductor structures are stacked as described in item 18 of the scope of the patent application, wherein the first wafer and the second wafer, the third wafer and the second wafer A heat sink is further sandwiched between the four wafers and between the second substrate and the third substrate. 20. The semiconductor structure structure in which a plurality of semiconductor structure components are stacked as described in item 18 of the scope of the patent application, wherein the other surface of the first substrate and the circuit board are in between Solder balls are connected. 21. The structure of a semiconductor structure in which a plurality of semiconductor structures are stacked in a stack of 70 pieces as described in item 18 of the scope of the patent application, wherein the plurality of components are erected on a circuit board and at least one of the connection lines The middle section is connected to the circuit board by an intervening solder. "2 2 * As described in item 9 of the scope of the patent application, the structure of a semiconductor structure in which one of a plurality of semiconductor structures is stacked 'further includes: a third element, which is stacked on the second element, said The third element contains-the third beauty board 451455 The scope of the patent application and the third wafer are configured on one surface of the third substrate, and the other surface of the third substrate and the other surface of the second substrate are interspersed with each other through a ball of spheres. link. 2 3. The structure of a semiconductor structure in which a plurality of semiconductor structured elements are stacked as described in item 22 of the scope of the patent application, further includes: a fourth element stacked on the third element, the fourth element The device includes a fourth substrate and a fourth wafer mounted on the fourth substrate, and the fourth wafer and the third wafer are bonded with a bonding adhesive; and a first connection line is formed on a flexible substrate. On the substrate, a signal is connected between the third substrate and the fourth substrate. 2 4. The structure of a semiconductor structure in which a plurality of semiconductor structured elements are stacked as described in item 23 of the scope of the patent application, wherein the first wafer and the second wafer and the third wafer and the fourth wafer A heat sink is sandwiched between the chips. 2 5. The semiconductor structure structure in which a plurality of semiconductor structure elements are stacked as described in item 23 of the scope of the patent application, wherein the other surface of the first substrate and a circuit board are interposed with solder therebetween. The balls are connected. 26 · —A semiconducting T method of stacking a plurality of semiconductor-constructed components includes at least the following steps: The government provides a plurality of semiconductor-constructed components, each of which has a-board 'the substrate system The layout of the wires and I / O pads has been completed in advance, and a chip is mounted on a surface of each substrate; ° the substrates of the plurality of components are connected in series by a connection line; and Seventeenth education 451455 VI < Patent application scope The plurality of components are sequentially stacked in a wafer-to-wafer, substrate-to-substrate manner ' and the bonding surfaces are bonded with each other to form a component module. 2 7. As described in item 26 of the scope of the patent application, the method of semiconductor assembly in which a plurality of semiconductor-structured components are stacked one by one further includes: a step of sandwiching heat sinks between the stacked components. . 28. The method of semiconductor assembly in which a plurality of semiconductor-structured components are stacked as described in item 26 of the scope of the patent application, further comprising the step of bonding the component module to a circuit board with solder balls. 29. The method of semiconductor assembly in which a plurality of semiconductor-structured components are stacked as described in item 26 of the scope of patent application, further comprising: erecting the component module on a circuit board and connecting them by soldering. The step of connecting the circuit board to a circuit described above. 30. The method for stacking a plurality of semiconductor structures, as described in item 26 of the scope of application for a patent, further comprising: stacking another component module to connect the component module with a solder ball. step. 3 1 _Female mouth y4 * y X | • A method of semiconductor structure of a plurality of semiconductor structures = f-phase stacked as described in item No. 26 of the Th patent scope ', wherein the wafer is mounted on the 32 soil The & way of the board is achieved by flip chip construction. Π '-The method of semiconductor assembly of f-phase stacking of a plurality of semiconductor structures as described in item 26 of the scope of the patent application, wherein the wafer is mounted on the 33 soil structure in a tape-and-reel configuration Reached. Λ The method of semiconductor assembly in which a plurality of semiconductor structures are stacked as described in item 26 of the patent application, wherein the wafer is mounted on the Page 18 VI. * Scope of patent application The method of the substrate is achieved by the wafer directly assembled on the substrate. 3 4. The method of semiconductor assembly in which a plurality of semiconductor-structured elements are stacked as described in item 26 of the scope of the patent application, wherein the connection line is formed on a flexible substrate. Page 19