TWI260069B - Memory module and method for manufacturing the same - Google Patents

Abstract

A memory module mainly includes a plurality of memory packages, a module sealant and a plurality of outer connecting pads. The memory packages are stacked one above the other. Each memory package includes a memory chip and a chip carrier having a plurality of outer fingers. The outer fingers are formed on a same side of the corresponding chip carriers. The module sealant seals the memory packages and has a mounting surface which exposes the side surfaces of the outer fingers. The outer connecting pads are formed on the mounting surface of the module sealant for connecting the side surfaces of the outer fingers. The outer connecting pads connect the memory packages to a modulus substrate. Thus the memory module has a smaller outline.

Description

1260069 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a memory module, and more particularly to a miniaturized case for sealing a plurality of memory packages to a module sealant. Body module and its manufacturing method. ~ [Prior Art] Increasing the memory capacity has always been the goal pursued by the improved memory module. The more memory chips are placed on a module substrate, the more the memory capacity of the sensible body module can be increased. The memory chip is arranged in a plurality of memory chips disposed on the module substrate, and the memory chips are disposed on the surface of the module substrate in a row and column two-dimensional matrix, so the memory module The group has a larger area. In order to achieve the purpose of increasing the memory capacity, the addressing mode of the memory is developed into a three-dimensional matrix arrangement. In addition to the original planar arrangement, the number of the memory chips is increased by stacking the memory chips. At the same time, the memory utilization of the module substrate is achieved, and a conventional high-capacity memory semiconductor package structure is disclosed, for example, in US Patent Publication No. 6,686,656, "Integrated Multi-Wafer Wafer Size Sealing Structure" There is a package structure in which a plurality of chip scale packages (CSPs) are vertically stacked. Referring to FIG. 1, the combined wafer size package structure i 00 includes a plurality of wafer size packages 110 and a plurality of sides. The edge bonding wire 14A and the encapsulant 15 〇 each of the 尺寸 chip size packages 110 includes a substrate 120, a wafer 130 and a plurality of inner bonding wires 111, the substrate 12 having an opening 121 And comprising a plurality of lines 122 formed on a surface 123 of the substrate 120 and extending to two corresponding sides 124 of the substrate 12, the substrate 12

1260069 V. The invention (2) is slightly larger than the wafer 130. The wafer 130 includes an active surface 131 and has a plurality of pads 132 arranged in a central position of the active surface 131. The active surface 131 of the wafer i 30 is bonded to the substrate 120 by a die bond 112, and the pads 132 are exposed to the opening 12 1 . The inner bonding wires 11 11 are connected to the pads. The pads 32 and the lines 122 of the substrate 120, a gel 113 seals the inner connecting wires 11'. The chip-sized packages 110 are bonded to each other by a glue 114, and the sides are stacked The bonding wire 1 40 is connected to the upper and lower adjacent wafer-sized packages 110, and the encapsulating layer 〇5 密封 seals the chip-sized packages 11 and the side bonding wires 4 〇, a plurality of solder balls 160 are disposed on the substrate 12 stacked on the lowermost layer, and the combined wafer size package structure 100 is connected to the two adjacent substrates by the side bonding wires 14 1 These lines 122, when one of the side wire bonds 14 is damaged, will affect the pile The electrical connection of the chip-sized packages 叠1〇 stacked on the upper side, so that the side soldering wires 140 can be connected to the slab=the road 122, the basics must be =0. According to the table, the size of the sheet must be gradually increased. Therefore, the larger the number of stacks of the chip-size packages 110, the larger the minimum area must be. Therefore, the area size of the combined wafer size is 20 The larger the system, the more i 2 2 and the t-to-county mines, the roads, the welding line, and the welding line, which is not suitable for the ancient [invention] 'Abandon's electronic products. The main object of the present invention is to provide a memory package including a plurality of memory packages, a module, a system, and a metal layer.

Page 8 1260069 V. Invention Description (3) Forming a plurality of column plates, each of which should be the face of the chip memory package, due to the manner in which the memory modules are stacked, the strip-shaped memory is thin The portable external finger of the invention has the same side joint surface of the board, and the external finger is connected vertically, and the connection is not required, and then the electronic product of the memory is used. And cause inferior goods. In the method of the present invention, the phase package package is an external pad, and the body package is a memory package comprising a memory chip and a plurality of external fingers, the side of which is The module sealing system joint surface is formed to reveal that the outer parts are coated in the module sealing system; the memory sealing module has a slight appearance, and the memory module is It is more suitable for the same carrier board and has the moisture resistance of a memory package group to reach the memory module, the electronic product. The second object is to provide a memory phantom in which a wafer carrier includes a plurality of surfaces externally connected to the wafer carriers, and the plurality of external pads are formed in a module to seal the external fingers. On the side, the external 塾 体 体 封装 封装 塾 § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § Shortly, it can be avoided that the connection of the electrical connecting elements is further provided by providing a memory module stacked with a plurality of memory packages, including a wafer carrier, each wafer carrier stacking A wafer carrier is formed on the side colloid for sealing the fingers, and the device is used in the group instead of the conventional one. Each finger, one of the wafer carrier and the pad is externally charged. Connection, for high-frequency junction failure, the manufacture of the group contains each complex

Page 9 1260069 V. Invention Description (4) 个: Bu =, 3 = in the same-side-memory package of the corresponding wafer carrier = open connection process, so each board, or bend Each 曰H4: a plurality of solder balls are connected to each wafer, and the plurality of lead pins are recorded on the έ board for internal electrical connection of a plurality of external pads. Pick up. a side of the r-clip for external electrical connection according to the present invention, a module pad, the memory device includes a plurality of sides, the module sealing surface to reveal the sealing body The memory module of the embodiment has a seal body and a gold body package stacked on each other with a memory chip and a crystal external finger, which are formed by a glue system to seal the external fingers. The side joint surface is connected to the plurality of outer stacks formed by the plurality of memory seal layers, and each of the memory package sheet carrier 'mother wafer carrier board is attached to the same side of the corresponding wafer carrier The package has a connection to form the sides of the external fingers. The invention will now be described by way of example with reference to the accompanying drawings. According to a specific embodiment of the present invention, referring to FIGS. 2 and 3, a memory module 2000 includes a plurality of memory packages 2, a module encapsulant 2 20, and a metal layer. 231, a plurality of external rafts 230 are formed, and the memory packages 20 0 are stacked on each other. Each of the memory packages 20 0 includes a memory chip 2 11 and a wafer carrier 2 i 2 . The body wafer 211 is disposed on the corresponding wafer carrier 2 1 2, each wafer carrying

Page 10 1260069 V. Description of invention (5)

The board 2 1 2 includes a plurality of lines, and the memory chips 21 1 can be connected by wire bonding or flip chip bonding to the corresponding lines of the chip carriers 2 1 2 in this embodiment. The memory chips 211 are connected to the corresponding pads of the wafer carriers 21 2 by flip chip bonding, and each circuit is connected with an external finger 2 1 3 , and the external fingers 2 1 3 are formed. On the same side of the corresponding wafer carrier 2 1 2, a colloid 2 15 seals the memory chips 2 1 1 and the lines, and exposes the external fingers 2丨3, preferably The memory packages 21 have a slightly identical appearance. In this embodiment, the memory packages 2 are arranged in the same direction, and the adhesives are bonded by a glue. 5 and the adjacent wafer carrier 21 2 ' Therefore, the external fingers 21 3 of the wafer carrier 2 1 2 are oriented in the same direction, and the wafer carrier 212 can be a flexible substrate (^16^1316) Substrate) or a printed circuit board. In this embodiment, the wafer carrier boards 2 1 2 are flexible substrates, Preferably, a plurality of reinforcing plates 21 6 (s t i f f ener ) are bonded to the corresponding wafer carriers 21 2 .

The module encapsulant 2 20 seals the memory packages 21 〇 and has a bonding surface 2 2 1 ′ to expose the side surfaces 2 1 4 of the external fingers 2 1 3 , and the metal layer 231 is formed on For the surface of the module encapsulant 2 2 , please refer to FIGS. 2 and 3 , the metal layer 231 includes the external 塾 ο , the external 塾 2 3 0 forms the module encapsulant 2 2 〇 The external interface 230 is perpendicular to the external fingers 213 of the wafer carrier 21 2, that is, the external connectors are connected to the external fingers 2丨3. The side surface 214, each of the external pads 203 can be connected to at least one of the external fingers 2丨3, such that the number of the external pads 230 is smaller than the number of the external fingers 2丨3.

Page 11 1260069 V. Inventive Note (6) Ground, the area of the external pads 230 is greater than the area of the side of the corresponding external fingers 213, and the 4 points of the external pads 2 3 0 are perpendicular to the wafer carriers. 2 1 2 direction connection mother one § memory box 2 1 q the same message finger 2 1 3 The module substrate 2 4 G has a plurality of connections 塾 2 41 , and the interface 221 of the module encapsulant 2 20 is connected to the module substrate 240 by an electrical coupling medium 242 to turn on the external pads 23 . The module substrate 24 includes the connection pads 24 1, and the electrical coupling medium can be an anisotropic conductive adhesive (ACF), a solder or a plurality of bumps. In this embodiment, a plurality of solder balls 250 may be disposed on the other surface of the module substrate 240. Alternatively, a plurality of gold fingers may be disposed on one side of the module substrate 24 for insertion. To a motherboard, communication board or other 2 connection boards. In addition, the memory module 2 of the present invention may further comprise a suitable passive component and a controller, wherein the passive components may be disposed in each memory package, and the component 21 0 The controller can be disposed on the module substrate 240 or other external electronic device (not shown). The method for manufacturing the memory module 200 according to the present invention is described in detail below. Referring to FIG. 4A, the memory packages 210 are stacked on top of each other. The memory packages 21 are externally connected. 213 is formed on the same side of the corresponding wafer carrier 21 2, and the external fingers 2丨3 are oriented in the same direction; please refer to the “FIG., Form the Module Sealant” 220 to seal The memory package 21〇; please refer to the figure, cut the module encapsulant 22 0 near one side of the external finger 213, so that the module

Page 12 1260069 V. Description of invention (7)

The colloid 220 has the joint surface 221 and the side surface 214 of the outer finger 213 is exposed; please refer to FIG. 4D to form the metal layer 231 on the surface of the module seal body 220 by electroplating, and cover the metal layer 231. The side surface 214 of the external finger 213; please refer to FIG. 4E again to form the outer pad 2 3 0 in the manner of laser cutting the metal layer 2 3 1 to the bonding surface 2 2 of the module sealing body 2 2 1. The external 塾2 3 0 is perpendicularly connected to the side 2 1 4 of the external fingers 2 丨 3; please refer to FIG. 2 again. In this embodiment, an anisotropic conductive adhesive is used. The film, ACF is electrically coupled to the bonding surface 221 of the module encapsulant 220 and the module substrate 24 to turn on the external pads 230 to complete the memory module 2 .

In the above memory module 2, the memory packages 210 are stacked to achieve the miniaturization of the memory module 2 instead of the long memory module. Therefore, the memory module 2 is more suitable for use in a thin and portable portable electronic product, and the external 230 series are vertically connected to the external fingers 213 of each of the wafer carriers 212. The body package 2 can be externally made by the external pads. In the process, a plurality of electrical connection elements can be omitted for internal transmission, so that the memory module has a shorter Electrical H-channel, = 'and the memory module means that the memory packages are not exposed and therefore have better moisture resistance. The scope of the invention is defined by the scope of the invention, without departing from the spirit and scope of the invention. The scope of protection of the present invention is subject to the circumstance, and any changes and modifications made by the person skilled in the art,

Page 13 1260069 Simple illustration of the diagram [Simple description of the diagram]

/1 Fig. 1 is a schematic view; Fig. 2 is a cross-sectional view of a memory module according to one embodiment of the present invention. FIG. 3 is a schematic view showing a joint surface of one of the memory modules according to the present invention. And 4th to 4th drawings: a method of manufacturing the memory module according to the present invention, a cross-sectional view of a memory package in a manufacturing process. a cross-section of a conventional integrated polycrystalline germanium-sized package structure;

Brief description of component symbols: 1 0 0 combined wafer size package structure 110 wafer size sealer 111 internal connection wire 112 113 sealant 114 120 substrate 121 123 surface 124 130 wafer 131 140 side wire 150 200 memory module 210 Memory Package 211 Memory Chip 212 213 External Finger 214 216 Reinforced Plate 220 Module Sealant 221 Adhesive Adhesive Opening 1 2 2 Line Side Active Surface 132 Pad Packing Glue 160 Solder Ball Wafer Carrier Side 21 5 sealant joints

1260069

Brief description of the diagram 230 external pads 231 metal layer 240 module substrate 241 connection pad 242 electrically coupled medium 250 fresh ball

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Claims (1)

1260069 VI. Scope of Application Patent [Scope of Application] 1. A memory module comprising: a plurality of ά 忆 体 package, which are stacked on each other, each memory package comprising a memory chip and a a wafer carrier, each wafer carrier comprising a plurality of external fingers formed on the same side of the corresponding wafer carrier; a pole assembly encapsulant sealing the memory packages and having an engagement The surface is formed to expose the sides of the external fingers; and a plurality of external pads formed by a metal layer are formed on the joint surface of the module seal body and connected to the sides of the external fingers. 2. The memory module of claim 1, wherein the external pads are vertically connected to the external fingers of the wafer carriers. 3. The memory module of claim 2, wherein the number of the external pads is less than the number of the external fingers of the wafer carrier 4, as described in the scope of the patent application. The memory module, the area of the bean is larger than the side surface of the external fingers of the wafer carrier 5, + the memory module as described in the scope of the patent application, the group of beans The substrate has a plurality of connection pads, and the connection pads of the n groups of substrates. An external mat and the mold 6. The memory module according to claim 5, wherein the plurality of solder balls are directly disposed on the module substrate. And eight further comprise, as described in the patent application scope, the memory module, wherein the Page 16 1260069 Memory packages have the same size appearance. S8. The memory module of claim 1, wherein the plurality of carrier substrates are from a flexible substrate and a printed circuit board. 9. The memory module of claim 1, wherein each of the memory packages comprises a suffener that is bonded to the corresponding wafer carrier. 10. A method of fabricating a memory module, comprising: stacking a plurality of memory packages stacked on each other, each memory package comprising a memory chip and a wafer carrier, each wafer carrier comprising a plurality of An external finger is formed on the same side of the corresponding wafer carrier; a module encapsulant is formed to seal the memory packages; and the module encapsulant is cut to have a bonding of the module encapsulant Forming a metal layer on the module sealing body, the metal layer is formed on the bonding surface of the module sealing body; and a plurality of external pads are formed by the metal layer The external pads are connected to the sides of the external fingers. 1 1. The method of manufacturing a memory module according to claim 10, wherein the metal layer is formed by electroplating. 12. The method of fabricating a memory module according to claim 1, wherein the external pads are formed by laser cutting the metal layer. 1 3. The manufacturer of the memory module as described in the first paragraph of the patent application scope Page 17 1260069 ——-~^ VI. Application for patent scope and law, in which the external fingers of this &amp;&amp; ^ u 0 carrier board are vertical, T, and the external pads and the month Privately connected. 14. The memory module of claim 10, wherein the number of the external pads is less than the number of the δ Λ fingers of the wafer carriers. 15. The method of manufacturing a memory module according to claim 10, wherein the area of the external pads is greater than the side area of the external fingers. The method of loading a memory module according to the first aspect of the invention, further comprising: bonding the bonding surface of the module sealing body to a module substrate; the module substrate has a plurality of The connection pad is electrically connected to the external device. The method for manufacturing a memory module according to claim 16 is further comprising a plurality of solder balls attached to the module substrate. The method of manufacturing a memory module as described in claim </ RTI> wherein the memory packages have the same size appearance. 19. The method of claim 4, wherein the wafer carrier is selected from the group consisting of a flexible substrate and a printed circuit board. The memory module method of claim 10, wherein each of the memory packages comprises a reinforced stencil & splicer, which is bonded to the corresponding wafer carrier . Page 18