TWI395319B - Semiconductor assembly to avoid break of solder joints of pop stack - Google Patents

Description

Semiconductor combination structure to avoid package joint breakage

This invention relates to semiconductor devices, and more particularly to a semiconductor composite construction that avoids breakage of package stack contacts.

According to the semiconductor technology and network communication products, the functions of computers and network communication should be diversified, portable and light and thin. Therefore, stacked package on package (POP) applications are growing rapidly. The stacked package stack (POP) is also called a 3D package, that is, after the integrated circuit completes the wafer process and the package process, the plurality of integrated circuit package components are stacked on each other to be combined into a surface-free joint. High-density integrated device for area. POP is packaged and tested by two separate package components and then surface-bonded to reduce process risk and improve product yield.

Please refer to FIG. 1 for a schematic cross-sectional view of a conventional semiconductor composite structure. The semiconductor composite structure 100 includes a lower first semiconductor package 110 and an upper second semiconductor package 120, both of which are soldered together via solder balls 130 using surface mount technology (SMT). The inner surface 111B of the first substrate 111 of the first semiconductor package 110 is provided with the first wafer 112, the first encapsulant 113 is formed, and the intermediate solder ball 130 or the interposer substrate located at the periphery of the substrate is disposed, and the inner surface 111B of the first substrate 111 is further There is a first finger 111C for wire bonding to the first wafer 112. A plurality of first substrate contacts 115 are further disposed around the inner and outer surfaces 111A, 111B of the first substrate 111 for the solder balls 130 to be disposed. Therefore, a position where the sealant is not sealed for soldering the solder ball 130 must be reserved around the inner surface 111B of the first substrate 111, so that the size of the first substrate 111 cannot be reduced. However, in various heating processes such as reflow, the warpage phenomenon of the substrate may be caused by the difference in thermal expansion coefficient between different materials, or the stress phenomenon may occur in the package stack, which may cause the solder joints of the solder balls 130 to be broken, resulting in poor bonding. Reduce the yield and reliability of semiconductor packages.

Another invention is a semiconductor composite structure in which a plurality of pins are disposed around the package and are respectively inserted into the connection holes of the substrate to electrically connect the upper and lower packages. However, when the substrate warpage occurs, the stitches may also be bent or broken.

The main purpose of the present invention is to provide a semiconductor composite structure that avoids breakage of the package stack contacts. The substrate contacts at the periphery of the substrate can be omitted, and the joint solder joints of the conventional POP stack can be broken to generate electricity between the upper and lower packages. The problem of sexual connection failure.

A second object of the present invention is to provide a semiconductor composite structure that avoids breakage of a package stack joint. The peripheral board portion of a conventional substrate to which a substrate joint is to be reserved can be omitted, and the size of the package stack assembly structure can be effectively reduced to achieve a semiconductor package. Light and short, and reduce substrate warpage.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor assembly structure for avoiding breakage of a package stack joint, and mainly comprises a first semiconductor package, a second semiconductor package and an interposer. The first semiconductor package includes a first substrate, a first wafer disposed on the first substrate, and a first encapsulant sealing the first wafer, wherein a top surface of the first encapsulant is formed A first wafer revealing surface of the first wafer is partially exposed, and the first wafer revealing surface is provided with a plurality of first wafer contacts. The second semiconductor package includes a second substrate, a second wafer disposed on the second substrate, and a second encapsulant sealing the second wafer, wherein a center of the top surface of the second encapsulant is formed A second wafer exposure surface of the second wafer is partially exposed, and the second wafer exposure surface is provided with a plurality of second wafer contacts. The interposer substrate is disposed between the first wafer exposure surface and the second wafer exposure surface. The second semiconductor package is reversely stacked on the first semiconductor package such that the second wafer exposure surface is aligned with the first wafer exposure surface, and the interposer is connected to the first The wafer contacts are in contact with the second wafers.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor composite structure, the interposer substrate may be a semiconductor material, and the interposer substrate may have a size no larger than any of the first wafer and the second wafer.

In the aforementioned semiconductor composite structure, the interposer may be a dummy wafer having a via hole.

In the foregoing semiconductor composite structure, the center of the top surface of the first encapsulant and the second encapsulant may be recessed.

In the above semiconductor combination structure, the upper surface of the interposer may be provided with a plurality of metal bumps to electrically connect the first wafer contacts and the second wafer contacts.

In the foregoing semiconductor composite structure, a conductive paste may be further included to be connected to the metal bumps to the corresponding first and second wafer contacts.

In the foregoing semiconductor composite structure, the conductive paste may be an anisotropic conductive paste to fill a gap from the interposer to the exposed surface of the first wafer and to the exposed surface of the second wafer.

In the foregoing semiconductor combination structure, the first semiconductor package may further include a plurality of first bonding wires connecting a plurality of first peripheral pads of the first wafer and the plurality of first substrates The first sealing body seals the first bonding wires.

In the foregoing semiconductor combination structure, the second semiconductor package may further include a plurality of second bonding wires connecting the plurality of second peripheral pads of the second wafer and the plurality of second portions of the second substrate The second sealing body seals the second bonding wires.

In the foregoing semiconductor composite structure, the first semiconductor package may further include a plurality of first solder balls disposed on an outer surface of the first substrate.

In the foregoing semiconductor combination structure, the second semiconductor package may further include a plurality of second solder balls disposed on an outer surface of the second substrate.

In the foregoing semiconductor composite structure, the first wafer exposure surface may be a central area of the active surface of the first wafer.

In the foregoing semiconductor combination structure, the first wafer exposure surface may be a central region of the back surface of the first wafer, and the first wafer is flip-chip bonded to the first substrate by a plurality of first flip-chip bumps. .

In the foregoing semiconductor composite construction, the first encapsulation system can completely cover the inner surface of the first substrate.

In the foregoing semiconductor composite construction, the second semiconductor package can be substantially identical to the first semiconductor package.

It can be seen from the above technical solutions that the semiconductor combined structure of the present invention for avoiding breakage of the package stack contacts has the following advantages and effects:

1. The interposer can be connected to the wafer contact at the center of the package as a technical means, instead of the conventional solder ball or the peripheral interposer connecting the substrate contacts at the periphery of the package to avoid stress on the substrate warpage or package stack. The resulting solder joint breaks.

2. The first wafer and the second wafer having a size of the interposer substrate are not more than one of the technical means, and the stress generated by the package stack can be reduced.

Third, the second semiconductor package can be stacked on the first semiconductor package and the interposer is connected to the wafer contact at the center of the package as one of the technical means, and the substrate can be omitted. The peripheral plate portion of the point can effectively reduce the size of the package stacking structure, achieve the requirements of thinness and shortness of the semiconductor package, and reduce substrate warpage.

4. The wafer contacts located at the center of the package can be connected by the interposer substrate as one of the technical means for carrying and connecting the second semiconductor packages of different sizes.

5. The specific combination relationship between the interposer substrate and the conductive adhesive can be used as one of the technical means, and the interposer substrate, the first wafer contact and the second wafer contact are covered by the conductive adhesive to avoid external pollution.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with a first embodiment of the present invention, a semiconductor composite structure that avoids breakage of package stack contacts is illustrated in a cross-sectional view of FIG. 2 and a top view of a semiconductor package used in FIG. The semiconductor composite structure 200 mainly includes a first semiconductor package 210, a second semiconductor package 220, and an interposer substrate 230. In particular, in order to make it easier to understand the structural features of the present invention, the magnification of FIG. 2 is larger than the magnification of FIG. 1, and when the wafers have the same size when the same semiconductor process capability is used, in fact, FIG. The structure of the present invention is more miniaturized than the conventional structure of Fig. 1.

The first semiconductor package 210 includes a first substrate 211, a first wafer 212 disposed on the first substrate 211, and a first encapsulant 213 sealing the first wafer 212. A first exposed surface 214 of the first wafer 212 is partially formed in the center of the top surface of the colloid 213. The first wafer exposure surface 214 is provided with a plurality of first wafer contacts 215.

The second semiconductor package 220 includes a second substrate 221, a second wafer 222 disposed on the second substrate 221, and a second encapsulant 223 sealing the second wafer 222. A second wafer exposure surface 224 partially exposing the second wafer 222 is formed in the center of the top surface of the colloid 223. The second wafer exposure surface 224 is provided with a plurality of second wafer contacts 225. Preferably, the first semiconductor package 210 and the second semiconductor package 220 are packages having the same structure and size, that is, the second semiconductor package 220 can be substantially the same as the first semiconductor package. 210, to simplify the production process, but can also be different.

The substrates 211 and 221 may be a multi-layer printed wiring board made of a glass fiber reinforced resin such as FR-4, FR-5 or BT resin, or a flexible circuit board of polyamidamide. The wafers 212 and 222 can be adhered to the inner surfaces 211B and 221B of the substrates 211 and 221 by using a double-sided tape, a liquid epoxy adhesive or a B-stage colloid. Thereafter, the plurality of first peripheral pads 212A of the first wafer 212 and the plurality of first peripheral fingers 211C of the first substrate 211 are connected by a plurality of first bonding wires 216, and the first sealing body 213 is further connected to the first sealing member 211C. The first bonding wires 216 are sealed. Similarly, a plurality of second bonding pads 226 can be used to connect the plurality of second peripheral pads 222A of the second wafer 222 and the plurality of second peripheral fingers 221C of the second substrate 221, and the second sealing body can be used. The second bonding wires 226 are sealed 223 to complete the first semiconductor package 210 and the second semiconductor package 220. As shown in FIG. 3, the first peripheral pads 212A and the second peripheral pads 222A are arranged in a single (multiple) row around the active surfaces of the first wafer 212 and the second wafer 222. In order to connect the external terminals of the integrated circuit, the first peripheral pads 212A and the second peripheral pads 222A are usually aluminum or copper pads. The first chip contacts 215 and the second chip contacts 225 can be arranged in an array in the center of the first wafer 212 and the second wafer 222 active surface.

Specifically, as shown in FIG. 2, the center of the top surface of the first sealant 213 and the second sealant 223 may be recessed to expose the first wafer exposed surface 214 and the second wafer exposed surface. 224. The first wafer exposure surface 214 can be a central region of the active surface of the first wafer 212. The second wafer exposure surface 224 can also be the central area of the active surface of the second wafer 222. When the second semiconductor package 220 is reversely stacked, the active surface of the first wafer 212 faces upward. The active surface of the second wafer 222 is facing downward. As shown in FIG. 3, the first wafer exposure surface 214 is not covered by the first encapsulant 213, and the first wafer contacts 215 are disposed. Similarly, the second wafer exposure surface 224 is not covered by the second encapsulant 223, and the second wafer contacts 225 are disposed. In detail, the first wafer contacts 215 and the second wafer contacts 225 may be contacts of a reconfigurable circuit layer formed by sputtering or photolithography. The relocation wiring layer is covered with an insulating film called a passivation film composed of SiN or polyimide, which is a surface protective film, in addition to the contact.

The interposer substrate 230 is disposed between the first wafer exposure surface 214 and the second wafer exposure surface 224. The second semiconductor package 220 is reversely stacked on the first semiconductor package 210 such that the second wafer 222 is exposed to face the first wafer exposure surface 214, and the interposer substrate 230 is The first wafer contacts 215 and the second wafer contacts 225 are connected. Therefore, the interposer substrate 230 is connected to the wafer contacts 215 and 225 located at the center of the package. Instead of the conventional interposer substrate connecting the substrate contacts located at the periphery of the package, the soldering of the substrate 211, 221 or the soldering of the package stack can be avoided. The point breaks. Moreover, since the wafer contacts 215 and 225 are disposed at the center of the package members 210 and 220, the substrates 211 and 221 do not need to retain the unsealed peripheral plate portion to set the substrate contacts of the POP stack for the ball placement. Or setting the peripheral interposer substrate can effectively reduce the size of the package stacking composite structure, and achieve the requirements of thinness and shortness of the semiconductor package.

Specifically, as shown in FIG. 2, the interposer substrate 230 can be made of a semiconductor material, and the size of the interposer substrate 230 can be no larger than any of the first wafer 212 and the second wafer 222, which can reduce package stacking. Stress. A plurality of metal bumps 231 are disposed on the upper surface of the interposer substrate 230. The metal bumps 231 are electrically connected to the first wafer contacts 215 and the second wafer contacts 225. The metal bumps 231 may be composed of solder, stud bump, tin/lead (Sn/Pb) alloy, gold (Au) or other materials. In detail, the interposer substrate 230 can be a dummy wafer having a plurality of turns-through holes 232. The through holes 232 pass through the interposer 230 and can be formed by a drilling and etching process. The through holes 232 correspond to the metal bumps 231 on the upper and lower surfaces of the interposer substrate 230 to electrically connect the first semiconductor package 210 and the second semiconductor package 220.

In addition, as shown in FIG. 2, the semiconductor composite structure 200 may further include a conductive paste 240 connected to the metal bumps 231 to the corresponding first and second wafer contacts 215, 216. Preferably, the conductive paste 240 can be an anisotropic conductive paste (ACP) to fill the interposer substrate 230 to the first wafer exposed surface 214 and to the second wafer exposed surface 224. The interposer substrate 230, the first wafer contacts 215 and the second wafer contacts 225 are covered by the conductive paste 240 to avoid external pollution. The anisotropic conductive paste contains conductive particles to electrically connect the metal bumps 231 to the first wafer contacts 215 and the second wafer contacts 216 without directly soldering to the first wafer. Contact 215 and the second wafer contacts 216 have no metal diffusion problems.

When performing the package stacking, the conductive paste 240 may be pre-coated on the first wafer exposed surface 214 (ie, the central recess of the top surface of the first sealant 213), and then the interposer substrate 230 is disposed. And performing a second application on the upper surface of the interposer substrate 230, and then stacking the second semiconductor package 220 on the interposer substrate 230, and the second wafer contacts 225 and the first wafers The contacts 215 are aligned with the metal bumps 231. It is worth mentioning that the interposer substrate 230 can carry and bond the second semiconductor package 220 of different sizes to make the package more flexible.

In addition, the first semiconductor package 210 may further include a plurality of first solder balls 217 disposed on an outer surface 211A of the first substrate 211. The second semiconductor package 220 may further include a plurality of second solder balls 227 disposed on an outer surface 221A of the second substrate 221. The solder balls 217, 227 can be electrically connected to an external printed circuit board (PCB) or stacked in another semiconductor.

In the second embodiment of the present invention, another semiconductor assembly structure for avoiding breakage of the package stack contacts is disclosed. A cross-sectional view of the fourth embodiment is illustrated in FIG. 4, wherein the same main elements as those of the first embodiment will be denoted by the same reference numerals. . In this embodiment, the semiconductor composite structure 300 can be a memory module or a memory card, and the chips 212 and 222 can be SDRAM chips (synchronous dynamic random access memory) and DDR SDRAM chips (double data). Transmission rate synchronous dynamic random access memory), DDR II SDRAM chip, DDR III SDRAM chip, SRAM chip (static random access memory) or Flash chip (flash memory). The outer surface 211A of the first substrate 211 and the outer surface 221A of the second substrate 221 include a plurality of external fingers 350. The external fingers 350 are exposed and formed on the corresponding substrates 211 and 221 The same side. The semiconductor composite structure 300 achieves miniaturization of the memory module in a stacked manner. The semiconductor packages 210 and 220 can be externally electrically connected by the external fingers 350. The solder balls 217 and 227 can be omitted in the process, and the internal components of the semiconductor packages 210 and 220 are not It is exposed and therefore has better moisture resistance.

In a third embodiment of the present invention, another semiconductor assembly structure 400 for avoiding breakage of the package stack contacts is disclosed. FIG. 5 is a schematic cross-sectional view of the fifth embodiment, wherein the same main elements as those of the first embodiment will be denoted by the same symbols. It. The semiconductor assembly structure 400 mainly includes a first semiconductor package 210, a second semiconductor package 220, and an interposer substrate 230.

In this embodiment, the first wafer 212 of the first semiconductor package 210 has a first active surface 412B and a first first back surface 412C. The second wafer 222 has a second active surface 422B and a second opposite back surface 422C. The first wafer exposure surface 214 can be a central region of the first back surface 412C of the first wafer 212. Therefore, in the embodiment, the first active surface 412B of the first wafer 212 faces the first substrate 210. Similarly, the second active surface 422B of the second wafer 222 faces the second substrate 220. The first peripheral pads 212A and the first wafer contacts 215 are disposed on the first back surface 412C, and can be realized by using one of the crystal backs to reconfigure the wiring layer. The first wafer 212 is flip-chip bonded to the inner surface 211B of the first substrate 211 by a plurality of first flip-chip bumps 418. The second wafer 222 is flip-chip bonded to the inner surface 221B of the second substrate 211 by a plurality of second flip-chip bumps 428. Moreover, the first encapsulant 213 can completely cover the inner surface 211B of the first substrate 211 and seal the first flip-chip bumps 418. Therefore, the first substrate 210 does not need to reserve an unsealed peripheral plate portion. Conventional substrate contacts can be omitted. The second semiconductor package 220 can be substantially the same as the first semiconductor package 210, and detailed components and functions will not be described again.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100. . . Semiconductor composite structure

110. . . First semiconductor package

111. . . First substrate

111A. . . The outer surface

111B. . . The inner surface

111C. . . First finger

112. . . First wafer

113. . . First gel

115. . . First substrate contact

120. . . Second semiconductor package

130. . . Solder ball

200. . . Semiconductor composite structure

210. . . First semiconductor package

211. . . First substrate

211A. . . The outer surface

211B. . . The inner surface

211C. . . First peripheral finger

212. . . First wafer

212A. . . First peripheral pad

213. . . First gel

214. . . First wafer exposure surface

215. . . First wafer contact

216. . . First wire bond

217. . . First solder ball

220. . . Second semiconductor package

221. . . Second substrate

221A. . . The outer surface

221B. . . The inner surface

221C. . . Second peripheral finger

222. . . Second chip

222A. . . Second peripheral pad

223. . . Second seal

224. . . Second wafer exposure surface

225. . . Second wafer contact

226. . . Second wire

227. . . Second solder ball

230. . . Intermediary substrate

231. . . Metal bump

232. . .矽 through hole

240. . . Conductive plastic

300. . . Semiconductor composite structure

350. . . External finger

400. . . Semiconductor composite structure

412B. . . First active surface

412C. . . First back

418. . . First flip chip bump

422B. . . Second active surface

422C. . . Second back

428. . . Second flip chip bump

Fig. 1 is a schematic cross-sectional view showing a conventional POP type semiconductor composite structure.

2 is a schematic cross-sectional view of a semiconductor composite structure for avoiding breakage of package stack contacts in accordance with a first embodiment of the present invention.

Figure 3 is a plan view of a semiconductor package used in a semiconductor composite structure in accordance with a first embodiment of the present invention.

Figure 4 is a cross-sectional view showing a semiconductor composite structure for avoiding breakage of package stack contacts in accordance with a second embodiment of the present invention.

Figure 5 is a cross-sectional view showing a semiconductor composite structure for avoiding breakage of package stack contacts in accordance with a third embodiment of the present invention.

200. . . Semiconductor composite structure

210. . . First semiconductor package

211. . . First substrate

211A. . . The outer surface

211B. . . The inner surface

211C. . . First peripheral finger

212. . . First wafer

212A. . . First peripheral pad

213. . . First gel

214. . . First wafer exposure surface

215. . . First wafer contact

216. . . First wire bond

217. . . First solder ball

220. . . Second semiconductor package

221. . . Second substrate

221A. . . The outer surface

221B. . . The inner surface

221C. . . Second peripheral finger

222. . . Second chip

222A. . . Second peripheral pad

223. . . Second seal

224. . . Second wafer exposure surface

225. . . Second wafer contact

226. . . Second wire

227. . . Second solder ball

230. . . Intermediary substrate

231. . . Metal bump

232. . .矽 through hole

240. . . Conductive plastic

Claims (11)

A semiconductor assembly structure for avoiding breakage of a package stack joint includes: a first semiconductor package comprising a first substrate, a first wafer disposed on the first substrate, and a first sealing the first wafer An encapsulant, wherein a first wafer exposed surface partially exposing the first wafer is formed in a center of a top surface of the first encapsulant, the first wafer revealing surface is provided with a plurality of first wafer contacts; and a second semiconductor The package comprises a second substrate, a second wafer disposed on the second substrate, and a second encapsulant sealing the second wafer, wherein a partial exposure is formed in a center of a top surface of the second encapsulant a second wafer exposure surface of the second wafer, the second wafer exposure surface is provided with a plurality of second wafer contacts; and an interposer substrate is disposed on the first wafer exposure surface and the second wafer exposure surface The second semiconductor package is reversely stacked on the first semiconductor package such that the second wafer exposure surface is aligned to face the first wafer exposure surface, and the interposer is connected to the second semiconductor package. First The plurality of wafer contact and a second die contacts; wherein the upper and lower surfaces of each interposer substrate provided with a plurality of metal bumps for electrically connecting the plurality of contacts of the first wafer and the second wafer contacts; And the semiconductor assembly structure further includes a conductive paste connected to the metal bumps to the corresponding first and second wafer contacts; wherein the first semiconductor package further comprises a plurality of first solder balls, The first substrate is electrically connected to the first substrate by a plurality of first bonding wires or a plurality of first flip-chip bumps; wherein the second semiconductor package is The device further includes a plurality of second solder balls disposed on an outer surface of the second substrate, and the second wafer is electrically connected by a plurality of second bonding wires or a plurality of second flip-chip bumps To the second substrate. The semiconductor composite structure for avoiding breakage of a package stack joint according to the first aspect of the patent application, wherein the interposer substrate is made of a semiconductor material, and the size of the interposer substrate is not larger than any of the first wafer and the second wafer. A semiconductor composite structure for avoiding breakage of a package stack joint according to the second aspect of the patent application, wherein the interposer substrate is a dummy wafer having a via hole. The semiconductor composite structure of the first aspect of the first sealant and the second sealant is recessed according to the first aspect of the patent application. The semiconductor composite structure for avoiding breakage of a package stack joint according to the first aspect of the patent application, wherein the conductive adhesive is an anisotropic conductive adhesive to fill the exposed surface of the first substrate to the first wafer The second wafer reveals a void in the face. The semiconductor assembly structure for avoiding breakage of a package stack joint according to the first aspect of the patent application, wherein the first semiconductor package further includes the first bonding wires, which are connected to the plurality of first peripheral solders of the first wafer The pad and the plurality of first peripheral fingers of the first substrate further seal the first bonding wires. The semiconductor assembly structure for avoiding breakage of a package stack joint according to claim 6 of the scope of the patent application, wherein the second semiconductor package further comprises the second bonding wires, which are connected to the plurality of second peripheral electrodes of the second wafer The pad and the plurality of second peripheral fingers of the second substrate further seal the second bonding wires. A semiconductor composite structure for avoiding breakage of a package stack joint according to the first aspect of the patent application, wherein the first wafer exposure surface is a central area of the active surface of the first wafer. The semiconductor composite structure for avoiding breakage of a package stack joint according to the first aspect of the patent application, wherein the first wafer exposure surface is a back central region of the first wafer, and the first wafer is formed by the first flip chip The bump is bonded to the first substrate by flip chip bonding. A semiconductor composite construction for avoiding breakage of a package stack joint according to the first aspect of the patent application, wherein the first sealant system completely covers an inner surface of the first substrate. A semiconductor composite construction that avoids breakage of package stack contacts according to claim 1 of the scope of the patent application, wherein the second semiconductor package is substantially identical to the first semiconductor package.