TW201209971A - Semiconductor package with bonding wires in window encapsulated by underfill material and method fabricated for the same - Google Patents
Semiconductor package with bonding wires in window encapsulated by underfill material and method fabricated for the same Download PDFInfo
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- TW201209971A TW201209971A TW099127483A TW99127483A TW201209971A TW 201209971 A TW201209971 A TW 201209971A TW 099127483 A TW099127483 A TW 099127483A TW 99127483 A TW99127483 A TW 99127483A TW 201209971 A TW201209971 A TW 201209971A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
201209971 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種以底 膠密封窗口内銲線之封裝構造及其製造方法。 _ 【先前技術】 現有窗口球格陣列（window BaU Grid Array，wBga) 封裝構造因有打線製程，故必須要有模封注膠製程（或稱 轉移成型transfer molding)來將晶片與銲線包覆起來以 作為保護，而無法直接裸露晶片增加散熱效能，封膠= 尺寸也因模封膠體有一尺寸而無法有效縮小。 » 如第1圖所示，為習知一種以模封膠體密封窗口内銲 線之封㈣造1G()，其是以一基板UG做為晶片载體與 内部電性傳遞媒介。該基板11〇係具有一第一表面丨^、 一第二表面112以及一貫穿之槽孔113。該第一表面^ 係為晶片言免置面，該第二表面112係為外接端子（例如鲜 球）之設置面。該第二表面112係設有複數個外接墊 116’以供設置複數個銲球16〇。一晶片12〇之主動面^ 係藉由一黏晶層（例如環氧黏膠或ρι膠帶）而貼 板110之該第一表面m，並使形成於該主動面12〗二 複數個銲墊122係對準並顯露於該槽孔113中。並以打 線形成的複數個銲線13〇穿過該槽孔113以電性連接該 晶片12〇之該些銲墊122至該基板11〇。一模封膠體二 係以轉移成型方式形成於該第一表面lu上與該槽孔 113内，以密封該晶片120與該些銲線13〇，以免受^外 3 201209971 界污染物的污染，但製造上不可覆蓋到該些外接墊11 6 導致良率降低，並且在形成該模封膠體150時灌注塑料 的壓力甚高，容易沖線進而造成該些銲線130的位移受 損。當模封之後，再將該些銲球160設置於該基板11〇 之該些外接墊11 6做為對外之焊接接點。由於該模封膠 體150具有一定尺寸與高度，故該封裝構造1〇〇之尺寸 無法有效縮小’且無法直接裸露該晶片12〇來增加散熱 效能。而習知之覆晶（flip Chip)晶片雖可裸露晶片，但無 法做有效堆疊’達到應用於高密度多晶片堆疊。 【發明内容】 有鑒於此，本發明之主要目的係在於提供一種以底膠 密封窗口内銲線之封裝構造及其製造方法，在形成底部 填充膠時’可具有無氣泡（VGid)快速填充避免打線受損之 功效。 種以底膠密封窗口 片可裸露而增加散 種以底膠密封窗口 省略模封製程，進201209971 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a package structure for sealing a wire bonding wire in a window with a primer and a method of manufacturing the same. _ [Prior Art] The existing window box array (wBga) package structure has a wire bonding process, so it is necessary to have a molding process (or transfer molding) to coat the wafer and the wire. As a protection, it is impossible to directly expose the wafer to increase the heat dissipation performance. The sealant size also cannot be effectively reduced due to the size of the mold sealant. » As shown in Fig. 1, a conventional package (4) is used to seal the inner wire of the window sealant (4), which is a substrate carrier UG as a wafer carrier and an internal electrical transfer medium. The substrate 11 has a first surface, a second surface 112, and a through hole 113. The first surface is a wafer-free surface, and the second surface 112 is a mounting surface of an external terminal (e.g., a fresh ball). The second surface 112 is provided with a plurality of external pads 116' for providing a plurality of solder balls 16A. An active surface of a wafer 12 is attached to the first surface m of the board 110 by a bonding layer (for example, epoxy adhesive or ρι), and is formed on the active surface 12 by a plurality of pads The 122 series is aligned and exposed in the slot 113. A plurality of bonding wires 13 formed by wire bonding are passed through the slots 113 to electrically connect the pads 122 of the wafer 12 to the substrate 11A. A mold encapsulant is formed on the first surface lu and the slot 113 by transfer molding to seal the wafer 120 and the bonding wires 13 to prevent contamination of the contaminants of the 201209971 boundary. However, the manufacturing of the external pads 11 6 may result in a decrease in yield, and the pressure of injecting the plastic when forming the molding compound 150 is very high, and the wiring is easily broken to cause the displacement of the bonding wires 130 to be damaged. After the molding, the solder balls 160 are disposed on the external pads 11 6 of the substrate 11 as external solder joints. Since the molding compound 150 has a certain size and height, the size of the package structure cannot be effectively reduced and the wafer 12 can not be directly exposed to increase the heat dissipation performance. While conventional flip chip wafers can expose wafers, they cannot be effectively stacked' to achieve high density multi-wafer stacking. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a package structure for sealing a wire in a window with a primer and a manufacturing method thereof, which can have a bubble-free (VGid) fast filling when forming an underfill. The effect of damage to the line. The bottom seal can be used to seal the window. The sheet can be exposed and the powder can be sealed with a primer to seal the window.
本發明之次一目的係在於提供一 内辉線之封裝構造及其製造方法，蓋 熱效能，並可縮小封裝構造的尺寸。 本發明之再一目的係在於提供一 内銲線之封裝構造及其製造方法，可 而節省封裝成本。 本發明的目的及艇也合 案來實現的。本發二==…技 封裝構造’主要包含—基板、―：膠曰密封窗二内銲 -^ - Β μ 乐 日日片、複數個銲 “以及一底部填充膠。該基板係具有一第 201209971 面、一第二表面以及一貫穿該第二表面與該第一表面之 狹長狀槽孔。該第一晶片係具有一第一主動面以及複數 個設在該第一主動面上之銲墊，其中該第一晶片之該第 一主動面係貼附至該第一表面，並使該些銲墊位於該槽 孔内。該些銲線係經由該槽孔而電性連接該些銲墊至該 基板。該第二晶片係具有一第二主動面以及複數個設在 該第二主動面上之柱狀凸塊’該第二主動面係朝向該第A second object of the present invention is to provide an inner glow wire package structure and a method of fabricating the same, to cover thermal efficiency, and to reduce the size of the package structure. Still another object of the present invention is to provide a package structure of an inner bonding wire and a method of manufacturing the same, which can save packaging cost. The objects and boats of the present invention are also implemented in combination. The second two ==...Technical package structure 'mainly includes-substrate, ―: plastic sealing window 2 inner welding-^ - Β μ 乐日日, multiple weldings and one underfill. The substrate has a first a surface of the second surface and an elongated slot extending through the second surface and the first surface. The first wafer has a first active surface and a plurality of pads disposed on the first active surface The first active surface of the first wafer is attached to the first surface, and the solder pads are located in the slot. The soldering wires are electrically connected to the solder pads via the slot. To the substrate, the second wafer has a second active surface and a plurality of columnar bumps disposed on the second active surface, the second active surface facing the first
二表面並以該些柱狀凸塊接合至該基板之該第二表面。 該底部填充膠係填滿該槽孔以及填滿位在該第二晶片之 該第二主動面與該基板之該第二表面之間之間隙，以密 封該些銲線與該些柱狀凸塊。其中該第一晶片與該第二 晶片係具有一晶片尺寸差，以使該槽孔之兩端分別構成 用來形成該底部填充膠之一非貫穿注膠口與一非貫穿排 氣口。本發明另揭示上述以底膠密封窗口内銲線之封裝 構造之製造方法。 本發月的目的及解決其技術問題還可採用以下技術 措施進一步實現。 _在/述的封裝構造中，該第二晶片之尺寸係可大於該 第一晶f之尺寸’俾使該槽孔之該非貫穿注膠口與該非 貫穿排氣口皆朝向該基板之該第一表面。 在前述的封裝構造中，該第-表面係可設有複數個外 封裝構造另包含有複數個銲球，係設置於該些 &墊上而位在該第一晶片之側邊。 在刖迷的封裝構造中，該些銲球係可具有一超過該第 5 201209971 一晶片之表面接合高度。 _在/』述的封裝構造中，該第一晶片之尺寸係可大於該 第一曰曰=之尺寸，俾使該槽孔之該非貫穿注膠口與該非 貫穿排氣口皆朝向該基板之該第二表面。 在%述的封裝構造中，該第二表面係可設有複數個外 接墊’該封裝構造另包含有複數個銲球，係設置於該些 外接塾上而位在該第二晶片之側邊。 Φ 在前述的封裝構造中，該些柱狀凸塊係可提供一間隙 s ^使該些銲線之線弧不碰觸到該第二晶片之該第 二主動面》 在前述的封裝構造中，可另包含有銲料，係接合該些 柱狀凸塊至該基板在該第二表面之複數個内接塾。 由以上技術方案可以看出’本發明之以底膠密封窗口 内銲線之封裝構造及其製造方法，具有以下優點與功效： 一、可藉由將大晶片、小晶片與基板之狹長狀槽孔之特 # 定組合關係作為其中之一技術手段，在形成底部填 充勝時’可具有無氣泡快速填充避免打線受損之功 效。 一、可藉由將大晶片、小晶片分別設置於基板兩側作為 其中之一技術手段，可一次填膠同時保護銲線與柱 狀凸塊’晶片可裸露增加散熱效能，並可縮小封裝 構造的尺寸。 三、可藉由將大晶片、小晶片分別設置於基板兩側作為 其中之一技術手段，利用底部填充膠填滿基板之槽…、 6 201209971 孔以及填滿覆晶晶片之主動面與基板之間的間隙， 可省略模封製程’進而節省封裝成本。 四、可藉由將外接墊設置在打線晶片之側邊作為其中之 技術手段，在形成底部填充膠時，具有避免底膠 污染外接墊之功效。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 Φ 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種以底膠密封窗口 鲁内銲線之封裝構造舉例說明於第2圖之截面示意圖以及 第3至6圖於製程中元件示意圖。該封裝構造2〇〇主要 包含一基板210、一第一晶片22〇、複數個銲線23〇、一 第二晶片240以及一底部填充膠25〇。該第一晶片22〇 係為一打線晶片’該第二晶片24〇係為一覆晶晶片。在 本實施例中’該第二晶片24〇之尺寸係大於該第一晶片 220之尺寸。 如第2圖所示，該基板21〇係具有一第一表面211、 一第二表面212以及一貫穿該第二表面212與該第一表 201209971 面2η之狹長狀槽孔213。該基板21〇係可作為晶片載 •體並具有單層或多層線路結構，例如印刷電路板、陶曼 線路板、電路薄膜或是預模壓製之導線架（即以導線架為 主體預先模封形成一薄片狀封膠體，以構成上下表面以 及貫穿之狹長槽孔）。該第一表面211係供該第一晶片 22〇(即打線晶片）設置之表面。該第二表面212係供Ζ第 二晶片240(即覆晶晶片）設置之表面。該第一表面2li與 φ 該第二表面2 1 2依所設置晶片大小皆可作為外接表面。 在本實施例中，打線連接之第一晶片22〇之尺寸小於該 第一晶片240’故以設置該第一晶片220之第一表面211 作為外接表面’可供設置複數個銲球26(^此外，如第3 與4圖所示’該槽孔213之形狀係為狹長狀，其兩端可 為方形或是圓31形，由該第一表面211貫穿至該第-表 面212。該槽孔213可利用雷射、機械鑽孔或其它已知 之方法形成。具體而言’該槽孔213之長度應小於該基 鲁 板2 1 〇之平行對應側邊之長度，但更應小於大晶片（即第 二晶片2 4 0)之晶片平行側長度且大於小晶片（即第一晶 片220)之晶片平行侧長度（容後詳述）。該第二表面 於該槽孔213之周圍係可設有複數個内接指218，以供 該第一晶片220打線電性連接之用，該些内接指218或 可設於該槽孔213内之一階梯部（圖中未繪出）。 请再參閲第2圖所示，該第一晶片220係具有一第一 主動面221以及複數個設在該第一主動面221上之鲜塾The two surfaces are joined to the second surface of the substrate by the stud bumps. The underfill fills the slot and fills a gap between the second active surface of the second wafer and the second surface of the substrate to seal the bonding wires and the columnar protrusions Piece. The first wafer and the second wafer have a wafer size difference such that the two ends of the slot respectively form a non-penetrating injection port and a non-through air outlet for forming the underfill. The present invention further discloses a method of manufacturing the above-described package structure for sealing a wire in a window with a primer. The purpose of this month and the resolution of its technical problems can be further realized by the following technical measures. In the package structure described above, the size of the second wafer may be greater than the size of the first crystal f, such that the non-penetrating injection opening of the slot and the non-through venting opening are toward the substrate a surface. In the above package structure, the first surface structure may be provided with a plurality of outer package structures and further comprising a plurality of solder balls disposed on the pads of the & pads and located on the side of the first wafer. In the encapsulation structure of the fascinating structure, the solder ball systems may have a surface bonding height exceeding the wafer of the 5th 201209971. The size of the first wafer may be greater than the size of the first 曰曰=, such that the non-penetrating injection opening and the non-through venting opening of the slot are toward the substrate. The second surface. In the package structure of %, the second surface system may be provided with a plurality of external pads. The package structure further includes a plurality of solder balls disposed on the external ports and located on the side of the second wafer. . Φ In the foregoing package structure, the columnar bumps may provide a gap s ^ such that the line arcs of the bonding wires do not touch the second active surface of the second wafer" in the foregoing package structure The solder may be further included to bond the columnar bumps to a plurality of interconnects of the substrate on the second surface. It can be seen from the above technical solution that the package structure and the manufacturing method of the wire bonding wire in the bottom seal sealing window of the present invention have the following advantages and effects: 1. The elongated groove can be formed by using a large wafer, a small wafer and a substrate. As a technical means, the combination of the pores and the combination of the bottom-filling wins can have the effect of quickly filling without bubbles to avoid damage to the wire. 1. By placing large wafers and small wafers on both sides of the substrate as one of the technical means, the glue can be filled at one time while protecting the bonding wires and the columnar bumps. The wafer can be exposed to increase heat dissipation efficiency, and the package structure can be reduced. size of. 3. The large wafer and the small wafer can be respectively disposed on the two sides of the substrate as one of the technical means, and the substrate can be filled with the underfill material... 6, 201209971 hole and the active surface and the substrate filled with the flip chip The gap between the two can eliminate the molding process' and thus save the packaging cost. Fourth, the external pad can be disposed on the side of the wire-bonding chip as a technical means thereof, and when the underfill is formed, the external pad can be prevented from contaminating the external pad. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a package structure of a bottom seal wire in a primer seal window is illustrated in a cross-sectional view of Fig. 2 and a schematic view of components in the process of Figs. 3 to 6. The package structure 2 includes a substrate 210, a first wafer 22, a plurality of bonding wires 23, a second wafer 240, and an underfill. The first wafer 22 is a wire wafer. The second wafer 24 is a flip chip. In the present embodiment, the size of the second wafer 24 is larger than the size of the first wafer 220. As shown in FIG. 2, the substrate 21 has a first surface 211, a second surface 212, and an elongated slot 213 extending through the second surface 212 and the first surface 201209971. The substrate 21 can be used as a wafer carrier and has a single-layer or multi-layer circuit structure, such as a printed circuit board, a Taman circuit board, a circuit film or a pre-molded lead frame (ie, pre-molded with a lead frame as a main body) A sheet-like sealant is formed to constitute the upper and lower surfaces and the elongated slits therethrough. The first surface 211 is for the surface on which the first wafer 22 (i.e., the wire wafer) is disposed. The second surface 212 is provided for the surface on which the second wafer 240 (i.e., the flip chip) is disposed. The first surface 2li and φ of the second surface 2 1 2 can be used as an external surface depending on the size of the wafer to be disposed. In this embodiment, the size of the first wafer 22 is less than the size of the first wafer 240, so that the first surface 211 of the first wafer 220 is disposed as an external surface, and a plurality of solder balls 26 can be disposed (^ Further, as shown in FIGS. 3 and 4, the shape of the slot 213 is elongated, and both ends thereof may be square or round 31, and the first surface 211 penetrates through the first surface 212. The hole 213 can be formed by laser, mechanical drilling or other known methods. Specifically, the length of the slot 213 should be less than the length of the parallel corresponding side of the base plate 2 1 ,, but should be smaller than the large chip. The length of the wafer parallel side of the second wafer 240 is greater than the length of the wafer parallel side of the small wafer (ie, the first wafer 220) (described in detail later). The second surface is surrounded by the slot 213. A plurality of internal fingers 218 are provided for electrically connecting the first wafers 220. The internal fingers 218 may be disposed in one of the slots 213 (not shown). Referring to FIG. 2 again, the first wafer 220 has a first active surface 221 and a plurality of Sook fresh active surface 221 on the first
Γ· T 222，其中該第一晶片220之該第一主動面221係貼附至r 1 8 201209971 該第一表面211，並使該些銲墊222位於該槽孔213内。 該第一晶片220的積體電路（例如記憶體元件）係形成於 該第一主動面221，而該些銲墊222係為連接積體電路 之晶片對外端點，其材質通常為鋁或銅。在本實施例中， 可利用一非液態黏晶層，例如膠帶、B階黏膠（B_stage adhesive)或是晶片貼附物質（Die Attach Material， DAM)’以黏接該第一晶片220之該第一主動面221至該 籲 基板2丨〇之該第一表面211。該些辉塾222係可設置於 該第一晶片220之該第一主動面221之中央位置，即中 央型銲墊（central pad)，而對準於該槽孔213内。 該些鋅線230係經由該槽孔213而電性連接該些銲塾 22 2至該基板210。該些銲線230可利用打線製程所形成 之金屬細線，其材質可為金、或是採用類似的高導電性 的金屬材料（例如銅或鋁）。通常該些銲線2 3 〇係具有— 超過該第二表面212之弧高。 φ 該第二晶片240係具有一第二主動面241以及複數個 設在該第二主動面241上之柱狀凸塊242，該第二主動 面241係朝向該第二表面212並以該些枉狀凸塊242接 合至該基板210之該第二表面212，以達到記憶體容量 或是功能的擴充。故該第二晶片240係與該第一晶片220 係分別設於該基板210之不同表面，而為隔著基板之面 對面譟置型態。在本實施例中，該第二晶片24〇之該第 二主動面241係朝向該基板210，該些柱狀凸塊242係 以預定間隔排列並突出於該第二主動面241上，以作為 201209971 連接其積體電路之對外端點。具體而言，該些柱狀凸塊 242係可為銅柱’可利用電鐘形成，例如運用於晶圓級 的凸塊製作技術而得。此外，如第2圖所示，在本實施 例中’該封裝構造200中可另包含有銲料27〇，其係接 合該些柱狀凸塊242至該基板210在該第二表面212之 複數個内接墊217〇銲料270係形成在該些枉狀凸塊242 之端面。在一適當之回焊（refl〇w)溫度條件下，將銲料 籲 270溶化並焊接至該基板210之該些内接塾217，以使得 該第二晶片240可藉由該些柱狀凸塊242與銲料270電 性輕接至該基板210。較佳地，再如第2圖所示，該些 柱狀凸塊242係可提供一間隙高度H2，以使該些銲線 230之線弧不碰觸到該第二晶片240之該第二主動面 241 〇 該底部填充膠（underfill material)250係填滿該槽孔 2 1 3以及填滿位在該第二晶片240之該第二主動面24 1 φ 與該基板210之該第二表面212之間之間隙，以密封該 些銲線230與該些柱狀凸塊242，用以抵抗在該第二晶 片240與該基板21〇之間的熱應力集中至該些柱狀凸塊 242與銲料270。細部而言，在該基板210與該第二晶片 240之間隙内填入該底部填充膠25〇，藉以降低該些柱狀 凸塊242所受到的應力，如此便可減少接點破裂 (crack) ’抑制破裂之延伸，而延長接點之疲勞壽命。此 外’該底部填充膠250係為絕緣物質且在固化前具有高 流動性’利用點塗方式形成，可防止接點間有雜質造成 10 201209971 漏電流（leakage)的傳遞以及防止外界污染物的入侵而受 ' 到破壞。此外’本發明利用一次單點填膠之方法，形成 該底部填充膠250 ’同時保護該些銲線230與該些柱狀 凸塊242 ’可避免接合點脫落，並可使該兩晶片22〇、24〇 為裸晶型態，而可增加散熱效能，並可縮小封裝構造的 尺寸。 特別的是，如第4圖所示，該第一晶片220與該第二 _ 晶片240係具有一晶片尺寸差D，以使該槽孔213之兩 端分別構成用來形成該底部填充膠250之一非貫穿注膠 口 214與一非貫穿排氣口 21s。換言之，該第一晶片22〇 與該第一晶片240之主動面尺寸係不相同，彼此間係具 有一晶片尺寸差D，即尺寸大小之差距，特別是指依該 槽孔213之延伸方向而使該兩晶片22〇、24〇具有一尺寸 差D，得以露出該槽孔213之兩端而分別構成該非貫穿 注膠口 2 1 4與該非貫穿排氣口 2丨5。在此指「非貫穿注 • 膠口」與「非貫穿排氣口」是指由該槽孔213往下填入 底膠時，該槽孔213下方還有較大晶片（在本實施例中為 該第二晶片240)作為支撐底面，而非鏤空貫穿的，可達 到如第5圖所示單點往下點膠、橫向流動並往上排氣之 底膠填充作業。 在本實施例中，如第5與6圖所示，該第二晶片24〇 之尺寸係可大於該第一晶片220之尺寸，俾使該槽孔213 之該非貫穿注膠口 214與該非貫穿排氣口 215皆朝向該 基板210之該第一表面211 ’故在填底膠時可由該第 11 201209971 一表面2U將該底部填充膠由該非貫穿注膠口 2i4填充 入該槽孔213以及該第二晶片24〇與該基板21〇之間 隙，填充底膠時的空氣並可由該非貫穿排氣口 215排出。 更進一步地’如第2與6圖所示，該第一表面211係 可設有複數個外接塾216，該封展構造2〇〇另包含有複 數個銲球㈣der baU)26()，該些銲球·係設置於該些 外接塾2 1 6上而位在該第一晶片22〇之側邊，可為雙側 邊並成栅狀陣列排列。由於在填底膠時，底部填充膠係 由該非貫穿注膠口 2 1 4點入’往下流動而不會污染到上 方側邊之外接墊216，而具有避免底膠污染該些外接墊 2 1 6之功效。 此外，如第2圖所示，該些銲球26〇係可具有一超過 該第一晶片220之表面接合高度H1，以使該些銲球26〇 叮表面接。至外部印刷電路板（printed circuit board, PCB)，而不會撞擊至該第一晶片22〇。 请參閱第2至6圖所示，本發明進一步說明該封裝構 造200以底膠密封窗口内銲線之製造方法，以彰顯本案 的功效。 首先’如第2圖所示’在該基板21〇上進行該第一晶 片220之黏晶（die attach)步驟，即將該第一晶片22〇之 該第一主動面221貼附至該基板21〇之該第一表面211， 並使該些銲墊222位於該槽孔213内。之後，可利用打 線機（wire bonder，圖未繪出）打線形成該些銲線23〇並 經由該槽孔213而電性連接該些銲墊222至該基板210【 12 201209971 之該些内接指218。之後，再進行該第二晶片24〇之覆 晶接合（flip chip bonding)步驟，而將該第二晶片24〇之 該第二主動面241朝向該第二表面212並以該些柱狀凸 塊242接合至該基板210之該些内接塾21?。 更具體的，如第3與4圖所示，在形成該底部填充膠 之步驟之前，可另包含翻轉該基板21〇之步驟，以使該 基板210之該第一表面211為朝上，而往上顯露出該非 貫穿注膠口 214與該非貫穿排氣口 215，以利於底膠填 充0 最後，如第5與6圖所示，可利用一點膠針頭1〇以 點膠（dispensing)方式將該底部填充膠填滿該槽孔213以 及填滿位在該第二晶片240之該第二主動面241與該基 板2Π)之該第二表面212之間之_，以密封該些鲜線 與該ik柱狀凸塊242。細部而言，如第3與5圖所示，The first active surface 221 of the first wafer 220 is attached to the first surface 211 of r 1 8 201209971, and the pads 222 are located in the slot 213. The integrated circuit (for example, a memory device) of the first wafer 220 is formed on the first active surface 221, and the pads 222 are connected to the outer end of the wafer of the integrated circuit, and the material is usually aluminum or copper. . In this embodiment, a non-liquid adhesive layer such as a tape, a B-stage adhesive, or a Die Attach Material (DAM) can be utilized to bond the first wafer 220. The first active surface 221 is to the first surface 211 of the substrate 2 . The illuminating 222 can be disposed at a central position of the first active surface 221 of the first wafer 220, that is, a central pad, and aligned in the slot 213. The zinc wires 230 are electrically connected to the solder pads 22 2 to the substrate 210 via the slots 213 . The bonding wires 230 may be formed by a metal wire formed by a wire bonding process, and may be made of gold or a similar highly conductive metal material such as copper or aluminum. Typically, the wire bonds 2 have an arc height that exceeds the second surface 212. The second active surface 241 has a second active surface 241 and a plurality of columnar bumps 242 disposed on the second active surface 241. The second active surface 241 faces the second surface 212 and A bead bump 242 is bonded to the second surface 212 of the substrate 210 to achieve memory capacity or functional expansion. Therefore, the second wafer 240 and the first wafer 220 are respectively disposed on different surfaces of the substrate 210, and are opposite to each other across the surface of the substrate. In this embodiment, the second active surface 241 of the second wafer 24 is oriented toward the substrate 210, and the columnar bumps 242 are arranged at predetermined intervals and protrude from the second active surface 241 to serve as 201209971 Connects to the external endpoint of its integrated circuit. In particular, the stud bumps 242 can be copper pillars that can be formed using an electric clock, such as bump fabrication techniques applied at the wafer level. In addition, as shown in FIG. 2, in the present embodiment, the package structure 200 may further include a solder 27 that is bonded to the plurality of columnar bumps 242 to the plurality of the second surface 212 of the substrate 210. An inner pad 217 〇 solder 270 is formed on the end faces of the ridges 242. The solder 270 is melted and soldered to the inner vias 217 of the substrate 210 under a suitable reflow temperature to allow the second wafer 240 to pass through the stud bumps. 242 is electrically connected to the substrate 210 with the solder 270. Preferably, as shown in FIG. 2, the columnar bumps 242 can provide a gap height H2 such that the line arcs of the bonding wires 230 do not touch the second portion of the second wafer 240. The underfill material 250 fills the slot 2 1 3 and fills the second active surface 24 1 φ of the second wafer 240 and the second surface of the substrate 210 a gap between the 212 to seal the bonding wires 230 and the columnar bumps 242 for resisting thermal stress concentration between the second wafer 240 and the substrate 21A to the columnar bumps 242 With solder 270. In the detail, the underfill 25 填 is filled in the gap between the substrate 210 and the second wafer 240, thereby reducing the stress on the columnar bumps 242, thereby reducing the crack of the contacts. 'Suppress the extension of the fracture and extend the fatigue life of the joint. In addition, the underfill rubber 250 is an insulating material and has high fluidity before curing. It is formed by spot coating to prevent impurities between the contacts and the leakage of 10 201209971 leakage and the prevention of external pollutants. And suffer from 'destruction. In addition, the present invention utilizes a single-point filling method to form the underfill 250' while protecting the bonding wires 230 and the columnar bumps 242' to avoid the joints from falling off, and to enable the two wafers 22 to be folded. 24 〇 is a bare crystal type, which can increase the heat dissipation performance and reduce the size of the package structure. In particular, as shown in FIG. 4, the first wafer 220 and the second wafer 240 have a wafer size difference D such that the two ends of the slot 213 are respectively formed to form the underfill 250. One of the non-penetrating injection ports 214 and one non-penetrating exhaust port 21s. In other words, the first wafer 22 is different from the active surface of the first wafer 240, and has a wafer size difference D, that is, a size difference, in particular, according to the extending direction of the slot 213. The two wafers 22A and 24B have a size difference D, so that the two ends of the slot 213 are exposed to form the non-penetrating injection port 2 1 4 and the non-penetrating exhaust port 2丨5, respectively. Herein, the term "non-penetration" and "non-through vent" means that when the primer 213 is filled down into the primer, there is a larger wafer below the slot 213 (in this embodiment). The second wafer 240 is used as a supporting bottom surface instead of being hollowed out, and the bottom glue filling operation of the single point downward dispensing, lateral flow, and upward exhausting as shown in FIG. 5 can be achieved. In this embodiment, as shown in FIGS. 5 and 6, the size of the second wafer 24 is greater than the size of the first wafer 220, so that the non-penetrating injection port 214 of the slot 213 and the non-penetration The exhaust port 215 is directed toward the first surface 211 ′ of the substrate 210. Therefore, when the primer is filled, the underfill can be filled into the slot 213 from the non-penetrating glue injection port 2i4 by the surface 11U. The gap between the second wafer 24 and the substrate 21 is filled with air from the primer and discharged from the non-through vent 215. Further, as shown in FIGS. 2 and 6, the first surface 211 may be provided with a plurality of external ridges 216, and the sealing structure 2 〇〇 further includes a plurality of solder balls (four) der baU) 26 (), The solder balls are disposed on the outer cymbal 216 and located on the side of the first wafer 22, and may be arranged on both sides in a grid array. Since the underfill glue flows from the non-penetrating glue injection port 2 1 4 to the lower side without contaminating the upper side outer pad 216, the bottom pad is prevented from contaminating the outer pad 2 The effect of 1 6 . In addition, as shown in FIG. 2, the solder balls 26 may have a surface bonding height H1 exceeding the first wafer 220 to surface the solder balls. To an external printed circuit board (PCB) without hitting the first wafer 22〇. Referring to Figures 2 through 6, the present invention further illustrates the method of manufacturing the bond wire in the package structure 200 with a primer to demonstrate the efficacy of the present invention. First, as shown in FIG. 2, a die attaching step of the first wafer 220 is performed on the substrate 21, that is, the first active surface 221 of the first wafer 22 is attached to the substrate 21. The first surface 211 is disposed, and the pads 222 are located in the slot 213. Then, the bonding wires 23 can be formed by wire bonding (wire bond), and the pads 222 are electrically connected to the substrate 210 via the slots 213. [12 201209971 Refers to 218. Thereafter, a flip chip bonding step of the second wafer 24 is performed, and the second active surface 241 of the second wafer 24 is turned toward the second surface 212 and the columnar bumps are formed. 242 is bonded to the inner ends 21 of the substrate 210. More specifically, as shown in FIGS. 3 and 4, before the step of forming the underfill, the step of flipping the substrate 21 may be further included so that the first surface 211 of the substrate 210 is upward, and The non-penetrating injection port 214 and the non-through vent 215 are exposed upward to facilitate the filling of the primer. Finally, as shown in Figures 5 and 6, a dispensing needle can be used to dispense. The underfill fills the slot 213 and fills the gap between the second active surface 241 of the second wafer 240 and the second surface 212 of the substrate 2 to seal the fresh lines. And the ik stud bump 242. In detail, as shown in Figures 3 and 5,
該底4填充膠係為液態封膠材料可利用該點膠針頭i 〇 由該非貫穿注膠口 214填入，利用液體在該第二晶片 與該基< 210間微細孔隙所形成的毛細壓力（—y pressure)作為驅動力 加以滲透並填滿該些柱狀凸塊242 2 1 3 ’以包覆該些銲線230。填底 該非貫穿排氣口 215以及該第二 間的間隙並填滿該槽孔 膠時擠出之空氣並可由 晶片240之周邊排出，而可 線受損之功效。另可省略模 進而節省封裝成本。此外， 穿注膠口 214的下方還有該 具有無氣泡快速填充避免打 封製程來密封銲線之步驟， 由於在填充底膠時，該非貫 第二晶片240之阻擋，故由 13 201209971 該非貫穿注膠口 214填入之未固化底部填充膠會沿著該 第二晶片240之該第二主動面241順流至該非貫穿排氣 口 215,藉以填滿位在該第二晶片24〇與該第二表面212 之間隙以及填滿該槽孔2 13。 因此，形成該底部填充膠之點注端即為該非貫穿注膠 口 214，不同習知在晶片一側邊或兩側邊塗晝注膠，而 具有在該第二晶片240周邊呈現更為完整的底膠外形， φ 並且該底部填充膠的流動方向是由該第二晶片240底部 沿該槽孔213之中心線往外擴散流動，不同於以往由曰 * 曰曰 片側邊開始流佈的底膠流動，故可快速填充且不會有氣 泡之問題。此外，即使一旦有任何多餘的底膠溢膠將優 先積存在該槽孔213之該非貫穿注膠口 214與該非貫穿 排氣口 215朝向該第一表面211之空間，恰好隱藏在該 封裝構造之底部，不影響整體封裝外觀。 在一較佳實施例中’如第2與6圖所示，在填充該底 • 部填充膠之後’可另包含設置複數個銲球260於該些外 接墊216上，可在該基板210的該些外接塾216上分別 形成錫膏（solder paste)(未繪示於圖面）或助焊劑 (flux)(未繪示於圖面）’再在上述錫膏或助焊劑上分別放 置一具有預定球徑的錫球（solder ball)(未繪示於圖面）， 再經由一回焊製程將上述錫球接合於該些外接墊216 上，形成該些銲球260。其中該些銲球260之設置與該 底部填充膠之固化可同時進行在一加熱程序，以令該底 部填充膠完成固化。 14 201209971 依據本發明之第二具體實施例’另一種以底膠密封窗 口内鲜線之封裝構造說明於第7圖之截面示意圖與第8 圖之立體不意圖。該封裝構造3 00主要包含一基板210、 一第一晶片220、複數個銲線230、一第二晶片240以及 一底部填充膠250。其中與第一實施例相同的主要元件 將以相同符號標示，並具備相同的基本功效，不再予以 贅述。 φ 在本實施例中，該第一晶片220之尺寸係可大於該第 一晶片240之尺寸，俾使該槽孔2 13之該非貫穿注膠口 214與該非貫穿排氣口 215皆朝向該基板21〇之該第二 表面212’故在填底膠時，該第二表面212朝上，固化 前該底部填充膠250由該非貫穿注膠口 214填充，進而 先流入該槽孔213,再填滿該第二晶片24〇與該基板21〇 之間隙’填底膠的空氣並可由該非貫穿排氣口 2丨5排 出’可具有無氣泡快速填充避免打線受損之功效。 # 此外，該些外接墊216與該些銲球260係可設置在該 第二表面212之側邊，而具有避免底膠污染外接墊之功 效。另，該基板210可選用一種低成本具有單面線路層 之電路基板’可省去電性佈局之複雜度與製程困擾，提 高訊號處理高速化，並降低基板之製作成本。 因此，本發明之以底膠密封窗口内銲線之封裝構造可 利用將大晶片、小晶片與基板之狹長狀槽孔之特定組合 關係作為其中之一技術手段。形成該底部填充膠之點注 端即為該非貫穿注膠口 214，並且該底部填充膠的流動：” 15 201209971The bottom 4 filling glue is a liquid sealing material, and the dispensing needle can be filled by the non-penetrating injection opening 214, and the capillary pressure formed by the fine pores between the second wafer and the base < 210 is utilized by the liquid. (—y pressure) is infiltrated as a driving force and fills the columnar bumps 242 2 1 3 ' to cover the bonding wires 230. The non-through vent 215 and the second gap are filled and filled with air which can be discharged from the periphery of the wafer 240, and the wire is damaged. The module can be omitted to save packaging costs. In addition, there is a step of sealing the bonding wire with the bubble-free rapid filling avoiding the sealing process under the plastic injection port 214. Since the non-transparent second wafer 240 is blocked when the primer is filled, it is not penetrated by 13 201209971. The uncured underfill filled in the glue filling port 214 flows along the second active surface 241 of the second wafer 240 to the non-through vent 215, thereby filling the second wafer 24 and the first The gap between the two surfaces 212 and fills the slot 2 13 . Therefore, the spotting end of the underfill is the non-penetrating glue injection port 214. Differently, it is known to apply glue on one side or both sides of the wafer, and has a more complete appearance around the second wafer 240. The bottom rubber shape, φ and the flow direction of the underfill is diffused outwardly from the bottom of the second wafer 240 along the center line of the slot 213, which is different from the primer which has been flown from the side of the 曰* 曰曰 sheet. Flows, so it can be quickly filled without bubbles. In addition, even if any excess primer overflows preferentially accumulates in the non-penetrating injection opening 214 of the slot 213 and the space of the non-throughing opening 215 facing the first surface 211, it is hidden in the package structure. The bottom does not affect the overall package appearance. In a preferred embodiment, as shown in FIGS. 2 and 6, after filling the underfill, it may additionally include a plurality of solder balls 260 disposed on the external pads 216, which may be on the substrate 210. Solder pastes (not shown) or fluxes (not shown) are formed on the external contacts 216, respectively, and then placed on the solder paste or the flux respectively. A solder ball of a predetermined ball diameter (not shown) is attached to the outer pads 216 via a reflow process to form the solder balls 260. The setting of the solder balls 260 and the curing of the underfill can be performed simultaneously in a heating process to complete the curing of the bottom filling glue. 14 201209971 According to a second embodiment of the present invention, another package structure in which a fresh line is sealed with a primer is described in a cross-sectional view of Fig. 7 and a perspective view of Fig. 8. The package structure 300 mainly includes a substrate 210, a first wafer 220, a plurality of bonding wires 230, a second wafer 240, and an underfill paste 250. The same main elements as those in the first embodiment will be denoted by the same reference numerals and have the same basic functions, and will not be described again. In this embodiment, the size of the first wafer 220 may be larger than the size of the first wafer 240, so that the non-penetrating injection port 214 and the non-through vent 215 of the slot 2 13 are all facing the substrate. The second surface 212 ′ of the 21 故, the second surface 212 faces upward when the primer is filled, and the underfill rubber 250 is filled by the non-penetrating injection port 214 before being solidified, and then flows into the slot 213 first, and then fills The gap between the second wafer 24 and the substrate 21 is 'the liquid filled with the primer and can be discharged from the non-through vent 2 丨 5'. It can have the effect of quick filling without bubbles to avoid damage to the wire. In addition, the external pads 216 and the solder balls 260 can be disposed on the side of the second surface 212 to prevent the primer from contaminating the external pads. In addition, the substrate 210 can be selected from a low-cost circuit board having a single-sided wiring layer, which can eliminate the complexity of the electrical layout and process troubles, improve the speed of the signal processing, and reduce the manufacturing cost of the substrate. Therefore, the package structure of the bonding wire in the underfill sealing window of the present invention can take a specific combination of the large-sized wafer, the small wafer and the elongated slot of the substrate as one of the technical means. The non-penetrating injection port 214 is formed by the dot filling end of the underfill, and the underfill is flowed:" 15 201209971
方向疋由該第二晶片240沿該槽孔21 3之中心線往外擴 散流動，不同於以往由晶片側邊開始流佈的底膠流動， 故可快速填充且不會有氣泡之問題。此外，即使一旦有 任何夕餘的底膠溢膠將優先積存在該槽孔213之該非貫 穿注膠口 214與該非貫穿排氣口 215朝向該第二表面 212之二間，恰好隱藏在該封裝構造之底部，不影響整 體封裝外觀。因此，在形成底部填充膠時，具有無氣泡 快速填充避免打線受損之功效。The direction 疋 is diffused and diffused by the second wafer 240 along the center line of the slot 21 3 , which is different from the flow of the primer which has been flowed from the side of the wafer, so that it can be quickly filled without bubbles. In addition, even if there is any excess gel overflow, the non-penetrating glue injection port 214 preferentially accumulates in the slot 213 and the non-penetrating exhaust port 215 faces the second surface 212, which is hidden in the package. The bottom of the construction does not affect the overall package appearance. Therefore, when the underfill is formed, there is no bubble fast filling to avoid the damage of the wire.
所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者，在*脫離本發明之技術範圍内，所作的任何簡單 二等效性變化與修飾，均屬於本發明的技術範圍θ内。 【圖式簡單說明】 固円 第1圖.-種習知以封膠體密封窗口内銲線之封裝構造 之截面示意圖。 依據本發明之第一具體實施例的一 封窗口内鲜線之封裝構造.之截面示意圖严 f據本發明之第—具體實施例的封裝構造在形 成底部填充膠製程中之元件截面示意圖。 依據本發明之第—具體實施例的封 成底部填充膠製程中之基板俯視示意圖Γ在' 依據本發明之第一具體實施例的封裝構造沿第 5-5線剖切之元件截面示意圖。 第2圖 第3圖 第4圖 第5圖 16 201209971 第6圖·依據本發明之第一具體實施例的封裝構造在形 成底部填充膠製程中之元件立體示意圖。 第7圖.依據本發明之第二具體實施例的另一種以底膠 密封窗口内銲線之封裝構造之截面示意圖。 第8圖：依據本發明之第二具體實施例的封裝構造在形 成底部填充膠製程中之元件立體示意圖。 【主要元件符號說明】The present invention is not limited to the embodiments of the present invention, and the present invention has been described above by way of preferred embodiments, but is not intended to limit the present invention, and any one skilled in the art. Any simple two-equivalent variation and modification made within the technical scope of the present invention are within the technical scope θ of the present invention. [Simple description of the figure] Solid 円 Figure 1 - A schematic cross-sectional view of the package structure of the inner wire bond wire sealed in the sealant. BRIEF DESCRIPTION OF THE DRAWINGS The package structure of a fresh line in a window according to a first embodiment of the present invention is a schematic cross-sectional view of an element in accordance with a first embodiment of the present invention in forming an underfill process. A schematic plan view of a substrate in a packaged underfill process in accordance with a first embodiment of the present invention is a cross-sectional view of an element taken along line 5-5 of the package structure according to the first embodiment of the present invention. Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 16 201209971 Fig. 6 is a perspective view showing the components of the package structure according to the first embodiment of the present invention in forming an underfill process. Fig. 7 is a cross-sectional view showing another package structure for sealing a wire in a window with a primer in accordance with a second embodiment of the present invention. Fig. 8 is a perspective view showing the components of the package structure according to the second embodiment of the present invention in the process of forming an underfill. [Main component symbol description]
D 晶片尺寸差 10 點勝針頭 100封裝構造 110基板 113槽孔 12 〇晶片 130銲線 2 0 0封裝構造 21〇基板 H1表面接合高度 111第一表面 11 6 外接塾 121主動面 150模封膠體 211第一表面 213狹長狀槽孔 214非貫穿注膠口 2 1 5非貫穿排氣口 2 1 7内接墊 220第一晶片 2 3 0銲線 240第二晶片 21 8内接指 221第一主動面 24 1第二主動面 25〇底部填充膠 260銲球 300封裝構造 H2間隙高度 112第二表面 122銲墊 160銲球 2 1 2第二表面 216.外接墊 222銲墊 242柱狀凸塊 270銲料 S1 17D wafer size difference 10 points wins needle 100 package structure 110 substrate 113 slot 12 〇 wafer 130 bond wire 2 0 0 package structure 21 〇 substrate H1 surface joint height 111 first surface 11 6 external 塾 121 active surface 150 mold seal 211 First surface 213 elongated slot 214 non-penetrating glue port 2 1 5 non-through air outlet 2 1 7 inner pad 220 first wafer 2 3 0 wire 240 second chip 21 8 inner finger 221 first active Face 24 1 second active surface 25 〇 underfill 260 solder ball 300 package structure H2 gap height 112 second surface 122 pad 160 solder ball 2 1 2 second surface 216. external pad 222 pad 242 column bump 270 Solder S1 17
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099127483A TW201209971A (en) | 2010-08-17 | 2010-08-17 | Semiconductor package with bonding wires in window encapsulated by underfill material and method fabricated for the same |
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| Application Number | Priority Date | Filing Date | Title |
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| TW099127483A TW201209971A (en) | 2010-08-17 | 2010-08-17 | Semiconductor package with bonding wires in window encapsulated by underfill material and method fabricated for the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI611535B (en) * | 2013-05-31 | 2018-01-11 | Renesas Electronics Corp | Semiconductor device |
| TWI643303B (en) * | 2017-01-31 | 2018-12-01 | 加藤電器製作所股份有限公司 | Electronic device and manufacturing method of electronic device |
| WO2022188415A1 (en) * | 2021-03-08 | 2022-09-15 | 京东方科技集团股份有限公司 | Flexible circuit board, display panel and preparation method therefor, and display device |
-
2010
- 2010-08-17 TW TW099127483A patent/TW201209971A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI611535B (en) * | 2013-05-31 | 2018-01-11 | Renesas Electronics Corp | Semiconductor device |
| TWI643303B (en) * | 2017-01-31 | 2018-12-01 | 加藤電器製作所股份有限公司 | Electronic device and manufacturing method of electronic device |
| WO2022188415A1 (en) * | 2021-03-08 | 2022-09-15 | 京东方科技集团股份有限公司 | Flexible circuit board, display panel and preparation method therefor, and display device |
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