TWI240388B - Stacked semiconductor package and fabrication method thereof - Google Patents

Stacked semiconductor package and fabrication method thereof Download PDF

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Publication number
TWI240388B
TWI240388B TW092119212A TW92119212A TWI240388B TW I240388 B TWI240388 B TW I240388B TW 092119212 A TW092119212 A TW 092119212A TW 92119212 A TW92119212 A TW 92119212A TW I240388 B TWI240388 B TW I240388B
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Taiwan
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wafer
layer
semiconductor package
bump
patent application
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TW092119212A
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Chinese (zh)
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TW200503202A (en
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Han-Ping Pu
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

A stacked semiconductor package and a fabrication method thereof are provided. A pre-solder layer is formed on an active surface of a first chip, and a plurality of bumps are formed on an active surface of a second chip. The first chip is mounted and wire-bonded to a chip carrier. The second chip is mounted in a flip-chip manner on and electrically connected to the first chip by the bumps. An underfill layer is formed between the first chip and the second chip. An encapsulation body encapsulates the first chip, second chip, and a portion of the chip carrier. The above semiconductor package and its fabrication method can enhance the adhesion between the first chip and the second chip.

Description

1240388 五、發明說明（1) 【發明所屬之技術領域】 一種堆豐晶片半遂顺 關於一種藉由形成一預^ ^衣件衣法，更詳而言之，係有 度之堆疊晶片半導體封筆件二力^半導體晶片間接合程 【先前技術】 、午及”衣法。 由於電子產品之料 為求提昇單一半導體封m j 2作速度需求的増加， 品小型化、大容量盘古^牛之性此，、容量，以符合電子產 以多晶片的形式呈現，卜μ從 ^ ^ 夕丰將+ V肢封裝件1240388 V. Description of the invention (1) [Technical field to which the invention belongs] A semi-smooth wafer is a method for forming a garment by forming a pre-^^ garment, more specifically, a semiconductor chip with a degree of stacked wafer sealing The second process is the joining process between semiconductor wafers [prior art], the afternoon, and the "clothing method." Because electronic materials are designed to increase the speed requirements of a single semiconductor package mj 2, the product is miniaturized and has a large capacity. Therefore, the capacity is presented in the form of multi-chips in accordance with the electronics production. From μ ^^ Xifeng will + V limb package

^ t胃 此種封裝件得縮減整體封f彳it _ H 並提昇電性功能，遂成A M U ^ 件體積 心战馮一種封裝的主流。 目前封裝業界提彳址右 _ ..., ρ 1 οτη, 仏有—種糸統級封裝（System in π，ge，、 )t結構，又稱為系統整合封裝，包括用於地 址子糸統或功能整合中的封裝技術。簡言t，系統級封裝 為在基板上經由堆疊或連結不同功能的晶片之封裝技術， 可應用於可攜式裝置之記憶卡如SD( Secure Digital) 卡、MS( Memory Stick)卡、MMC( Multi Media Card )、無線通訊模組與數位相機的光電轉換模組等，其得概 分成三種技術：第一種是多晶片模組（Multi-chip Modules ; MCM)，其係適用於數位與類比的電路整合；第 二種是多晶片組封裝（Multi Chip Packages; MCP)，為 3 D立體的封裝技術，亦即在一個封裝結構中將多個封裝件 或多個晶片層疊；第三種則是由三洋電機開發的I SB (Integrated System in Board)技術，其係將電源與地 線的佈線與晶片分開，與某種晶圓級封裝（w a f e r 1 e v e 1^ t stomach This kind of package has to reduce the overall sealing f 彳 it _ H and improve the electrical function, which has become the A M U ^ volume. At present, the packaging industry proposes address _ ..., ρ 1 οτη, and there is a type of system-in-package (System in π, ge,,) t structure, also known as system integration package, including for address subsystems. Or packaging technology in functional integration. In short, system-level packaging is a packaging technology that stacks or connects chips with different functions on a substrate. It can be applied to portable memory cards such as SD (Secure Digital) cards, MS (Memory Stick) cards, MMC ( Multi Media Card), wireless communication modules, and photoelectric conversion modules for digital cameras, etc., which can be divided into three technologies: the first is Multi-chip Modules (MCM), which is suitable for digital and analog Circuit integration; the second is Multi Chip Packages (MCP), which is a 3D packaging technology, that is, multiple packages or multiple chips are stacked in a package structure; the third is ISB (Integrated System in Board) technology developed by Sanyo Electric Co., Ltd. separates the power supply and ground wiring from the chip, and is separated from some wafer-level packages (wafer 1 eve 1

17370石夕品.ptd 第5頁 1240388 五、發明說明（2) -- packaging; WLP)再分配技術一起用於覆晶式封裝（η Chip in Package; FCIP)解決方案。 。以前述之具多晶片模組之半導體封裝件為例，其係在 單一封裝件之晶片承載件上接置並電性連接有至少兩個以 上的半導體晶片，且晶片與晶片承載件間之接置方式大 ，分為將半導體晶片一 一垂直疊接於該晶片承載件上之堆 豐式（stacked);以及將複數個半導體晶片彼此並排 女裝於該晶片承載件的晶片接置區之並排方式（side side) 等兩種。17370 石 夕 品 .ptd Page 5 1240388 V. Description of the Invention (2)-Packaging; WLP) redistribution technology is used together for η Chip in Package (FCIP) solution. . Taking the aforementioned semiconductor package with a multi-chip module as an example, it is connected and electrically connected to at least two or more semiconductor wafers on a wafer carrier of a single package, and the connection between the wafer and the wafer carrier is The placement methods are large, divided into a stacked type in which semiconductor wafers are vertically stacked on the wafer carrier one by one; and a plurality of semiconductor wafers are arranged side by side with each other in a wafer receiving area of the wafer carrier. There are two ways: side.

田言月芩閱第la圖，如USP 5, 8 1 5, 3 7 2揭露，其中顯示一 ，疊晶片之球栅陣列式（BaU Grid Array; bga)半 j，件1之剖面示意圖，如圖所示，該封裝件丨具有一藉 :各接合（wire bonding)形式接置並電性連接於_曰 承载件1 〇之筮—曰ΰ^ 曰曰 f f 曰曰片11，一第二晶片1 2則是透過覆晶 該从丨^曰以113)形式藉由複數個凸塊13接置並電性連接方 1 4激曰曰片Η之上，俾使该第二晶片1 2得透過複數條辞 =該晶片承載件丨〇電性連接。之後，再透過一封裝膠 :别述之構件加以封裝成一封裝件。Tian Yanyue read the la diagram, as disclosed in USP 5, 8 1 5, 3 7 2 which shows a schematic diagram of the cross section of a stacked wafer with a BaU Grid Array (bga) half j, piece 1. As shown in the figure, the package 丨 has a borrow: each bonding (wire bonding) form is connected and electrically connected to the _ said carrier 1 〇 之 筮-ΰ ^ ^ ff 曰 片 11, a second chip 1 2 is through a flip chip, and is connected in the form of 113) through a plurality of bumps 13 and is electrically connected to the side 14, and the second chip 12 is transmitted through Plural terms = The chip carrier is electrically connected. After that, it is packaged into a package through a sealing glue: other components are not mentioned.

請參閱第lb圖，如USP 6, 518, 161揭露，欲將該凸塊 丄〜結至該第一晶片11時，首先需在該第一晶片11之銲墊 上形成 凸塊底部金屬化（Under Bump Metallurgy; ϋβΜ)結構層1 12，該結構層112包含有一形成於該銲墊111 上之勒著層（Adhesion Layer) 112a，例如為铭金屬層； 防止擴散之阻障層（B a r r i e r L a y e r) 1 1 2 b，例如為鎳Please refer to FIG. Lb. As disclosed in USP 6, 518, 161, when the bumps are to be bonded to the first wafer 11, the bottom metallization of the bumps must be formed on the pads of the first wafer 11 (Under Bump Metallurgy (ϋβΜ) structural layer 112, the structural layer 112 includes an adhesion layer 112a formed on the pad 111, such as a metal layer; a barrier layer for preventing diffusion (Barrier L ayer) ) 1 1 2 b, such as nickel

第6頁 1240388 五、發明說明（3) 飢合金層，以及一用以接著該凸塊1 3之濕潤層（w e 11 i n g Layer) 1 1 2c，例如銅金屬層。前述之結構特徵在於利用 該UBM結構層1 1 2以於該第一晶片1 1之銲墊1 1 1與該凸塊1 3 間’能提供第二晶片之接置凸塊1 3之擴散阻障以及適當黏 著性等功能’俾使接置凸塊1 3能穩固地電性連接至第一晶 片上。 承别所述’習知技術為解決凸塊與鋁的因結合力不佳 而造成產品h賴性暨良率降低的問題，遂提出預先形成 UB Μ結構層之方式’以利銲墊與凸塊之電性結合。惟，由 於該UBM結構層係預先形成於該銲墊上，且該濕潤層通常 孫為了銅層，故在進行堆疊晶片前，該濕潤層會有產生氧 牝及被〉可染的問題，進而導致凸塊與UBM結構層接合失 蛛，大幅降低了封裝件之信賴性暨良率。 t上所述’如何能夠提供一種增加凸塊與UBM結構層 换合私度之堆豐晶片半導體封裝件及其製法，遂成為亟待 解決之課題。 【發明内容】 ^解决以上所述習知技術之缺點，本發明之主要目 在於提供一種堆疊晶片半導體封裴件及其製法，透過於 UBM、e構層上預先形成一銲錫層，藉以避免該說構層 表面於堆疊晶片前產生氧化及/或污染。 *及i π之ΐ要目的在於提供一種堆疊晶片半導體封 件:ί:: 透過於一 UBM結構層上預先形成一銲錫芦， 俾；行迴鲜私序時，藉由預銲錫層與該UBM結構層^ ^Page 6 1240388 V. Description of the invention (3) Hunger alloy layer, and a wet layer (we e 11 i n g Layer) 1 1 2c, such as a copper metal layer, for adhering the bump 13. The aforementioned structural feature is that the UBM structure layer 1 12 is used to provide a diffusion resistance between the bumps 1 3 of the first wafer 11 and the bumps 1 3 of the second wafer. Functions such as barriers and proper adhesion enable the connecting bumps 13 to be electrically connected to the first chip firmly. According to the description of the conventional technology, in order to solve the problem of poor product quality and yield reduction caused by the poor bonding force between bumps and aluminum, a method of forming a UB Μ structure layer in advance was proposed to facilitate solder pads and bumps. Electrical combination of blocks. However, because the UBM structure layer is formed in advance on the pad, and the wet layer is usually a copper layer, the wet layer may generate oxygen and be dyeable before stacking the wafers, which in turn causes problems The bonding of the bump and the UBM structure layer to the lost spider greatly reduces the reliability and yield of the package. As described above, how to provide a semiconductor chip package and a method for increasing the density of bumps and UBM structural layers, and a manufacturing method thereof, have become urgent problems to be solved. [Summary of the Invention] ^ To solve the shortcomings of the conventional technology described above, the main purpose of the present invention is to provide a stacked wafer semiconductor package and a method for manufacturing the same, by pre-forming a solder layer on the UBM and e-structure layers to avoid this. It is said that the surface of the formation layer is oxidized and / or contaminated before the wafers are stacked. The main purpose of * and i π is to provide a stacked wafer semiconductor package: ί :: by forming a solder reed on a UBM structure layer in advance, 俾; when returning to the private sequence, the pre-solder layer and the UBM are used. Structure layer ^ ^

1240388 五、發明說明（4) 密銲合之結果，提高晶片間之接合程度。 為達成以上所述及其他之目的，本發明之堆疊晶片半 導體封裝件包括有：一用以提供該半導體封裝件電性連接 外部之晶片承載件；一透過複數條銲線藉由銲線接合形式 接置並電性連接於該晶片承載件上之第一晶片，其中，於 該第一晶片之作用表面上形成有複數個銲墊，且該銲墊上 復形成有一 UBM結構層，而於該UBM結構層上則預先形成有 一銲錫層；一藉由覆晶形式接置並電性連接於該第一晶片 上，俾透過該第一晶片與該晶片承載件電性連接之第二晶 片，其中，於該第二晶片之作用表面上形成有複數個用以 與該預銲錫層融熔之金屬凸塊；一用以強化該第一晶片與 該第二晶片間之銲結強度之底部填膠；以及一形成於該晶 片承載件上並全部或部分包覆住前述之封裝件構件的封裝 膠體。 前述之堆疊晶片半導體封裝件其製法包括：首先，於 該第一晶片與該第二晶片之作用表面上分別形成有預銲錫 層與複數個金屬凸塊，其中，該預銲錫層係形成於該第一 晶片之UBM結構層上；其次，接置並透過複數條銲線電性 連接該第一晶片於該晶片承載件上；接著，接置並電性連 接該第二晶片之金屬凸塊於該第一晶片之預銲錫層上；再 者，形成該底部填膠於該第一晶片與該第二晶片之間；以 及形成一封裝膠體用以包覆該第一晶片、第二晶片及該晶 片承載件等構件。 相較於習知的堆疊晶片半導體封裝件及其製法，本發1240388 V. Description of the invention (4) The result of close welding improves the degree of bonding between wafers. In order to achieve the above and other objectives, the stacked wafer semiconductor package of the present invention includes: a wafer carrier for providing the semiconductor package to be electrically connected to the outside; and a form of bonding through a plurality of bonding wires through bonding wires. A first wafer is connected and electrically connected to the wafer carrier, wherein a plurality of bonding pads are formed on an active surface of the first wafer, and a UBM structure layer is formed on the bonding pads, and the UBM is formed on the bonding pad. A solder layer is formed in advance on the structural layer; a second chip is connected in a flip-chip form and is electrically connected to the first chip, and a second chip is electrically connected to the wafer carrier through the first chip, wherein, A plurality of metal bumps are formed on the active surface of the second wafer for melting with the pre-soldering layer; an underfill for enhancing the bonding strength between the first wafer and the second wafer; And an encapsulating gel formed on the wafer carrier and completely or partially covering the aforementioned package component. The aforementioned method for manufacturing a stacked wafer semiconductor package includes: first, forming a pre-solder layer and a plurality of metal bumps on the active surfaces of the first wafer and the second wafer, respectively, wherein the pre-solder layer is formed on the The UBM structure layer of the first wafer; secondly, the first wafer is connected and electrically connected to the wafer carrier through a plurality of bonding wires; then, the metal bumps of the second wafer are connected and electrically connected to On the pre-soldering layer of the first wafer; further, forming the underfill between the first wafer and the second wafer; and forming an encapsulating gel to cover the first wafer, the second wafer and the Wafer carrier and other components. Compared with the conventional stacked wafer semiconductor package and its manufacturing method, the present invention

17370石夕品.ptd 第8頁 1240388 五、發明說明（5) 明之堆疊晶片半導體封裝件及其製法，除得透過於一 UBM 結構層上預先形成之銲錫層，藉以避免該UBM結構層之表 面於堆疊晶片前產生氧化及/或污染，復得於執行迴銲程 序時，藉由預銲錫層與該UBM結構層間緊密銲合之結果， 提高晶片間之接合程度。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 & 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 請參閱第2 a圖，其中顯示於本實施例中本發明之堆疊 晶片半導體封裝件2之剖面示意圖，需特別說明者，係該 圖式與本說明書中之其他圖式同為一簡化示意圖，僅以示 意方式顯示與本發明之堆疊晶片半導體封裝件及其製法有 關之構件，實際之半導體封裝件其結構佈局與製程應更加 複雜。 於本實施例中，本發明之堆疊晶片半導體封裝件2主 要係包括有一晶片承載件2卜一第一晶片2 2、一第二晶片 # 2 3、一底部填膠2 4以及一封裝膠體2 5。 該晶片承載件2 1，其具有一第一表面2 1 a及一相對於 該第一表面21 a之第二表面21b，其中，於該第一表面21a 上形成有一晶片接置區2 1 1以供該晶片承載件2 1接置半導17370 石 夕 品 .ptd Page 8 1240388 V. Description of the invention (5) The stacked semiconductor chip package and its manufacturing method can be eliminated through a pre-formed solder layer on a UBM structure layer to avoid the surface of the UBM structure layer Oxidation and / or contamination is generated before the wafers are stacked. When the reflow process is performed, the result of the tight soldering between the pre-soldering layer and the UBM structure layer is used to improve the bonding between the wafers. [Embodiment] The following describes the embodiment of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. Please refer to FIG. 2a, which is a schematic cross-sectional view of a stacked wafer semiconductor package 2 of the present invention shown in this embodiment. For special explanation, this drawing is a simplified schematic diagram similar to other drawings in this specification. Only the components related to the stacked wafer semiconductor package and its manufacturing method of the present invention are shown in a schematic manner. The actual semiconductor package's structural layout and manufacturing process should be more complicated. In this embodiment, the stacked wafer semiconductor package 2 of the present invention mainly includes a wafer carrier 2, a first wafer 2 2, a second wafer # 2 3, an underfill 24, and a packaging gel 2. 5. The wafer carrier 21 has a first surface 21a and a second surface 21b opposite to the first surface 21a, and a wafer receiving area 21 is formed on the first surface 21a. For the wafer carrier 2 1 to be connected to the semiconductor

]7370石夕品.ptd 第9頁 1240388 五、發明說明（6) _~ --——--- 體晶片之用；至少-用以依據 線路圖案化以佈設有福I夕遑+ :兀仵之鲜結圖式進灯 )，並同時於該導Ϊ 線的佈線層（未圖示 置區8之鲜墊212係形成於該晶片接 衣¢7 z i b之知墊2 1 2則伤闲以担糾—n 7 ^ ^ ^ ^ ^ ^ ,j # „ Λ. Λ ;!B ^# 21ii # 該晶片承載件21上二；：：solder baii) 2i3,俾供 -mi 子兀件與外部裝置電性連接。於本 ’該晶片承載件21係為一球柵陣列式（bga)基本 導邮ΐ ΐ 一晶片22 ’於本實施例中係為一銲線接合型之半 =:日片’其具有—非作用表面2 表面22a之作用表面22b，並Φ，兮非从m太 ％非作用 —黏著# (夫圖干）Μ八中s亥非作用表面22a係透過 上1/未）接置於該晶片承載件21之晶片接置區 土^上，而於該作用表面22b上則形成有複數 ^ =性”覆晶式晶片“塊銲塾221，以及接置 f = 一晶片2 2藉由複數條銲線2 6以 ^^片 承載件21電性連接之銲線墊2 22。 飞曰片 睛簽閱第2b圖，需特別說明者，係於該作用表 ===銲塾221上復形成有一 υβΜ結構層2 23,其中’該uL 曰22 3包括有、一形成於該凸塊銲墊221上由鋁金屬（亦 鉻金屬）組成，用以提供該凸塊銲墊2 2丨與該 層m間良好黏著性之點著層223a; 一由…金以防。止構 X凸塊紅墊2 2 1與凸塊因電極反應生成共金屬化合物之阻] 7370 石 夕 品 .ptd Page 9 1240388 V. Description of the invention (6) _ ~ ---------- For the use of body wafers; at least-for patterning according to the circuit to be provided with a cloth I Xi 遑 +: Vulture Freshly enter the lamp), and at the same time on the wiring layer (not shown in Figure 8 of the fresh pad 212 is formed on the wafer adapter ¢ 7 Zib know pad 2 1 2 Responsibility—n 7 ^ ^ ^ ^ ^ ^, j # „Λ. Λ;! B ^ # 21ii # The wafer carrier 21 on the second; :: solder baii) 2i3, 俾 -mi sub-elements and external devices Electrical connection. In this case, the wafer carrier 21 is a ball grid array (bga) basic guide. Ϊ́ A wafer 22 is a half of a wire bonding type in this embodiment =: Japanese slice. It has-the non-active surface 2 surface 22a of the active surface 22b, and Φ, the non-active surface from the m too% non-active-adhesion # (夫 图 干) MH eight middle non-active surface 22a through the upper 1 / not) connected It is placed on the wafer receiving area of the wafer carrier 21, and a plurality of ^ = "Crystal-Chip Wafers" 221 are formed on the active surface 22b, and the connection f = a wafer 2 2 With a plurality of bonding wires 2 6 to ^ ^ The chip bearing member 21 is electrically connected to the bonding pad 2 22. The sheet 2 is shown in Figure 2b. If you need special explanation, it is attached to the functional sheet === weld 221 and a υβΜ structure layer 2 23 is formed. Wherein, the uL 223 includes an aluminum metal (also chrome metal) formed on the bump pad 221 to provide good adhesion between the bump pad 2 2 and the layer m. The point is the layer 223a; one is protected by gold. The stopper X bump red pad 2 2 1 reacts with the bump to form a co-metal compound due to the electrode resistance

1737〇 矽品.ptd 111 1111 RI 11 111 lit 第10頁 1240388 五、發明說明（7) 障層2 2 3 b ;以及一由銅金屬（亦得為鎳、鉑或鉬等金屬） 組成用以接著凸塊之濕潤層2 2 3 c。此外，該濕潤層2 2 3 c上 復形成有一預銲錫層2 2 4，於本實施例中，該預銲錫層2 2 4 係與該第二晶片2 3之金屬凸塊材質相同，均由錫鉛合金所 組成者。 該第二晶片2 3，具有一作用表面2 3a與一非作用表面 2 3 b，其中，於該作用表面2 3 a上形成有複數個金屬凸塊 2 3卜並將該金屬凸塊2 3 1銲結該第一晶片2 2之凸塊銲墊 2 2 1上之預銲錫層2 2 4知上，俾供該第二晶片2 3得以覆晶方 式接置並電性連接於該第一晶片2 2上。此外，該第一晶片 2 2與該第二晶片2 3間復形成有一底部填膠2 4，俾強化凸塊 之銲結性。 該封裝膠體2 5，其係形成於該晶片承載件2 1上並用以 包覆住該第一晶片2 2、第二晶片2 3、複數之銲線2 6等電子 元件以及部分之晶片承載件2卜藉以避免其受外界之水氣 或污染物所侵害。於本實施例中，該封裝膠體2 5係透過模 壓（m ο 1 d i n g)作業藉以將樹脂化合物如環氧樹脂（Ε ρ οX y Resin) %封裝材料形成於該晶片承載件2 1之上。 請併同參照第2a圖及第3至8圖，前述之堆疊晶片半導 體封裝件2其製法包括以下步驟： β 請參閱第3圖，於該第一晶片22之作用表面22b與該第 二晶片2 3之作用表面2 3 a上分別形成有該預銲錫層2 2 4與該 複數個金屬凸塊2 3 1，其中，該預銲錫層2 2 4係形成於該 UBM結構層2 2 3上。其中，於該第二晶片2 3形成該金屬凸塊1737〇Silicon products.ptd 111 1111 RI 11 111 lit Page 10 1240388 V. Description of the invention (7) Barrier layer 2 2 3 b; and a copper metal (also may be nickel, platinum or molybdenum metal) composed of Next, the wet layer 2 2 c of the bumps. In addition, a pre-solder layer 2 2 4 is formed on the wet layer 2 2 3 c. In this embodiment, the pre-solder layer 2 2 4 is made of the same material as the metal bumps of the second wafer 2 3. Composition of tin-lead alloy. The second wafer 2 3 has an active surface 2 3a and a non-active surface 2 3 b, wherein a plurality of metal bumps 2 3 are formed on the active surface 2 3 a and the metal bumps 2 3 are formed. 1 solder the bump 2 of the first wafer 2 2 and the pre-soldering layer 2 2 4 on the 1st board, so that the second wafer 2 3 can be flip-chip connected and electrically connected to the first Wafer 2 2 on. In addition, an underfill 24 is formed between the first wafer 2 2 and the second wafer 23 to strengthen the solderability of the bumps. The encapsulating gel 25 is formed on the wafer carrier 21 and is used to cover the first wafer 2 2, the second wafer 2 3, a plurality of bonding wires 26, and other electronic components and part of the wafer carrier. (2) To prevent them from being damaged by outside water vapor or pollutants. In this embodiment, the packaging colloid 25 is formed by molding a resin compound such as an epoxy resin (E ρ ο X y Resin)% packaging material on the wafer carrier 21 through a molding (m ο 1 d i n g) operation. Please refer to FIG. 2a and FIGS. 3 to 8 together. The method for manufacturing the aforementioned stacked wafer semiconductor package 2 includes the following steps: β Please refer to FIG. 3, the active surface 22b of the first wafer 22 and the second wafer The pre-solder layer 2 2 4 and the plurality of metal bumps 2 3 1 are respectively formed on the action surface 2 3 a of 2 3, wherein the pre-solder layer 2 2 4 is formed on the UBM structure layer 2 2 3 . Wherein, the metal bump is formed on the second wafer 23.

17370矽品.ptd 第11頁 124038817370 Silicone.ptd Page 11 1240388

17370 矽品.ptd 第12頁 1240388 五、發明說明（9) 性連接該第二晶片2 3於該第一晶片2 2上。 請參閱第7圖，再者，形成該底部填膠2 4於該第一晶 片2 2與該第二晶片2 3之間，於本實施例中，該底部填膠2 4 並未形成於該銲線墊2 2 2之上，避免產生信賴性問題。 請參閱第8圖，形成該封裝膠體2 5用以包覆住前述該 第一晶片2 2、第二晶片2 3、底部填膠2 4、銲線2 6及部分之 該晶片承載件21等等構件。 需特別說明者，於本實施例中，於進行該銲線2 6之銲 線接合程序及/或該封裝膠體2 5進行模壓作業之前，均得 透過一電漿清洗系統（Plasma Cleaning System)進行封 裝構件表面之清洗，俾增加作業時之可靠性。 上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此項技藝之人士均可在不 違背本發明之精神及範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。17370 Silicon Product.ptd Page 12 1240388 V. Description of the Invention (9) The second chip 23 is connected to the first chip 22 in a sexual manner. Please refer to FIG. 7. Furthermore, the underfill 24 is formed between the first wafer 22 and the second wafer 23. In this embodiment, the underfill 2 4 is not formed on the first wafer 22 and the second wafer 23. To avoid reliability problems, the bonding pads 2 2 2 are used. Referring to FIG. 8, the encapsulation gel 2 5 is formed to cover the first wafer 2 2, the second wafer 2 3, the underfill 2 4, the bonding wire 26, and a part of the wafer carrier 21, etc. And other components. It should be particularly noted that, in this embodiment, before the bonding process of the bonding wire 26 and / or the molding of the encapsulating gel 25 is performed, it can be performed through a plasma cleaning system. The cleaning of the surface of the package member increases the reliability during operation. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

17370石夕品.ptd 第13頁 1240388 圖式簡單說明 【圖式簡單說明】 第1 a圖為習知之堆疊晶片半導體封裝件之局部剖視 圖； 第1 b圖為習知之凸塊底部金屬化結構層之局部剖面示 意圖； 第2a圖為本發明之堆疊晶片半導體封裝件之剖面示意 圖； 第2b圖為本發明之UBM結構層與該預銲層之局部剖面 示意圖； 第3、5、6、7及8圖為本發明之堆疊晶片半導體封裝 件之製法示意圖；以及 第4a至4e圖為本發明之UBM結構層之製法示意圖。 1 半 導 體 封 裝 件 10 晶 片 承 載 件 11 第 一 晶 片 111 銲 墊 112 UBM結構層 112a 黏 著 層 112b 阻 障 層 112c 濕 潤 層 12 第 二 晶 片 13 凸 塊 14 銲 線 15 封 裝 膠 體 2 堆 疊 晶 片 半 導體封裝件 21 晶 片 承 載 件 21a 第 一 表 面 21b 第 表 面 211 晶 片 接 置 區 212^ 212’ 銲 墊 213 銲 球 22 第 一 晶 片 22a 非 作 用 表 面 22b 作 用 表 面17370 石 夕 品 .ptd Page 13 1240388 Brief description of the drawings [Simplified illustration of the drawings] Figure 1a is a partial cross-sectional view of a conventional stacked wafer semiconductor package; Figure 1b is a conventional metallization structure layer at the bottom of a bump Partial cross-sectional schematic diagram; Figure 2a is a schematic cross-sectional schematic diagram of a stacked wafer semiconductor package of the present invention; Figure 2b is a partial cross-sectional schematic diagram of the UBM structure layer and the pre-soldering layer of the present invention; Figures 3, 5, 6, 7, and FIG. 8 is a schematic view of a method for manufacturing a stacked wafer semiconductor package according to the present invention; and FIGS. 4a to 4e are schematic views of a method for manufacturing a UBM structure layer according to the present invention. 1 Semiconductor package 10 Wafer carrier 11 First wafer 111 Solder pad 112 UBM structure layer 112a Adhesive layer 112b Barrier layer 112c Wet layer 12 Second wafer 13 Bump 14 Welding wire 15 Packaging gel 2 Stacked wafer semiconductor package 21 Wafer Carrier 21a first surface 21b first surface 211 wafer receiving area 212 ^ 212 'pad 213 solder ball 22 first wafer 22a non-active surface 22b active surface

17370 矽品.ptd 第14頁 1240388 圖式簡單說明 221 凸 塊 銲 墊 222 銲 線 墊 223 UBM結構層 2 2 3a 黏 著 層 2 2 3b 阻 障 層 2 2 3c 濕 潤 層 224 預 銲 錫 層 225 光 阻 層 226 開 孔 2 3 第 --- 晶 片 23a 作 用 表 面 23b 非 作 用 表面 231 金 屬 凸 塊 24 底 部 填 膠 25 封 裝 膠 體 26 銲 線 Φ17370 Silicone.ptd Page 14 1240388 Brief description of the diagram 221 Bump pads 222 Wire pads 223 UBM structure layer 2 2 3a Adhesive layer 2 2 3b Barrier layer 2 2 3c Wet layer 224 Pre-solder layer 225 Photoresist layer 226 Opening hole 2 3 The first --- chip 23a active surface 23b non-active surface 231 metal bump 24 underfill 25 encapsulant 26 welding wire Φ

17370石夕品.ptd 第15頁17370 Shi Xipin.ptd Page 15

Claims (1)

1240388 六、申請專利範圍 1 . 一種堆疊晶片半導體封裝件，係包括： 一晶片承載件，其係用以提供該半導體封裝件與 外部構件電性連接； 至少一第一晶片，其具有一用以接置於該晶片承 載件上之非作用表面，以及一形成有複數個凸塊銲墊 與銲線墊，俾透過複數條銲線與該晶片承載件電性連 接之作用表面； 複數個凸塊底部金屬化結構層，其包括有多數個 形成於該凸塊銲墊上之金屬層，其中該金屬層包括有 一形成於該凸塊銲墊上用以提供該凸塊銲墊與該凸塊 底部金屬化結構層間良好黏著性之第一金屬層；一用 以防止該凸塊銲墊與凸塊因電極反應生成共金屬化合 物之第二金屬層；以及一用以銲接凸塊之第三金屬 層； 複數個預銲層，其係形成於該第三金屬層上用以 增加凸塊與該凸塊底部金屬化結構層接合程度； 至少一第二晶片，其係藉由覆晶形式接置並電性 連接於該第一晶片之凸塊銲墊上；以及 一封裝膠體，其係形成於該晶片承載件上用以包 覆住該第一晶片、第二晶片及其他構件，並部分包覆 住該晶片承載件。 2. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其 中，該晶片承載件可為一基板及導線架其中之一者。 3. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其1240388 6. Scope of patent application 1. A stacked wafer semiconductor package, comprising: a wafer carrier, which is used to provide electrical connection between the semiconductor package and external components; at least one first wafer, which has a A non-active surface connected to the wafer carrier, and an active surface electrically connected to the wafer carrier through a plurality of bonding wires, and a plurality of bumps and wire bonding pads; The bottom metallization structure layer includes a plurality of metal layers formed on the bump pads, wherein the metal layer includes a metal pad formed on the bump pads to provide the bump pads and the bottom metallization. A first metal layer with good adhesion between the structural layers; a second metal layer to prevent the bump pad and the bump from forming a co-metal compound due to an electrode reaction; and a third metal layer to solder the bumps; a plurality of A pre-soldering layer, which is formed on the third metal layer to increase the degree of bonding between the bump and the metallization structure layer on the bottom of the bump; at least one second wafer, which is covered by Formally connected and electrically connected to the bump pad of the first wafer; and a packaging gel formed on the wafer carrier to cover the first wafer, the second wafer and other components, and The wafer carrier is partially covered. 2. For the stacked wafer semiconductor package of the first scope of the patent application, the wafer carrier may be one of a substrate and a lead frame. 3. For a stacked chip semiconductor package in the scope of patent application item 1, the 17370石夕品.ptd 第16頁 1240388 六、申請專利範圍 中，該晶片承載件復形成有複數個用以連接銲球之銲 球銲墊（s ο 1 d e r b a 1 1 pad)，以及用以連接銲線之銲 線墊（f i nger)。 4. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其 中，該晶片承載件復包括有至少一用以依據該電子元 件之銲結圖式進行線路圖案化以佈設有複數之導電跡 線的佈線層。 5. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其 中，該第一金屬層之主要材質可為鋁及鉻其中之一 者。 如 6. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其 中，該第二金屬層之主要材質可為鎳飢合金。 7. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其 中，該第三金屬層之主要材質可為銅、鎳、鉑及鉬其 中之一者。 8. 如申請專利範圍第1項之堆疊晶片半導體封裝件，其 中，該第二晶片係透過複數個金屬凸塊與該第一晶片 之凸塊銲墊接置並電性連接。 9. 如申請專利範圍第8項之堆疊晶片半導體封裝件，其 中，該複數個金屬凸塊與該預銲層之主要材質相同， 俾於進行銲接程序時增加該第二晶片與該凸塊銲墊之 接合程度。 1 0 .如申請專利範圍第9項之堆疊晶片半導體封裝件，其 中，該複數個金屬凸塊與該預銲層之主要材質可為一17370 石 夕 品 .ptd Page 16 1240388 6. In the scope of the patent application, the wafer carrier is formed with a plurality of solder ball pads (s ο 1 derba 1 1 pad) for connecting the solder balls, and for connecting Welding wire pad (finger). 4. The stacked chip semiconductor package according to item 1 of the scope of patent application, wherein the wafer carrier further includes at least one circuit pattern for conducting a plurality of conductive traces in accordance with a soldering pattern of the electronic component. Wiring layer. 5. For the stacked chip semiconductor package of the first patent application scope, wherein the main material of the first metal layer may be one of aluminum and chromium. For example, if the stacked chip semiconductor package according to item 1 of the patent application scope, wherein the main material of the second metal layer may be nickel alloy. 7. For the stacked wafer semiconductor package of the first patent application scope, wherein the main material of the third metal layer may be one of copper, nickel, platinum, and molybdenum. 8. The stacked chip semiconductor package according to the first patent application scope, wherein the second wafer is connected to and electrically connected to the bump pads of the first wafer through a plurality of metal bumps. 9. For the stacked wafer semiconductor package with the scope of patent application No. 8, wherein the plurality of metal bumps are the same as the main material of the pre-soldering layer, the second wafer and the bump welding are added during the soldering process. Degree of mat engagement. 10. The stacked wafer semiconductor package according to item 9 of the scope of patent application, wherein the plurality of metal bumps and the main material of the pre-solder layer may be one 17370石夕品.ptd 第17頁 1240388 六、申請專利範圍 錫錯合金。 11 .如申請專利範圍第1項之堆疊晶片半導體封裝件，於該 第一晶片與該第二晶片間復形成有一底部填膠。 1 2. —種堆疊晶片半導體封裝件製法，係包括： 於一第一晶片與一第二晶片上分別形戍有一預銲 錫層與複數個金屬凸塊，其中，該預銲錫層係形成於 一第二晶片之凸塊銲墊之凸塊底部金屬化結構層上； 接置並透過複數條銲線以銲線接合方式電性連接 該第一晶片於該晶片承載件上； 透過於該金屬凸塊與該預銲錫層間之銲接程序， 接置並電性連接該第二晶片於該第一晶片之銲墊上； 形成一底部填膠於該第一晶片與該第二晶片之 間；以及 形成一封裝膠體用以用以包覆住前述該第一晶 片、第二晶片及其他構件’並部分包覆住該晶片承載 件。 1 3 .如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，其中，該凸塊底部金屬化結構層包括有多數個形 成於該凸塊銲墊上之金屬層，其中該金屬層包括有一 形成於該凸塊銲墊上用以提供該凸塊銲墊與該凸塊底 部金屬化結構層間良好黏著性之第一金屬層；一用以 防止該凸塊銲墊與凸塊因電極反應生成共金屬化合物 之第二金屬層；以及一用以銲接凸塊之第三金屬層。 1 4 .如申請專利範圍第1 3項之堆疊晶片半導體封裝件製17370 石 夕 品 .ptd Page 17 1240388 6. Scope of patent application Tin alloy. 11. The stacked wafer semiconductor package according to item 1 of the patent application scope, an underfill is formed between the first wafer and the second wafer. 1 2. A method for manufacturing a stacked wafer semiconductor package, comprising: forming a pre-solder layer and a plurality of metal bumps on a first wafer and a second wafer, respectively, wherein the pre-solder layer is formed on a The metallized structure layer on the bottom of the bumps of the bump pads of the second wafer; is connected and electrically connected to the wafer carrier through a plurality of bonding wires in a wire bonding manner; and passes through the metal bumps A soldering procedure between the block and the pre-soldering layer, connecting and electrically connecting the second wafer to the pad of the first wafer; forming a bottom glue between the first wafer and the second wafer; and forming a The encapsulant is used to cover the first wafer, the second wafer, and other components, and to partially cover the wafer carrier. 13. The method for manufacturing a stacked wafer semiconductor package according to item 12 of the patent application scope, wherein the metallization structure layer at the bottom of the bump includes a plurality of metal layers formed on the bump pads, wherein the metal layer includes a A first metal layer formed on the bump pad to provide good adhesion between the bump pad and the metallization structure layer at the bottom of the bump; a first metal layer to prevent the bump pad and the bump from forming a common electrode reaction. A second metal layer of a metal compound; and a third metal layer for solder bumps. 1 4. Manufacturing of stacked wafer semiconductor packages as described in item 13 of the patent application 17370石夕品.ptd 第18頁 1240388 六、申請專利範圍 法，其中，該第一金屬層之主要材質可為鋁及鉻其中 之一者。 1 5 .如申請專利範圍第1 3項之堆疊晶片半導體封裝件製 法，其中，該第二金屬層之主要材質可為鎳釩合金。 1 6.如申請專利範圍第1 3項之堆疊晶片半導體封裝件製 法，其中，該第三金屬層之主要材質可為銅、鎳、鉑 及鉬其中之一者。 1 7.如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，其中，形成該凸塊底部金屬化結構層之步驟包括 有： 置備該第一晶片並於其作用表面上形成複數個凸 塊銲墊與銲線墊； 形成該凸塊底部金屬化結構層於該作用表面之凸 塊銲墊與銲線墊上； 形成一以圖案化之光阻層於該凸塊底部金屬化結 構層上，其中該光阻層對應該凸塊銲墊之部分係形成 有將該凸塊底部金屬化結構層裸露於外之開孔； 形成該預銲層於該開孔中之該凸塊底部金屬化結 構層上；以及 將該光阻層移除並蝕刻該凸塊底部金屬化結構 層，藉以形成該預銲層。 1 8.如申請專利範圍第1 7項之堆疊晶片半導體封裝件製 法，其中，該凸塊底部金屬化結構層係透過濺鍍程序 以形成於該作用表面之凸塊銲墊與銲線墊上。17370 Shi Xipin.ptd Page 18 1240388 6. Application for Patent Scope Method, where the main material of the first metal layer may be one of aluminum and chromium. 15. The method for manufacturing a stacked wafer semiconductor package according to item 13 of the patent application scope, wherein the main material of the second metal layer may be a nickel-vanadium alloy. 16. The method for manufacturing a stacked-chip semiconductor package according to item 13 of the patent application scope, wherein the main material of the third metal layer may be one of copper, nickel, platinum, and molybdenum. 1 7. The method for manufacturing a stacked wafer semiconductor package according to item 12 of the patent application scope, wherein the step of forming a metallization structure layer at the bottom of the bump includes: preparing the first wafer and forming a plurality of bumps on an active surface thereof. A block pad and a wire pad; forming the metallization structure layer on the bottom of the bump on the bump pad and the wire pad on the active surface; forming a patterned photoresist layer on the metallization structure layer on the bottom of the bump Wherein, the part of the photoresist layer corresponding to the bump pad is formed with an opening for exposing the metallization structure layer at the bottom of the bump to the outside; forming the presoldering layer at the bottom of the bump for metallization On the structure layer; and removing the photoresist layer and etching the metallization structure layer on the bottom of the bump to form the pre-soldering layer. 1 8. The method for manufacturing a stacked wafer semiconductor package according to item 17 of the patent application scope, wherein the metallization structure layer at the bottom of the bump is formed on the bump pads and wire pads of the active surface through a sputtering process. 17370石夕品.ptd 第19頁 1240388 六、申請專利範圍 1 9 .如申請專利範圍第1 7項之堆疊晶片半導體封裝件製 法，其中，該預銲層係透過電鍍程序以形成於該開孔 中之該凸塊底部金屬化結構層上。 2 0 .如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，其中，該晶片承載件可為一基板及導線架其中之 一者。 2 1.如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，其中，該晶片承載件復形成有複數個用以連接銲 球之銲球銲墊，以及用以連接銲線之銲線墊。 2 2 .如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，其中，該晶片承載件復包括有至少一用以依據該 電子元件之銲結圖式進行線路圖案化以佈設有複數之 導電跡線的佈線層。 2 3 .如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，其中，該第二晶片係透過複數個金屬凸塊與該第 一晶片之凸塊銲墊接置並電性連接。 2 4.如申請專利範圍第2 3項之堆疊晶片半導體封裝件製 法，其中，該複數個金屬凸塊與該預銲層之主要材質 相同，俾於進行銲結程序時增加該第二晶片與該凸塊 銲墊之接合程度。 2 5 .如申請專利範圍第2 4項之堆疊晶片半導體封裝件製 法，其中，該複數個金屬凸塊與該預銲層之主要材質 可為一錫雜合金。 2 6 .如申請專利範圍第1 2項之堆疊晶片半導體封裝件製17370 石 夕 品 .ptd Page 19 1240388 6. Application for Patent Scope 1 9. For the manufacturing method of stacked chip semiconductor package No. 17 in the scope of patent application, wherein the pre-solder layer is formed in the opening through a plating process. The metallization structure layer on the bottom of the bump. 20. The method for manufacturing a stacked wafer semiconductor package according to item 12 of the patent application, wherein the wafer carrier may be one of a substrate and a lead frame. 2 1. The method for manufacturing a stacked wafer semiconductor package according to item 12 of the patent application scope, wherein the wafer carrier is further formed with a plurality of solder ball pads for connecting solder balls, and bonding wires for connecting solder wires. pad. 2 2. The method for manufacturing a stacked wafer semiconductor package according to item 12 of the scope of the patent application, wherein the wafer carrier further includes at least one circuit pattern for arranging a plurality of circuits in accordance with a soldering pattern of the electronic component. A wiring layer for conductive traces. 2 3. The method for manufacturing a stacked wafer semiconductor package according to item 12 of the patent application scope, wherein the second wafer is connected to and electrically connected to the bump pads of the first wafer through a plurality of metal bumps. 2 4. According to the method for manufacturing a stacked wafer semiconductor package according to item 23 of the patent application scope, wherein the plurality of metal bumps are the same as the main material of the pre-soldering layer, the second wafer and the second wafer are added during the bonding process. The degree of bonding of the bumps. 25. The method for manufacturing a stacked wafer semiconductor package according to item 24 of the patent application, wherein the main material of the plurality of metal bumps and the pre-solder layer may be a tin alloy. 2 6. The stacked wafer semiconductor package as in item 12 of the patent application 17370 矽品.ptd 第20頁 1240388 六、申請專利範圍 法，復包括於該第一晶片與該第二晶片間形成有一底 部填膠。 2 7 .如申請專利範圍第1 2項之堆疊晶片半導體封裝件製 法，復包括於該銲線接合及模壓其中之一程序前，藉 由一電漿清潔設備進行該凸塊銲墊、銲線墊及該晶片 承載件之電漿清洗作業。17370 silicon product. Ptd page 20 1240388 6. The scope of patent application method, which includes forming a bottom glue between the first chip and the second chip. 27. If the method for manufacturing a stacked wafer semiconductor package according to item 12 of the scope of the patent application includes the process of bonding and molding one of the bonding wires, the bump pads and bonding wires are performed by a plasma cleaning device. Plasma cleaning of the pad and the wafer carrier. 17370石夕品.ptd 第21頁17370 Shi Xipin.ptd Page 21
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8138599B2 (en) 2006-03-31 2012-03-20 Intel Corporation Wireless communication device integrated into a single package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8138599B2 (en) 2006-03-31 2012-03-20 Intel Corporation Wireless communication device integrated into a single package
US10439265B2 (en) 2006-03-31 2019-10-08 Intel Corporation Single-package wireless communication device
US10727567B2 (en) 2006-03-31 2020-07-28 Intel Corporation Single-package wireless communication device
US11552383B2 (en) 2006-03-31 2023-01-10 Tahoe Research, Ltd. Single-package wireless communication device
US11942676B2 (en) 2006-03-31 2024-03-26 Tahoe Research, Ltd. Single-package wireless communication device

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