TW200939451A - Stacked semiconductor package - Google Patents

Stacked semiconductor package Download PDF

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Publication number
TW200939451A
TW200939451A TW097107901A TW97107901A TW200939451A TW 200939451 A TW200939451 A TW 200939451A TW 097107901 A TW097107901 A TW 097107901A TW 97107901 A TW97107901 A TW 97107901A TW 200939451 A TW200939451 A TW 200939451A
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Taiwan
Prior art keywords
substrate
stacked semiconductor
semiconductor package
package structure
wafer
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TW097107901A
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Chinese (zh)
Inventor
Tong-Hong Wang
Shu-Hua Lee
Ching-Chun Wang
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Advanced Semiconductor Eng
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Priority to TW097107901A priority Critical patent/TW200939451A/en
Publication of TW200939451A publication Critical patent/TW200939451A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

The present invention relates to a stacked semiconductor package. The stacked semiconductor package comprises a first substrate, an upper package, a set of dies, an interposed layer and a first molding compound. The set of dies comprises a first die, a second die and a middle layer. The second die is electrically connected to the first substrate. The middle layer is sandwiched between the first die and the second die. The first die comprises a plurality of first connecting pads that are directly connected to the upper package. The interposed layer is positioned between the first substrate and the upper package, so that the first substrate is electrically connected to the upper package, and a gap is formed between the first substrate and the upper package to accommodate the set of dies. Whereby, the first substrate can receive a plurality of dies, the size of the stacked semiconductor package is reduced, and the density of stacked semiconductor package is increased.

Description

200939451 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體封裝結構，詳言之，係關於一 種堆疊式半導體封裝結構。 【先前技術】 參考圖1，顯示中華民國專利第554509號所揭示之第一 種習知堆疊式半導體封裝結構之示意圖。該第一種習知堆 疊式半導體封裝結構1包括一第一基板11、至少一封裝體 12、一第一晶片13、一中介層14及一第一封膠材料15。該 第一基板11係用以承載該第一晶片13及該中介層14。每一 封裝體12具有一第二基板121、一第二晶片122及一第二封 膠材料123。該第二封膠材料123係包覆該第二晶片122。 該中介層14具有一中介板141及複數個中介接點143，該中 介板141具有一開口 142，用以容置該第一晶片13，該等中 介接點143係用以電性連接該第一基板丨丨、該中介板丨4 j及 該第二基板121 ^該第一封膠材料15係用以包覆該第一晶 片13 〇 該第一種習知堆疊式半導體封裝結構1之缺點如下。該 第基板11及該第二基板121之間僅容納一個第一晶片 13，未能有效提升該第一種習知堆疊式半導體封裝結構1 之晶片堆疊密度。 參考圖2，顯不美國專利公開第2〇〇4/〇〇7〇〇83號所揭示 之第二種習知堆叠式半導體封裝結構之示意圖。該第二種 習知堆疊式半導體封裝結構2包括一第一基板21、一第一 125377.doc 200939451 晶片22、一第二基板23、一第二晶片24、一封膠材料25及 一導電層26。該第一基板21係用以承載該第一晶片22 ^該 第一晶片22係電性連接至該第一基板21。該第二基板23係 位於該第二晶片24之上方。該第二晶片24係電性連接至該 第二基板23。該封膠材料25係用以填充該第一基板21及該 第二基板23間之縫隙。該導電層26係用以使該第一基板2 i 電性連接至該第二基板23。 ❹該第二種習知堆疊式半導體封裝結構2之缺點如下。該 導電層26係垂直連通該第一基板21及該第二基板23，使該 第二種習知堆疊式半導體封裝結構2於電路設計上受限。 因此，有必要提供一種創新且具進步性的堆疊式半導體 封裝結構，以解決上述問題。 【發明内容】 本發明係關於一種堆疊式半導體封裝結構，該堆疊式半 導體封裝結構包括一第一基板、一封裝體、一晶片組、一 〇 中介層及一第一封膠材料。該第一基板具有一第一表面及 一第二表面。該封裝體位於該第一基板上方。該晶片組具 有一第一晶片、一第二晶片及一中間層，該第二晶片係電 性連接至該第一基板之該第一表面，該中間層位於該第二 曰a片及該第一晶片之間，該第一晶片設有複數個第一接 點’且該等第一接點係直接連接至該封裝體。該中介層位 於該第一基板之該第一表面及該封裝體之間，使該第一基 板電性連接至該封裝體，並使該第一基板及該封裝體之間 保持一間距以容納該晶片組。該第一封膠材料包覆該晶片 125377.doc 200939451 組及該中介層。 藉此，該中介層可調整該第一基板及該封裝體之間距， 使該第一基板承載複數個晶片，以縮小封裝體積，增加晶 片堆疊密度。此外，該中介層更包括一中介板 (interp〇ser) ’該中介板係有助於增加該堆疊式半導體封裝 結構於電路設計上之彈性。 【實施方式】 @ 參考圖3’顯示本發明堆疊式半導體封裝結構之第一實 施例之示意圖。該堆疊式半導體封裝結構3包括一第一基 板31、一封裝體32、一晶片組33、一中介層3 4及一第一封 勝材料3 5。 該第一基板31具有一第一表面311及一第二表面312。該 封裝體32位於該第一基板31上方。在本實施例中，該封裝 體32具有一第二基板321、一第三晶片322及一第二封膠材 料323。該弟一基板321具有一第一表面3 24及一第二表面 0 325 ’該第二基板321之該第二表面325設有複數個第二接 點326，該等第二接點326係為銲球。該第三晶片322係黏 附於該第一基板321之該第一表面324上，且利用複數條導 線327電性連接至該第二基板321。該第二封膠材料323係 用以包覆該第三晶片322及該第二基板321之該第一表面 324 ° 該晶片組33具有一第一晶片331、一第二晶片332及一中 間層333。該第一晶片331設有複數個第一接點334，該等 第一接點334係直接連接至該封裝體32。在本實施例中， 125377.doc 200939451200939451 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor package structure, and more particularly to a stacked semiconductor package structure. [Prior Art] Referring to Fig. 1, there is shown a schematic view of a first conventional stacked semiconductor package structure disclosed in the Republic of China Patent No. 554509. The first conventional stacked semiconductor package structure 1 includes a first substrate 11, at least one package 12, a first wafer 13, an interposer 14, and a first encapsulant 15. The first substrate 11 is used to carry the first wafer 13 and the interposer 14. Each package 12 has a second substrate 121, a second wafer 122, and a second sealing material 123. The second sealant 123 covers the second wafer 122. The interposer 14 has an interposer 141 and a plurality of interposing contacts 143. The interposer 141 has an opening 142 for receiving the first chip 13. The intermediate contacts 143 are electrically connected to the first layer. a substrate 丨丨, the interposer 丨 4 j and the second substrate 121 . The first encapsulant 15 is used to coat the first wafer 13 . The disadvantage of the first conventional stacked semiconductor package structure 1 as follows. Having only one first wafer 13 between the first substrate 11 and the second substrate 121 fails to effectively increase the wafer stack density of the first conventional stacked semiconductor package structure 1. Referring to Fig. 2, there is shown a schematic view of a second conventional stacked semiconductor package structure disclosed in U.S. Patent Application Serial No. 2/4/83. The second conventional stacked semiconductor package structure 2 includes a first substrate 21, a first 125377.doc 200939451 wafer 22, a second substrate 23, a second wafer 24, an adhesive material 25, and a conductive layer. 26. The first substrate 21 is used to carry the first wafer 22. The first wafer 22 is electrically connected to the first substrate 21. The second substrate 23 is located above the second wafer 24. The second wafer 24 is electrically connected to the second substrate 23. The encapsulant 25 is used to fill a gap between the first substrate 21 and the second substrate 23. The conductive layer 26 is used to electrically connect the first substrate 2 i to the second substrate 23 . The disadvantages of the second conventional stacked semiconductor package structure 2 are as follows. The conductive layer 26 is perpendicularly connected to the first substrate 21 and the second substrate 23, so that the second conventional stacked semiconductor package structure 2 is limited in circuit design. Therefore, it is necessary to provide an innovative and progressive stacked semiconductor package structure to solve the above problems. SUMMARY OF THE INVENTION The present invention is directed to a stacked semiconductor package structure including a first substrate, a package, a wafer set, an interposer, and a first encapsulant. The first substrate has a first surface and a second surface. The package is located above the first substrate. The chip set has a first chip, a second chip and an intermediate layer, the second chip is electrically connected to the first surface of the first substrate, the intermediate layer is located on the second 曰a piece and the first Between a wafer, the first wafer is provided with a plurality of first contacts 'and the first contacts are directly connected to the package. The interposer is located between the first surface of the first substrate and the package, electrically connecting the first substrate to the package, and maintaining a spacing between the first substrate and the package to accommodate The chip set. The first encapsulant material coats the wafer 125377.doc 200939451 group and the interposer. Thereby, the interposer can adjust the distance between the first substrate and the package, so that the first substrate carries a plurality of wafers to reduce the package volume and increase the wafer stack density. In addition, the interposer further includes an interposer, which helps to increase the flexibility of the stacked semiconductor package structure in circuit design. [Embodiment] @ Referring to Fig. 3', there is shown a schematic view of a first embodiment of a stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 3 includes a first substrate 31, a package 32, a chip set 33, an interposer 34, and a first encapsulating material 35. The first substrate 31 has a first surface 311 and a second surface 312. The package body 32 is located above the first substrate 31. In this embodiment, the package body 32 has a second substrate 321, a third wafer 322, and a second sealing material 323. The second substrate 321 has a first surface 3 24 and a second surface 0 325 ′. The second surface 325 of the second substrate 321 is provided with a plurality of second contacts 326. The second contacts 326 are Solder balls. The third wafer 322 is adhered to the first surface 324 of the first substrate 321 and electrically connected to the second substrate 321 by using a plurality of wires 327. The second encapsulant 323 is used to cover the first surface 324 of the third wafer 322 and the second substrate 321 . The wafer set 33 has a first wafer 331 , a second wafer 332 and an intermediate layer . 333. The first wafer 331 is provided with a plurality of first contacts 334, and the first contacts 334 are directly connected to the package body 32. In this embodiment, 125377.doc 200939451

該等第-接點33错為銲球1第二晶片332係電性連接至 該第-基板31之該第—表面31卜在本實施例中，該第二 晶片332係以覆晶方式附著至該第_基板31之該第一表面 3η上。在本實施例中，該第二晶片332和該第—基板31之 該第-表面311之間沒有填人底膠，但在其他應用中該第 二晶片332和該第-基板31之該第一表面311之間可更包含 -底膠335’用以保護該第二晶片说和該第—基板η的電 性連接，如圖4所示。該中間層333位於該第二晶片332及 該第一晶片331之間。在本實施例中，該中間層333係為-黏合劑，用以黏合該第一晶片331及該第二晶片332。 該中介層34位於該第一基板31之該第一表面3ιι及該封 裝體32之間’使該第一基板31電性連接至該封裝體32，並 使該第-基板31及該封裝體32之間保持一間^以容納該 晶片組33。在本實施例中，該中介層34與該封裝體32相連 接，該中介層34具有一中介板（interp〇ser)341及複數個中 介接點（包括複數個第一中介接點342及複數個第二中介接 點343)。在本實施例中，該中介板341具有一開口 、一 上表面345及一下表面346，該開口 344使該中介板341得以 容置該晶片組33。該等第一中介接點342係為銲球，位於 該上表面345，且與該封裝體32電性連接。該等第二中介 接點343係為銲球，位於該下表面346,且與該第一基板31 電性連接。 該第一封穋材料35包覆該晶片組33及該中介層34。在本 實施例中，該第一封膠材料35更包覆該第一基板31之該第 125377.doc •10- 200939451 —表面311，並顯露出部分該晶片組33之第一接點334及部 分該中介層34之該等第一中介接點342。 參考圖5,顯示本發明堆疊式半導體封裝結構之第二實 施例之不意圖。本實施例之堆疊式半導體封裝結構4與第 一實施例之堆疊式半導體封裝結構3大致相同（圖3)，其中 相同之元件賦予相同之編號。本實施例與第一實施例之不 同處，僅在於該第二晶片332與該第一基板31之電性連接 ❹方式。在本實施例中，該第二晶片332係黏附於該第一基 板31之該第一表面311上，且利用複數條導線336電性連接 至該第一基板31之該第一表面311。 參考圖6,顯示本發明堆疊式半導體封裝結構之第三實 施例之不意圖。本實施例之堆疊式半導體封裝結構5與第 一實施例之堆疊式半導體封裝結構3大致相同（圖3)，其中 相同之元件賦予相同之編號。本實施例與第一實施例之不 同處，僅在於該第三晶片322與該第二基板321之電性連接 ❹ 方式。在本實施例中，該第三晶片322係以覆晶方式附著 至該第二基板321，利用複數個凸塊328電性連接至該第二 基板321之該第一表面324。此外，在該第三晶片322與該 第二基板321之間填入一底膠329以保護該等凸塊328。 參考圖7，顯示本發明堆疊式半導體封裝結構之第四實 施例之示意圖。本實施例之堆疊式半導體封裝結構6與第 一實施例之堆疊式半導體封裝結構3大致相同（圖3)，其中 相同之元件賦予相同之編號。本實施例與第一實施例之不 同處，僅在於該中介層34之結構。在本實施例中，該中介 125377.doc -11 - 200939451 層34具有—中介板（interP〇ser)341及複數個中介接點348， •該中介板341具有一開口 344及複數個貫穿孔347，該開口 344使該中介板341得以容置該晶片組。該等貫穿孔μ? 係環繞該開口 344。該等中介接點348係為銲球，位於該等 貫穿孔347内，且電性連接該第一基板31之第一表面311及 該封裝體32之第二接點326。 參考圖8,顯示本發明堆疊式半導體封裝結構之第五實 〇 施例之示意圖。本實施例之堆疊式半導體封裝結構7與第 一實施例之堆疊式半導體封裝結構3大致相同（圖3)，其中 相同之元件賦予相同之編號。本實施例與第一實施例之不 同處，僅在於該中介層34之結構。在本實施例中，該中介 層34係為複數個中介接點348，且該等中介接點348係電性 連接該第-基板31之第一表面311及該封裝體32之第二接 點 326。 參考圖9，顯示本發明堆疊式半導體封裝結構之第六實 〇 _之示意、®。本實施例之堆叠式半導體封裝結構8與第 實施例之堆疊式半導體封裝結構3大致相同（圖3)，其中 相同之元件賦予相同之編號。本實施例與第一實施例之不 同處在於該封裝體32之結構及該第一封膠材料所包覆 之範圍。在本實施例中，該等第二接點326(圖3)係省略， 因此，該等第一接點334及該等第一中介接點342係直接連 接該第一基板321之第二表面325。該第一封膠材料35係包 覆該第一基板31之第一表面311、該封裝體32、該晶片組 33及該中介層34。 125377.doc •12- 200939451 參考圖ίο，顯示本發明堆疊式半導體封裝結構之第七實 施例之示意圖。本實施例之堆疊式半導體封裝結構9與第 一實施例之堆疊式半導體封裝結構3大致相同（圖3)，其中 相同之元件賦予相同之編號。本實施例與第一實施例2不 同處’在於該封裝體32之結構及該第—封膠材㈣所包覆 之範圍。在本實施例中，該封震體32不具有該第二封勝材 料323(圖3)。該等第二接點326⑽3)係省略，因此，該等 Ο ❹ 第-接點334及該等第一中介接點342係直接連接該第二基 板切之第二表面325。該第一封膠材料35係包覆該第一基 ㈣之第-表面311、該封裝體32、該晶片組似該中介 層34。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士對上述實施例進 行修改及變化仍不脫本發明之精神。本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示第—種習知堆疊式半導體封裝結構之示意圖； 圖2顯示第二種習知堆疊式半導體封ι结構之示意圖； 圖3顯示本發明堆疊式半導體封裝結 例之 示意圖； β β 圖4顯示本發明堆疊式 另-種態樣以意圖+導體封裝結構之第—實施例之 顯不本發明堆疊式半導體封裝結構之第二實施例之 尔惠圖， 125377.doc 13- 200939451 圖6顯示本發明堆疊式半導體封裝結構之第三實施例之 不意圖， 圖7顯示本發明堆疊式半導體封裝結構之第四實施例之 不意圖； 圖8顯示本發明堆疊式半導體封裝結構之第五實施例之 示意圖； 圖9顯示本發明堆叠式半導體封裝結構之第六實施例之 不意圖；及The second contact 332 of the solder ball 1 is electrically connected to the first surface 31 of the first substrate 31. In the embodiment, the second wafer 332 is attached in a flip chip manner. Up to the first surface 3n of the first substrate 31. In this embodiment, the second wafer 332 and the first surface 311 of the first substrate 31 are not filled with a primer, but in other applications, the second wafer 332 and the first substrate 31 are A surface 311 may further include a primer 335' for protecting the second wafer from being electrically connected to the first substrate η, as shown in FIG. The intermediate layer 333 is located between the second wafer 332 and the first wafer 331. In the embodiment, the intermediate layer 333 is a bonding agent for bonding the first wafer 331 and the second wafer 332. The interposer 34 is located between the first surface 3 of the first substrate 31 and the package 32. The first substrate 31 is electrically connected to the package 32, and the first substrate 31 and the package are provided. A ^ is held between 32 to accommodate the wafer set 33. In this embodiment, the interposer 34 is connected to the package 32. The interposer 34 has an interposer 341 and a plurality of intervening contacts (including a plurality of first intervening contacts 342 and plural). A second intermediary contact 343). In the present embodiment, the interposer 341 has an opening, an upper surface 345 and a lower surface 346. The opening 344 allows the interposer 341 to accommodate the wafer set 33. The first intermediate contacts 342 are solder balls located on the upper surface 345 and electrically connected to the package 32. The second intermediate contacts 343 are solder balls located on the lower surface 346 and electrically connected to the first substrate 31. The first sealing material 35 covers the wafer set 33 and the interposer 34. In this embodiment, the first sealing material 35 further covers the surface 311 of the first substrate 31 and exposes a portion of the first contact 334 of the chip set 33 and The first intermediate contacts 342 of the interposer 34 are partially. Referring to Fig. 5, there is shown a second embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 4 of the present embodiment is substantially the same as the stacked semiconductor package structure 3 of the first embodiment (Fig. 3), wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment lies only in the electrical connection mode of the second wafer 332 and the first substrate 31. In this embodiment, the second wafer 332 is adhered to the first surface 311 of the first substrate 31, and is electrically connected to the first surface 311 of the first substrate 31 by using a plurality of wires 336. Referring to Fig. 6, there is shown a third embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 5 of the present embodiment is substantially the same as the stacked semiconductor package structure 3 of the first embodiment (Fig. 3), wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is only in the manner of electrically connecting the third wafer 322 and the second substrate 321 . In this embodiment, the third wafer 322 is attached to the second substrate 321 in a flip chip manner, and is electrically connected to the first surface 324 of the second substrate 321 by using a plurality of bumps 328. In addition, a primer 329 is filled between the third wafer 322 and the second substrate 321 to protect the bumps 328. Referring to Fig. 7, there is shown a schematic view of a fourth embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 6 of the present embodiment is substantially the same as the stacked semiconductor package structure 3 of the first embodiment (Fig. 3), wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment lies only in the structure of the interposer 34. In this embodiment, the intermediary 125377.doc -11 - 200939451 layer 34 has an interposer 341 and a plurality of intervening contacts 348. The interposer 341 has an opening 344 and a plurality of through holes 347. The opening 344 allows the interposer 341 to accommodate the wafer set. The through holes μ are surrounded by the opening 344. The intermediate contacts 348 are solder balls, and are located in the through holes 347 and electrically connected to the first surface 311 of the first substrate 31 and the second contact 326 of the package 32. Referring to Figure 8, there is shown a schematic diagram of a fifth embodiment of a stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 7 of the present embodiment is substantially the same as the stacked semiconductor package structure 3 of the first embodiment (Fig. 3), wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment lies only in the structure of the interposer 34. In this embodiment, the interposer 34 is a plurality of interposing contacts 348, and the interposing contacts 348 are electrically connected to the first surface 311 of the first substrate 31 and the second contact of the package 32. 326. Referring to Fig. 9, there is shown a sixth embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 8 of the present embodiment is substantially the same as the stacked semiconductor package structure 3 of the first embodiment (Fig. 3), wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment lies in the structure of the package body 32 and the extent to which the first sealant material is covered. In this embodiment, the second contacts 326 (FIG. 3) are omitted. Therefore, the first contacts 334 and the first intermediate contacts 342 are directly connected to the second surface of the first substrate 321 . 325. The first encapsulant 35 covers the first surface 311 of the first substrate 31, the package 32, the wafer set 33, and the interposer 34. 125377.doc • 12- 200939451 Referring to the drawings, a schematic view of a seventh embodiment of a stacked semiconductor package structure of the present invention is shown. The stacked semiconductor package structure 9 of the present embodiment is substantially the same as the stacked semiconductor package structure 3 of the first embodiment (Fig. 3), wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment 2 lies in the structure of the package body 32 and the extent to which the first sealant (4) is covered. In the present embodiment, the sealing body 32 does not have the second sealing material 323 (Fig. 3). The second contacts 326(10)3) are omitted. Therefore, the first contacts 334 and the first intermediate contacts 342 are directly connected to the second substrate 325 of the second substrate. The first encapsulant 35 coats the first surface 311 of the first base (4), the package 32, and the wafer group resembles the interposer 34. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can devise modifications and variations of the embodiments described above without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a first conventional stacked semiconductor package structure; FIG. 2 is a schematic view showing a second conventional stacked semiconductor package structure; FIG. 3 is a view showing a stacked semiconductor package according to the present invention. FIG. 4 shows a second embodiment of the stacked semiconductor package structure of the present invention in the form of a stacked-in other embodiment of the present invention, which is intended to be a +-conductor package structure, 125377. Doc 13-200939451 FIG. 6 shows a third embodiment of the stacked semiconductor package structure of the present invention, FIG. 7 shows a fourth embodiment of the stacked semiconductor package structure of the present invention; FIG. 8 shows a stacked semiconductor of the present invention. FIG. 9 is a schematic view showing a sixth embodiment of the stacked semiconductor package structure of the present invention; and

❹ 圖10顯示本發明堆疊式半導體封裝結構之第七實施例之 示意圖。 【主要元件符號說明】 1 第一種習知堆疊式半導體封裝結構 2 第二種習知堆疊式半導體封裝結構 3 本發明堆疊式半導體封裝結構之第一實施例 4 本發明堆疊式半導體封裝結構之第二實施例 5 本發明堆疊式半導體封裝結構之第三實施例 6 本發明堆疊式半導體封裝結構之第四實施例 7 本發明堆疊式半導體封裝結構之第五實施例 8 本發明堆疊式半導體封裝結構之第六實施例 9 本發明堆疊式半導體封裝結構之第七實施例 11 第一基板 12 封裝體 13 第一晶片 14 中介層 125377.doc •14- 200939451 ❹Figure 10 is a view showing a seventh embodiment of the stacked semiconductor package structure of the present invention. [Main component symbol description] 1 The first conventional stacked semiconductor package structure 2 The second conventional stacked semiconductor package structure 3 The first embodiment of the stacked semiconductor package structure of the present invention 4 The stacked semiconductor package structure of the present invention Second Embodiment 5 Third Embodiment 6 of Stacked Semiconductor Package Structure of Present Invention Fourth Embodiment 7 of Stacked Semiconductor Package Structure of Present Invention Fifth Embodiment 8 of Stacked Semiconductor Package Structure of Present Invention Stacked Semiconductor Package of Present Invention Sixth Embodiment of Structure 9th Embodiment 11 of the stacked semiconductor package structure of the present invention 11 First substrate 12 Package 13 First wafer 14 Interposer 125377.doc • 14- 200939451 ❹

15 第一封膠材料 21 第一基板 22 第一晶片 23 第二基板 24 苐二晶片 25 封膠材料 26 導電層 31 第一基板 32 封裝體 33 晶片組 34 中介層 35 第一封膠材料 121 第二基板 122 第二晶片 123 第二封膠材料 141 中介板 142 開口 143 中介接點 311 第一表面 312 第二表面 321 第二基板 322 第三晶片 323 第二封膠材料 324 第一表面 125377.doc -15- 20093945115 first adhesive material 21 first substrate 22 first wafer 23 second substrate 24 second wafer 25 encapsulant 26 conductive layer 31 first substrate 32 package 33 wafer set 34 interposer 35 first adhesive material 121 Second substrate 122 second wafer 123 second encapsulant 141 interposer 142 opening 143 intermediate contact 311 first surface 312 second surface 321 second substrate 322 third wafer 323 second encapsulant 324 first surface 125377.doc -15- 200939451

325 第二表面 326 第二接點 327 導線 328 凸塊 329 底膠 331 第'一晶片 332 第二晶片 333 中間層 334 第一接點 335 底膠 336 導線 341 中介板 342 第一中介接點 343 第二中介接點 344 開口 345 上表面 346 下表面 347 貫穿孔 348 中介接點 125377.doc -16325 second surface 326 second contact 327 wire 328 bump 329 primer 331 first wafer 332 second wafer 333 intermediate layer 334 first contact 335 primer 336 wire 341 interposer 342 first intermediate contact 343 Two intermediate contacts 344 openings 345 upper surface 346 lower surface 347 through holes 348 intermediate contacts 125377.doc -16

Claims (1)

200939451 十、申請專利範圍： L 一種堆疊式半導體封裝結構，包括： -第-基板’具有一第一表面及一第二表面； 一封裝體，位於該第一基板上方； -晶片組’具有一第一晶片、一第二晶片及一中間 層，該第二晶片係電性連接至該第一基板之該第一表 ::該中間層位於該第二晶片及該第—晶片之間，該第200939451 X. Patent Application Range: L A stacked semiconductor package structure comprising: - a first substrate having a first surface and a second surface; a package above the first substrate; - a wafer set 'having a a first wafer, a second wafer, and an intermediate layer, the second wafer is electrically connected to the first surface of the first substrate: the intermediate layer is located between the second wafer and the first wafer, First ❹ 一晶片設有複數個第-接點，且該等第—接點係直接連 接至該封裝體； 一中介層，位於該第一基板之該第一表面及該封裝體 之間，使該第一基板電性連接至該封裝體，並使該第一 基板及該封裝體之間保持一間距以容納該晶片組；及 一第一封膠材料，包覆該晶片組及該中介層。 2·如請求項丨之堆疊式半導體封裝結構，其中該等第一接 點係為銲球。 3·如凊求項1之堆疊式半導體封裝結構，其中該第一封膠 材料更包覆該第一基板之該第一表面。 4. 如請求項1之堆疊式半導體封裝結構，其中該第一封膠 材料顯露出部分該晶片組之第一接點及部分該中介層。 5. 如請求項1之堆疊式半導體封裝結構，其中該第一封膠 材料更包覆該第一基板之該第一表面及該封裝體。 6. 如請求項1之堆疊式半導體封裝結構，其中該封裝體具 有一第二基板、一第三晶片，該第二基板具有一第一表 面及一第二表面’該第二基板之該第二表面設有複數個 125377.doc 200939451 二基板之該第一表面 第二接點係連接該等第一接點 第二接點，該等 晶片係位於該第 第一表面。 ，該第三 且電性連接至該 7·:請求項6之堆疊式半導體封裝結構，其中該封裝體更 匕含-第二封膠材料’該第二封膠材料包覆該第三晶片 及該第二基板之部分該第一表面。 東項6之堆疊式半導體封裝結構，其中該等第二接❹ a chip is provided with a plurality of first contacts, and the first contacts are directly connected to the package; an interposer is located between the first surface of the first substrate and the package, so that The first substrate is electrically connected to the package, and a gap is maintained between the first substrate and the package to accommodate the chip set; and a first encapsulant material covers the chip set and the interposer. 2. A stacked semiconductor package structure as claimed in claim 1, wherein the first contacts are solder balls. 3. The stacked semiconductor package structure of claim 1, wherein the first encapsulant further covers the first surface of the first substrate. 4. The stacked semiconductor package structure of claim 1, wherein the first encapsulant material exposes a portion of the first contact of the wafer set and a portion of the interposer. 5. The stacked semiconductor package structure of claim 1, wherein the first encapsulant further covers the first surface of the first substrate and the package. 6. The stacked semiconductor package structure of claim 1, wherein the package has a second substrate and a third wafer, the second substrate having a first surface and a second surface The second surface is provided with a plurality of 125377.doc 200939451. The first surface of the second substrate is connected to the second contacts of the first contacts, and the wafers are located on the first surface. The third semiconductor device is electrically connected to the stacked semiconductor package structure of claim 7 , wherein the package further comprises a second sealing material, the second sealing material coating the third wafer and A portion of the second substrate is the first surface. Stacked semiconductor package structure of the East Asia 6, wherein the second connection 點係為鲜球。 =求項6之堆疊式半導體封裝結構，其中該封裝體之 三晶片係以覆晶方式附著至該第二基板。 1〇.如=求項6之堆疊式半導體封裝結構，其中該封裝體更 包：：底膠填充於該第三晶片及該第二基板之間。 U·如請求項6之堆疊式半導體封裝結構，其中該封裝體之 該第三晶片係黏附於該第二基板之該第一表面上，且利 用複數條導線電性連接至該第二基板。 12.如請求項1之堆疊式半導體封裝結構，纟中該封裝體與 該中介層相連接。 13 =請求項1之堆叠式半導體封裝結構，纟中該晶片組之 該第一晶片係以覆晶方式附著至該第一基板之該第一表 面上。 14_如請求項1之堆疊式半導體封裝結構，其中該晶片組之 以第二晶片係黏附於該第一基板之該第一表面上，且利 15 ^數條導線電性連接至該第-基板之該第-表面。 /項1之堆疊式半導體封裝結構，其中該中間層係 125377.doc 200939451 為一黏合劑。 16. 如請求項丨之堆疊式半導體封裝結構，其中該中介層包 括一中介板（interposer)及複數個中介接點，該中介板具 有一開口 ’以容置該晶片組。 17. 如請求項16之堆疊式半導體封裝結構，其中該等中介接 點係為銲球。 18·如請求項16之堆疊式半導體封裝結構，其中該中介板 (interp〇Ser)更包括一上表面及一下表面，該等中介接點 〇 包括複數個第一中介接點及複數個第二中介接點，該等 第一中介接點位於該上表面，該等第一中介接點係與該 封裝體電性連接’該等第二中介接點位於該下表面該 等第二中介接點係與該第一基板電性連接。 19.如請求項18之堆疊式半導體封裝結構，其中該等第一中 介接點及該等第二中介接點係為銲球。 20·如請求項16之堆疊式半導體封裝結構，其中該中介板 (_ΓΡ_)更包括複數個貫纽，該等貫穿孔係環繞該 開口，該等中介接點係位於該等貫穿孔内，且該等中介 接點係與該封裝體電性連接。 2!.如請求項20之堆疊式半導體封裝結構，其中該等十介接 點係為銲球》 22·如請求項！之堆疊式半導體封裝結構，其中該中介層係 為複數個巾介接點，該# _介接點係與該封裝體電性連 結構，其中該等中介接 23.如請求項22之堆疊式半導體封裝 點係為銲球。 125377.docThe point is a fresh ball. = The stacked semiconductor package structure of claim 6, wherein the three wafers of the package are attached to the second substrate in a flip chip manner. 1. The stacked semiconductor package structure of claim 6, wherein the package further comprises: a primer filled between the third wafer and the second substrate. The stacked semiconductor package structure of claim 6, wherein the third wafer of the package is adhered to the first surface of the second substrate, and the plurality of wires are electrically connected to the second substrate. 12. The stacked semiconductor package structure of claim 1, wherein the package is connected to the interposer. 13 = The stacked semiconductor package structure of claim 1, wherein the first wafer of the wafer set is flip-chip bonded to the first surface of the first substrate. The stacked semiconductor package structure of claim 1, wherein the second wafer is adhered to the first surface of the first substrate, and the plurality of wires are electrically connected to the first The first surface of the substrate. The stacked semiconductor package structure of item 1, wherein the intermediate layer is 125377.doc 200939451 is a binder. 16. The stacked semiconductor package structure of claim 1, wherein the interposer comprises an interposer and a plurality of interposers, the interposer having an opening to accommodate the wafer set. 17. The stacked semiconductor package structure of claim 16, wherein the intermediate contacts are solder balls. 18. The stacked semiconductor package structure of claim 16, wherein the interposer further comprises an upper surface and a lower surface, the intermediate contacts comprising a plurality of first intermediate contacts and a plurality of second The first intermediate contact is located on the upper surface, and the first intermediate contact is electrically connected to the package. The second intermediate contacts are located on the lower surface of the second intermediate contact. And electrically connected to the first substrate. 19. The stacked semiconductor package structure of claim 18, wherein the first intermediate contact points and the second intermediate contacts are solder balls. The stacked semiconductor package structure of claim 16, wherein the interposer (_ΓΡ_) further comprises a plurality of through-holes surrounding the opening, the intermediate contacts being located in the through holes, and The intermediate contacts are electrically connected to the package. 2! The stacked semiconductor package structure of claim 20, wherein the ten contacts are solder balls. 22 If requested! The stacked semiconductor package structure, wherein the interposer is a plurality of towel interface points, and the #_ interface is electrically connected to the package, wherein the interposer is 23. The stacking of claim 22 The semiconductor package points are solder balls. 125377.doc
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI468086B (en) * 2012-11-07 2015-01-01 Universal Scient Ind Shanghai Electronic device, system package module and method of manufactoring system package module
TWI587412B (en) * 2014-05-08 2017-06-11 矽品精密工業股份有限公司 Package structures and methods for fabricating the same
TWI614865B (en) * 2010-12-16 2018-02-11 英特爾公司 Lower ic package structure for coupling with an upper ic package to form a package-on-package (pop) assembly and pop assembly including such a lower ic package structure
TWI791881B (en) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 Electronic package, assemble substrate and fabrication method thereof
US11610844B2 (en) 2017-10-11 2023-03-21 Octavo Systems Llc High performance module for SiP

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614865B (en) * 2010-12-16 2018-02-11 英特爾公司 Lower ic package structure for coupling with an upper ic package to form a package-on-package (pop) assembly and pop assembly including such a lower ic package structure
US10879219B2 (en) 2010-12-16 2020-12-29 Intel Corporation Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure
TWI468086B (en) * 2012-11-07 2015-01-01 Universal Scient Ind Shanghai Electronic device, system package module and method of manufactoring system package module
TWI587412B (en) * 2014-05-08 2017-06-11 矽品精密工業股份有限公司 Package structures and methods for fabricating the same
US11610844B2 (en) 2017-10-11 2023-03-21 Octavo Systems Llc High performance module for SiP
TWI791881B (en) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 Electronic package, assemble substrate and fabrication method thereof

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