TWM521807U - Package structure and intermediate board thereof - Google Patents

Description

Package structure and its interposer

This creation is about a package structure, especially regarding a package structure and its interposer for applying wire bonding technology.

At present, there are many technologies applied in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (referred to as Multi-Chip Module). MCM) and other flip-chip package modules, or three-dimensional stacking of wafers into a three-dimensional integrated circuit (3D IC) wafer stacking technology.

1A to 1C are schematic cross-sectional views showing the fabrication of a conventional 2.5D and/or 3D semiconductor package 1.

As shown in Fig. 1A, a substrate 10' is provided, and a plurality of vias 100a are formed on the substrate 10'.

As shown in FIG. 1B, the insulating material 100b is first formed on the hole walls of the through holes 100a, and the metal material is filled in the through holes 100a, and a line redistribution layer (RDL) 15 is formed thereon. The germanium substrate 10' is formed to form a silicon interposer 10 having a through-silicon via (TSV) 100.

As shown in FIG. 1C, a semiconductor wafer 11 has a small pitch. The electrode pad 110 is electrically coupled to the conductive via hole 100 by a plurality of solder bumps 13 , and the solder bumps 13 are covered with the primer 12 . Next, an encapsulant 16 is formed on the germanium interposer 10 to cover the semiconductor wafer 11. Then, a plurality of solder pads 180 are electrically connected to the package substrate 18 by the plurality of solder balls 17 on the circuit redistribution structure 15 , and the solder balls 17 are covered with the primer 14 .

However, in the conventional method for fabricating the 2.5D and/or 3D semiconductor package 1, when the germanium interposer 10 is fabricated, the process of the conductive germanium via 100 needs to be punctured on the germanium substrate 10' (ie, via exposure development). The patterning process such as etching forms the through holes 100a) and the metal filling holes, so that the manufacturing cost of the overall process is increased, and the manufacturing time is time consuming (since the foregoing steps are tedious, in particular, etching the germanium substrate 10' to form the perforations. 100a), so that the cost and price of the final product are difficult to reduce.

Furthermore, the end face width D of the conductive crucible 100 is extremely large, and the end face of the conductive crucible 100 is used as an external contact. Therefore, when the number of the external contacts is increased, the spacing between the conductive crucibles 100 needs to be reduced. When the solder bumps 13 are reflowed, bridging problems easily occur between the solder bumps 13.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides an interposer comprising: an encapsulation layer; and a plurality of conductor bodies embedded in the encapsulation layer and each having an opposite ball end exposed to the encapsulation layer With the line end.

The present invention also provides a package structure, comprising: an encapsulation layer; at least one electronic component embedded in the encapsulation layer; a plurality of conductor bodies embedded in the encapsulation layer and each having an exposed encapsulation layer The opposite ball end and the wire end; and a circuit layer are formed on the encapsulation layer and electrically connected to each of the wire bodies.

In the above package structure, the electronic component is provided with a plurality of conductive elements located in the package layer and exposed to the package layer. For example, the conductive element includes a spike line and a solder bump that covers the spike line.

In the foregoing package structure, another electronic component is disposed on the circuit layer and the encapsulation layer.

In the foregoing package structure, another circuit layer, another encapsulation layer and another electronic component disposed on the circuit layer and the encapsulation layer are further included, wherein the other electronic component is disposed on the circuit layer and the encapsulation layer The other encapsulation layer is disposed on the circuit layer and the encapsulation layer and covers the other electronic component, and the other circuit layer is disposed on the other encapsulation layer.

In the above package structure and interposer, the wire system is in the shape of a nail.

In the foregoing package structure and interposer, the wire body has a line width of not more than 300 micrometers.

It can be seen from the above that in the package structure and the interposer thereof, the wire body can be used as a conductive path, and the line width can be no more than 300 micrometers, so that the distance between the wire bodies can be reduced, so The known technology is limited by the specification of the conductive perforation. The package structure and the interposer of the present invention can reduce the distance between the contacts to increase the contact density, thereby reducing the package structure (and the interposer). Area or volume, and can increase the electronic component Electrical I/O density.

Moreover, the wire system is manufactured by a simple existing wire bonding method, so that the intermediate board of the present invention can significantly reduce the cost and manufacturing cycle compared to the process of the conventional 矽 interposer.

1‧‧‧Semiconductor package

10‧‧‧矽Intermediary board

10'‧‧‧矽 substrate

100‧‧‧ Conductive piercing

100a‧‧‧Perforation

100b‧‧‧Insulation

11‧‧‧Semiconductor wafer

110,300‧‧‧electrode pads

12,14‧‧‧Bottom

13,31a‧‧‧ solder bumps

15‧‧‧Line redistribution structure

16‧‧‧Package colloid

17,36‧‧‧ solder balls

18‧‧‧Package substrate

180‧‧‧ solder pads

2‧‧‧Intermediary board

20‧‧‧Loading board

21‧‧‧ release layer

22‧‧‧metal layer

23,23’‧‧‧ wire body

23a‧‧‧ ball end

23b‧‧‧Line end

24, 24', 24" ‧ ‧ encapsulation

24a‧‧‧ first surface

24b‧‧‧second surface

3‧‧‧Package structure

30‧‧‧First electronic components

30a‧‧‧Action surface

30b‧‧‧Non-active surface

31,31’,31”‧‧‧Electrical components

32‧‧‧Staple line

32a‧‧‧ head end

32b‧‧‧ cutting-edge

33,33’‧‧‧Line layer

34‧‧‧Second electronic components

35‧‧‧ Third electronic component

37‧‧‧Electrical contact pads

D‧‧‧ face width

D‧‧‧distance

T‧‧‧thickness

w‧‧‧Line width

1A to 1C are schematic cross-sectional views showing a method of manufacturing a conventional 2.5D and/or 3D semiconductor package; FIGS. 2A to 2D are schematic cross-sectional views showing a method of manufacturing the interposer of the present invention; and Figs. 3A to 3F A schematic cross-sectional view of a method of fabricating a package of the present invention; wherein the 3A' is a partially enlarged view of an embodiment of FIG. 3A.

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure of the present disclosure.

It is to be understood that the structure, the proportions, the size and the like of the drawings are only used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effectiveness and the purpose of the creation. The technical content revealed by the creation can be covered. At the same time, the terms "upper", "first", "second", "third" and "one" as quoted in this specification are only It is convenient to describe the scope, not to limit the scope of the creation of the creation, and the change or adjustment of the relative relationship is considered to be the scope of the creation of the creation without any substantial change in the technical content.

The 2A to 2D drawings are schematic cross-sectional views of the manufacturing method of the intervening board 2 of the present invention.

As shown in FIG. 2A, a carrier 20 is provided, and a release layer 21 and a metal layer 22 are sequentially formed on the carrier 20.

In the embodiment, the material of the carrier plate 20 is made of a polymer material or a composite material. Specifically, the material forming the carrier plate 20 is a metal material, a dielectric material, a ceramic material, a glass material, a semiconductor material, a circuit board, a plastic material, a homogenous composite material or a heterogeneous composite material, but is not limited thereto, and A viscous release layer 21 is formed on the carrier sheet 20 by coating or lamination.

Further, the metal layer 22 is a copper foil, an aluminum foil, a silver foil or a gold foil, but is not limited thereto, and its thickness t may be 50 micrometers (μm) or less.

As shown in FIG. 2B, a plurality of wire bodies 23 are formed on the metal layer 22, and the wire body 23 has a ball end 23a that bonds the metal layer 22 and a wire end 23b that faces the ball end 23a.

In this embodiment, the wire body 23 is formed by a wire bonding (WB) method to form an upright stub, which is used as an interconnected circuit structure, which can be uniformly or non-uniformly distributed, and the wire is fabricated. The material of the body 23 is gold, silver, copper, an alloy of the above materials, nickel-coated copper, nickel-coated silver, palladium-coated copper or nickel-palladium-coated copper.

Furthermore, the line width w of the wire body 23 can be made according to requirements, and the size can be more than one type. Specifically, the line width w of the wire body 23 is not More than 300 microns, more preferably no more than 100 microns, and most preferably no more than 50 microns.

Moreover, since the combination of the wire body 23 and the metal material is preferred, the wire body 23 can be advantageously erected on the carrier plate 20 by the design of the metal layer 22.

As shown in FIG. 2C, an encapsulation layer 24 for covering the lead bodies 23 is formed on the metal layer 22, and the encapsulation layer 24 has a first surface 24a for bonding the metal layer 22 and opposite thereto. The second surface 24b of the first surface 24a.

In this embodiment, the process of the encapsulation layer 24 may be selected from a liquid compound, an injection, or a compression molding process.

Furthermore, the wire end 23b of the wire body 23 is exposed on the second surface 24b of the encapsulation layer 24. For example, the wire end 23b of the wire body 23 is exposed to the second surface 24b of the encapsulation layer 24 by a leveling process. Specifically, the flattening process removes a portion of the material of the encapsulation layer 24 and a portion of the wire end 23b of the wire body 23 by grinding and polishing, so that the wire end 23b of the wire body 23 is flush with the package. The second surface 24b of layer 24.

As shown in FIG. 2D, the carrier 20, the release layer 21 and the metal layer 22 are removed to expose the ball end 23a of the lead body 23 to the first surface 24a of the encapsulation layer 24, thereby forming the present invention. Intermediary board 2.

In the present embodiment, the carrier layer 20 is first peeled off from the metal layer 22 by the release layer 21, and the metal layer 22 is etched.

In other embodiments, the metal layer 22 may also be retained for subsequent processing. In the process, the metal layer 22 is used to fabricate the RDL.

The manufacturing method of the interposer 2 mainly adopts the wire body 23 as a conductive path, and the line width w can be no more than 50 micrometers (μm), so that the distance d between the wire bodies 23 can be extremely small, so Due to the limitation of the conventional technology to the specification of the conductive perforation, the intervening board 2 of the present invention can meet the demand for miniaturization.

Furthermore, by replacing the conventional conductive crucible with the wire body 23, the density of the contact between the contacts (such as the ball end 23a or the wire end 23b) can be increased, so that the area or volume of the interposer 2 can be reduced, and Increase the density of electrical I/O.

Moreover, the lead body 23 is manufactured by a simple conventional wire bonding method, so that the interposer of the present invention can significantly reduce the cost compared with the conventional interposer.

3A to 3F are schematic cross-sectional views showing the manufacturing method of the package structure 3 of the present invention. In this embodiment, the process of the above-mentioned interposer 2 is applied, so that only the differences will be described below, and the same points will not be described again.

As shown in FIG. 3A, following FIG. 2A, a plurality of conductor bodies 23 are placed on the metal layer 22 and a first electronic component 30 is disposed.

In this embodiment, the first electronic component 30 is, for example, an active component (such as a semiconductor wafer) or a passive component (such as a capacitor, an inductor, or a resistor). Specifically, the first electronic component 30 is a semiconductor wafer having an opposite active surface 30a and a non-active surface 30b, the active surface 30a having a plurality of electrode pads 300 (as shown in FIG. 3A'), and each of the electrodes The pad 300 is bonded to the metal layer 22 by a plurality of conductive elements 31.

Further, as shown in Fig. 3A', the conductive member 31 is composed of a spike line 32 and a solder bump 31a, which is a gold made by a wire bonding machine. A wire, a silver wire, a copper wire or an alloy thereof, and the solder bump 31a covers the spike line 32. Specifically, the spike line 32 has a tip end 32a that is coupled to the electrode pad 300 and a tip end 32b opposite the head end 32a, and the solder bump 31a contacts the metal layer 22, and the tip end 32b is selectively contactable or untouched. The metal layer 22 is.

Moreover, in other embodiments, a plurality of first electronic components 30 may also be disposed on the metal layer 22.

As shown in FIG. 3B, an encapsulation layer 24 is formed on the metal layer 22 such that the encapsulation layer 24 covers each of the lead bodies 23 and the first electronic component 30.

In this embodiment, the inactive surface 30b of the first electronic component 30 is embedded in the second surface 24b of the encapsulation layer 24, and the line end 23b of the lead body 23 is exposed to the second portion of the encapsulation layer 24. Surface 20b.

As shown in FIG. 3C, a wiring layer 33 is formed on the second surface 24b of the encapsulation layer 24, and the wiring layer 33 is in contact with and electrically connected to the line ends 23b of the respective lead bodies 23.

In this embodiment, the circuit layer 33 is a layer of a redistribution layer (RDL), which is a fan out type. In other embodiments, a multi-layer line weight can be selected according to actual needs. A layer of cloth (RDL) is on the second surface 24b of the encapsulation layer 24.

As shown in FIG. 3D, the process of FIGS. 3A to 3C is repeated as needed, that is, the wire body 23' is formed on the circuit layer 33, and at least one second electronic component 34 is disposed, and another package layer 24' is formed. The second surface 24b of the encapsulation layer 24 is formed on the other encapsulation layer 24', and the circuit layer 33' contacts and electrically connects the respective lead bodies 23'.

In this embodiment, the second electronic component 34 is, for example, an active component (such as a semiconductor wafer) or a passive component (such as a capacitor, an inductor, or a resistor).

Furthermore, the second electronic component 34 is bonded to the wiring layer 33 by a plurality of conductive elements 31', and the structure of the conductive component 31' can be the same as that of the conductive component 31.

As shown in FIG. 3E, the partial process of FIGS. 3A to 3B is repeated as needed, that is, at least one third electronic component 35 is disposed on the circuit layer 33', and another package layer 24 is formed on the package layer 24. 'on.

In this embodiment, the third electronic component 35 is, for example, an active component (such as a semiconductor wafer) or a passive component (such as a capacitor, an inductor, or a resistor).

Furthermore, the third electronic component 35 is bonded to the circuit layer 33' by a plurality of conductive elements 31", and the structure of the conductive element 31" can be the same as that of the conductive element 31.

It should be understood that each layer of encapsulation layers 24, 24', 24" may contain unequal numbers of first electronic component 30, second electronic component 34 and third electronic component 35, and they may each be of different sizes and may be They are distributed in the same package without equidistant distance according to design requirements.

As shown in FIG. 3F, the carrier 20, the release layer 21 and the metal layer 22 are removed, so that the ball end 23a of the wire body 23 and the conductive element 31 are exposed on the first surface 24a of the encapsulation layer 24, In order to become a stacked package structure 3. Then, a plurality of solder balls 36 are formed on the ball end 23a of the wire body 23, and the solder balls 36 are electrically connected to the wire body 23, so that the stacked package structure 3 is connected by the solder balls 36. Such as the electronic device of the circuit board (not shown).

In this embodiment, on the first surface 24a of the encapsulation layer 24, First, an electrical contact pad 37 is formed on the ball end 23a of the wire body 23 and the conductive member 31, and the solder ball 36 is formed on the electrical contact pad 37.

The manufacturing method of the package structure 3 of the present invention uses the wire body 23 as a conductive path, and the line width w can be no more than 50 micrometers (μm), so that the distance d between the wire bodies 23 can be extremely small, so Due to the limitation of the conventional technology to the specification of the conductive perforation, the package structure 3 of the present invention can meet the demand for miniaturization.

Furthermore, by replacing the conventional conductive germanium perforations with the lead body 23, the density of the contacts (such as the respective electrical contact pads 37 or the respective circuit layers 33, 33') can be increased, that is, the distance between the contacts is reduced. Therefore, not only can the area or volume of the package structure 3 be reduced, but the density of the electrical I/O can be increased.

In addition, if a plurality of electronic components are embedded in each of the encapsulation layers 24, 24, 24', the electronic components may be uniformly or non-uniformly disposed.

In summary, the package structure and the interposer of the present invention mainly use the wire body as a conductive path, and the distance between the wire bodies can be minimized because of the extremely small line width, so that it can not only meet the miniaturization. Demand, and can significantly reduce costs. At the same time, the wire bodies do not generate a significant stress field in the interposer, and there is no known problem of functional attenuation and reliability caused by the residual stress accompanying the perforation of the conductive crucible.

The above embodiments are intended to illustrate the principles of the present invention and its effects, and are not intended to limit the present invention. Anyone who is familiar with the art may modify the above embodiments without departing from the spirit and scope of the creation. Therefore, the scope of protection of this creation should be as listed in the scope of patent application described later.

2‧‧‧Intermediary board

23‧‧‧ wire body

23a‧‧‧ ball end

23b‧‧‧Line end

24‧‧‧Encapsulation layer

24a‧‧‧ first surface

24b‧‧‧second surface

Claims (10)

An interposer includes: an encapsulation layer; and a plurality of conductor bodies embedded in the encapsulation layer and each having an opposite ball end and a line end exposed to the encapsulation layer. The interposer of claim 1, wherein the wire system is in the shape of a nail. The interposer of claim 1, wherein the wire body has a line width of no more than 300 microns. A package structure includes: an encapsulation layer; at least one electronic component embedded in the encapsulation layer; a plurality of conductor bodies embedded in the encapsulation layer and each having an opposite ball exposed to the encapsulation layer And a circuit layer formed on the encapsulation layer and electrically connected to each of the wire bodies. The package structure of claim 4, wherein the electronic component is provided with a plurality of conductive elements located in the package layer and exposed to the package layer. The package structure of claim 5, wherein the conductive element comprises a spike line and a solder bump covering the nail line. The package structure of claim 4, wherein the wire system is in the shape of a nail. The package structure of claim 4, wherein the wire The line width of the body is no more than 300 microns. The package structure as claimed in claim 4, further comprising another electronic component disposed on the circuit layer and the encapsulation layer. The package structure of claim 4, further comprising another circuit layer disposed on the circuit layer and the encapsulation layer, another encapsulation layer and another electronic component, wherein the other electronic component is disposed on On the circuit layer and the encapsulation layer, the other encapsulation layer is disposed on the circuit layer and the encapsulation layer and covers the other electronic component, and the other circuit layer is disposed on the other encapsulation layer.