TWI790945B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package is provided, in which a panel wafer body includes a plurality of electronic structures arranged in an array, electronic components are stacked on each of the electronic structures, a plurality of conductive pillars are formed on the electronic structure, at least one groove is formed between the electronic structures, a encapsulating layer is formed on the panel wafer body, and a circuit structure is formed on the encapsulating layer, so when a dicing process is performed along the groove, the electronic structure does not need to be formed solder bump. Therefore, the overall height of the electronic package can be reduced, and the current transmission path can be effectively shortened to improve the electrical performance.

Description

Electronic package and its manufacturing method

The invention relates to a semiconductor device, in particular to an electronic package and its manufacturing method.

With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. Technologies currently used in the field of chip packaging include, for example, Chip Scale Package (CSP for short), Direct Chip Attached (DCA for short) or Multi-Chip Module (Multi-Chip Module, Flip-chip packaging modules such as MCM for short, or three-dimensional integrated circuit (3D IC) stacking technology that integrates three-dimensional stacking of chips.

FIG. 1 is a schematic cross-sectional view of a conventional three-dimensional integrated circuit stacked packaging structure 1 . As shown in FIG. 1 , in the package structure 1 , a Through Silicon interposer (TSI) 1 a is placed on a package substrate 19 via solder bumps 16 , and the solder bumps 16 are covered with a primer 191 . . The silicon interposer 1a has a silicon plate body 10 and a plurality of conductive through-silicon vias (TSV for short) 101 formed therein, and a surface of the silicon plate body 10 is formed to electrically connect the conductive through-silicon vias 101 The circuit redistribution structure (Redistribution layer, RDL for short), wherein, the circuit redistribution structure comprises a dielectric layer 11 and a circuit layer 12 formed on the dielectric layer 11, and the circuit layer 12 is electrically connected to The conductive TSV 101, and an insulating protection layer 13 is formed on the dielectric layer 11 and the circuit layer 12, and the insulating protection layer 13 The exposed portion of the circuit layer 12 is used to combine a plurality of solder bumps 14 for disposing the semiconductor chip 17 , and then the primer 171 is used to cover the solder bumps 14 . Afterwards, an encapsulation material 18 is formed on the encapsulation substrate 19 so that the encapsulation material 18 covers the semiconductor chip 17 and the silicon interposer 1a.

Furthermore, another insulating protection layer 15 can be formed on the silicon plate body 10, and the insulating protection layer 15 exposes the end faces of the conductive TSVs 101, so as to combine and electrically connect the end faces of the conductive TSVs 101. A plurality of solder bumps 16 are connected, wherein an under bump metallurgy (UBM) 160 for connecting to the solder bumps 16 can be selectively formed on the end surface of the conductive TSV 101 .

In subsequent applications, the package structure 1 can form a plurality of solder balls 192 on the underside of the package substrate 19 to be connected to a circuit board 1b.

However, in the conventional packaging structure 1, when manufacturing the silicon interposer 1a, the silicon board body 10 needs to be placed on a glass carrier first, and then the conductive TSV 101 and the RDL are fabricated, and the conductive TSV is to be fabricated After 101 and RDL, the glass carrier needs to be removed, which increases the cost of materials and troubles the process.

Therefore, how to overcome the problems of the above-mentioned conventional technologies has become a difficult problem to be overcome urgently in the industry.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: an electronic structure with a plurality of contacts, and the plurality of contacts do not protrude from the surface of the electronic structure; On the electronic structure; a plurality of conductive pillars are arranged on the electronic structure to electrically connect the multiple contacts of the electronic structure; a coating layer is formed on the electronic structure to cover the electronic component and the A plurality of conductive pillars; and a circuit structure arranged on the cladding layer to electrically connect the plurality of conductive pillars.

The present invention further provides a method for manufacturing an electronic package, which includes: providing a wafer body with a full layout, which includes a plurality of electronic structures arranged in an array, and each of the electronic structures has a plurality of contacts; an electronic component is arranged on each On the electronic structure, and each of the electronic structures is formed with a plurality of conductive pillars electrically connected to the plurality of contacts; grooves are formed between each of the electronic structures, and the grooves do not penetrate through the electronic structures; A cladding layer is placed on the entire pattern wafer, so that the cladding layer covers the electronic components and the plurality of conductive columns; a circuit structure is formed on the cladding layer, so that the circuit structure is electrically connected to the plurality of conductive columns ; and performing a single-cutting process along the groove.

In the aforementioned electronic package and its manufacturing method, the electronic component is in contact with the surface of the electronic structure.

In the aforementioned electronic package and its manufacturing method, the electronic component is fixed on the electronic structure through a bonding layer.

In the aforementioned electronic package and its manufacturing method, the electronic component is electrically connected to the circuit structure.

In the aforementioned electronic package and its manufacturing method, the electronic component has a plurality of electrode pads, so that the electronic component is correspondingly bonded to the plurality of contacts of the electronic structure with the plurality of electrode pads and electrically connected to the plurality of contacts.

In the aforementioned electronic package and its manufacturing method, the electronic structure is configured with a wiring structure for connecting and electrically connecting the plurality of conductive columns. Further, the electronic component is multiplexed and electrically connected on the wiring structure.

In the aforementioned electronic package and its manufacturing method, the edge of the electronic structure is formed with a stepped portion.

In the aforementioned electronic package and its manufacturing method, the end surfaces of the plurality of conductive pillars are flush with the surface of the cladding layer.

In the aforementioned electronic package and its manufacturing method, further comprising forming a plurality of conductive elements on the circuit structure, and electrically connecting the plurality of conductive elements to the circuit structure.

It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the traditional glass substrate without circuit is mainly replaced by the full-face wafer body, so compared with the prior art, the manufacturing method of the present invention is free of glass substrates. board to save material costs.

Furthermore, the electronic structure does not need to form solder bumps, so the overall height of the electronic package can be reduced, and the current transmission path can be effectively shortened to improve electrical performance.

In addition, the cladding layer encapsulates the electronic structure and the electronic component on five sides, so that the five sides of the electronic structure and the five sides of the electronic component are protected, so as to prevent the electronic structure and the electronic component from being separated during the manufacturing process. collapsed.

1: Package structure

1a: Silicon interposer

1b: circuit board

10: Silicon plate body

101: Conductive TSV

11,260: dielectric layer

12,241,441: line layer

13,15: insulation protection layer

14,16: Solder bumps

160: The metal layer under the bump

17: Semiconductor wafer

171,191: Primer

18: Packaging material

19: Package substrate

192: solder ball

2: Electronic package

2a: Full layout wafer body

21: Electronic components

21a: Action surface

21b: Non-active surface

210,310: electrode pads

211: Protective film

212: Conductor

23: Conductive column

23a: end face

24,44: Wiring structure

240: insulating layer

25: cladding layer

25a: first surface

25b: second surface

26: Line structure

261:Line redistribution layer

27: Conductive element

29,49: Electronic structure

290,291,391,490,491: contacts

32: bonding layer

411: Conductive bump

412: metal column

42: primer

49a: wafer body

S: Groove

R: Ladder

t: thickness

L: cutting path

FIG. 1 is a schematic cross-sectional view of a conventional packaging structure.

2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

FIG. 2E is a schematic cross-sectional view of another embodiment corresponding to FIG. 2D .

3A and 3B are schematic cross-sectional views of other configurations of FIG. 2A .

4A and 4B are schematic cross-sectional views of other aspects of the electronic structure of the electronic package of the present invention.

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the present invention. Changes or adjustments of their relative relationships are not Substantial changes in technical content shall also be regarded as the scope of implementation of the present invention.

2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in Figure 2A, a full layout wafer body 2a is provided, which includes a plurality of electronic structures 29 arranged in an array, and at least one electronic component 21 is arranged on each of the electronic structures 29, and each of the electronic structures 29 is formed There are a plurality of conductive pillars 23 . Next, a groove S is formed between each of the electronic structures 29, and the groove S is located on the cutting path L (as shown in FIG. 2C ) required for the subsequent singulation process. The pre-cutting method does not go through the entire wafer body 2 a (electronic structure 29 ).

In this embodiment, the electronic structure 29 is an active component, such as a System-On-Chip (SOC) type semiconductor chip, which has a plurality of non-bump contacts 290, 291, and the plurality of contacts 290,291 do not protrude from the surface of the electronic structure 29 . For example, a part of the contacts 290 has an electrical function to electrically connect the conductive column 23, while another part of the contacts 291 corresponds to the position of the electronic component 21, so as to have an electrical function or serve as a dummy pad as required. ).

Moreover, the electronic component 21 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has an opposite active surface 21a and a non-active surface 21b, and the electronic component 21 is placed in such a way that its non-active surface 21b directly contacts the electronic structure 29 On the electronic structure 29, the active surface 21a is in the face up mode. At this time, the contact 291 of the electronic structure 29 is used as a virtual pad to dissipate heat from the non-active surface 21b, while the active surface 21a It has a plurality of electrode pads 210 and a protective film 211 such as a passivation material, wherein, the plurality of electrode pads 210 are combined and electrically connected to a plurality of conductors 212, such as conductive lines, spherical balls of solder balls, or copper pillars Columns of metal materials such as solder bumps, or stud-shaped conductive elements made by a wire bonding machine, but not limited thereto, so that the conductive body 212 is located in the protective film 211 . It should be understood that, in another embodiment, as shown in FIG. 3A , the non-active surface 21 b of the electronic component 21 can also be adhered to the electronic structure 29 via a bonding layer 32 .

Or, as shown in FIG. 3B, the contact 391 of the electronic structure 29 has an electrical function, and the active surface 21a of the electronic component 21 adopts a face-down (face down) type, so that the electronic component 21 is face-to-face (face-down). The multiple electrode pads 310 of the electronic component 21 are correspondingly bonded to the contact point 391 of the electronic structure 29 and electrically connected to the contact point 391 in a to-face hybrid bond method.

It should be understood that there are various configurations of the electronic component 21 relative to the electronic structure 29 , and are not limited to the above.

In other embodiments, as shown in FIG. 4A, the electronic structure 49 includes a chip body 49a and a wiring structure 24 disposed on the chip body 49a. The wiring structure 24 includes at least one insulating layer 240, and is arranged on The circuit layer 241 in the form of RDL on the insulating layer 240, and the circuit layer 241 of the outermost layer is configured with a plurality of contacts 490, 491 for setting the electronic component 21 and the conductive column 23, wherein the electronic component 21 is connected by the circuit layer on it. A plurality of metal pillars 412 such as copper pillars are covered by conductive bumps 411 such as solder materials. The electronic structure 49 is disposed on the electronic structure 49 and electrically connected to the contact 491 , and the metal post 412 and the conductive bump 411 are covered with a primer 42 .

Or, as shown in FIG. 4B, the wiring structure 44 is arranged on a partial surface of the chip body 49a of the electronic structure 49, and the circuit layer 441 of the outermost layer of the wiring structure 44 is configured with a plurality of contacts for setting the plurality of conductive columns 23 490. At this time, the electronic component 21 can be provided on the chip body 49a in a direct contact mode (or adhering mode) with its non-active surface 21b as required, or as shown in FIG. 4B, a plurality of electronic components 21 The electrode pads 310 are correspondingly bonded to the contact points 391 of the chip body 49 a of the electronic structure 49 and are electrically connected to the contact points 391 .

Moreover, the material for forming the wiring layers 241, 441 is copper, and the material for forming the insulating layer 240 is such as polyparabenazole (PBO), polyimide (PI), prepreg (PP) or others. The dielectric material.

In addition, the material forming the plurality of conductive pillars 23 is metal material such as copper or solder material, and the plurality of conductive pillars 23 are arranged on the contacts 290, 490 with electrical functions to electrically connect the contacts 290, 490.

As shown in FIG. 2B, following the process of FIG. 2A or FIG. 3A, a cladding layer 25 is formed on the electronic structure 29 and in the groove S, so that the cladding layer 25 covers the electronic components 21 and the The conductive pillar 23, wherein the cladding layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the cladding layer 25 is bonded to the electronic structure 29 with its second surface 25b. Then, through a leveling process, the first surface 25a of the cladding layer 25 is flush with the upper surface of the protective film 211, the end surface of the conductor 212 and the end surface 23a of the conductive pillar 23, so that the protective film 211 , the conductor 212 and the conductive column 23 are exposed on the first surface 25 a of the cladding layer 25 .

In this embodiment, the cladding layer 25 is an insulating material, such as epoxy resin encapsulant, which can be formed on the electronic structure 29 by lamination or molding.

Furthermore, the leveling process removes part of the material of the conductive pillar 23 , part of the material of the protective film 211 (even part of the material of the conductor 212 ) and part of the material of the cladding layer 25 by grinding.

As shown in FIG. 2C , a circuit structure 26 is formed on the first surface 25 a of the cladding layer 25 , and the circuit structure 26 is electrically connected to the conductive pillars 23 .

In this embodiment, the circuit structure 26 includes a plurality of dielectric layers 260 and a plurality of redistribution layers (RDL) 261 disposed on the plurality of dielectric layers 260, and the outermost dielectric layer 260 can be used as an anti- Solder layer, so that part of the outermost circuit redistribution layer 261 exposes the solder resist layer. Alternatively, the wiring structure 26 may also only include a single dielectric layer 260 and a single wiring redistribution layer 261 .

Furthermore, the material for forming the redistribution layer 261 is copper, and the material for forming the dielectric layer 260 is such as polyparabenazole (PBO), polyimide (PI), prepreg (PP) ) or other dielectric materials.

Moreover, the circuit redistribution layer 261 of the circuit structure 26 is directly electrically connected to the conductor 212 of the electronic component 21 . It should be understood that if the configuration shown in FIG. 3B , FIG. 4A or FIG. 4B is continued in the manufacturing process of FIG. 2B , the circuit redistribution layer 261 of the circuit structure 26 will not be directly electrically connected to the electronic device 21 .

In addition, a plurality of conductive elements 27 such as solder balls can be formed on the outermost circuit redistribution layer 261 , so that the plurality of conductive elements 27 are electrically connected to the plurality of conductive columns 23 and/or the conductor 212 .

As shown in FIG. 2D , a cutting tool (not shown) is aligned with each of the grooves S, and a singulation process is performed along the cutting path L shown in FIG. 2C to obtain the electronic package 2 .

In this embodiment, the edge of the electronic structure 29 forms a stepped portion R corresponding to the groove S thereof.

Therefore, the manufacturing method of the present invention uses the design of the full-face wafer body 2a, that is, the wafer-level electronic structure 29, 49 as a carrier to replace the traditional glass carrier without circuits. Therefore, compared with the conventional technology, the manufacturing method of the present invention avoids the use of a glass carrier plate and can save material costs.

Furthermore, the electronic structures 29 and 49 do not need to be provided with conventional solder bumps, so the overall height of the electronic package 2 can be reduced, and the current transmission path can be effectively shortened to improve electrical performance.

Again, this cladding layer 25 is to enclose the electronic structure 29,49 and the electronic component 21 on five sides, so that the five faces of the electronic structure 29,49 and the five faces of the electronic component 21 are protected to avoid The electronic structures 29, 49 and the electronic component 21 collapse during the manufacturing process. Further, in the subsequent process, the exposed surface of the electronic structure 29, 49 (such as the bottom surface of Figure 2D) can be ground, so that the thickness t of the electronic structure 29 (or the wafer body 49a) can be less than 50 microns (um), as shown in the figure 2E, and in the grinding process, since each side of the electronic structure 29 is protected by the cladding layer 25, even if the electronic structure 29, 49 is ground to an extremely thin situation, no cracking will occur, so It is beneficial to the overall thinning requirement of the electronic package 2 .

The present invention further provides an electronic package 2 , which includes: an electronic structure 29 , 49 , an electronic component 21 , a plurality of conductive pillars 23 , a cladding layer 25 and a circuit structure 26 .

The electronic structure 29, 49 has multiple contacts 290, 291, 391, 490, 491, and the multiple contacts 290, 291, 391, 490, 491 do not protrude from the surface of the electronic structure 29, 49.

The electronic components 21 are stacked on the electronic structures 29 , 49 .

The plurality of conductive pillars 23 are arranged on the electronic structure 29, 49 to electrically connect the plurality of contacts 290, 490 of the electronic structure 29, 49.

The cladding layer 25 is formed on the electronic structures 29 , 49 to cover the electronic components 21 and the plurality of conductive pillars 23 .

The circuit structure 26 is disposed on the cladding layer 25 to electrically connect the plurality of conductive pillars 23 .

In one embodiment, the electronic component 21 is in contact with the surface of the electronic structure 29 .

In one embodiment, the electronic component 21 is fixed on the electronic structure 29 through the bonding layer 32 .

In one embodiment, the electronic component 21 is electrically connected to the circuit structure 26 .

In one embodiment, the electronic component 21 has a plurality of electrode pads 310, so that the electronic component 21 is bonded to the contacts 391 of the electronic structure 29 in a hybrid bonding manner and electrically connected The contact 391 .

In one embodiment, the electronic structure 49 is configured with a wiring structure 24 , 44 to connect and electrically connect the conductive pillar 23 . For example, the electronic component 21 is multiplexed and electrically connected to the wiring structure 24 .

In one embodiment, a stepped portion R is formed on the edge of the electronic structure 29 .

In one embodiment, the end surface 23 a of the conductive pillar 23 is flush with the first surface 25 a of the cladding layer 25 .

In one embodiment, the electronic package 2 further includes a plurality of conductive elements 27 formed on the circuit structure 26 , and the plurality of conductive elements 27 are electrically connected to the circuit structure 26 .

To sum up, the electronic package and its manufacturing method of the present invention replace the traditional glass substrate without circuits by the full-area wafer body, so the manufacturing method of the present invention can effectively save material costs.

Furthermore, the electronic structure does not need to form solder bumps, so the overall height of the electronic package can be reduced, and the current transmission path can be effectively shortened to improve electrical performance.

In addition, the cladding layer encapsulates the electronic structure and the electronic component on five sides, so that the five sides of the electronic structure and the five sides of the electronic component are protected, so as to prevent the electronic structure from being separated from the electronic component. Crashed during the process.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

2: Electronic package

21: Electronic components

23: Conductive column

25: cladding layer

26: Line structure

27: Conductive element

29: Electronic Structure

290,291: contacts

R: Ladder

Claims (14)

An electronic package, comprising: an electronic structure with a plurality of contacts, and the plurality of contacts do not protrude from the surface of the electronic structure; electronic components are arranged on the electronic structure directly contacting the surface of the electronic structure; A plurality of conductive pillars are arranged on the electronic structure to electrically connect multiple contacts of the electronic structure; a coating layer is formed on the electronic structure to cover the electronic component and the plurality of conductive pillars; and a circuit structure , is arranged on the cladding layer to electrically connect the plurality of conductive pillars. The electronic package as claimed in claim 1, wherein the electronic component is electrically connected to the circuit structure. The electronic package according to claim 1, wherein the electronic component has a plurality of electrode pads, and the electronic component is correspondingly bonded and electrically connected to the plurality of contacts of the electronic structure through the plurality of electrode pads. The electronic package according to claim 1, wherein the electronic structure is provided with a wiring structure for connecting and electrically connecting the plurality of conductive columns. The electronic package as claimed in claim 1, wherein a stepped portion is formed on the edge of the electronic structure. The electronic package according to claim 1, wherein the end surfaces of the plurality of conductive pillars are flush with the surface of the cladding layer. The electronic package as claimed in claim 1 further includes a plurality of conductive elements formed on the circuit structure, and the plurality of conductive elements are electrically connected to the circuit structure. A method for manufacturing an electronic package, comprising: Provide a full layout wafer body, which includes a plurality of electronic structures arranged in an array, and each of the electronic structures has a plurality of contacts; an electronic component is provided on each of the electronic structures by directly contacting the surface of each of the electronic structures, And forming a plurality of conductive columns electrically connected to the plurality of contacts on each of the electronic structures; forming grooves between each of the electronic structures, wherein each of the grooves does not penetrate each of the electronic structures; forming a cladding layer on the On the entire wafer body, so that the cladding layer covers the electronic components and the plurality of conductive pillars; forming a circuit structure on the cladding layer, so that the circuit structure is electrically connected to the plurality of conductive pillars; and along the The groove is cut to order. The method for manufacturing an electronic package according to claim 8, wherein the electronic component is electrically connected to the circuit structure. The method for manufacturing an electronic package as described in claim 8, wherein the electronic component has a plurality of electrode pads, and the electronic component is correspondingly bonded and electrically connected to the plurality of contacts of the electronic structure through the plurality of electrode pads. The method for manufacturing an electronic package according to claim 8, wherein the electronic structure is provided with a wiring structure for connecting and electrically connecting the plurality of conductive columns. The method for manufacturing an electronic package according to claim 8, wherein a stepped portion is formed on the edge of the electronic structure. The method for manufacturing an electronic package according to claim 8, wherein the end surfaces of the plurality of conductive pillars are flush with the surface of the cladding layer. The method for manufacturing an electronic package according to claim 8 further includes forming a plurality of conductive elements on the circuit structure, and electrically connecting the plurality of conductive elements to the circuit structure.

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