TWI746310B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic packaging comprises a encapsulating layer, at least one electron interposer block embedded in the encapsulating layer and having a plurality of conductive through holes, a plurality of conductive pillars embedded in the encapsulating layer, and at least one electronic component provided on the encapsulating layer, such that the conductive pillar and the electronic component are manufactured separately to improve the reliability of the electronic package.

Description

Electronic package and its manufacturing method

The present invention relates to a semiconductor device, in particular to an electronic package and its manufacturing method.

With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multi-function and high performance. For example, an integrated voltage regulator (IVR) is embedded in a high-performance processor to improve efficiency, such as switching frequency, reduce power consumption, and improve reliability and even reduce production costs. In addition, the technologies currently applied in the field of chip packaging include, for example, Chip Scale Package (CSP), Direct Chip Attached (DCA), or Multi-Chip Module Packaging (Multi-Chip). Module, MCM for short) and other flip-chip packaged modules.

In addition, as the electrical functions of the terminal products are becoming more advanced in the current package structure, more and more semiconductor chips are placed on the Through Silicon Interposer (TSI), so that the bonding area of the silicon interposer is also increasing. It will become larger and larger, so the number of through-silicon vias (TSV) of the silicon interposer will also increase, resulting in a variety of process defects in the manufacturing process, resulting in the yield rate of the package structure decline.

The industry then cuts a single silicon interposer into multiple smaller silicon interposers to reduce the difficulty of the manufacturing process.

FIGS. 1A to 1D are schematic cross-sectional views of the manufacturing method of the conventional semiconductor package structure 1.

As shown in FIG. 1A, a semiconductor device 10, such as a logic die, is first disposed on the release layer 90 of a carrier board 9, and then a circuit portion 18 is formed on the semiconductor device 10, and the circuit portion 18 is It includes a plurality of insulating layers 180 and a plurality of redistribution layers (RDL) 181, and a plurality of copper bumps 19 are formed on the redistribution layer 181. Next, a conductive seed layer 130 is formed on the circuit portion 18 to form a plurality of copper pillars 13 on the circuit redistribution layer 181 through the conductive seed layer 130.

As shown in FIG. 1B, the conductive seed layer 130 that is not covered by the copper pillar 13 is removed, and then a plurality of silicon interposers 11 with conductive through holes 110 are fixed on the circuit portion through the conductor 12 and the primer 14 18 and make the conductive through hole 110 electrically connect to the copper bump 19 through the conductor 12. Then, the silicon interposer 11, the primer 14 and the copper pillars 13 are covered with a coating layer 15.

As shown in FIG. 1C, a leveling process is performed to remove part of the material of the copper pillar 13, part of the material of the silicon interposer 11, and part of the material of the cladding layer 15 by grinding, so that the copper pillar 13 The end surface of the conductive through hole 110 and the end surface of the conductive through hole 110 are exposed on the surface 15 a of the coating layer 15.

As shown in FIG. 1D, a circuit structure 16 is formed on the surface 15 a of the cladding layer 15, and the circuit structure 16 is electrically connected to the copper pillars 13 and the conductive through holes 110 of the silicon interposer 11. After that, the carrier board 9 and the release layer 90 thereon are removed to expose the semiconductor device 10, and then the dicing process is performed.

In the aforementioned manufacturing process, the traditional TSV is mainly replaced by a larger-sized copper pillar 13 to reduce the manufacturing process difficulty of the conductive through hole 110, that is, only a small amount of silicon interposer 11 is required, instead of a large-area traditional TSI. Therefore, it is beneficial to reduce the production cost of the end product.

In the subsequent manufacturing process, the semiconductor package structure 1 can form a plurality of solder balls 17 on the circuit structure 16 to be connected to a package substrate (the figure is omitted) or a circuit board (the figure is omitted).

However, in the conventional manufacturing method of the semiconductor package structure 1, it is necessary to electroplate the larger-sized copper pillar 13 on the circuit portion 18 by the conductive seed layer 130. Therefore, during the electroplating process, as shown in FIG. 1A, The copper material at the bottom of the copper pillar 13 will be infiltrated to the copper bumps 19 adjacent to the copper pillar 13 through the conductive seed layer 130, so that when the conductive seed layer 130 other than the copper pillar 13 is removed, part of the copper material The copper pillar 13 and the copper bump 19 will be connected, thus causing a short circuit.

Furthermore, during the leveling process, as shown in FIG. 1C, since part of the material of the copper pillar 13 and part of the material of the silicon interposer 11 are polished at the same time, during the polishing process, the copper pillar 13 with a larger end surface area The copper ions (or copper particles) will migrate with the grinding tool to the end surface of the conductive through hole 110, so that after the circuit structure 16 is formed, part of the copper ions (or copper particles) will conduct the copper pillar 13 and the conductive hole. Perforation 110 causes problems such as short circuit or leakage.

Therefore, how to overcome the various problems of the above-mentioned conventional technology has actually become a problem that the industry urgently needs to overcome.

In view of the various deficiencies of the aforementioned conventional technologies, the present invention provides an electronic package including: a coating layer; at least one electronic intermediary block embedded in the coating layer and having a plurality of conductive through holes; a plurality of conductive pillars , Is embedded in the cladding layer and has a conductive block at the end, wherein the width of the conductive block is smaller than the width of the conductive column; and at least one electronic component is disposed on the cladding layer and the The conductive block is electrically connected to the conductive pillar and the conductive through hole.

The present invention also provides a method for manufacturing an electronic package, which includes: providing at least one electronic component and a carrier board with a plurality of conductive pillars, wherein the conductive pillar has a conductive block at its end, and the width of the conductive block is Less than the width of the conductive pillar; at least one electronic intermediary block is combined with the electrical On the sub-element to form an electronic structure, wherein the intermediate board has a plurality of conductive through holes electrically connected to the electronic element; Support the electronic component, and make the electronic component electrically connect the conductive block and the conductive through hole, wherein the electronic intermediary block is located between the electronic component and the carrier board; a coating layer is formed between the carrier board and the carrier board Between the electronic components, the coating layer covers the electronic intermediary block and the plurality of conductive pillars; and the carrier board is removed.

In the aforementioned electronic package and its manufacturing method, the surface of the coating layer is flush with the surface of the electronic intermediary block.

In the aforementioned electronic package and its manufacturing method, the surface of the coating layer is flush with the end surface of the conductive pillar.

In the aforementioned electronic package and its manufacturing method, the conductive through hole is exposed on the surface of the coating layer.

In the aforementioned electronic package and its manufacturing method, the end surface of the conductive pillar is exposed on the surface of the coating layer.

In the aforementioned electronic package and its manufacturing method, the electronic component is electrically connected to the conductive block and the conductive through hole through a circuit portion.

In the aforementioned electronic package and its manufacturing method, the electronic component has a plurality of conductive bumps, so that the plurality of conductive bumps are electrically connected to the conductive through hole and/or the conductive block.

In the aforementioned electronic package and its manufacturing method, the electronic component is electrically connected to the conductive through hole by a conductor, and the conductor is not connected to the conductive block.

The aforementioned electronic package and its manufacturing method further include forming a circuit structure on the coating layer, and the circuit structure is electrically connected to the conductive pillar and the conductive through hole.

The aforementioned electronic package and its manufacturing method further include a plurality of conductive elements formed on the coating layer, and the plurality of conductive elements are electrically connected to the conductive pillar and the conductive through hole.

It can be seen from the above that in the electronic package and the manufacturing method of the present invention, the conductive pillar is mainly fabricated on the carrier board, and the conductive pillar is not electroplated on the electronic component, so that the conductive pillar is manufactured in the process of manufacturing the conductive pillar. , The metal material used to make the conductive post will not be infiltrated on the electronic component, so after the conductive post is manufactured, the metal material of the conductive post will not connect the conductive post and the electronic component, so it is compared with the conventional Technology. After the electronic structure of the present invention is stacked on the carrier board, the conductive pillars will not electrically conduct the conductive through holes of the electronic intermediate block, and thus will not cause a short circuit.

Furthermore, in the manufacturing method of the present invention, the electronic structure and the conductive pillar are combined in a stacking manner, so that the coating layer is filled between the carrier board and the electronic component, and then the electronic intermediary block and the electronic components are covered. Conductive pillars, so after removing the carrier board, the surface of the coating layer is flush with the end faces of the conductive pillars and the end faces of the electronic interposer and the conductive through holes. Therefore, compared with the conventional technology, the manufacturing method of the present invention is After the coating layer is formed, there is no need to perform a leveling process for the coating layer. Therefore, the copper ions (or copper particles) of the conductive pillars with a larger end surface area will not migrate to the end surface of the conductive through hole, thereby avoiding the formation of the After the circuit structure, the copper ions (or copper particles) of the conductive pillar conduct the conductive pillar and the conductive through hole, so as to effectively avoid problems such as short circuit or leakage.

1: Semiconductor package structure

10: Semiconductor components

11: Silicon Intermediary Block

110,210: Conductive perforation

12, 22: Conductor

13: Copper pillar

130: conductive seed layer

14: primer

15,25: cladding

15a: surface

16,26: Line structure

17: Solder ball

18, 28: Line Department

180: insulating layer

181,261: Line re-layout

19: Copper bump

2,2’: Electronic package

2a: Full-page wafer body

2b: Electronic structure

20: Electronic components

20a: Action surface

20b: Inactive surface

200: Electrode pad

21: Electronic Intermediary Block

21a: first side

21b: second side

210a: Cushion

23: Conductive column

23b: end face

230: conductive block

24: Bonding layer

25a: first surface

25b: second surface

260: Dielectric layer

27: Conductive element

28a: circuit layer

28b: Passivation layer

28c: insulating film

280,280’: Opening

29, 29’: conductive bump

8: Wiring board

9,9’: Carrier plate

90,90’: Release layer

91’: Adhesive layer

d1, d2: width

L, S: cutting path

1A to 1D are schematic cross-sectional views of a conventional method of manufacturing a semiconductor package structure.

2A to 2G are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

Fig. 2A' is a schematic cross-sectional view of another embodiment corresponding to Fig. 2A.

Fig. 2H is a schematic cross-sectional view of the subsequent manufacturing process of Fig. 2G.

FIG. 2H' is a schematic cross-sectional view of another embodiment of FIG. 2H.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment should still fall within the original The technical content disclosed by the invention can be covered. At the same time, the terms such as "above", "first", "second", "one", etc. cited in this specification are only for ease of description, and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall be regarded as the scope of the implementation of the present invention without substantial changes to the technical content.

2A to 2G are schematic cross-sectional views of the first embodiment of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, a full-page wafer body 2 a is provided, which includes a plurality of electronic components 20 arranged in an array, and a single electronic component 20 has a plurality of conductive bumps 29.

In this embodiment, the electronic component 20 is an active component, a passive component, or a combination of the two, etc., wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 20 is a semiconductor chip, such as a logic chip, which has an active surface 20a and a non-active surface 20b opposite to each other, and the active surface 20a has a plurality of electrode pads 200 on the active surface 20a.

Furthermore, the electronic component 20 can form a circuit portion 28 on the active surface 20a. The circuit portion 28 includes a plurality of passivation layers 28b and a plurality of circuits arranged on the passivation layer 28b and electrically connected to the electrode pads 200 Layer 28a, the outermost passivation layer 28b has a plurality of openings 280, 280' that expose portions of the circuit layer 28a, so that the conductive bumps 29 are provided on the circuit layer 28a in a part of the openings 280, so that the conductive The electrical bump 29 is electrically connected to the electrode pad 200. Or, as shown in FIG. 2A', the configuration of the circuit portion 28 can be omitted, so that the conductive bumps 29, 29' are directly provided on all the electrode pads 200, and the conductive bumps 29 are covered with an insulating film 28c , 29' to protect the conductive bumps 29, 29'.

In addition, the conductive bumps 29, 29' are in the shape of a conductive circuit, a spherical shape of a solder ball, or a columnar shape of a metal material such as a copper column, a solder bump, or a stud-shaped conductive material made by a wire bonding machine. The component, but not limited to the above, can be made of welding metal, such as titanium/copper, copper, gold, nano twin Cu, or other materials.

As shown in FIG. 2B, following the process of FIG. 2A, at least one electronic intermediary block 21 is disposed on the conductive bump 29 of the electronic component 20, and the electronic intermediary block 21 has a first side 21a and a second side 21b opposite to each other. .

In this embodiment, the electronic interposer 21 is a through silicon interposer (TSI) structure, which has a plurality of conductive vias 210 exposed on the first side 21a and the second side 21b, such as conductive silicon vias. (Through-silicon via, TSV for short). For example, the conductive through hole 210 has a pad portion 210a at the end of the first side 21a to electrically connect the electronic component 20 by bonding a plurality of conductive bodies 22 to the conductive bumps 29, wherein the pad portion 210a It is a welding metal, such as copper, gold, nickel or other materials. Furthermore, the conductive bodies 22 can be covered with a bonding layer 24 such as a primer as required.

Furthermore, the other end surface of the conductive through hole 210 is exposed on the second side 21b. For example, the surface of the second side 21b of the electronic intermediary block 21 is flush with the other end surface of the conductive through hole 210 by a leveling process, such as a grinding method.

In addition, the conductor 22 is a welding metal, such as titanium/copper, copper, gold, nickel, tin-silver (SnAg) or other solder materials, to weld the pad portion 210a and the conductive bump 29. For example, the conductor 22 may be formed on the pad 210a of the electronic intermediary block 21 on the first side 21a; alternatively, the conductor 22 may be formed on the conductive bump 29 first, as shown in FIG. 2A' Then, the electronic intermediary block 21 is combined with the conductor 22 with the pad portion 210a of the conductive through hole 210. Further, if the conductive body 22 is formed on the conductive bump 29 first, the conductive The electrical body 22 is formed only on part of the conductive bumps 29 and not on all the conductive bumps 29, 29', as shown in FIG. 2A'.

In addition, the conductor 22 is not formed at another part of the opening 280' of the electronic component 20, as shown in FIG. 2B.

As shown in FIG. 2C, the singulation process is performed along the cutting path L shown in FIG. 2B to obtain a complex electronic structure 2b.

As shown in FIGS. 2D to 2E, the electronic structure 2b is disposed on a carrier board 9'with a plurality of conductive pillars 23, wherein the plurality of conductive pillars 23 are used to support the electronic component 20, so that the electronic structure 2b The conductive pillars 23 are stacked on the supporting board 9', and the electronic component 20 is electrically connected to the conductive pillars 23, and the electronic intermediary block 21 is located between the electronic component 20 and the supporting board 9' . Next, a coating layer 25 is formed between the carrier board 9'and the active surface 20a of the electronic component 20, so that the coating layer 25 covers the electronic intermediary block 21, the bonding layer 24 and the conductive pillars 23 Wherein, the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the first surface 25a is bonded to the active surface 20a of the electronic component 20 (or the circuit portion 28).

In this embodiment, the conductive pillar 23 is a metal pillar or a metal pillar made of titanium/copper, copper or other metal materials by performing a patterning process on the carrier board 9'by methods such as electroplating, etching, deposition, etc. Solder pillars, and the carrier board 9'is, for example, a board made of semiconductor material (such as silicon or glass), on which a release layer 90' and an adhesive layer 91' are sequentially formed in a coating manner for disposing the The conductive pillars 23 and the electronic intermediate block 21.

Furthermore, the conductive pillar 23 is connected to the active surface 20 a of the electronic component 20. For example, the conductive pillar 23 is inserted into another part of the opening 280' of the electronic component 20 to electrically connect the circuit layer 28a of the circuit portion 28, and the conductive pillar 23 may be formed with a corresponding opening 280' at the top end. The conductive block 230 makes the conductive pillar 23 fill the space of the conductive bump 29 in the opening 280' by the conductive block 230, wherein the conductive block 230 is a welding metal, such as copper, Nano twin copper or other materials. Should be Understandably, if the process shown in FIG. 2A' is continued, the conductive block 230 of the conductive pillar 23 can make up the space for the conductive body 22.

In addition, the width d2 of the conductive block 230 is smaller than the width d1 of the conductive pillar 23, and the conductive block 230 and the conductive pillar 23 can be manufactured separately or integrally formed. For example, the material of the conductive block 230 and the conductive pillar 23 may be the same (such as copper) or different.

In addition, the coating layer 25 is an insulating material, such as an epoxy resin encapsulant, which can be formed between the carrier board 9'and the active surface 20a of the electronic component 20 by filling or molding.

As shown in FIG. 2F, the carrier board 9'and the release layer 90' and the adhesive layer 91' are removed, and the second surface 25b of the coating layer 25 is exposed, so that the second surface of the electronic intermediary block 21 The side 21 b, the conductive through hole 210 and the conductive pillar 23 are exposed on the second surface 25 b of the covering layer 25.

In this embodiment, the second surface 25b of the coating layer 25 is flush with the end surface 23b of the conductive pillar 23 and the second side 21b of the electronic interposer 21 and the end surface of the conductive through hole 210.

As shown in FIG. 2G, a circuit structure 26 is formed on the second surface 25b of the cladding layer 25, and the circuit structure 26 is electrically connected to the conductive pillars 23 and the conductive through holes 210 of the electronic interposer 21. After that, a singulation process is performed along the cutting path S as shown in FIG. 2F to obtain the electronic package 2.

In this embodiment, the circuit structure 26 includes a plurality of dielectric layers 260 and a plurality of circuit redistribution layers (RDL) 261 provided on the plurality of dielectric layers 260, and the outermost dielectric layer 260 can be used as a solder mask Layer, so that the solder mask is exposed outside the circuit redistribution layer 261 of the outermost layer. Alternatively, the circuit structure 26 can also only include a single dielectric layer 260 and a single circuit redistribution layer 261.

Furthermore, the material for forming the circuit redistribution layer 261 is copper, and the material for forming the dielectric layer 260 is such as polyparabenzazole (PBO), polyimide (PI), prepreg (PP ) Or other dielectric materials.

As shown in FIG. 2H, a plurality of conductive elements 27 such as solder balls are formed on the outermost circuit redistribution layer 261, so that the plurality of conductive elements 27 are electrically connected to the conductive pillar 23 and/or the conductive through hole 210.

In this embodiment, the circuit structure 26 is a fan-in configuration, so that the layout range of the conductive elements 27 does not exceed the area of the active surface 20a of the electronic element 20.

Furthermore, in the subsequent manufacturing process, the conductive elements 27 can be connected to the upper side of a wiring board 8, such as an organic material board (such as a package substrate with a core layer and a circuit part or a circuit part). Coreless packaging substrate) or inorganic material board (such as silicon plate), and the lower side of the wiring board 8 can be connected to an electronic device (not shown) like a circuit board.

Furthermore, if the process shown in FIG. 2A' is continued, the electronic package 2'shown in FIG. 2H' will be obtained.

Therefore, in the manufacturing method of the present invention, the conductive pillars 23 are mainly fabricated on the carrier board 9'without electroplating the conductive pillars 23 of the large-size copper pillars on the electronic component 20, that is, the conductive pillars 23 It is fabricated separately from the electronic structure 2b, so that in the process of fabricating the conductive pillar 23, as shown in FIG. 2D, the metal material of the conductive pillar 23 will not be infiltrated to the conductive bump 29 on the electronic component 20, so After the conductive pillar 23 is manufactured, the metal material of the conductive pillar 23 does not connect the conductive pillar 23 and the electronic component 20 to the conductive bump 29 of the conductive through hole 210. Therefore, compared with the conventional technology, the present invention After the electronic structure 2b of the invention is stacked on the carrier board 9', as shown in FIG. 2E, the single conductive pillar 23 will be connected to its corresponding electrode pad 200, instead of directly electrically connecting the electronic intermediary block 21 The conductive through hole 210 (or the conductor 22) does not cause a short circuit.

Furthermore, in the manufacturing method of the present invention, the electronic structure 2b and the conductive pillar 23 are combined in a stacking manner, as shown in FIG. 2D, so that the coating layer 25 is filled between the carrier board 9'and the electronic component 20 As shown in FIG. 2E, the electronic intermediary block 21 and the conductive pillars 23 can be covered. Therefore, after the carrier board 9'is removed, the second surface 25b of the covering layer 25 is flush with the conductive pillars The end surface 23b of the electronic intermediate block 21 and the end surface of the second side 21b of the electronic intermediate block 21 and the conductive through hole 210 are compared with the conventional technology. Therefore, the method of the present invention forms the coating After the layer 25, there is no need to perform a leveling process for the cladding layer 25, as shown in FIG. 2F, so the copper ions (or copper particles) of the conductive pillar 23 with a larger end surface 23b area will not migrate to the conductive through hole The end surface of 210 can further avoid the problem that the copper ions (or copper particles) of the conductive pillar 23 conduct the conductive pillar 23 and the conductive through hole 210 after the circuit structure 26 is formed, so as to effectively avoid problems such as short circuit or leakage.

The present invention further provides an electronic package 2, 2', which includes: a coating layer 25, an electronic component 20, a plurality of conductive pillars 23, and at least one electronic intermediary block 21.

The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other.

The electronic intermediary block 21 is embedded in the cladding layer 25 and has a plurality of conductive through holes 210.

The conductive pillar 23 is formed in the cladding layer 25 and has a conductive block 230 at the end, wherein the width d2 of the conductive block 230 is smaller than the width d1 of the conductive pillar 23.

The electronic component 20 is disposed on the first surface 25 a of the coating layer 25 and the conductive block 230 and electrically connects the conductive pillar 23 and the conductive through hole 210.

In one embodiment, the second surface 25b of the coating layer 25 is flush with the surface of the second side 21b of the electronic interposer 21.

In one embodiment, the second surface 25b of the coating layer 25 is flush with the end surface 23b of the conductive pillar 23.

In one embodiment, the conductive through hole 210 is exposed on the second surface 25 b of the covering layer 25.

In one embodiment, the end surface 23 b of the conductive pillar 23 is exposed on the second surface 25 b of the coating layer 25.

In one embodiment, the electronic component 20 is electrically connected to the conductive block 230 and the conductive through hole 210 through a circuit portion 28.

In one embodiment, the electronic component 20 has a plurality of conductive bumps 29, 29', so that the plurality of conductive bumps 29, 29' are electrically connected to the conductive through hole 210 and/or the conductive block 230.

In one embodiment, the electronic component 20 is electrically connected to the conductive through hole 210 through a conductive body 22, and the conductive body 22 does not contact the conductive block 230.

In one embodiment, the electronic package 2, 2'includes a circuit structure 26, which is formed on the second surface 25b of the cladding layer 25 and electrically connects the conductive pillar 23 and the conductive through hole 210 .

In one embodiment, the electronic package 2, 2'includes a plurality of conductive elements 27 formed on the second surface 25b of the coating layer 25, and the plurality of conductive elements 27 are directly electrically connected ( Or indirectly and electrically connected by the circuit structure 26) the conductive pillar 23 and the conductive through hole 210.

In summary, the electronic package of the present invention and its manufacturing method are manufactured by fabricating the conductive post on the carrier board without electroplating the conductive post on the electronic component, so that the conductive post is manufactured in the process , The metal material used to make the conductive post will not be infiltrated onto the electronic component, so after the conductive post is manufactured, the metal material of the conductive post will not connect the conductive post and the electronic component, so the electronic structure of the present invention After being stacked on the carrier board, the conductive pillars will not directly electrically conduct the conductive through holes of the electronic intermediary block, and thus will not cause a short circuit.

Furthermore, in the manufacturing method of the present invention, the electronic structure and the conductive pillar are combined in a stacking manner, so that the coating layer is filled between the carrier board and the electronic component, and then the electronic intermediary block and the electronic components are covered. Conductive pillars, so after removing the carrier board, the surface of the coating layer is flush with the end surfaces of the conductive pillars and the end surfaces of the electronic interposer and conductive through holes. Therefore, the manufacturing method of the present invention is after the coating layer is formed. There is no need to perform a leveling process for the cladding layer, so the copper ions (or copper particles) of the conductive column with a larger end surface area will not migrate to the end surface of the conductive through hole, which can avoid the conductive column after the circuit structure is formed. The copper ions (or copper particles) are connected to the conductive pillar and the conductive through hole, so as to effectively avoid problems such as short circuit or leakage.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2: Electronic package

20: Electronic components

21: Electronic Intermediary Block

210: Conductive perforation

210a: Cushion

22: Conductor

23: Conductive column

230: conductive block

25: Cladding

25a: first surface

25b: second surface

26: Line structure

260: Dielectric layer

261: Line re-layout

28: Line Department

29: conductive bump

Claims (18)

An electronic package includes: a cladding layer; at least one electronic intermediary block embedded in the cladding layer and having a plurality of conductive through holes; a plurality of conductive pillars embedded in the cladding layer and at the end There is a conductive block, wherein the width of the conductive block is smaller than the width of the conductive pillar; the circuit part is provided on the coating layer and the conductive block and electrically connects the conductive pillar and the conductive through hole; At least one electronic component is arranged on the circuit part and electrically connects the conductive block and the conductive through hole; a plurality of conductive bumps are arranged in the circuit part and flush with the surface of the circuit part; and a plurality of conductive The body is used to respectively combine with the plurality of conductive bumps and electrically connect to the plurality of conductive through holes. The electronic package according to claim 1, wherein the surface of the coating layer is flush with the surface of the electronic interposer. The electronic package according to claim 1, wherein the surface of the coating layer is flush with the end surface of the conductive pillar. The electronic package according to claim 1, wherein the conductive through hole is exposed on the surface of the coating layer. The electronic package according to claim 1, wherein the end surface of the conductive pillar is exposed on the surface of the coating layer. The electronic package according to claim 1, wherein the conductor does not contact the conductive block. The electronic package according to claim 1, further comprising a circuit structure formed on the coating layer and electrically connecting the conductive pillar and the conductive through hole. The electronic package according to claim 1, further comprising a plurality of conductive elements formed on the coating layer, and the plurality of conductive elements are electrically connected to the conductive pillar and the conductive through hole. A manufacturing method of an electronic package includes: providing at least one electronic component and a carrier board with a plurality of conductive pillars, wherein the conductive pillar has a conductive block at the end, and the width of the conductive block is smaller than the conductive pillar The width; at least one electronic intermediary block is combined with the electronic component to form an electronic structure, wherein the interposer has a plurality of conductive through holes electrically connected to the electronic component; the electronic structure is stacked by the plurality of conductive pillars On the carrier board, so that the plurality of conductive pillars support the electronic component, and the electronic component is electrically connected to the conductive block and the conductive through hole, wherein the electronic intermediary block is located between the electronic component and the carrier board Between; forming a coating layer between the carrier board and the electronic component, so that the coating layer covers the electronic intermediary block and the plurality of conductive pillars; and remove the carrier board. The method for manufacturing an electronic package according to claim 9, wherein the surface of the coating layer is flush with the surface of the electronic interposer. The method for manufacturing an electronic package according to claim 9, wherein the surface of the coating layer is flush with the end surface of the conductive pillar. The method for manufacturing an electronic package according to claim 9, wherein the conductive through hole is exposed on the surface of the coating layer. The method for manufacturing an electronic package according to claim 9, wherein the end surface of the conductive pillar is exposed on the surface of the coating layer. The method for manufacturing an electronic package according to claim 9, wherein the electronic component is electrically connected to the conductive block and the conductive through hole through a circuit portion. The method for manufacturing an electronic package according to claim 9, wherein the electronic component has a plurality of conductive bumps, so that the plurality of conductive bumps are electrically connected to the conductive through hole and/or the conductive block. The method for manufacturing an electronic package according to claim 9, wherein the electronic component is electrically connected to the conductive through hole by a conductor, and the conductor is not connected to the conductive block. The manufacturing method of the electronic package according to claim 9 further includes forming a circuit structure on the cladding layer, and the circuit structure is electrically connected to the conductive pillar and the conductive through hole. The method for manufacturing an electronic package according to claim 9, further comprising a plurality of conductive elements formed on the coating layer, and the plurality of conductive elements are electrically connected to the conductive pillar and the conductive through hole.

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