TW202339130A - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package is provided, in which a panel wafer body includes a plurality of electronic structures arranged in an array, electronic components are stacked on each of the electronic structures, a plurality of conductive pillars are formed on the electronic structure, at least one groove is formed between the electronic structures, a encapsulating layer is formed on the panel wafer body, and a circuit structure is formed on the encapsulating layer, so when a dicing process is performed along the groove, the electronic structure does not need to be formed solder bump. Therefore, the overall height of the electronic package can be reduced, and the current transmission path can be effectively shortened to improve the electrical performance.

Description

Electronic packages and manufacturing methods

The present invention relates to a semiconductor device, and in particular to an electronic package and a manufacturing method thereof.

With the vigorous development of the electronics industry, electronic products are gradually moving towards multi-function and high performance. Technologies currently used in the field of chip packaging include, for example, Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module. MCM) and other flip-chip packaging modules, or three-dimensional stacking of chips integrated into three-dimensional integrated circuit (3D IC) stacking technology.

FIG. 1 is a schematic cross-sectional view of a conventional three-dimensional integrated circuit stack packaging structure 1 . As shown in Figure 1, the packaging structure 1 has a silicon interposer (TSI) 1a disposed on a packaging substrate 19 through solder bumps 16, and covers the solder bumps 16 with a primer 191 . The silicon interposer 1a has a silicon plate body 10 and a plurality of conductive silicon vias (TSVs) 101 formed therein, and an electrically connected conductive silicon through hole 101 is formed on the surface of the silicon plate body 10 A redistribution layer (RDL), wherein the redistribution structure includes a dielectric layer 11 and a circuit layer 12 formed on the dielectric layer 11, and the circuit layer 12 is electrically connected The conductive silicon through hole 101 forms an insulating protective layer 13 on the dielectric layer 11 and the circuit layer 12, and the insulating protective layer 13 The exposed portion of the circuit layer 12 is used to combine a plurality of solder bumps 14 for setting the semiconductor chip 17 , and then the solder bumps 14 are covered with a primer 171 . After that, a packaging material 18 is formed on the packaging substrate 19 so that the packaging material 18 covers the semiconductor chip 17 and the silicon interposer 1 a.

Furthermore, another insulating protective layer 15 can be formed on the silicon plate body 10, and the insulating protective layer 15 exposes the end surfaces of the conductive silicon through holes 101, so as to combine and electrically connect to the end surfaces of the conductive silicon through holes 101. A plurality of solder bumps 16 are connected, wherein an under-bump metallurgy (UBM) 160 for connecting the solder bumps 16 can be selectively formed on the end surface of the conductive silicon through hole 101.

In subsequent applications, the packaging structure 1 can form a plurality of solder balls 192 on the lower side of the packaging substrate 19 to be connected to a circuit board 1b.

However, in the conventional packaging structure 1, when manufacturing the silicon interposer 1a, the silicon plate body 10 needs to be placed on a glass carrier first, and then the conductive silicon through holes 101 and RDL are made. 101 and RDL, the glass carrier needs to be removed again, causing increased material costs and trouble in the manufacturing process.

Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem that the industry needs to overcome.

In view of the deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: an electronic structure having a plurality of contacts, and the plurality of contacts do not protrude from the surface of the electronic structure; electronic components are stacked On the electronic structure, a plurality of conductive pillars are provided on the electronic structure to electrically connect a plurality of contacts of the electronic structure; a coating layer is formed on the electronic structure to cover the electronic component and the electronic structure. A plurality of conductive pillars; and a circuit structure are provided on the coating layer to electrically connect the plurality of conductive pillars.

The present invention further provides a method for manufacturing an electronic package, which includes: providing a full-layout wafer body, which includes a plurality of electronic structures arranged in an array, and each electronic structure has a plurality of contacts; and arranging an electronic component on each On the electronic structure, a plurality of conductive pillars electrically connected to the plurality of contacts are formed on each electronic structure; grooves are formed between the electronic structures, and the grooves do not penetrate the electronic structure; forming a package Coating the full-layout wafer, so that the coating layer covers the electronic component and the plurality of conductive pillars; forming a circuit structure on the coating layer, so that the circuit structure is electrically connected to the plurality of conductive pillars ; and perform a cutting process along the groove.

In the aforementioned electronic package and its manufacturing method, the electronic component is in contact with the surface of the electronic structure.

In the aforementioned electronic package and its manufacturing method, the electronic component is bonded to the electronic structure through a bonding layer.

In the aforementioned electronic package and its manufacturing method, the electronic component is electrically connected to the circuit structure.

In the aforementioned electronic package and its manufacturing method, the electronic component has a plurality of electrode pads, so that the electronic component is connected to a plurality of contacts of the electronic structure through the plurality of electrode pads and is electrically connected to the plurality of contacts.

In the aforementioned electronic package and its manufacturing method, the electronic structure is equipped with a wiring structure for connecting and electrically connecting the plurality of conductive pillars. Further, the electronic component is multiplexed and electrically connected to the wiring structure.

In the aforementioned electronic package and its manufacturing method, a step portion is formed on the edge of the electronic structure.

In the aforementioned electronic package and its manufacturing method, the end surfaces of the plurality of conductive pillars are flush with the surface of the coating layer.

The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the circuit structure, and electrically connecting the plurality of conductive elements to the circuit structure.

It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the full-layout wafer is mainly used to replace the glass carrier of the traditional wireless circuit. Therefore, compared with the conventional technology, the manufacturing method of the present invention eliminates the need for a glass carrier. The board can save material costs.

Furthermore, the electronic structure does not require the formation of solder bumps, so the overall height of the electronic package can be reduced, and the current transmission path can be effectively shortened to improve electrical performance.

In addition, the coating layer encapsulates the electronic structure and the electronic component on five sides, so that the five sides of the electronic structure and the five sides of the electronic component are protected to prevent the electronic structure and the electronic component from being damaged during the manufacturing process. Medium collapse.

1:Package structure

1a: Silicon interposer

1b: Circuit board

10:Silicon plate body

101:Conductive silicon perforation

11,260: dielectric layer

12,241,441: Line layer

13,15: Insulating protective layer

14,16:Solder bumps

160: Metal layer under the bump

17:Semiconductor wafer

171,191: Primer

18:Packaging material

19:Package substrate

192: Solder ball

2: Electronic packages

2a:Full-layout wafer

21:Electronic components

21a:Action surface

21b: Non-active surface

210,310:Electrode pad

211:Protective film

212: Electrical conductor

23:Conductive pillar

23a:End face

24,44: Wiring structure

240:Insulation layer

25: Cladding layer

25a: First surface

25b: Second surface

26:Line structure

261: Line redistribution layer

27:Conductive components

29,49:Electronic structure

290,291,391,490,491:Contact

32: Bonding layer

411: Conductive bumps

412:Metal pillar

42: Bottom glue

49a: Chip body

S: Groove

R: step part

t:Thickness

L: cutting path

Figure 1 is a schematic cross-sectional view of a conventional packaging structure.

2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

FIG. 2E is a schematic cross-sectional view corresponding to another embodiment of FIG. 2D.

Figures 3A and 3B are schematic cross-sectional views of other configurations of Figure 2A.

4A and 4B are schematic cross-sectional views of other aspects of the electronic structure of the electronic package of the present invention.

The following describes the implementation of the present invention through specific embodiments. Those familiar with the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to coordinate with the content disclosed in the specification for the understanding and reading of those familiar with the art, and are not used to limit the implementation of the present invention. Therefore, it has no technical substantive significance. Any structural modifications, changes in proportions, or adjustments in size shall still fall within the scope of this invention without affecting the effects that can be produced and the purposes that can be achieved. The technical content disclosed by the invention must be within the scope that can be covered. At the same time, terms such as "above" and "a" cited in this specification are only used to facilitate the description and are not used to limit the scope of the present invention. Changes or adjustments in their relative relationships will not occur without Substantial changes in the technical content shall also be deemed to be within the scope of the present invention.

2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , a full-layout wafer 2 a is provided, which includes a plurality of electronic structures 29 arranged in an array. At least one electronic component 21 is provided on each electronic structure 29 , and a pattern formed on each electronic structure 29 is provided. There are a plurality of conductive pillars 23 . Next, a groove S is formed between the electronic structures 29, and the groove S is located on the cutting path L required for the subsequent dicing process (as shown in FIG. 2C). That is, the groove S is formed by The pre-cut method does not penetrate the entire wafer 2a (electronic structure 29).

In this embodiment, the electronic structure 29 is an active component, such as a System-On-Chip (SOC) type semiconductor chip, which has a plurality of non-bump contacts 290, 291, and the plurality of contacts 290,291 do not protrude from the surface of the electronic structure 29. For example, some of the contacts 290 have electrical functions to electrically connect the conductive pillars 23 , while the other contacts 291 correspond to the positions of the electronic components 21 to have electrical functions or serve as dummy pads as required. ).

Furthermore, the electronic component 21 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has an active surface 21a and a non-active surface 21b facing each other. The electronic component 21 is placed with its non-active surface 21b in direct contact with the electronic structure 29 On the electronic structure 29, the active surface 21a is in a face up state. At this time, the contact 291 of the electronic structure 29 serves as a virtual pad for heat dissipation of the non-active surface 21b, and the active surface 21a It has a plurality of electrode pads 210 and a protective film 211 such as a passivation material. The plurality of electrode pads 210 are combined and electrically connected to a plurality of conductors 212, such as conductive lines, spherical solder balls, or copper pillars. , pillar-shaped metal materials such as solder bumps, or stud-shaped conductive parts made by wire bonding machines, but are not limited to these, so that the conductor 212 is located in the protective film 211 . It should be understood that in another embodiment, as shown in FIG. 3A , the inactive surface 21 b of the electronic component 21 can also be bonded to the electronic structure 29 through a bonding layer 32 .

Alternatively, as shown in FIG. 3B , the contact point 391 of the electronic structure 29 has an electrical function, and the active surface 21 a of the electronic component 21 adopts a face down type, so that the electronic component 21 is face-to-face. A to-face hybrid bonding method connects the plurality of electrode pads 310 of the electronic component 21 to the contacts 391 of the electronic structure 29 and electrically connects the contacts 391 .

It should be understood that there are many ways of arranging the electronic component 21 relative to the electronic structure 29 and are not limited to the above.

In other embodiments, as shown in FIG. 4A , the electronic structure 49 includes a chip body 49a and a wiring structure 24 disposed on the chip body 49a. The wiring structure 24 includes at least an insulating layer 240 and is provided on The circuit layer 241 in the form of RDL is on the insulating layer 240, and the outermost circuit layer 241 is equipped with a plurality of contacts 490, 491 for setting the electronic component 21 and the conductive pillar 23, wherein the electronic component 21 is connected by the A plurality of metal pillars 412 such as copper pillars are covered by conductive bumps 411 such as solder material. The crystal is disposed on the electronic structure 49 and electrically connected to the contact 491 , and the metal pillar 412 and the conductive bump 411 are covered with the base glue 42 .

Alternatively, as shown in FIG. 4B , the wiring structure 44 is disposed on a partial surface of the chip body 49 a of the electronic structure 49 , and the outermost circuit layer 441 of the wiring structure 44 is disposed with a plurality of contacts for setting the plurality of conductive pillars 23 490. At this time, the electronic component 21 can be disposed on the chip body 49a with its inactive surface 21b in direct contact (or bonding) as required, or as shown in FIG. 4B, multiple electronic components 21 can be placed on the chip body 49a. The electrode pad 310 is correspondingly joined to the contact point 391 of the chip body 49a of the electronic structure 49 and is electrically connected to the contact point 391.

In addition, the material forming the circuit layers 241 and 441 is copper, and the material forming the insulating layer 240 is such as poly(p-oxadiazobenzene) (PBO), polyimide (PI), prepreg (PP) or others. of dielectric materials.

In addition, the plurality of conductive pillars 23 are made of a metal material such as copper or a solder material, and the plurality of conductive pillars 23 are disposed on the contacts 290, 490 with electrical functions to electrically connect the contacts 290, 490.

As shown in FIG. 2B , following the process of FIG. 2A or FIG. 3A , a coating layer 25 is formed on the electronic structure 29 and in the groove S, so that the coating layer 25 covers the electronic components 21 and the electronic components 21 . Conductive pillar 23, wherein the cladding layer 25 has an opposite first surface 25a and a second surface 25b, and the cladding layer 25 is bonded to the electronic structure 29 with its second surface 25b. Then, through a leveling process, the first surface 25a of the coating layer 25 is flush with the upper surface of the protective film 211, the end surface of the conductor 212 and the end surface 23a of the conductive pillar 23, so that the protective film 211 , the conductor 212 and the conductive pillar 23 are exposed on the first surface 25a of the coating layer 25.

In this embodiment, the coating layer 25 is an insulating material, such as an epoxy resin encapsulant, which can be formed on the electronic structure 29 by lamination or molding.

Furthermore, the leveling process removes part of the material of the conductive pillar 23, part of the material of the protective film 211 (even part of the material of the conductor 212), and part of the material of the coating layer 25 through grinding.

As shown in FIG. 2C , a circuit structure 26 is formed on the first surface 25 a of the coating layer 25 , and the circuit structure 26 is electrically connected to the conductive pillars 23 .

In this embodiment, the circuit structure 26 includes a plurality of dielectric layers 260 and a plurality of redistribution layers (RDLs) 261 disposed on the plurality of dielectric layers 260, and the outermost dielectric layer 260 can be used as a protective layer. The solder layer is formed so that the outermost circuit redistribution layer 261 is partially exposed to the solder mask. Alternatively, the circuit structure 26 may only include a single dielectric layer 260 and a single circuit redistribution layer 261 .

Furthermore, the material forming the circuit redistribution layer 261 is copper, and the material forming the dielectric layer 260 is such as poly(p-oxadiazobenzene) (PBO), polyimide (PI), prepreg (PP). ) or other dielectric materials.

In addition, the circuit redistribution layer 261 of the circuit structure 26 is directly electrically connected to the conductor 212 of the electronic component 21 . It should be understood that if the configuration shown in FIG. 3B, FIG. 4A or FIG. 4B is continued during the manufacturing process of FIG. 2B, the circuit redistribution layer 261 of the circuit structure 26 will not be directly electrically connected to the electronic component 21.

In addition, a plurality of conductive elements 27 such as solder balls can be formed on the outermost line redistribution layer 261 so that the plurality of conductive elements 27 are electrically connected to the plurality of conductive pillars 23 and/or the conductor 212 .

As shown in FIG. 2D , a cutting tool (not shown) is aligned with each groove S, and a cutting process is performed along the cutting path L as shown in FIG. 2C to obtain the electronic package 2 .

In this embodiment, a stepped portion R is formed on the edge of the electronic structure 29 corresponding to the groove S thereof.

Therefore, the manufacturing method of the present invention uses the design of the full-layout wafer 2a, that is, the electronic structures 29, 49 in wafer form as a carrier to replace the glass carrier of the traditional wireless circuit. Therefore, compared with the conventional technology, the manufacturing method of the present invention eliminates the need for a glass carrier and can save material costs.

Furthermore, the electronic structures 29 and 49 do not need to be provided with conventional solder bumps, so the overall height of the electronic package 2 can be reduced, and the current transmission path can be effectively shortened to improve electrical performance.

In addition, the coating layer 25 encapsulates the electronic structure 29, 49 and the electronic component 21 on five sides, so that the five sides of the electronic structure 29, 49 and the five sides of the electronic component 21 are protected to avoid The electronic structures 29, 49 and the electronic component 21 are damaged during the manufacturing process. Furthermore, in subsequent processes, the electronic structures 29 and 49 can be polished to expose the exposed surfaces (the bottom surface of Figure 2D), so that the thickness t of the electronic structure 29 (or the chip body 49a) can be less than 50 microns (um), as shown in Figure As shown in 2E, during the grinding process, because each side of the electronic structure 29 is protected by the coating layer 25, even if the electronic structure 29, 49 is ground to an extremely thin state, it will not crack. Therefore, It is beneficial to the overall thinning requirement of the electronic package 2 .

The invention further provides an electronic package 2, which includes: an electronic structure 29, 49, an electronic component 21, a plurality of conductive pillars 23, a coating layer 25 and a circuit structure 26.

The electronic structure 29, 49 has a plurality of contacts 290, 291, 391, 490, 491, and the plurality of contacts 290, 291, 391, 490, 491 does not protrude from the surface of the electronic structure 29, 49.

The electronic components 21 are stacked on the electronic structures 29, 49.

The plurality of conductive pillars 23 are disposed on the electronic structures 29 and 49 to electrically connect the plurality of contacts 290 and 490 of the electronic structures 29 and 49.

The coating layer 25 is formed on the electronic structures 29 and 49 to cover the electronic component 21 and the plurality of conductive pillars 23 .

The circuit structure 26 is provided on the coating layer 25 to electrically connect the plurality of conductive pillars 23 .

In one embodiment, the electronic component 21 contacts the surface of the electronic structure 29 .

In one embodiment, the electronic component 21 is bonded to the electronic structure 29 through a bonding layer 32 .

In one embodiment, the electronic component 21 is electrically connected to the circuit structure 26 .

In one embodiment, the electronic component 21 has a plurality of electrode pads 310, so that the electronic component 21 connects the plurality of electrode pads 310 to the contacts 391 of the electronic structure 29 in a hybrid bonding manner and electrically connects them. The contact 391.

In one embodiment, the electronic structure 49 is configured with wiring structures 24, 44 to connect and electrically connect the conductive pillars 23. For example, the electronic component 21 is multiplexed and electrically connected to the wiring structure 24 .

In one embodiment, a step portion R is formed on the edge of the electronic structure 29 .

In one embodiment, the end surface 23a of the conductive pillar 23 is flush with the first surface 25a of the coating layer 25.

In one embodiment, the electronic package 2 further includes a plurality of conductive elements 27 formed on the circuit structure 26, and the plurality of conductive elements 27 are electrically connected to the circuit structure 26.

In summary, the electronic package and its manufacturing method of the present invention use the full-surface wafer to replace the glass carrier of the traditional wireless circuit. Therefore, the manufacturing method of the present invention can effectively save material costs.

Furthermore, the electronic structure does not require the formation of solder bumps, thereby reducing the overall height of the electronic package and effectively shortening the current transmission path to improve electrical performance.

In addition, the coating layer encapsulates the electronic structure and the electronic component on five sides, so that the five sides of the electronic structure and the five sides of the electronic component are protected to prevent the electronic structure and the electronic component from interfering with each other. Broken during the manufacturing process.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of rights protection of the present invention should be as listed in the patent application scope described below.

2: Electronic packages

21:Electronic components

23:Conductive pillar

25: Cladding layer

26:Line structure

27:Conductive components

29: Electronic structure

290,291: Contact

R: step part

Claims (20)

An electronic package including: The electronic structure has a plurality of contacts, and the plurality of contacts do not protrude from the surface of the electronic structure; Electronic components are stacked on the electronic structure; A plurality of conductive pillars are provided on the electronic structure to electrically connect a plurality of contacts of the electronic structure; A coating layer is formed on the electronic structure to cover the electronic component and the plurality of conductive pillars; and The circuit structure is provided on the coating layer to electrically connect the plurality of conductive pillars. The electronic package of claim 1, wherein the electronic component contacts the surface of the electronic structure. The electronic package of claim 1, wherein the electronic component is bonded to the electronic structure through a bonding layer. The electronic package as described in any one of claims 1 to 3, wherein the electronic component is electrically connected to the circuit structure. The electronic package of claim 1, wherein the electronic component has a plurality of electrode pads, and the electronic component is correspondingly joined and electrically connected to a plurality of contacts of the electronic structure using the plurality of electrode pads. The electronic package as claimed in claim 1, wherein the electronic structure is configured with a wiring structure for connecting and electrically connecting the plurality of conductive pillars. The electronic package of claim 6, wherein the electronic component is disposed and electrically connected to the wiring structure. The electronic package of claim 1, wherein a step portion is formed on an edge of the electronic structure. The electronic package as claimed in claim 1, wherein the end surfaces of the plurality of conductive pillars are flush with the surface of the coating layer. The electronic package of claim 1 further includes a plurality of conductive elements formed on the circuit structure, and the plurality of conductive elements are electrically connected to the circuit structure. A method for manufacturing electronic packages includes: Provide a full layout wafer body, which contains a plurality of electronic structures arranged in an array, and each of the electronic structures has a plurality of contacts; Arrange an electronic component on each of the electronic structures, and form a plurality of conductive pillars on each of the electronic structures that are electrically connected to the plurality of contacts; Forming grooves between the electronic structures, wherein each groove does not penetrate the electronic structures; Forming a cladding layer on the full-layout wafer body so that the cladding layer covers the electronic component and the plurality of conductive pillars; Forming a circuit structure on the cladding layer so that the circuit structure is electrically connected to the plurality of conductive pillars; and The cutting process is carried out along this groove. The method for manufacturing an electronic package as claimed in claim 11, wherein the electronic component is in contact with the surface of the electronic structure. The method for manufacturing an electronic package as claimed in claim 11, wherein the electronic component is bonded to the electronic structure through a bonding layer. The method for manufacturing an electronic package as described in any one of claims 11 to 13, wherein the electronic component is electrically connected to the circuit structure. The method of manufacturing an electronic package as claimed in claim 11, wherein the electronic component has a plurality of electrode pads, and the electronic component is correspondingly joined and electrically connected to a plurality of contacts of the electronic structure using the plurality of electrode pads. The method of manufacturing an electronic package as claimed in claim 11, wherein the electronic structure is configured with a wiring structure for connecting and electrically connecting the plurality of conductive pillars. The method of manufacturing an electronic package as claimed in claim 16, wherein the electronic component is disposed and electrically connected to the wiring structure. The method of manufacturing an electronic package as claimed in claim 11, wherein a step portion is formed on an edge of the electronic structure. The method for manufacturing an electronic package as claimed in claim 11, wherein the end surfaces of the plurality of conductive pillars are flush with the surface of the coating layer. The method of manufacturing an electronic package as claimed in claim 11 further includes forming a plurality of conductive elements on the circuit structure, and electrically connecting the plurality of conductive elements to the circuit structure.

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