TWI772816B - Electronic package and manufacturing method thereof - Google Patents

Abstract

This invention provides an electronic package which forms a encapsulating layer on an electronic component, and then bonds the encapsulating layer on a supporting structure, so that the encapsulating layer is free from crawling to a side of the electronic component due to capillary action. Therefore, when a packaging layer for covering the electronic component and the encapsulating layer is polished, an internal stress of the electronic component can be dispersed to avoid a problem of cracking of the electronic component due to stress concentration.

Description

Electronic package and method of making the same

The present invention relates to a semiconductor device, in particular to an electronic package of flip chip package type and a manufacturing method thereof.

With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. There are many technologies currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (Multi-Chip Module) MCM) and other flip-chip packaging modules, or three-dimensionally stacking and integrating chips into a three-dimensional integrated circuit (3D IC) chip stacking module.

FIG. 1 is a schematic cross-sectional view of a conventional 3D IC type semiconductor package 1 . First, provide a through silicon interposer (TSI) 10 having an opposite via side 10a and a die placement side 10b, and the silicon interposer 10 has a plurality of connections between the die placement side 10b and the interposer side 10a. A through-silicon via (TSV) 100 is formed, and a circuit structure 101 is formed on the die-mounting side 10b for connecting a plurality of semiconductor elements 11 with a plurality of solder bumps 12, and then covered with a primer 13 The solder bumps 12 are formed to form an encapsulation layer 14 to cover the semiconductor element 11 , and the encapsulation layer 14 is ground to expose the encapsulation layer 14 from the upper surface of the semiconductor element 11 . Next, the silicon interposer 10 is disposed on a package substrate 16 with its transfer side 10a through a plurality of conductive elements 15, and the package substrate 16 is electrically connected to the conductive elements Through silicon vias 100 , the conductive elements 15 are covered with primer 17 . Next, an encapsulant 18 is formed on the package substrate 16 , so that the encapsulant 18 covers the encapsulation layer 14 and the silicon interposer 10 . Finally, a plurality of solder balls 160 are formed on the lower side of the package substrate 16 for connecting to a circuit board 19 .

However, in the conventional semiconductor package 1, the semiconductor element 11 is flip-chip bonded to the circuit structure 101, and then the primer 13 is filled, so that the outer side 130 of the primer 13 is sloped, as shown in FIG. 1' As shown, the outer side 130 of the primer 13 will crawl on the side surface 11c of each semiconductor element 11 due to the capillary action generated by the gap S between the semiconductor elements 11, so that the inside of the semiconductor element 11 The stress increases, so when the encapsulation layer 14 is ground, the external grinding force will be transmitted to the semiconductor element 11 , causing the stress concentration of the semiconductor element 11 to break down, resulting in poor reliability of the semiconductor package 1 .

Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem to be solved at present.

In view of various deficiencies in the above-mentioned prior art, the present invention provides an electronic package, comprising: a bearing structure; a plurality of electronic components arranged on the bearing structure at intervals, so that any two adjacent electronic components are formed between them. There is a gap, wherein a plurality of conductive bumps and a cladding layer covering the plurality of conductive bumps are formed on each of the electronic components, so that each of the electronic components is fixed on the carrier structure by the cladding layer, and is The conductive bump is electrically connected to the carrying structure; and an encapsulation layer is formed on the carrying structure to cover the plurality of electronic components and the covering layer.

The present invention further provides a method for manufacturing an electronic package, which includes: providing a plurality of electronic components, wherein a plurality of conductive bumps and a coating layer covering the plurality of conductive bumps are formed on each of the electronic components; It is arranged on a carrying structure at intervals, so that a gap is formed between any two adjacent electronic components, wherein each electronic component is fixed on the carrying structure by the coating layer, and the conductive bump is used to form a gap. electrically connecting the carrying structure; and forming an encapsulation layer on the carrying structure to cover the plurality of electronic components and the covering layer.

In the aforementioned electronic package and its manufacturing method, the structures of the plurality of electronic components are different from each other.

In the aforementioned electronic package and its manufacturing method, the distance between the gaps is at most 300 microns.

In the aforementioned electronic package and its manufacturing method, the encapsulation layer may be ground, so that a surface of the electronic component is exposed on a surface of the encapsulation layer.

In the aforementioned electronic package and the manufacturing method thereof, the side surface of the cladding layer is flush with the side surface of the electronic component.

In the aforementioned electronic package and its manufacturing method, the cladding layer protrudes from the side surface of the electronic component, and the cladding layer does not contact the side surface of the electronic component. For example, the end of the cladding layer protrudes from the side surface of the electronic component, and the cross-section of the edge of the cladding layer is spherical.

In the aforementioned electronic package and its manufacturing method, the coating layer is a non-conductive film.

In the aforementioned electronic package and its manufacturing method, the Young's modulus of the package layer is at least 20 GPa.

In the aforementioned electronic package and the manufacturing method thereof, the Young's modulus of the packaging layer is greater than the Young's modulus of the cladding layer.

As can be seen from the above, in the electronic package and the manufacturing method thereof of the present invention, the coating layer is mainly arranged on the electronic component to be fixed on the bearing structure, so that the coating layer will not crawl due to capillary action to the side of the electronic component, so compared with the prior art, when the present invention grinds the encapsulation layer, even if the external grinding force is transmitted to the electronic component, the inside of the electronic component can still disperse the impact on the packaging layer. stress, so as to avoid the problem of cracking of the electronic component due to stress concentration, thereby improving the reliability of the electronic package.

1: Semiconductor package

10: Silicon interposer

10a: Transfer side

10b: chip placement side

100: Conductive TSV

101: Line structure

11: Semiconductor components

11c, 21c, 23c, 31c: Side

12: Solder bumps

13: Primer

130: Outside

14,24: Encapsulation layer

15: Conductive elements

16: Package substrate

160: Solder Ball

17: Primer

18: Encapsulating colloid

19: circuit board

2,2',3: Electronic package

2a: Full-page substrate structure

20: Bearing structure

200: circuit layer

21,31: Electronic Components

21a: Action surface

21b: Non-active surface

210: Electrode pads

22: Conductive bumps

23: Cladding

230: Edge

24b: Upper surface

310: Packaging material

311: Control Chip

312: High bandwidth memory chip

X: horizontal direction

L: cutting path

S: Clearance

t: spacing

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.

Fig. 1' is a schematic partial enlarged cross-sectional view of Fig. 1 .

2A to 2C are schematic cross-sectional views of a method for manufacturing an electronic package of the present invention.

Fig. 2B' is a schematic partial enlarged cross-sectional view of another aspect of Fig. 2B.

Fig. 2C' is a schematic cross-sectional view of another aspect of Fig. 2C.

FIG. 3 is a schematic cross-sectional view of another aspect of FIG. 2C .

The following specific embodiments are used to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it has no technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope of the present invention without affecting the effect and the purpose that the present invention can achieve. The technical content disclosed by the invention can be covered within the scope. At the same time, the terms such as "above" quoted in this specification are only for the convenience of description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments of their relative relationships do not substantially change the technical content. Hereinafter, it should also be regarded as the scope in which the present invention can be implemented.

2A to 2C are schematic cross-sectional views of a method of manufacturing the electronic package 2 of the present invention.

As shown in FIG. 2A , a full-page substrate structure 2 a is provided, which includes a plurality of electronic components 21 arranged in an array, and each of the electronic components 21 is provided with a plurality of conductive bumps 22 and a covering the conductive bumps 22 the cladding layer 23.

The electronic element 21 can be an active element, a passive element, a package structure or a combination thereof, and the active element is such as a semiconductor chip, and the passive element is such as a resistor, a capacitor and an inductor. In the present embodiment, the electronic element 21 is a semiconductor chip, and has an opposite active surface 21a and a non-active surface 21b, the active surface 21a has a plurality of electrode pads 210, and conductive electrodes are formed on each of the electrode pads 210. The bumps 22 are formed with the cladding layer 23 on the active surface 21 a to cover the conductive bumps 22 , and at the same time, the conductive bumps 22 are exposed to the cladding layer 23 .

Furthermore, the conductive bumps 22 are metal pillars (such as copper pillars), solder materials or a combination thereof, and the cladding layer 23 is a non-conductive film (NCF for short).

As shown in FIG. 2B , the whole-layout substrate structure 2 a is subjected to a singulation process along the cutting path L shown in FIG. 2A to separate the electronic components 21 , and then spaced along the horizontal direction X on a carrier structure 20 At least two electronic components 21 are arranged, and a space (gap) S is formed between any two adjacent electronic components 21 , and the distance t between the spaces (gap) S is at most 300 micrometers (μm).

The carrier structure 20 can be a package substrate with a core layer and a circuit structure or a circuit structure without a core layer, and the structure is formed by forming a plurality of circuit layers 200 on a dielectric material, such as a circuit redistribution layer ( redistribution layer, referred to as RDL). In this embodiment, the carrier structure 20 is a coreless circuit structure. However, in other embodiments, the carrier structure 20 may also be a semiconductor substrate having a plurality of conductive through-silicon vias (TSVs), which serve as a Through Silicon interposer (TSI). It should be understood that the carrying structure 20 can also be other carrying units capable of carrying electronic components such as chips, such as a lead frame, but is not limited to the above.

Furthermore, when the electronic device 21 is bonded on the carrier structure 20 by means of the cladding layer 23 , the conductive bumps 22 are electrically connected to the circuit layer 200 of the carrier structure 20 in a flip-chip manner.

In addition, through the singulation process, the side surface 21c of the electronic device 21 is flush with the side surface 23c of the cladding layer 23 . However, in another embodiment, the side surface 23c of the cladding layer 23 can be formed to protrude from the edge of the side surface 21c of the electronic element 21 based on the force of pressing the electronic element 21 on the carrier structure 20 . 230, as shown in Figure 2B'. Specifically, the cross-section of the edge 230 of the cladding layer 23 is convex (eg, a hemispherical spherical surface).

In addition, in this embodiment, although the electronic components 21 are of the same type (ie, active components), their internal structures may be the same or different.

As shown in FIG. 2C , an encapsulation layer 24 is formed on the carrier structure 20 to cover the cladding layer 23 and the electronic components 21 .

The encapsulation layer 24 can be an insulating material, such as polyimide (PI), dry film, epoxy, molding compound or other suitable materials. In this embodiment, the encapsulation layer 24 is formed on the carrier structure 20 by lamination or molding, so that the encapsulation layer 24 fills the gap S.

Furthermore, the Young's modulus of the encapsulation layer 24 is greater than the Young's modulus of the cladding layer 23 . In this embodiment, the Young's modulus of the encapsulation layer 24 is above 20 GPa.

In addition, the non-active surface 21b of the electronic element 21 and the upper surface 24b of the encapsulation layer 24 can be made coplanar by a leveling process or a thinning process, as shown in FIG. The active surface 21 b is exposed to the encapsulation layer 24 . For example, when the encapsulation layer 24 is formed on the carrier structure 20, the encapsulation layer 24 covers the inactive surface 21b of the electronic component 21, and then a part of the material of the encapsulation layer 24 is removed by grinding or cutting (or Part of the material of the inactive surface 21b of the electronic component 21 is removed at the same time as required, so that the inactive surface 21b of the electronic component 21 is flush with the top surface 24b of the encapsulation layer 24 .

In addition, after the encapsulation layer 24 is formed, a plurality of solder balls (not shown) can be formed on the lower side (or the ball-mounting side) of the carrier structure 20 for the electronic package 2 to be mounted on a circuit board such as a circuit board. electronic device (figure omitted).

It should be understood that the electronic components 21 may also be different types of electronic components. The two electronic components 21 and 31 shown in FIG. 3 , the electronic component 21 (active component) is an Application-specific integrated circuit (ASIC) type semiconductor chip, and the other electronic component 31 is The package structure includes a package material 310 , a control chip 311 and at least one package module of a High Bandwidth Memory (HBM) type chip 312 , and the conductive bumps are combined with the electrode pads 210 of the control chip 311 twenty two.

Therefore, in the manufacturing method of the present invention, the cladding layer 23 is formed on the electronic components 21 and 31 first, and then the cladding layer 23 is fixed on the bearing structure 20 so that the cladding layer 23 will not be damaged by The capillary action crawls to the side surfaces 21c, 31c of the electronic components 21, 31, so no matter the size of the distance t between the gaps S (for example, less than or equal to 150 microns), the coating layer 23 will not be in the gap S. There is a capillary phenomenon, so that the inside of the electronic components 21 and 31 can avoid the phenomenon of stress increase. Therefore, compared with the prior art, the manufacturing method of the present invention can grind the encapsulation layer 24 even if the external grinding force is transmitted to the Among the electronic components 21 and 31 , the internal stress of the electronic components 21 and 31 can still be dispersed, so as to avoid the problem of cracking of the electronic components 21 and 31 due to the stress concentration, thereby improving the reliability of the electronic package 2 . reliability.

Furthermore, the gap S is filled by the package layer 24 with a larger Young's modulus, which can strengthen the strength of the gap, so that the stress concentration inside the electronic components 21 and 31 will not cause the cracking of the package.

The present invention further provides an electronic package 2 , 2 ′, 3 , which includes: a bearing structure 20 , a plurality of electronic components 21 , 31 , and a package layer 24 .

The plurality of electronic components 21, 31 are disposed on the carrier structure 20 at intervals, so that a gap S is formed between any two adjacent electronic components 21, 31, and each of the electronic components 21, 31 has a plurality of conductive The bumps 22 and a cladding layer 23 covering the plurality of conductive bumps 22 , so that the electronic components 21 and 31 are fixed on the carrier structure 20 by the covering layer 23 , and the conductive bumps 22 are used to electrically The carrier structure 20 is sexually connected.

The encapsulation layer 24 is formed on the carrier structure 20 to encapsulate the plurality of electronic components 21 , 31 and the encapsulation layer 23 .

In one embodiment, the structures of the plurality of electronic components 21, 31 are different from each other.

In one embodiment, the distance t between the gaps S is at most 300 microns.

In one embodiment, the surfaces (eg, inactive surfaces) of the electronic components 21 and 31 are exposed on the surface 24 b of the encapsulation layer 24 .

In one embodiment, the side surface 23c of the cladding layer 23 is flush with the side surfaces 21c and 31c of the electronic components 21 and 31 .

In one embodiment, the cladding layer 23 protrudes from the side surfaces 21c and 31c of the electronic components 21 and 31 , and the cladding layer 23 does not contact the side surfaces 21c and 31c of the electronic components 21 and 31 . For example, the edge 230 of the cladding layer 23 protrudes from the side surface 21c of the electronic device 21 , and the cross-section of the edge 230 of the cladding layer 23 is spherical.

In one embodiment, the cladding layer 23 is a non-conductive film.

In one embodiment, the Young's modulus of the encapsulation layer 24 is at least 20 GPa.

In one embodiment, the Young's modulus of the encapsulation layer 24 is greater than the Young's modulus of the cladding layer 23 .

To sum up, the electronic package of the present invention and the manufacturing method thereof are arranged on the electronic component by disposing the coating layer to be fixed on the supporting structure, so that the coating layer will not be pressed against the electronic component On the lateral side, the internal part of the electronic component of the present invention can avoid the problem of cracking due to stress concentration, thereby improving the reliability of the electronic package. In addition, the encapsulation layer 24 fills the gap S, which can strengthen the strength of the gap, so that the internal stress concentration of the electronic component will not cause the package to break.

The above embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the right of the present invention should be listed in the scope of the patent application described later.

2: Electronic packages

20: Bearing structure

21: Electronic Components

22: Conductive bumps

23: Cladding

24: Encapsulation layer

S: Clearance

Claims (12)

An electronic package includes: a bearing structure; a plurality of electronic components are arranged on the bearing structure at intervals, so that a gap is formed between any two adjacent electronic components, wherein each of the electronic components is formed with a A plurality of conductive bumps and a cladding layer covering the plurality of conductive bumps, the cladding layer is a non-conductive film (Non-Conductive Film, referred to as NCF), so that the electronic components are fixed by the cladding layer After the carrying structure, the carrying structure is electrically connected by the conductive bump, and the end of the cladding layer protrudes from the side surface of the electronic component, and the cross-section of the edge of the cladding layer is spherical, so that the The cladding layer will not crawl to the side of the electronic element due to capillary action, and the cladding layer does not contact the side of the electronic element; and the encapsulation layer is formed on the carrier structure to cover the plurality of electronic elements with cladding. The electronic package of claim 1, wherein the structures of the plurality of electronic components are different from each other. The electronic package of claim 1, wherein the distance between the gaps is at most 300 microns. The electronic package as claimed in claim 1, wherein a surface of the electronic component is exposed on a surface of the packaging layer. The electronic package of claim 1, wherein the Young's modulus of the package layer is at least 20GPa. The electronic package of claim 1, wherein the Young's modulus of the encapsulation layer is greater than the Young's modulus of the cladding layer. A manufacturing method of an electronic package, comprising: A plurality of electronic components are provided, wherein a plurality of conductive bumps and a coating layer covering the plurality of conductive bumps are formed on each of the electronic components, and the coating layer is a non-conductive film; the plurality of electronic components are arranged at intervals on the On a carrier structure, a gap is formed between any two adjacent electronic components, wherein each of the electronic components is fixed on the carrier structure with the cladding layer, and is electrically connected with the conductive bumps the carrying structure, the end of the cladding layer protrudes from the side of the electronic component, the cross-section of the edge of the cladding layer is spherical, the cladding layer does not contact the side of the electronic component; and the encapsulation layer is formed on On the carrying structure, the plurality of electronic components and the cladding layer are covered. The manufacturing method of an electronic package as claimed in claim 7, wherein the structures of the plurality of electronic components are different from each other. The method for manufacturing an electronic package as claimed in claim 7, wherein the distance between the gaps is at most 300 microns. The method for manufacturing an electronic package as claimed in claim 7 further comprises grinding the package layer, so that a surface of the electronic component is exposed on a surface of the package layer. The manufacturing method of an electronic package as claimed in claim 7, wherein the Young's modulus of the package layer is at least 20GPa. The method for manufacturing an electronic package as claimed in claim 7, wherein the Young's modulus of the encapsulation layer is greater than the Young's modulus of the cladding layer.

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