TWI772816B - Electronic package and manufacturing method thereof - Google Patents
Electronic package and manufacturing method thereof Download PDFInfo
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- TWI772816B TWI772816B TW109118804A TW109118804A TWI772816B TW I772816 B TWI772816 B TW I772816B TW 109118804 A TW109118804 A TW 109118804A TW 109118804 A TW109118804 A TW 109118804A TW I772816 B TWI772816 B TW I772816B
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- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 230000009471 action Effects 0.000 claims abstract description 6
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 97
- 238000005253 cladding Methods 0.000 claims description 46
- 238000005538 encapsulation Methods 0.000 claims description 36
- 239000011247 coating layer Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000005336 cracking Methods 0.000 abstract description 5
- 230000009193 crawling Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 20
- 239000000758 substrate Substances 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000012792 core layer Substances 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
本發明係有關一種半導體裝置,尤指一種覆晶封裝型之電子封裝件及其製法。 The present invention relates to a semiconductor device, in particular to an electronic package of flip chip package type and a manufacturing method thereof.
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術繁多,例如晶片尺寸構裝(Chip Scale Package,簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached,簡稱DCA)或多晶片模組封裝(Multi-Chip Module,簡稱MCM)等覆晶型封裝模組,或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊模組。 With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. There are many technologies currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (Multi-Chip Module) MCM) and other flip-chip packaging modules, or three-dimensionally stacking and integrating chips into a three-dimensional integrated circuit (3D IC) chip stacking module.
圖1係為習知3D IC式半導體封裝件1之剖面示意圖。首先,提供一具有相對之轉接側10a與置晶側10b之矽中介板(Through Silicon interposer,簡稱TSI)10,且該矽中介板10具有複數連通該置晶側10b與轉接側10a之導電矽穿孔(Through-silicon via,簡稱TSV)100,並於該置晶側10b上形成線路結構101以供接置多個具有複數銲錫凸塊12之半導體元件11,再以底膠13包覆該些銲錫凸塊12,並形成封裝層14以包覆該半導體元件11,並研磨該封裝層14,以令該半導體元件11之上表面外露出該封裝層14。接著,將該矽中介板10以其轉接側10a透過複數導電元件15設於一封裝基板16上,並使該封裝基板16電性連接該些導電
矽穿孔100,再以底膠17包覆該些導電元件15。接著,形成封裝膠體18於該封裝基板16上,以令該封裝膠體18包覆該封裝層14與該矽中介板10。最後,形成複數銲球160於該封裝基板16之下側,以供接置於一電路板19上。
FIG. 1 is a schematic cross-sectional view of a conventional 3D IC type semiconductor package 1 . First, provide a through silicon interposer (TSI) 10 having an opposite via
惟,習知半導體封裝件1中,係先將該半導體元件11覆晶接合該線路結構101,再填入該底膠13,致使該底膠13之外側130會呈坡狀,如圖1’所示,導致該底膠13之外側130會因各該半導體元件11之間的間隙S所產生之毛細作用而爬流於各該半導體元件11之側面11c上,以致於該半導體元件11的內部應力增高,故於研磨該封裝層14時,外部的研磨作用力會傳遞至該半導體元件11中,而造成該半導體元件11之應力集中而發生破裂,導致該半導體封裝件1之可靠度不佳。
However, in the conventional semiconductor package 1, the
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem to be solved at present.
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:承載結構;複數電子元件,係間隔設置於該承載結構上,以令任二相鄰之該電子元件之間形成有一間隙,其中,各該電子元件上形成有複數導電凸塊及一包覆該複數導電凸塊之包覆層,使各該電子元件以該包覆層黏固於該承載結構上,且以該導電凸塊電性連接該承載結構;以及封裝層,係形成於該承載結構上,以包覆該複數電子元件與包覆層。 In view of various deficiencies in the above-mentioned prior art, the present invention provides an electronic package, comprising: a bearing structure; a plurality of electronic components arranged on the bearing structure at intervals, so that any two adjacent electronic components are formed between them. There is a gap, wherein a plurality of conductive bumps and a cladding layer covering the plurality of conductive bumps are formed on each of the electronic components, so that each of the electronic components is fixed on the carrier structure by the cladding layer, and is The conductive bump is electrically connected to the carrying structure; and an encapsulation layer is formed on the carrying structure to cover the plurality of electronic components and the covering layer.
本發明復提供一種電子封裝件之製法,係包括:提供複數電子元件,其中,各該電子元件上形成有複數導電凸塊及一包覆該複數導電凸塊之包覆層;將複數電子元件間隔設置於一承載結構上,以令任二相鄰之該電子元件之間形成有一間隙,其中,各該電子元件係以該包覆層黏固於該承載結構上,且以該導電凸塊電性連接該承載結構;以及形成封裝層於該承載結構上,以包覆該複數電子元件與包覆層。 The present invention further provides a method for manufacturing an electronic package, which includes: providing a plurality of electronic components, wherein a plurality of conductive bumps and a coating layer covering the plurality of conductive bumps are formed on each of the electronic components; It is arranged on a carrying structure at intervals, so that a gap is formed between any two adjacent electronic components, wherein each electronic component is fixed on the carrying structure by the coating layer, and the conductive bump is used to form a gap. electrically connecting the carrying structure; and forming an encapsulation layer on the carrying structure to cover the plurality of electronic components and the covering layer.
前述之電子封裝件及其製法中,該複數電子元件之構造係彼此不同。 In the aforementioned electronic package and its manufacturing method, the structures of the plurality of electronic components are different from each other.
前述之電子封裝件及其製法中,該間隙之間距係至多為300微米。 In the aforementioned electronic package and its manufacturing method, the distance between the gaps is at most 300 microns.
前述之電子封裝件及其製法中,復包括對該封裝層進行研磨,以令該電子元件之一表面外露於該封裝層之一表面。 In the aforementioned electronic package and its manufacturing method, the encapsulation layer may be ground, so that a surface of the electronic component is exposed on a surface of the encapsulation layer.
前述之電子封裝件及其製法中,該包覆層之側面係齊平於該電子元件之側面。 In the aforementioned electronic package and the manufacturing method thereof, the side surface of the cladding layer is flush with the side surface of the electronic component.
前述之電子封裝件及其製法中,該包覆層係凸出該電子元件之側面,且該包覆層未接觸該電子元件之側面。例如,該包覆層以其端部凸出該電子元件之側面,且該包覆層之邊緣之剖面係呈球面。 In the aforementioned electronic package and its manufacturing method, the cladding layer protrudes from the side surface of the electronic component, and the cladding layer does not contact the side surface of the electronic component. For example, the end of the cladding layer protrudes from the side surface of the electronic component, and the cross-section of the edge of the cladding layer is spherical.
前述之電子封裝件及其製法中,該包覆層係為非導電性膜。 In the aforementioned electronic package and its manufacturing method, the coating layer is a non-conductive film.
前述之電子封裝件及其製法中,該封裝層之楊氏模數係至少為20GPa。 In the aforementioned electronic package and its manufacturing method, the Young's modulus of the package layer is at least 20 GPa.
前述之電子封裝件及其製法中,該封裝層之楊氏模數係大於該包覆層之楊氏模數。 In the aforementioned electronic package and the manufacturing method thereof, the Young's modulus of the packaging layer is greater than the Young's modulus of the cladding layer.
由上可知,本發明之電子封裝件及其製法中,主要藉由該電子元件上佈設該包覆層,以黏固於該承載結構上,使該包覆層不會因毛細作用而爬流至該電子元件之側面上,故相較於習知技術,本發明於研磨該封裝層時,即使外部的研磨作用力傳遞至該電子元件中,該電子元件之內部仍可分散其所受之應力,以避免該電子元件因應力集中而發生破裂之問題,因而能提高該電子封裝件之可靠度。 As can be seen from the above, in the electronic package and the manufacturing method thereof of the present invention, the coating layer is mainly arranged on the electronic component to be fixed on the bearing structure, so that the coating layer will not crawl due to capillary action to the side of the electronic component, so compared with the prior art, when the present invention grinds the encapsulation layer, even if the external grinding force is transmitted to the electronic component, the inside of the electronic component can still disperse the impact on the packaging layer. stress, so as to avoid the problem of cracking of the electronic component due to stress concentration, thereby improving the reliability of the electronic package.
1:半導體封裝件 1: Semiconductor package
10:矽中介板 10: Silicon interposer
10a:轉接側 10a: Transfer side
10b:置晶側 10b: chip placement side
100:導電矽穿孔 100: Conductive TSV
101:線路結構 101: Line structure
11:半導體元件 11: Semiconductor components
11c,21c,23c,31c:側面 11c, 21c, 23c, 31c: Side
12:銲錫凸塊 12: Solder bumps
13:底膠 13: Primer
130:外側 130: Outside
14,24:封裝層 14,24: Encapsulation layer
15:導電元件 15: Conductive elements
16:封裝基板 16: Package substrate
160:銲球 160: Solder Ball
17:底膠 17: Primer
18:封裝膠體 18: Encapsulating colloid
19:電路板 19: circuit board
2,2’,3:電子封裝件 2,2',3: Electronic package
2a:整版面基材結構 2a: Full-page substrate structure
20:承載結構 20: Bearing structure
200:線路層 200: circuit layer
21,31:電子元件 21,31: Electronic Components
21a:作用面 21a: Action surface
21b:非作用面 21b: Non-active surface
210:電極墊 210: Electrode pads
22:導電凸塊 22: Conductive bumps
23:包覆層 23: Cladding
230:邊緣 230: Edge
24b:上表面 24b: Upper surface
310:封裝材 310: Packaging material
311:控制晶片 311: Control Chip
312:高頻寬記憶體型晶片 312: High bandwidth memory chip
X:水平方向 X: horizontal direction
L:切割路徑 L: cutting path
S:間隙 S: Clearance
t:間距 t: spacing
圖1係為習知半導體封裝件之剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.
圖1’係為圖1的局部放大剖視示意圖。 Fig. 1' is a schematic partial enlarged cross-sectional view of Fig. 1 .
圖2A至圖2C係為本發明之電子封裝件之製法的剖視示意圖。 2A to 2C are schematic cross-sectional views of a method for manufacturing an electronic package of the present invention.
圖2B’係為圖2B之另一態樣的局部放大剖視示意圖。 Fig. 2B' is a schematic partial enlarged cross-sectional view of another aspect of Fig. 2B.
圖2C’係為圖2C之另一態樣的剖視示意圖。 Fig. 2C' is a schematic cross-sectional view of another aspect of Fig. 2C.
圖3係為圖2C之另一態樣的剖視示意圖。 FIG. 3 is a schematic cross-sectional view of another aspect of FIG. 2C .
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following specific embodiments are used to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it has no technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope of the present invention without affecting the effect and the purpose that the present invention can achieve. The technical content disclosed by the invention can be covered within the scope. At the same time, the terms such as "above" quoted in this specification are only for the convenience of description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments of their relative relationships do not substantially change the technical content. Hereinafter, it should also be regarded as the scope in which the present invention can be implemented.
圖2A至圖2C係為本發明之電子封裝件2之製法之剖視示意圖。
2A to 2C are schematic cross-sectional views of a method of manufacturing the
如圖2A所示,提供一整版面基材結構2a,其包含複數陣列排設之電子元件21,且各該電子元件21上佈設有複數導電凸塊22及一包覆該些導電凸塊22之包覆層23。
As shown in FIG. 2A , a full-
該電子元件21可為主動元件、被動元件、封裝結構或其組合者,且該主動元件係如半導體晶片,而該被動元件係如電阻、電容及電感。於本實施例中,該電子元件21係為半導體晶片,並具有相對之作用面21a與非作用面21b,該作用面21a上具有複數電極墊210,且於各該電極墊210上形成有導電凸塊22,且於該作用面21a上形成有該包覆層23以包覆該些導電凸塊22,同時,各該導電凸塊22係外露於該包覆層23。
The
再者,該導電凸塊22係為金屬柱(如銅柱)、焊錫材或其組合,且該包覆層23係為非導電性膜(Non-Conductive Film,簡稱NCF)。
Furthermore, the
如圖2B所示,沿如圖2A所示之切割路徑L對該整版面基材結構2a進行切單製程,以分離各該電子元件21,再於一承載結構20上沿水平方向X上間隔佈設至少兩個電子元件21,且任二相鄰之該電子元件21之間係形成一空間(間隙)S,該空間(間隙)S之間距t至多為300微米(μm)。
As shown in FIG. 2B , the whole-
該承載結構20可為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路構造,且其構成係於介電材上形成複數線路層200,如線路重佈層(redistribution layer,簡稱RDL)。於本實施例中,該承載結構20係無核心層(coreless)之線路構造。然而,於其它實施例中,該承載結構20亦可為具有複數導電矽穿孔(Through-silicon via,簡稱TSV)之半導體基板,以作為矽中介板(Through Silicon interposer,簡稱TSI)。應可理解地,該承載結構20亦可為其它可供承載如晶片等電子元件之承載單元,如導線架(lead frame),但並不限於上述。
The
再者,當該電子元件21藉其包覆層23壓合黏固於該承載結構20上時,係以覆晶方式使該些導電凸塊22電性連接該承載結構20之線路層200。
Furthermore, when the
又,藉由切單製程,該電子元件21之側面21c係齊平該包覆層23之側面23c。然而,於另一實施例中,基於將該電子元件21壓合於該承載結構20上之作用力,可使該包覆層23之側面23c形成為凸出該電子元件21之側面21c的邊緣230,如圖2B’所示。具體地,該包覆層23之邊緣230之剖面係呈凸狀(如半球狀之球面)。
In addition, through the singulation process, the
另外,於本實施例中,該些電子元件21雖均為相同類型(即主動元件),但其內部構造可相同或不相同。
In addition, in this embodiment, although the
如圖2C所示,形成一封裝層24於該承載結構20上,以包覆該包覆層23與該些電子元件21。
As shown in FIG. 2C , an
該封裝層24可為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)、模封化合物(molding compound)或其它適當材料。於本實施例中,該封裝層24係採用壓合(lamination)或模壓(molding)之方式形成於該承載結構20上,以令該封裝層24填滿該間隙S。
The
再者,該封裝層24之楊氏模數(Young's modulus)係大於該包覆層23之楊氏模數。於本實施例中,該封裝層24之楊氏模數係為20GPa以上。
Furthermore, the Young's modulus of the
又,可藉由整平製程或薄化製程,使該電子元件21之非作用面21b與該封裝層24之上表面24b共平面,如圖2C’所示,以令該電子元件21之非作用面21b外露於該封裝層24。例如,當形成該封裝層24於該承載結構20上時,該封裝層24係覆蓋該電子元件21之非作用面21b,再以研磨或切割方式移除該封裝層24之部分材質(亦可依需求同時移除該電子元件21之非作用面21b之部分材質),使該電子元件21之非作用面21b齊平於該封裝層24之上表面24b。
In addition, the
另外,於形成該封裝層24後,可於該承載結構20之下側(或植球側)上形成複數銲球(圖略),以供該電子封裝件2接置於一如電路板之電子裝置(圖略)上。
In addition, after the
應可理解地,該些電子元件21亦可為不相同類型的電子元件。如圖3所示之兩電子元件21,31,該電子元件21(主動元件)係為特殊應用積體電路(Application-specific integrated circuit,簡稱ASIC)型半導體晶片,而另一電子元件31係為封裝結構,其包含有封裝材310、控制晶片311及至少一高頻寬記憶體(High Bandwidth Memory,簡稱HBM)型晶片312之封裝模組,並以控制晶片311之電極墊210結合該些導電凸塊22。
It should be understood that the
因此,本發明之製法,主要先於該電子元件21,31上形成該包覆層23,再藉該包覆層23黏固於該承載結構20上,以使該包覆層23不會因毛細作用而爬流至該電子元件21,31之側面21c,31c上,因而不論該間隙S之間距t大小(如小於或等於150微米),該包覆層23於該間隙S中均不會有毛細現象,使該電子元件21,31的內部能避免應力增大之現象,故相較於習知技術,本發明之製法於研磨該封裝層24時,即使外部的研磨作用力傳遞至該電子元件21,31中,該電子元件21,31之內部仍可分散其所受之應力,以避免該電子元件21,31因應力集中而發生破裂之問題,因而能提高該電子封裝件2之可靠度。
Therefore, in the manufacturing method of the present invention, the
再者,藉由楊氏模數較大之封裝層24填滿該間隙S,能強化該間隙的強度,使該電子元件21,31的內部不會發生應力集中造成封裝件破裂之現象。
Furthermore, the gap S is filled by the
本發明復提供一種電子封裝件2,2’,3,係包括:一承載結構20、複數電子元件21,31、以及一封裝層24。
The present invention further provides an
所述之複數電子元件21,31係間隔設置於該承載結構20上,以令任二相鄰之該電子元件21,31之間形成有一間隙S,各該電子元件21,31係具有複數導電凸塊22及一包覆該複數導電凸塊22之包覆層23,使各該電子元件21,31以該包覆層23黏固於該承載結構20上,且以該導電凸塊22電性連接該承載結構20。
The plurality of
所述之封裝層24係形成於該承載結構20上,以包覆該複數電子元件21,31與包覆層23。
The
於一實施例中,該複數電子元件21,31之構造係彼此不同。
In one embodiment, the structures of the plurality of
於一實施例中,該間隙S之間距t係至多為300微米。 In one embodiment, the distance t between the gaps S is at most 300 microns.
於一實施例中,該電子元件21,31之表面(如非作用面)係外露於該封裝層24之表面上24b。
In one embodiment, the surfaces (eg, inactive surfaces) of the
於一實施例中,該包覆層23之側面23c係齊平該電子元件21,31之側面21c,31c。
In one embodiment, the
於一實施例中,該包覆層23係凸出該電子元件21,31之側面21c,31c,且該包覆層23未接觸該電子元件21,31之側面21c,31c。例如,該包覆層23以其邊緣230凸出該電子元件21之側面21c,且該包覆層23之邊緣230之剖面係呈球面。
In one embodiment, the
於一實施例中,該包覆層23係為非導電性膜。
In one embodiment, the
於一實施例中,該封裝層24之楊氏模數係至少為20GPa。
In one embodiment, the Young's modulus of the
於一實施例中,該封裝層24之楊氏模數係大於該包覆層23之楊氏模數。
In one embodiment, the Young's modulus of the
綜上所述,本發明之電子封裝件及其製法,係藉由該電子元件上佈設該包覆層,以黏固於該承載結構上,使該包覆層不會擠壓至該電子元件之側面上,故本發明之電子元件之內部能避免因應力集中而發生破裂之問題,因而能提高該電子封裝件之可靠度。另外,封裝層24填滿該間隙S,能強化該間隙的強度,使該電子元件的內部不會應力集中造成封裝件破裂。
To sum up, the electronic package of the present invention and the manufacturing method thereof are arranged on the electronic component by disposing the coating layer to be fixed on the supporting structure, so that the coating layer will not be pressed against the electronic component On the lateral side, the internal part of the electronic component of the present invention can avoid the problem of cracking due to stress concentration, thereby improving the reliability of the electronic package. In addition, the
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the right of the present invention should be listed in the scope of the patent application described later.
2:電子封裝件 2: Electronic packages
20:承載結構 20: Bearing structure
21:電子元件 21: Electronic Components
22:導電凸塊 22: Conductive bumps
23:包覆層 23: Cladding
24:封裝層 24: Encapsulation layer
S:間隙 S: Clearance
Claims (12)
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TW201401458A (en) * | 2012-06-22 | 2014-01-01 | 矽品精密工業股份有限公司 | Semiconductor package and method of forming the same |
TW201411745A (en) * | 2012-09-10 | 2014-03-16 | 矽品精密工業股份有限公司 | Method for forming semiconductor packages |
US20140264813A1 (en) * | 2013-03-13 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Package and Method |
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TW201411745A (en) * | 2012-09-10 | 2014-03-16 | 矽品精密工業股份有限公司 | Method for forming semiconductor packages |
US20140264813A1 (en) * | 2013-03-13 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Package and Method |
US20170358560A1 (en) * | 2015-02-09 | 2017-12-14 | Amkor Technology, Inc. | Semiconductor Package Using A Coreless Signal Distribution Structure |
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